ADV7182 [ADI]
10-Bit, SDTV Video Decoder with Differential Inputs; 10位， SDTV视频解码器，差分输入
| 型号： | ADV7182 |
| 厂家： | 
ADI |
| 描述： | 10-Bit, SDTV Video Decoder with Differential Inputs |
| 文件： | 总96页 (文件大小：1844K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
10-Bit, SDTV Video Decoder with
Differential Inputs
ADV7182
Data Sheet
RoviTM (Macrovision) copy protection detection
NTSC/PAL/SECAM autodetection
FEATURES
Worldwide NTSC/PAL/SECAM color demodulation support
One 10-bit analog-to-digital converter (ADC), 4× oversampling
per channel for CVBS, Y/C mode, and YPrPb
Four analog video input channels with on-chip antialiasing filter
CVBS (composite), Y/C (S-Video), and YPrPb (component) video
input support
8-bit ITU-R BT.656 YCrCb 4:2:2 output and HS, VS, or FIELD
Full-featured VBI data slicer with teletext support (WST)
Power-down mode and ultralow sleep mode current
Two-wire serial MPU interface (I2C compatible)
Single 1.8 V supply possible
Qualified for automotive applications
−40°C to +105°C temperature grade
32-lead, 5 mm × 5 mm, RoHS-compliant LFCSP
Fully differential, pseudo differential, and single-ended CVBS
video input support
Up to 4 V common-mode input range solution
Excellent common-mode rejection capabilities
Five-line adaptive comb filters and CTI/DNR video enhancement
TBC functionality provided by adaptive digital line length
tracking (ADLLT), signal processing, and enhanced first in,
first out (FIFO) management
APPLICATIONS
Automotive infotainment
DVRs for video security
Media players
Integrated automatic gain control (AGC) with adaptive peak
white mode
Video fast switch capability
Adaptive contrast enhancement (ACE)
Down dither (8 bits to 6 bits)
FUNCTIONAL BLOCK DIAGRAM
CLOCK PROCESSING BLOCK
XTALP
XTALN
LLC
PLL
ADLLT PROCESSING
VS/FIELD/SFL
HS
DIGITAL
PROCESSING
BLOCK
10-BIT
ADC
AA
A
A
A
A
1
2
3
4
IN
IN
IN
IN
FILTER 1
2D COMB
AA
FILTER 2
DIFFERENTIAL
OR
SINGLE-ENDED
ANALOG VIDEO
INPUTS
+
SHA
ADC
VBI SLICER
AA
FILTER 3
–
8-BIT PIXEL DATA
P7 TO P0
COLOR
DEMOD
AA
FILTER 4
2
REFERENCE
I C/CONTROL
INTRQ
ADV7182
SCLK SDATA ALSB RESET PWRDWN
Figure 1.
Rev. A
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©2013 Analog Devices, Inc. All rights reserved.
www.analog.com
ADV7182
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
General Description......................................................................... 3
Overview of the Analog Front End............................................ 3
Overview of the Standard Definition Processor ...................... 4
Specifications..................................................................................... 5
Electrical Characteristics............................................................. 5
Video Specifications..................................................................... 6
Timing Specifications .................................................................. 7
Analog Specifications................................................................... 8
Thermal Specifications ................................................................ 8
Absolute Maximum Ratings............................................................ 9
ESD Caution.................................................................................. 9
Pin Configuration and Function Descriptions........................... 10
Power Supply Sequencing.............................................................. 11
Power-Up Sequence ................................................................... 11
SD Chroma Path......................................................................... 19
ACE and Dither Processing Blocks.......................................... 20
Sync Processing .......................................................................... 20
VBI Data Recovery..................................................................... 20
General Setup.............................................................................. 20
Color Controls............................................................................ 22
Free-Run Operation................................................................... 24
Clamp Operation........................................................................ 25
Luma Filter.................................................................................. 26
Chroma Filter.............................................................................. 29
Gain Operation........................................................................... 30
Chroma Transient Improvement (CTI) .................................. 34
Digital Noise Reduction (DNR) and Luma Peaking Filter... 35
Comb Filters................................................................................ 36
IF Filter Compensation ............................................................. 38
Adaptive Contrast Enhancement (ACE)................................. 38
Dither Function.......................................................................... 39
AV Code Insertion and Controls ............................................. 40
Synchronization Output Signals............................................... 41
Sync Processing .......................................................................... 48
VBI Data Decode ....................................................................... 48
I2C Readback Registers.............................................................. 56
Pixel Port Configuration ............................................................... 60
MPU Port Description................................................................... 61
Register Access............................................................................ 62
Register Programming............................................................... 62
I2C Sequencer.............................................................................. 62
I2C Register Maps ........................................................................... 63
PCB Layout Recommendations.................................................... 94
Analog Interface Inputs............................................................. 94
Power Supply Decoupling ......................................................... 94
VREFN and VREFP................................................................... 94
Digital Outputs (Both Data and Clocks) ................................ 94
Digital Inputs .............................................................................. 94
Typical Circuit Connection........................................................... 95
Outline Dimensions....................................................................... 96
Ordering Guide .......................................................................... 96
Automotive Products................................................................. 96
RESET
Power-On
....................................................................... 11
Universal Power Supply............................................................. 11
Input Networks ............................................................................... 12
Single-Ended Input Network.................................................... 12
Differential Input Network ....................................................... 12
Analog Front End ........................................................................... 13
Input Configuration................................................................... 13
Analog Input Muxing ................................................................ 13
Antialiasing Filters ..................................................................... 15
Global Control Registers ............................................................... 16
Power-Saving Modes.................................................................. 16
Reset Control .............................................................................. 16
Global Pin Control ..................................................................... 16
Global Status Register .................................................................... 18
Identification............................................................................... 18
Status 1 ......................................................................................... 18
Status 2 ......................................................................................... 18
Status 3 ......................................................................................... 18
Autodetection Result.................................................................. 18
Video Processor .............................................................................. 19
SD Luma Path ............................................................................. 19
REVISION HISTORY
3/13—Rev. 0 to Rev. A
Changes to Register 0x14, Table 94.............................................. 72
Changes to Register 0xF9, Table 94.............................................. 82
Change to Features Section ............................................................. 1
Changes to General Description Section ...................................... 4
Changes to Free Run Operation Section and Table 33, Added Luma
Ramp Test Pattern Section, VS_COAST_MODE[1:0], Address
0xF9[3:2] Section, and Table 34, Renumbered Sequentially.......... 24
1/13—Revision 0: Initial Version
Rev. A | Page 2 of 96
Data Sheet
ADV7182
GENERAL DESCRIPTION
The ADV7182 automatically detects and converts standard
analog baseband video signals compatible with worldwide NTSC,
PAL, and SECAM standards into a 4:2:2 component video data
stream. This video data stream is compatible with the 8-bit ITU-R
BT.656 interface standard.
OVERVIEW OF THE ANALOG FRONT END
The ADV7182 analog front end (AFE) comprises a single high
speed, 10-bit ADC that digitizes the analog video signal before
applying it to the standard definition processor. The AFE employs
differential channels to the ADC to ensure high performance in
mixed-signal applications and to enable differential CVBS to be
connected directly to the ADV7182
External HS, VS, and FIELD signals can provide timing references
for LCD controllers and other video ASICs. The accurate 10-bit
analog-to-digital conversion provides professional quality video
performance for consumer applications with true 8-bit data
resolution. The analog video inputs accept both single-ended,
pseudo-differential, and fully differential composite video signals
as well as S-Video and YPbPr video signals, supporting a wide
range of consumer and automotive video sources.
The front end also includes a 3-channel input mux that enables
multiple composite video signals to be applied to the ADV7182.
Current clamps are positioned in front of the ADC to ensure
that the video signal remains within the range of the converter.
A resistor divider network is required before each analog input
channel to ensure that the input signal is kept within the range
of the ADC (see Figure 23). The choice of this resistor divider
ratio provides a common-mode range of up to 4 V. Fine clamping
of the video signal is performed downstream by digital fine
clamping within the ADV7182.
The ADV7182 along with an external resistor divider provide a
common-mode input range of 4 V, enabling the removal of large
signal, common-mode transients present on the video lines.
Common-mode rejection (CMR) values of up to 80 dB can be
achieved without the need for external amplifier circuitry
Table 1 shows the three ADC clocking rates that are determined
by the video input format to be processed. These clock rates ensure
4× oversampling per channel for CVBS, Y/C, and YPrPb modes.
The AGC and clamp restore circuitry allow an input video signal
peak-to-peak range to 1.0 V at the analog video input pin of the
ADV7182. Alternatively, these can be bypassed for manual settings.
The ADV7182 has a fully differential AFE. This allows for inherent
small and large signal noise rejection, improved electromagnetic
interference (EMI), and the ability to absorb ground bounce.
Support is offered for both true differential and pseudo-
differential signals.
The ADV7182 can be protected from short-to-battery (STB)
events with standard ac coupling capacitors.
The ADV7182 is programmed via a two-wire, serial bidirectional
port (I2C® compatible) and is fabricated in a 1.8 V CMOS process.
Its monolithic CMOS construction ensures greater functionality
with lower power dissipation. The LFCSP package options make
the decoder ideal for space-constrained portable applications.
Table 1. ADC Clock Rates
Oversampling
Rate per Channel
Input Format
CVBS
Y/C (S-Video)2
YPrPb2
ADC Clock Rate (MHz)1
The ADV7182 is a versatile one-chip multiformat video decoder
that automatically detects PAL, NTSC, and SECAM standards in
the form of composite, S-Video, and component video. The
ADV7182 can receive composite signals in either single-ended
or differential modes. This makes the ADV7182 ideal for
automotive applications.
57.27
114
172
4×
4×
4×
1 Based on a 28.63636 MHz clock input to the ADV7182.
2 See INSEL[4:0] in Table 95 for writes needed to set Y/C (S-Video) and YPrPb
modes.
The ADV7182 converts these analog video formats into a
digital 8-bit ITU-R BT.656 video stream.
The digital video output stream of the ADV7182 interfaces
easily to a wide range of MPEG encoders, codecs, mobile video
processors, and Analog Devices, Inc., digital video encoders, such
as the ADV7391. External HS, VS, and FIELD signals provide
timing references for LCD controllers and other video ASICs.
Rev. A | Page 3 of 96
ADV7182
Data Sheet
VCD players, and camcorders. The ADV7182 contains a chroma
transient improvement (CTI) processor that sharpens the edge
rate of chroma transitions, resulting in sharper vertical transitions.
OVERVIEW OF THE STANDARD DEFINITION
PROCESSOR
The ADV7182 is capable of decoding a large selection of baseband
video signals in composite (both single-ended and differential),
S-Video, and component formats. The video standards supported
by the video processor include PAL B/PAL D/PAL I/PAL G/PAL H,
PAL 60, PAL M, PAL N, PAL Nc, NTSC M/NTSC J, NTSC 4.43,
and SECAM B/SECAM D/SECAM G/SECAM K/SECAM L. The
ADV7182 can automatically detect the video standard and process
it accordingly.
The ACE offers improved visual detail using an algorithm that
automatically varies contrast levels to enhance picture detail.
This enables the contrast in dark areas of an image to be increased
without saturating the bright areas of an image. This is particularly
useful in automotive applications, where it can be important to be
able to discern objects in shaded areas.
Down dithering from eight bits to six bits enables ease of design
for standard LCD panels.
The ADV7182 has a five-line, superadaptive, 2D comb filter that
gives superior chrominance and luminance separation when
decoding a composite video signal. This highly adaptive filter
automatically adjusts its processing mode according to the video
standard and signal quality without requiring user intervention.
Video user controls such as brightness, contrast, saturation, and
hue are also available with the ADV7182.
The video processor can process a variety of VBI data services,
such as closed captioning (CCAP), wide screen signaling (WSS),
copy generation management system (CGMS), and teletext data
slicing for world standard teletext (WST). Data is transmitted via
the 8-bit video output port as ancillary data packets (ANC). The
ADV7182 is fully Macrovision® certified; detection circuitry
enables Type I, Type II, and Type III protection levels to be
identified and reported to the user. The decoder is also fully
robust to all Macrovision signal inputs.
The ADV7182 implements a patented ADLLT™ algorithm to
track varying video line lengths from sources such as a VCR.
ADLLT enables the ADV7182 to track and decode poor quality
video sources such as VCRs and noisy sources from tuner outputs,
Rev. A | Page 4 of 96
Data Sheet
ADV7182
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
AVDD, DVDD, and PVDD = 1.71 V to 1.89 V; DVDDIO = 1.71 V to 3.46 V, specified at operating temperature range, unless otherwise noted.
Table 2.
Parameter
Symbol
Test Conditions/Comments
Min
Typ
Max
Unit
STATIC PERFORMANCE
Resolution (Each ADC)
Integral Nonlinearity
Differential Nonlinearity
DIGITAL INPUTS
N
INL
DNL
10
Bits
LSB
LSB
CVBS mode
CVBS mode
2
−0.6/+0.6
Input High Voltage (DVDDIO = 3.3 V)
Input High Voltage (DVDDIO = 1.8 V)
Input Low Voltage (DVDDIO = 3.3 V)
Input Low Voltage (DVDDIO = 1.8 V)
Crystal Inputs
VIH
VIH
VIL
VIL
VIH
VIL
IIN
2
1.2
V
V
V
V
V
V
µA
µA
µA
pF
0.8
0.4
1.2
0.4
Input Leakage Current
−10
−10
−10
+10
+15
+48
10
Input Leakage Current (SDATA, SCLK)
Input Leakage Current (PWRDWN, ALSB)
Input Capacitance
IIN
IIN
CIN
DIGITAL OUTPUTS
Output High Voltage (DVDDIO = 3.3 V)
Output High Voltage (DVDDIO = 1.8 V)
Output Low Voltage (DVDDIO = 3.3 V)
Output Low Voltage (DVDDIO = 1.8 V)
High Impedance Leakage Current
Output Capacitance
VOH
VOH
VOL
VOL
ILEAK
COUT
ISOURCE = 0.4 mA
ISOURCE = 0.4 mA
ISINK = 3.2 mA
ISINK = 1.6 mA
2.4
1.4
V
V
V
V
µA
pF
0.4
0.2
10
20
POWER REQUIREMENTS1, 2
Digital I/O Power Supply
PLL Power Supply
Analog Power Supply
Digital Power Supply
Digital I/O Supply Current
PLL Supply Current
Analog Supply Current
DVDDIO
PVDD
AVDD
DVDD
IDVDDIO
IPVDD
1.71 3.3
1.71 1.8
1.71 1.8
1.71 1.8
3.46
1.89
1.89
1.89
V
V
V
V
3
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
12
35
69
35
69
60
75
60
66
60
66
60
60
IAVDD
Single-ended CVBS input
Differential CVBS input
Single-ended CVBS fast switch
Differential CVBS fast switch
Y/C input
YPrPb input
Digital Supply Current
IDVDD
Single-ended CVBS input
Differential CVBS input
Single-ended CVBS fast switch
Differential CVBS fast switch
Y/C input
YPrPb input
Rev. A | Page 5 of 96
ADV7182
Data Sheet
Parameter
Symbol
Test Conditions/Comments
Min
Typ
Max
Unit
POWER DOWN PERFORMANCE1
Digital I/O Supply Power-Down Current
PLL Supply Power-Down Current
Analog Supply Power-Down Current
Digital Supply Power-Down Current
Total Power Dissipation in Power-Down Mode
IDVDDIO
IPVDD
IAVDD
IDVDD
73
38
0.15
368
1
µA
µA
µA
µA
mW
1 Guaranteed by characterization.
2 Typical current consumption values are recorded with nominal voltage supply levels and an SMPTEBAR test pattern.
VIDEO SPECIFICATIONS
Guaranteed by characterization. AVDD, DVDD, and PVDD = 1.71 V to 1.89 V; DVDDIO = 1.71 V to 3.46 V, specified at operating temperature
range, unless otherwise noted.
Table 3.
Parameter
Symbol
Test Conditions/Comments
Min Typ
Max
Unit
NONLINEAR SPECIFICATIONS1
Differential Phase
Differential Gain
Luma Nonlinearity
NOISE SPECIFICATIONS
SNR Unweighted
DP
DG
LNL
CVBS input, modulate five-step
CVBS input, modulate five-step
CVBS input, five-step
0.9
0.5
2.0
Degrees
%
%
Luma ramp
57
58
60
75
dB
dB
dB
dB
Luma flat field
Analog Front-End Crosstalk
Common-Mode Rejection2
LOCK TIME SPECIFICATIONS
Horizontal Lock Range
Vertical Lock Range
fSC Subcarrier Lock Range
Color Lock-In Time
Sync Depth Range
CMR
−5
40
1.3
60
20
5
+5
70
%
Hz
kHz
Lines
%
200
200
Color Burst Range
%
Vertical Lock Time
Autodetection Switch Speed3
Fast Switch Speed4
2
100
100
Fields
Lines
ms
LUMA SPECIFICATIONS
Luma Brightness Accuracy
Luma Contrast Accuracy
CVBS, 1 V input
CVBS, 1 V input
1
1
%
%
1 These specifications apply for all CVBS input types (NTSC, PAL, SECAM) as well as for single-ended and differential CVBS inputs.
2 The common-mode rejection (CMR) of this circuit design is critically dependent on the external resistor matching on its inputs. This measurement was performed with 0.1%
tolerant resistors, a common-mode voltage of 1 V, and a common-mode frequency of 10 kHz.
3 This is the time that it takes the ADV7182 to detect which video format is present at its input, for example, PAL I or NTSC M.
4 This is the time that it takes the ADV7182 to switch from one (single-ended or differential) analog input to another, for example, switching from AIN1 to AIN2.
Rev. A | Page 6 of 96
Data Sheet
ADV7182
TIMING SPECIFICATIONS
Guaranteed by characterization. AVDD, DVDD, and PVDD = 1.71 V to 1.89 V; DVDDIO = 1.71 V to 3.46 V, specified at operating temperature
range, unless otherwise noted.
Table 4.
Parameter
Symbol Test Conditions/Comments
Min
Typ
Max
Unit
SYSTEM CLOCK AND CRYSTAL
Nominal Frequency
Frequency Stability
I2C PORT
SCLK Frequency
28.63636
MHz
ppm
±±5
455
kHz
μs
μs
μs
μs
ns
ns
ns
μs
SCLK Minimum Pulse Width High
SCLK Minimum Pulse Width Low
Hold Time (Start Condition)
Setup Time (Start Condition)
SDATA Setup Time
SCLK and SDATA Rise Times
SCLK and SDATA Fall Times
Setup Time for Stop Condition
RESET FEATURE
t1
t2
t3
t4
t±
t6
t7
t8
5.6
1.3
5.6
5.6
155
355
355
5.6
RESET Pulse Width
±
ms
CLOCK OUTPUTS
LLC Mark Space Ratio
t9:t15
4±:±±
±±:4± % duty cycle
DATA AND CONTROL OUTPUTS
Data Output Transitional Time
t11
t12
Negative clock edge to start of valid data
(tACCESS = t15 − t11)
End of valid data to negative clock edge
(tHOLD = t9 + t12)
3.8
6.9
ns
ns
Timing Diagrams
t5
t3
t3
SDATA
SCLK
t1
t6
t4
t7
t8
t2
Figure 2. I2C Timing
t9
t10
OUTPUT LLC
t11
t12
OUTPUTS P0 TO P7, HS,
VS/FIELD/SFL
Figure 3. Pixel Port and Control Output Timing
Rev. A | Page 7 of 96
ADV7182
Data Sheet
ANALOG SPECIFICATIONS
Guaranteed by characterization. AVDD, DVDD, and PVDD = 1.71 V to 1.89 V; DVDDIO = 1.71 V to 3.46 V, specified at operating temperature
range, unless otherwise noted.
Table 5.
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
CLAMP CIRCUITRY
External Clamp Capacitor
Input Impedance
Large Clamp Source Current
Large Clamp Sink Current
Fine Clamp Source Current
Fine Clamp Sink Current
0.1
10
0.32
0.32
7
µF
Clamps switched off
MΩ
mA
mA
µA
7
µA
THERMAL SPECIFICATIONS
Table 6.
Parameter
Symbol Test Conditions/Comments
Min Typ Max Unit
THERMAL CHARACTERISTICS
Junction-to-Ambient Thermal Resistance (Still Air)
θJA
θJC
4-layer printed circuit board (PCB) with
solid ground plane, 32-lead LFCSP
4-layer PCB with solid ground plane,
32-lead LFCSP
32.5
2.3
°C/W
°C/W
Junction-to-Case Thermal Resistance
Rev. A | Page 8 of 96
Data Sheet
ADV7182
ABSOLUTE MAXIMUM RATINGS
This device is a high performance integrated circuit with an
ESD rating of <2 kV, and it is ESD sensitive. Proper precautions
should be taken for handling and assembly.
Table 7.
Parameter
Rating
AVDD to AGND
DVDD to DGND
2.2 V
2.2 V
ESD CAUTION
PVDD to AGND
2.2 V
DVDDIO to DGND
DVDDIO to AVDD
PVDD to DVDD
DVDDIO to PVDD
DVDDIO to DVDD
AVDD to PVDD
4 V
−0.3 V to +4 V
−0.3 V to +0.9 V
–0.3 V to +4 V
−0.3 V to +4 V
−0.3 V to +0.3 V
−0.3 V to +0.9 V
DGND − 0.3 V to DVDDIO + 0.3 V
DGND − 0.3 V to DVDDIO + 0.3 V
AGND − 0.3 V to AVDD + 0.3 V
140°C
AVDD to DVDD
Digital Inputs Voltage
Digital Outputs Voltage
Analog Inputs to AGND
Maximum Junction
Temperature (TJ max)
Storage Temperature Range
Infrared Reflow Soldering
(20 sec)
−65°C to +150°C
260°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev. A | Page 9 of 96
ADV7182
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
DGND 1
24 INTRQ
2
23
A
22 A
21 AVDD
DVDDIO
4
3
IN
DVDD 3
DGND 4
IN
ADV7182
TOP VIEW
5
6
20
19
P7
P6
VREFN
VREFP
(Not to Scale)
P5 7
P4 8
18 A
17 A
2
1
IN
IN
NOTES
1. THE EXPOSED PAD MUST BE CONNECTED TO DGND.
Figure 4. Pin Configuration
Table 8. Pin Function Descriptions
Pin No.
Mnemonic
Type Description
1, 4
2
3, 13
5 to 12
14
DGND
DVDDIO
DVDD
P7 to P0
XTALP
G
P
P
O
O
Ground for Digital Supply.
Digital I/O Supply Voltage (1.8 V to 3.3 V).
Digital Supply Voltage (1.8 V).
Video Pixel Output Port.
This pin should be connected to the 28.6363 MHz crystal or not connected if an external
1.8 V, 28.6363 MHz clock oscillator source is used to clock the ADV7182. In crystal mode, the
crystal must be a fundamental crystal.
15
XTALN
I
Input Pin for the 28.6363 MHz Crystal. This pin can be overdriven by an external 1.8 V,
28.6363 MHz clock oscillator source. In crystal mode, the crystal must be a fundamental crystal.
16
PVDD
P
I
PLL Supply Voltage (1.8 V).
17, 18, 22, 23
AIN1 to AIN4
Analog Video Input Channels.
19
20
21
24
25
VREFP
VREFN
AVDD
INTRQ
RESET
O
O
P
O
I
Internal Voltage Reference Output.
Internal Voltage Reference Output.
Analog Supply Voltage (1.8 V).
Interrupt Request Output. Interrupt occurs when certain signals are detected on the input video.
System Reset Input. Active low. A minimum low reset pulse width of 5 ms is required to
reset the ADV7182 circuitry.
26
ALSB
I
This pin selects the I2C address for the ADV7182. For ALSB set to Logic 0, the address
selected for a write is 0x40; for ALSB set to Logic 1, the address selected is 0x42.
27
28
SDATA
SCLK
I/O
I
I2C Port Serial Data Input/Output Pin.
I2C Port Serial Clock Input. The maximum clock rate is 400 kHz.
29
VS/FIELD/SFL
O
Vertical Synchronization Output Signal/Field Synchronization Output Signal/Subcarrier
Frequency Lock. This pin contains a serial output stream that can be used to lock the subcarrier
frequency when this decoder is connected to any Analog Devices digital video encoder.
30
31
32
HS
PWRDWN
LLC
O
I
Horizontal Synchronization Output Signal.
A logic low on this pin places the ADV7182 is in power-down mode.
O
Line-Locked Output Clock for Output Pixel Data. Nominally 27 MHz but varies up or down
according to the video line length.
EPAD (EP)
The exposed pad must be connected to DGND.
Rev. A | Page 10 of 96
Data Sheet
ADV7182
POWER SUPPLY SEQUENCING
POWER-UP SEQUENCE
POWER-ON RESET
After power-up, it is necessary to execute a reset operation. For
RESET
The recommended power-up sequence of the ADV7182 is
correct operation,
for 5 ms after power supplies are stable and within specification,
PWRDWN
should remain asserted (pulled low)
1. 3.3 V supply (DVDDIO)
2. 1.8 V supplies (DVDD, PVDD, AVDD)
and
is deasserted (pulled high).
Note the following:
POWER-DOWN SEQUENCE
Power up the DVDDIO supply first. This is true regardless
if DVDDIO is powered up to 3.3 V or 1.8 V.
Power up the 1.8 V supplies only after DVDDIO has been
fully asserted.
The ADV7182 supplies can be deasserted simultaneously as long
as DVDDIO does not go below a lower rated supply.
UNIVERSAL POWER SUPPLY
PWRDWN
RESET
pins while the
Assert (pull low) the
and
It is possible to power all the supplies (DVDD, PVDD, AVDD,
and DVDDIO) to 1.8 V.
supplies are being powered up. A 5 ms reset operation is
RESET
needed after power-up. See the Power-On
for further details.
After all the power supplies and the
section
In this setup, note the following:
Follow the power-up sequence described in the Power
Supply Sequencing section. Power up the DVDDIO supply
PWRDWN
and
RESET
pins are powered-up and stable, a further 5 ms
PWRDWN
to 1.8 V instead of 3.3 V. Also, power up the
RESET
delay is needed before I2C communication can be
performed with the ADV7182.
and
pins to 1.8 V instead of 3.3 V.
Set the drive strengths of the digital outputs of the
ADV7182 to their maximum setting. See the Global Pin
Control section.
Connect any pull-up resistors connected to pins on the
ADV7182 (such as the SCLK and SDATA pins) to 1.8 V
and not 3.3 V.
During power-up, all supplies must adhere to the
specifications listed in the Absolute Maximum Ratings
section.
The ADV7182 can be alternatively powered up by asserting all
supplies simultaneously. In this case, care must be taken to
ensure that a lower rated supply does not go above a higher
rated supply level as the supplies are being established.
3.3V
3.3V SUPPLIES
PWRDWN PIN
RESET PIN
1.8V
1.8V SUPPLIES
PWRDWN PIN
POWER-UP
RESET PIN
POWER-UP
3.3V SUPPLIES 1.8V SUPPLIES
POWER-UP POWER-UP
TIME
5ms
RESET
OPERATION
Figure 5. Recommended Power-Up Sequence
Rev. A | Page 11 of 96
ADV7182
Data Sheet
INPUT NETWORKS
This section describes the input networks (external resistor and
capacitor circuits) that should be placed on the analog video
input (AIN) pins of the ADV7182. Different input networks are
required for different analog input video formats.
DIFFERENTIAL INPUT NETWORK
Use the input network described in Figure 7 when differential
CVBS video is input on the AIN input pins of the ADV7182.
INPUT
CONNECTOR
100nF
1.3kΩ
SINGLE-ENDED INPUT NETWORK
A
1 OF ADV7182
IN
Use the input network described in Figure 6 on each AIN input
pin of the ADV7182 when any of the following video input
formats are used: single-ended CVBS, YC (S-Video), or YPrPb.
430Ω
EXT
ESD
VIDEO INPUT
FROM UNIT
75Ω
430Ω
100nF
INPUT
CONNECTOR
1.3kΩ
100nF
24Ω
A
2 OF ADV7182
IN
VIDEO INPUT
FROM UNIT
EXT
ESD
A
3 OF ADV7182
IN
INPUT
CONNECTOR
51Ω
Figure 7. Input Differential Network
Figure 6. Input Single-Ended Network
Differential video transmission involves transmitting two
complementary CVBS signals. It has several key advantages
over single-ended transmission, some of which include the
following:
The 24 Ω and 51 Ω resistors supply the 75 Ω end termination
required for the analog video input. In addition, these resistors
create a resistor divider with a 0.68 gain that attenuates the
amplitude of the inputted analog video and scales the input to the
ADC range of the ADV7182. This allows the ADV7182 to have
an input range of up to 1.47 V p-p.
•
•
•
Inherent small signal and large signal noise rejection
Improved EMI performance
Ability to absorb ground bounce
Note that amplifiers within the ADV7182 restore the amplitude
of the input signal so that signal-to-noise (SNR) performance is
maintained.
The 75 Ω resistor supplies the end termination required for the
analog video input. Note that, if a 150 Ω termination is required,
the 75 Ω resistor can be replaced with a 150 Ω resistor.
The 100 nF ac coupling capacitor removes the dc bias of the analog
input video before it is fed into the analog input pins of the
ADV7182.
The 1.3 kΩ and 430 Ω resistors provide a resistor divider with a
0.25 gain. This results in an attenuation of the inputted analog
video but also an increase in the input common-mode range of
the ADV7182 of up to 4 V p-p.
The clamping circuitry within the ADV7182 restores the dc bias
of the input signal to the optimal level before it is fed into the
ADC of the ADV7182. See the Clamp Operation section for
more information.
Note that amplifiers within the ADV7182 restore the amplitude
of the input signal so that SNR performance is maintained.
The 100 nF ac coupling capacitor removes the dc bias of the
analog input video before it is fed into the analog video input
pins of the ADV7182.
The clamping circuitry within the ADV7182 restores the dc bias of
the optimized level before it is fed into the ADC of the ADV7182.
See the Clamp Operation section for further information.
The combination of the 1.3 kΩ and 430 Ω resistors and the 100 nF
ac coupling capacitor limits current flow into the ADV7182
during short-to-battery (STB) events.
To achieve optimal performance, closely match the 1.3 kΩ and
430 Ω resistors; that is, all the 1.3 kΩ and 430 Ω resistors should
have the same resistance tolerance, and this tolerance should be
as low as possible.
Rev. A | Page 12 of 96
Data Sheet
ADV7182
ANALOG FRONT END
MAN_MUX_EN
INSEL[4:0], Input Control, Address 0x00[4:0]
The INSEL bits allow the user to select the input format. They also
configure the standard definition processor core to process CVBS,
differential CVBS, S-Video (Y/C), or component (YPrPb) format.
A
A
A
A
1
IN
2
MUX_0[3:0]
MUX_1[3:0]
IN
IN
IN
3
4
INSEL[4:0] has predefined analog input routing schemes that
do not require manual mux programming (see Table 9). This
allows the user to route the various video signal types to the
decoder and select them using INSEL[4:0] only. The added
benefit is that if, for example, the CVBS input is selected, the
remaining channels are powered down.
A
A
2
4
IN
IN
ADC
A
A
2
3
IN
IN
Table 9. INSEL[4:0]
MUX_2[3:0]
INSEL[4:0]
Video Format
Analog Input
00000
00001
00010
00011
CVBS
CVBS
CVBS
CVBS
CVBS input on AIN1
CVBS input on AIN2
CVBS input on AIN3
CVBS input on AIN4
Y input on AIN1
C input on AIN2
Y input on AIN3
C input on AIN4
Y input on AIN1
Pb input on AIN2
Pr input on AIN3
Positive on AIN1
Negative on AIN2
Positive on AIN3
Negative on AIN4
A
A
2
4
IN
IN
MUX_3[3:0]
01000
Y/C (S-Video)
Figure 8. Manual Muxing
01001
01100
Y/C (S-Video)
YPrPb
INPUT CONFIGURATION
The following two steps are key for configuring the ADV7182 to
correctly decode the input video.
1. Use INSEL[4:0] to configure the routing and format decoding
(CVBS, Y/C, or YPrPb).
01110
01111
Differential CVBS
Differential CVBS
2. If the input requirements are not met using the INSEL[4:0]
options, the analog input muxing section must be configured
manually to correctly route the video from the analog
input pins to the ADC. The standard definition processor
block, which decodes the digital data, should be configured
to process the CVBS, Y/C, or YPrPb format. This is performed
by INSEL[4:0] selection.
ANALOG INPUT MUXING
The ADV7182 has an integrated analog muxing section that
allows more than one source of video signal to be connected to
the decoder.
A maximum of four CVBS inputs can be connected to and
decoded by the ADV7182. As shown in the Pin Configuration and
Function Description section, these analog input pins lie in close
proximity to one another, which requires careful design of the PCB
layout. For example, route ground shielding between all signals
through tracks that are physically close together. It is strongly
recommended that any unused analog input pins be connected
to AGND to act as a shield.
Rev. A | Page 13 of 96
ADV7182
Data Sheet
MAN_MUX_EN, Manual Input Muxing Enable,
Address 0xC4[7]
The four mux sections are controlled by the signal buses,
MUX0/MUX1/MUX2/MUX3[2:0]. Table 10 explains the
control words used.
To configure the ADV7182 analog muxing section, the user
must select the analog input AIN1 to AIN8 that is to be processed
by the ADC. MAN_MUX_EN must be set to 1 to enable the
following muxing blocks:
The input signal that contains the timing information (HS and VS)
must be processed by MUX0. For example, in a Y/C input
configuration, connect MUX0 to the Y channel and MUX1 to
the C channel. When one or more muxes are not used to process
video, such as the CVBS input, the idle mux and associated channel
clamps and buffers should be powered down (see the description
of Register 0x3A in Table 95).
•
•
•
•
MUX0[2:0], ADC mux configuration, Address 0xC3[2:0]
MUX1[2:0], ADC mux configuration, Address 0xC3[6:4]
MUX2[2:0], ADC mux configuration, Address 0xC4[2:0]
MUX3[2:0], ADC mux configuration, Address 0x60[2:0]
Table 10. Manual Mux Settings for ADC (MAN_MUX_EN Must be Set to 1)
MUX0[2:0] ADC Connected To MUX1[2:0] ADC Connected To MUX2[2:0] ADC Connected To MUX3[2:0] ADC Connected To
000
001
010
011
100
No connect
AIN1
AIN2
AIN3
AIN4
000
001
010
011
100
No connect
No connect
AIN2
No connect
AIN4
000
001
010
011
100
No connect
No connect
AIN2
AIN3
No connect
000
001
010
011
100
No connect
No connect
AIN2
No connect
AIN4
Notes:
•
•
•
•
CVBS can only be processed by MUX0.
Differential CVBS can only be processed by MUX0 (positive channel) and MUX3 (negative channel).
Y/C can only be processed by MUX0 and MUX1.
YPrPb can only be processed by MUX0, MUX1, and MUX2.
Rev. A | Page 14 of 96
Data Sheet
ADV7182
AA_FILT_EN[2], Antialiasing Filter Enable,
Address 0xF3[2]
ANTIALIASING FILTERS
The ADV7182 has optional on-chip antialiasing (AA) filters on
each of the four channels that are multiplexed to the ADC (see
Figure 9). The filters are designed for standard definition video
up to 10 MHz bandwidth. Figure 10 and Figure 11 show the filter
magnitude and phase characteristics.
When AA_FILT_EN[2] is 0, AA Filter 3 is disabled.
When AA_FILT_EN[2] is 1, AA Filter 3 is enabled.
AA_FILT_EN[3], Antialiasing Filter Enable,
Address 0xF3[3]
The antialiasing filters are enabled by default and the selection
of INSEL[4:0] determines which filters are powered up at any
given time. For example, if CVBS mode is selected, the filter
circuits for the remaining input channels are powered down to
conserve power. However, the antialiasing filters can be disabled
or bypassed using the AA_FILT_MAN_OVR control.
When AA_FILT_EN[3] is 0, AA Filter 4 is disabled.
When AA_FILT_EN[3] is 1, AA Filter 4 is enabled.
0
–4
–8
10-BIT, 86MHz
–12
–16
–20
–24
–28
–32
–36
ADC
AA
A
A
A
A
1
2
3
4
IN
IN
IN
IN
FILTER 1
AA
FILTER 2
+
SHA
ADC
AA
FILTER 3
–
AA
FILTER 4
Figure 9. Antialias Filter Configuration
AA_FILT_MAN_OVR, Antialiasing Filter Override,
Address 0xF3[4]
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
This feature allows the user to override the antialiasing filters
on/off settings, which are automatically selected by INSEL[4:0].
Figure 10. Antialiasing Filter Magnitude Response
0
–10
–20
AA_FILT_EN[3:0], Antialiasing Filter Enable,
Address 0xF3[3:0]
–30
–40
These bits allow the user to enable or disable the antialiasing
filters on each of the three input channels multiplexed to the
ADC. When disabled, the analog signal bypasses the AA filters
and is routed directly to the ADC.
–50
–60
–70
–80
–90
AA_FILT_EN[0], Antialiasing Filter Enable,
Address 0xF3[0]
–100
–110
–120
–130
–140
–150
When AA_FILT_EN[0] is 0, AA Filter 1 is disabled.
When AA_FILT_EN[0] is 1, AA Filter 1 is enabled.
1k
10k
100k
1M
10M
100M
AA_FILT_EN[1], Antialiasing Filter Enable,
Address 0xF3[1]
FREQUENCY (Hz)
Figure 11. Antialiasing Filter Phase Response
When AA_FILT_EN[1] is 0, AA Filter 2 is disabled.
When AA_FILT_EN[1] is 1, AA Filter 2 is enabled.
Rev. A | Page 15 of 96
ADV7182
Data Sheet
GLOBAL CONTROL REGISTERS
Register control bits listed in this section affect the whole chip.
GLOBAL PIN CONTROL
Tristate Output Drivers
TOD, Address 0x03[6]
POWER-SAVING MODES
Power-Down
This bit allows the user to tristate the output drivers of the ADV7182.
PWRDWN, Address 0x0F[5]
Upon setting the TOD bit, the P7 to P0, HS, and VS/FIELD/SFL
pins are tristated.
The ADV7182 can be placed into a chip-wide, power-down mode
PWRDWN
by setting the PWRDWN bit or by using the
pin.
The power-down mode stops the clock from entering the digital
section of the chip, thereby freezing its operation. No I2C bits are
lost during power-down mode. The PWRDWN bit also affects
the analog blocks and switches them into low current modes.
The I2C interface is unaffected and remains operational in
power-down mode.
The timing pins (HS and VS/FIELD/SFL pins) can be forced active
via the TIM_OE bit. For more information on tristate control, see the
Tristate LLC Driver and the Timing Signals Output Enable sections.
Individual drive strength controls are provided via the
DR_STR_x bits.
When TOD is 0 (default), the output drivers are enabled.
When TOD is 1, the output drivers are tristated.
Tristate LLC Driver
When PWRDWN is 0, the chip is operational. When PWRDWN is
1 (default), the ADV7182 is in a chip-wide, power-down mode.
RESET CONTROL
Reset, Chip Reset, Address 0x0F[7]
TRI_LLC, Address 0x1D[7]
This bit allows the output drivers for the LLC pin of the ADV7182
to be tristated. For more information on tristate control, refer to the
Tristate Output Drivers and Timing Signals Output Enable sections.
RESET
Setting this bit, which is equivalent to controlling the
pin on the ADV7182, issues a full chip reset. All I2C registers are
reset to their default/power-up values. Note that some register bits
do not have a reset value specified. They keep their last written
value. Those bits are marked as having a reset value of x in the
register tables (see Table 95 and Table 97). After the reset
sequence, the part immediately starts to acquire the incoming
video signal.
Individual drive strength controls are provided via the
DR_STR_x bits.
When TRI_LLC is 0 (default), the LLC pin drivers work according
to the DR_STR_C[1:0] setting (pin enabled).
When TRI_LLC is 1, the LLC pin drivers are tristated.
Timing Signals Output Enable
RESET
After setting the reset bit (or initiating a reset via the
pin),
the part returns to the default for its primary mode of operation.
All I2C bits are loaded with their default values, making this bit
self-clearing. Executing a software reset takes approximately 2 ms.
However, it is recommended to wait 5 ms before any further I2C
writes are performed.
The I2C master controller receives a no acknowledge condition
on the ninth clock cycle when chip reset is implemented (see
the MPU Port Description section).
TIM_OE, Address 0x04[3]
The TIM_OE bit should be regarded as an addition to the TOD bit.
Setting it high forces the output drivers for HS, VS/FIELD/SFL into
the active state (that is, driving state) even if the TOD bit is set. If
TIM_OE is set to low, the HS and VS/FIELD/SFL pins are tristated
depending on the TOD bit. This functionality is beneficial if the
decoder is used only as a timing generator. This may be the case
if only the timing signals are extracted from an incoming signal or
if the part is in free-run mode, where a separate chip can output
a company logo, for example.
When the reset bit is 0 (default), operation is normal.
When the reset bit is 1, the reset sequence starts.
For more information on tristate control, see the Tristate
Output Drivers and Tristate LLC Driver sections.
Individual drive strength controls are provided via the
DR_STR_x bits.
When TIM_OE is 0 (default), HS and VS/FIELD/SFL are tristated
according to the TOD bit.
When TIM_OE is 1, HS and VS/FIELD/SFL are forced active all
the time.
Rev. A | Page 16 of 96
Data Sheet
ADV7182
Table 13. DR_STR Function
VS/FIELD/SFL Sync Mux Selection
DR_STR[1:0]
Description
FLD_OUT_SEL[2:0], Address 0x6B[2:0]
00
Low drive strength (1×)
The FLD_OUT_SEL[2:0] bits select whether the VS/FIELD/SFL
pin outputs vertical sync, horizontal sync, field sync, data
enable (DE), or subcarrier frequency lock (SFL) signals.
01 (default)
10
11
Medium low drive strength (2×)
Medium high drive strength (3×)
High drive strength (4×)
Note that the VS/FIELD/SFL pin must be active for this selection
to occur. See the Tristate Output Drivers and Tristate LLC
Driver sections.
Drive Strength Selection (Clock)
DR_STR_C[1:0], Address 0xF4[3:2]
The DR_STR_C[1:0] bits can be used to select the strength of
the clock signal output driver (LLC pin). For more information,
see the Drive Strength Selection (Data) Section.
Table 11. FLD_OUT_SEL Function
FLD_OUT_SEL[2:0] Description
000
The VS/FIELD/SFL pin outputs horizontal
sync information.
Table 14. DR_STR_C Function
001
The VS/FIELD/SFL pin outputs vertical sync
information.
DR_STR_C[1:0]
Description
00
Low drive strength (1×)
Medium low drive strength (2×)
Medium high drive strength (3×)
High drive strength (4×)
010 (default)
011
The VS/FIELD/SFL pin outputs field sync
information.
The VS/FIELD/SFL pin outputs data enable
(DE) information.
01 (default)
10
11
100
The VS/FIELD/SFL pin outputs subcarrier
frequency lock information.
Drive Strength Selection (I2C)
DR_STR_S[1:0], Address 0xF4[1:0]
HS Sync Mux Selection
The DR_STR_S[1:0] bits allow the user to select the strength of
the I2C signal output drivers. This affects the drive strength for
the SDA and SCL pins.
HS_OUT_SEL[2:0], Address 0x6A[2:0]
The HS_OUT_SEL[2:0] bits allow the user to change the operation
of the HS pin. The HS pin is set to output horizontal sync signals as
the default. The user can also set the HS pin to output vertical
sync, field sync, data enable (DE), or subcarrier frequency lock
(SFL) information.
Table 15. DR_STR_S Function
DR_STR_S[1:0]
Description
00
Low drive strength (1×)
Medium low drive strength (2×)
Medium high drive strength (3×)
High drive strength (4×)
01 (default)
10
11
Note that the HS pin must be active for this selection to occur.
See the Tristate Output Drivers and Tristate LLC Driver sections.
Table 12. HS_OUT_SEL Function
HS_OUT_SEL[2:0] Description
Enable Subcarrier Frequency Lock Pin
EN_SFL_PIN, Address 0x04[1]
000 (default)
The HS pin output horizontal sync
information.
The HS pin outputs vertical sync information.
The HS pin outputs field sync information.
The HS pin outputs data enable (DE)
information.
The HS pin outputs subcarrier frequency
lock (SFL) information.
The EN_SFL_PIN bit enables the output of subcarrier lock
information (also known as genlock) from the ADV7182 core
to an encoder in a decoder/encoder back-to-back arrangement.
001
010
011
When the EN_SFL_PIN is 0 (default), the subcarrier frequency
lock output is disabled.
100
When EN_SFL_PIN is 1, the subcarrier frequency lock information
is presented on the SFL pin.
Drive Strength Selection (Data)
DR_STR[1:0], Address 0xF4[5:4]
Polarity LLC Pin
PCLK, Address 0x37[0]
For EMC and crosstalk reasons, it may be desirable to strengthen or
weaken the drive strength of the output drivers. The DR_STR[1:0]
bits affect the drive strength for the pixel output pins (P[7:0])
and the timing pins (HS and VS/FIELD/SFL).
The polarity of the clock that leaves the ADV7182 via the LLC
pin can be inverted using the PCLK bit. Changing the polarity of
the LLC clock output may be necessary to meet the setup-and-hold
time expectations of follow-on chips. When PCLK is 0, the LLC
output polarity is inverted. When PCLK is 1 (default), the LLC
output polarity is normal (see the Timing Specifications section).
For more information on tristate control, see the Tristate
Output Drivers and Tristate LLC Driver sections.
Rev. A | Page 17 of 96
ADV7182
Data Sheet
GLOBAL STATUS REGISTER
Four registers provide summary information about the video
decoder. The IDENT register allows the user to identify the
revision code of the ADV7182. The other three registers
(Address 0x10, Address 0x12, and Address 0x13) contain
status bits from the ADV7182.
STATUS 2
Status 2[7:0], Address 0x12[7:0]
Table 18. Status 2 Function
Status 2[7:0] Bit Name
Description
Detected Macrovision color
0
MVCS DET
striping
IDENTIFICATION
IDENT[7:0], Address 0x11[7:0]
1
MVCS T3
Macrovision color striping
protection; conforms to Type 3
if high, Type 2 if low
Detected Macrovision pseudo-
sync pulses
This is the register identification of the ADV7182 revision. Table 16
describes the various versions of the ADV7182.
2
MV PS DET
Table 16. IDENT CODE
3
4
5
6
7
MV AGC DET
LL NSTD
FSC NSTD
Reserved
Reserved
Detected Macrovision AGC pulses
Line length is nonstandard
fSC frequency is nonstandard
IDENT[7:0]
Description
0x40
0x41
Initial release silicon
1st revision of silicon
STATUS 1
Status 1[7:0], Address 0x10[7:0]
STATUS 3
Status 3[7:0], Address 0x13[7:0]
Table 19. Status 3 Function
This read-only register provides information about the internal
status of the ADV7182.
Status 3[7:0] Bit Name
Description
Horizontal lock indicator
(instantaneous)
See the CIL[2:0], Count into Lock, Address 0x51[2:0] section
and the COL[2:0], Count out of Lock, Address 0x51[5:3] section
for details on timing.
0
INST_HLOCK
1
2
Reserved
SD_OP_50Hz
Depending on the setting of the FSCLE bit, the status registers are
based solely on horizontal timing information or on the horizontal
timing and lock status of the color subcarrier. See the FSCLE,
fSC Lock Enable, Address 0x51[7] section.
Flags whether 50 Hz or 60 Hz is
present at output
Reserved
3
4
Reserved
FREE_RUN_ACT Flags if ADV7182 has entered
free-run mode (see Free-Run
Table 17. Status 1 Function
Operation section)
Status 1[7:0] Bit Name
Description
5
STD FLD LEN
Field length is correct for
currently selected video
standard
Interlaced video detected
(field sequence found)
0
1
2
3
4
5
6
7
IN_LOCK
In lock (now)
Lost lock (since last read)
fSC locked (now)
LOST_LOCK
FSC_LOCK
FOLLOW_PW
AD_RESULT[0] Result of autodetection
AD_RESULT[1] Result of autodetection
AD_RESULT[2] Result of autodetection
6
7
Interlaced
AGC follows peak white algorithm
PAL_SW_LOCK
Reliable sequence of
swinging bursts detected
AUTODETECTION RESULT
AD_RESULT[2:0], Address 0x10[6:4]
COL_KILL
Color kill active
The AD_RESULT[2:0] bits report back on the findings from the
ADV7182 autodetection block. See the General Setup section for
more information on enabling the autodetection block and the
Autodetection of SD Modes section for more information on
how to configure it.
Table 20. AD_RESULT Function
AD_RESULT[2:0]
Description
NTSC M/NTSC J
NTSC 4.43
PAL M
PAL 60
PAL B/PAL G/PAL H/PAL I/PAL D
SECAM
PAL Combination N
SECAM 525
000
001
010
011
100
101
110
111
Rev. A | Page 18 of 96
Data Sheet
ADV7182
VIDEO PROCESSOR
STANDARD DEFINITION PROCESSOR
MACROVISION
DETECTION
STANDARD
AUTODETECTION
SLLC
CONTROL
VBI DATA
RECOVERY
DIGITIZED CVBS
DIGITIZED Y (YC)
LUMA
DIGITAL
FINE
LUMA
GAIN
CONTROL
LUMA
FILTER
LUMA
RESAMPLE
LUMA
2D COMB
CLAMP
LINE
AV
SYNC
EXTRACT
RESAMPLE
CONTROL
VIDEO DATA
OUTPUT
LENGTH
CODE
ACE
DITHER
PREDICTOR
INSERTION
DIGITIZED CVBS
DIGITIZED C (YC)
CHROMA
DIGITAL
FINE
CHROMA
GAIN
CONTROL
MEASUREMENT
BLOCK (≥ I C)
CHROMA
DEMOD
CHROMA
FILTER
CHROMA
RESAMPLE
CHROMA
2D COMB
2
CLAMP
VIDEO DATA
PROCESSING
BLOCK
f
SC
RECOVERY
Figure 12. Block Diagram of Video Processor
Figure 12 shows a block diagram of the ADV7182 video processor.
The ADV7182 can handle standard definition video in CVBS,
Y/C, and YPrPb formats. It can be divided into a luminance and
chrominance path. If the input video is of a composite type
(CVBS), both processing paths are fed with the CVBS input.
SD CHROMA PATH
The input signal is processed by the following blocks:
•
Chroma digital fine clamp. This block uses a high precision
algorithm to clamp the video signal.
•
Chroma demodulation. This block employs a color subcarrier
(fSC) recovery unit to regenerate the color subcarrier for
any modulated chroma scheme. The demodulation block
then performs an AM demodulation for PAL and NTSC,
and an FM demodulation for SECAM.
SD LUMA PATH
The input signal is processed by the following blocks:
•
Luma digital fine clamp. This block uses a high precision
algorithm to clamp the video signal.
•
•
Chroma filter. This block contains a chroma decimation filter
(CAA) with a fixed response and some shaping filters (CSH)
that have selectable responses.
•
Luma filter. This block contains a luma decimation filter
(YAA) with a fixed response and some shaping filters
(YSH) that have selectable responses.
Chroma gain control. AGC can operate on several different
modes, including gain based on the color subcarrier
amplitude, gain based on the depth of the horizontal sync
pulse on the luma channel, or fixed manual gain.
Chroma resample. The chroma data is digitally resampled
to keep it perfectly aligned with the luma data. The
resampling is done to correct for static and dynamic line
length errors of the incoming video signal.
•
•
Luma gain control. The AGC can operate on a variety of
different modes, including gain based on the depth of the
horizontal sync pulse, peak white mode, and fixed manual
gain.
Luma resample. To correct for line length errors as well as
dynamic line length changes, the data is digitally resampled.
Luma 2D comb. The 2D comb filter provides Y/C separation.
AV code insertion. At this point, the decoded luma (Y) signal
is merged with the retrieved chroma values. AV codes can
be inserted (as per ITU-R BT.656).
•
•
•
•
•
Chroma 2D comb. The 2D, five line, superadaptive comb
filter provides high quality Y/C separation in case the input
signal is CVBS.
AV code insertion. At this point, the demodulated chroma
(Cr and Cb) signal is merged with the retrieved luma values.
AV codes can be inserted (as per ITU-R BT.656).
Rev. A | Page 19 of 96
ADV7182
Data Sheet
ACE AND DITHER PROCESSING BLOCKS
GENERAL SETUP
Video Standard Selection
•
ACE. This block offers improved visual detail by using an
algorithm to automatically vary the contrast levels to enhance
picture detail. See the Adaptive Contrast Enhancement
section.
Dither. When enabled, this block converts the digital output
of the ADV7182 from 8-bit pixel data down to 6-bit pixel
data. This function makes it easier for the ADV7182 to
communicate with some LCD panels. See the Dither
Function section.
The VID_SEL[3:0] bits (Address 0x02[7:4]) allow the user to
force the digital core into a specific video standard. This is not
necessary under normal circumstances. The VID_SEL[3:0] bits
default to an autodetection mode that supports PAL, NTSC,
SECAM, and variants thereof.
•
Autodetection of SD Modes
To guide the autodetect system of the ADV7182, individual
enable bits are provided for each of the supported video standards.
Setting the relevant bit to 0 inhibits the standard from being
detected automatically. Instead, the system chooses the closest of
the remaining enabled standards. The results of the autodetection
block can be read back via the status registers (see the Global
Status Register section for more information).
SYNC PROCESSING
The ADV7182 extracts syncs embedded in the analog input
video signal. There is currently no support for external HS/VS
inputs. The sync extraction is optimized to support imperfect
video sources, such as VCRs with head switches. The actual
algorithm used employs a coarse detection based on a threshold
crossing, followed by a more detailed detection using an adaptive
interpolation algorithm. The raw sync information is sent to a
line length measurement and prediction block. The output of
this is then used to drive the digital resampling section to
ensure that the ADV7182 outputs 720 active pixels per line.
VID_SEL[3:0], Address 0x02[7:4]
Table 21. VID_SEL Function
VID_SEL[3:0]
Description
0000 (default)
Autodetect PAL B/PAL G/PAL H/PAL I/PAL D,
NTSC J (no pedestal), SECAM
0001
0010
0011
Autodetect PAL B/PAL G/PAL H/PAL I/PAL D,
NTSC M (pedestal), SECAM
Autodetect PAL N (pedestal), NTSC J
(no pedestal), SECAM
Autodetect PAL N (pedestal), NTSC M
(pedestal), SECAM
The sync processing on the ADV7182 also includes the following
specialized postprocessing blocks that filter and condition the
raw sync information retrieved from the digitized analog video:
•
VSync processor. This block provides extra filtering of the
detected VSyncs to improve vertical lock.
HSync processor. The HSync processor is designed to filter
incoming HSyncs that were corrupted by noise, providing
much improved performance for video signals with a stable
time base but poor SNR.
0100
0101
0110
0111
1000
1001
NTSC J
NTSC M
PAL 60
NTSC 4.43
•
PAL B/PAL G/PAL H/PAL I/PAL D
PAL N = PAL B/PAL G/PAL H/PAL I/PAL D (with
pedestal)
VBI DATA RECOVERY
The ADV7182 can retrieve the following information from the
input video:
1010
1011
1100
1101
1110
1111
PAL M (without pedestal)
PAL M
PAL Combination N
PAL Combination N (with pedestal)
SECAM
•
•
•
•
•
Wide screen signaling (WSS)
Copy generation management system (CGMS)
Closed captioning (CCAP)
Macrovision protection presence
Teletext
SECAM
AD_SEC525_EN, SECAM 525 Autodetect Enable,
Address 0x07[7]
The ADV7182 is also capable of automatically detecting the
incoming video standard with respect to the following:
Setting AD_SEC525_EN to 0 (default) disables the autodetection
of a 525-line system with a SECAM style, FM-modulated color
component.
•
•
•
Color subcarrier frequency
Field rate
Line rate
Setting AD_SEC525_EN to 1 enables the detection of a SECAM
style, FM-modulated color component.
The ADV7182 can configure itself to support PAL B/PAL D/
PAL I/PAL G/PAL H, PAL M, PAL N, PAL Combination N,
NTSC M/NTSC J, SECAM 50 Hz/60 Hz, NTSC 4.43, and PAL 60.
Rev. A | Page 20 of 96
Data Sheet
ADV7182
AD_SECAM_EN, SECAM Autodetect Enable,
Address 0x07[6]
AD_PAL_EN, PAL B/PAL D/PAL I/PAL G/PAL H
Autodetect Enable, Address 0x07[0]
Setting AD_SECAM_EN to 0 (default) disables the autodetection
of SECAM.
Setting AD_PAL_EN to 0 (default) disables the detection of
standard PAL.
Setting AD_SECAM_EN to 1 enables the detection of SECAM.
Setting AD_PAL_EN to 1 enables the detection of standard PAL.
SFL_INV, Subcarrier Frequency Lock Inversion,
Address 0x41[6]
AD_N443_EN, NTSC 4.43 Autodetect Enable,
Address 0x07[5]
This bit controls the behavior of the PAL switch bit in the SFL
(genlock telegram) data stream. It was implemented to solve
some compatibility issues with video encoders. It solves two
problems.
Setting AD_N443_EN to 0 disables the autodetection of NTSC
style systems with a 4.43 MHz color subcarrier.
Setting AD_N443_EN to 1 (default) enables the detection of
NTSC style systems with a 4.43 MHz color subcarrier.
First, the PAL switch bit is meaningful only in PAL. Some encoders
(including Analog Devices encoders) also look at the state of
this bit in NTSC.
AD_P60_EN, PAL 60 Autodetect Enable, Address 0x07[4]
Setting AD_P60_EN to 0 disables the autodetection of PAL
systems with a 60 Hz field rate.
Second, there was a design change in Analog Devices encoders
from ADV717x to ADV719x. The older versions used the SFL
(genlock telegram) bit directly, whereas the newer ones invert
the bit prior to using it. The reason for this is that the inversion
compensated for the one line delay of an SFL (genlock telegram)
transmission.
Setting AD_P60_EN to 1 (default) enables the detection of PAL
systems with a 60 Hz field rate.
AD_PALN_EN, PAL N Autodetect Enable,
Address 0x07[3]
Setting AD_PALN_EN to 0 (default) disables the detection of
the PAL N standard.
As a result, for the ADV717x and ADV73xx encoders, the PAL
switch bit in the SFL (genlock telegram) must be set to 0 for NTSC
to work. For the older video encoders, the PAL switch bit in the
SFL must be set to 1 to work in NTSC. If the state of the PAL switch
bit is wrong, a 180° phase shift occurs.
Setting AD_PALN_EN to 1 enables the detection of the PAL N
standard.
AD_PALM_EN, PAL M Autodetect Enable,
Address 0x07[2]
In a decoder/encoder back-to-back system in which SFL is used,
this bit must be set up properly for the specific encoder used.
Setting AD_PALM_EN to 0 (default) disables the autodetection
of PAL M.
Setting SFL_INV to 0 (default) makes the part SFL compatible
with the ADV717x and ADV73xx video encoders.
Setting AD_PALM_EN to 1 enables the detection of PAL M.
Setting SFL_INV to 1 makes the part SFL compatible with the
older video encoders.
AD_NTSC_EN, NTSC Autodetect Enable,
Address 0x07[1]
Lock Related Controls
Setting AD_NTSC_EN to 0 (default) disables the detection of
standard NTSC.
Lock information is presented to the user through Bits[2:0] of the
Status 1 register (see the Status 1[7:0], Address 0x10[7:0] section).
Figure 13 outlines the signal flow and the controls that are available
to influence the way the lock status information is generated.
Setting AD_NTSC_EN to 1 enables the detection of standard NTSC.
SELECT THE RAW LOCK SIGNAL
SRLS
FILTER THE RAW LOCK SIGNAL
CIL[2:0], COL[2:0]
TIME_WIN
FREE_RUN
1
0
0
1
COUNTER INTO LOCK
COUNTER OUT OF LOCK
STATUS 1[0]
STATUS 1[1]
f
LOCK
SC
MEMORY
TAKE f LOCK INTO ACCOUNT
SC
FSCLE
Figure 13. Lock Related Signal Path
Rev. A | Page 21 of 96
ADV7182
Data Sheet
SRLS, Select Raw Lock Signal, Address 0x51[6]
COL[2:0], Count out of Lock, Address 0x51[5:3]
Using the SRLS bit, the user can choose between two sources for
determining the lock status (per Bits[1:0] in the Status 1 register).
See Figure 13.
COL[2:0] determines the number of consecutive lines for which
the out-of-lock condition must be true before the system switches
into the unlocked state and reports this via Status 1[1:0]. It counts
the value in lines of video.
•
The TIME_WIN signal is based on a line-to-line evaluation
of the horizontal synchronization pulse of the incoming
video. It reacts quite quickly.
Table 23. COL Function
COL[2:0]
Number of Video Lines
•
The FREE_RUN signal evaluates the properties of the
incoming video over several fields, taking vertical
synchronization information into account.
000
1
001
2
010
5
011
100 (default)
101
110
111
10
Setting SRLS to 0 (default) selects the FREE_RUN signal (that is,
evaluate over several fields).
100
500
1000
100,000
Setting SRLS to 1 selects the TIME_WIN signal (that is, evaluate on
a line-to-line basis) .
FSCLE, fSC Lock Enable, Address 0x51[7]
COLOR CONTROLS
The FSCLE bit allows the user to choose whether the status of
the color subcarrier loop is taken into account when the overall
lock status is determined and presented via Bits[1:0] in the
Status 1 register. This bit must be set to 0 when operating the
ADV7182 in YPrPb component mode to generate a reliable
HLOCK status bit.
These registers allow the user to control picture appearance,
including control of active data in the event of video being lost.
These controls are independent of any other controls. For instance,
brightness control is independent of picture clamping, although
both controls affect the dc level of the signal.
CON[7:0], Contrast Adjust, Address 0x08[7:0]
When FSCLE is 0 (default), the overall lock status is dependent
only on horizontal sync lock.
This register allows the user to control contrast adjustment of
the picture.
When FSCLE is 1, the overall lock status is dependent on
horizontal sync lock and fSC lock.
Table 24. CON Function
CIL[2:0], Count into Lock, Address 0x51[2:0]
CON[7:0]
0x80 (default)
0x00
Description
Gain on luma channel = 1
Gain on luma channel = 0
Gain on luma channel = 2
CIL[2:0] determines the number of consecutive lines for which
the lock condition must be true before the system switches into
the locked state and reports this via Status 1[1:0]. The bit counts
the value in lines of video.
0xFF
SD_SAT_Cb[7:0], SD Saturation Cb Channel,
Address 0xE3[7:0]
Table 22. CIL Function
CIL[2:0]
Number of Video Lines
This register allows the user to control the gain of the Cb channel
only, which in turn adjusts the saturation of the picture.
000
1
001
010
011
2
5
10
Table 25. SD_SAT_Cb Function
SD_SAT_Cb[7:0] Description
0x80 (default)
0x00
0xFF
Gain on Cb channel = 0 dB
Gain on Cb channel = −42 dB
Gain on Cb channel = +6 dB
100 (default)
101
110
100
500
1000
100,000
111
Rev. A | Page 22 of 96
Data Sheet
ADV7182
SD_SAT_Cr[7:0], SD Saturation Cr Channel,
Address 0xE4[7:0]
HUE[7:0], Hue Adjust, Address 0x0B[7:0]
This register contains the value for the color hue adjustment. It
allows the user to adjust the hue of the picture.
This register allows the user to control the gain of the Cr channel
only, which in turn adjusts the saturation of the picture.
HUE[7:0] has a range of 90°, with 0x00 equivalent to an
adjustment of 0°. The resolution of HUE[7:0] is 1 bit = 0.7°.
Table 26. SD_SAT_Cr Function
The hue adjustment value is fed into the AM color demodulation
block. Therefore, it applies only to video signals that contain
chroma information in the form of an AM-modulated carrier
(CVBS or Y/C in PAL or NTSC). It does not affect SECAM
and does not work on component video inputs (YPrPb).
SD_SAT_Cr[7:0] Description
0x80 (default)
0x00
0xFF
Gain on Cr channel = 0 dB
Gain on Cr channel = −42 dB
Gain on Cr channel = +6 dB
SD_OFF_Cb[7:0], SD Offset Cb Channel, Address 0xE1[7:0]
Table 30. HUE Function
This register allows the user to select an offset for the Cb channel
only and to adjust the hue of the picture. There is a functional
overlap with the HUE[7:0] register (Address 0X0B).
HUE[7:0]
0x00 (default)
0x7F
Description (Adjust Hue of the Picture)
Phase of the chroma signal = 0°
Phase of the chroma signal = −90°
Phase of the chroma signal = +90°
Table 27. SD_OFF_Cb Function
0x80
SD_OFF_Cb[7:0] Description
DEF_Y[5:0], Default Value Y, Address 0x0C[7:2]
0x80 (default)
0x00
0xFF
0 mV offset applied to the Cb channel
−312 mV offset applied to the Cb channel
+312 mV offset applied to the Cb channel
When the ADV7182 loses lock on the incoming video signal or
when there is no input signal, the DEF_Y[5:0] register allows
the user to specify a default luma value to be output. This value
is used under the following conditions:
SD_OFF_Cr[7:0], SD Offset Cr Channel, Address 0xE2[7:0]
This register allows the user to select an offset for the Cr channel
only and to adjust the hue of the picture. There is a functional
overlap with the HUE[7:0] register.
•
If the DEF_VAL_AUTO_EN bit is 1 and the ADV7182 has
lost lock to the input video signal, this is the intended
mode of operation (automatic mode).
•
If the DEF_VAL_EN bit is 1, regardless of the lock status of
the video decoder, this is a forced mode that may be useful
during configuration.
Table 28. SD_OFF_Cr Function
SD_OFF_Cr[7:0]
0x80 (default)
0x00
Description
0 mV offset applied to the Cr channel
−312 mV offset applied to the Cr channel
+312 mV offset applied to the Cr channel
The DEF_Y[5:0] values define the six MSBs of the output video.
The remaining LSBs are padded with 0s. For example, in 8-bit
mode, the output is Y[7:0] = {DEF_Y[5:0], 0, 0}.
0xFF
BRI[7:0], Brightness Adjust, Address 0x0A[7:0]
For DEF_Y[5:0], 0x0D (blue) is the default value for Y.
Register 0x0C has a default value of 0x36.
This register controls the brightness of the video signal. It allows
the user to adjust the brightness of the picture.
DEF_C[7:0], Default Value C, Address 0x0D[7:0]
Table 29. BRI Function
The DEF_C[7:0] register complements the DEF_Y[5:0] value. It
defines the four MSBs of Cr and Cb values to be output if:
BRI[7:0]
0x00 (default)
0x7F
Description
Offset of the luma channel = 0 IRE
Offset of the luma channel = +30 IRE
Offset of the luma channel = −30 IRE
•
The DEF_VAL_AUTO_EN bit is set to high and the
ADV7182 cannot lock to the input video (automatic mode).
The DEF_VAL_EN bit is set to high (forced output).
0x80
•
The data that is finally output from the ADV7182 for the chroma
side is Cr[4:0] = {DEF_C[7:4]} and Cb[4:0] = {DEF_C[3:0]}.
For DEF_C[7:0], 0x7C (blue) is the default value for Cr and Cb.
Rev. A | Page 23 of 96
ADV7182
Data Sheet
DEF_VAL_AUTO_EN, Default Value Automatic Enable,
Address 0x0C[1]
FREE-RUN OPERATION
Free-run mode provides the user with a stable clock and
predictable data if the input signal cannot be decoded; for
example, if input video is not present.
This bit enables the ADV7182 to enter free-run mode if it
cannot decode the video signal that has been input.
The ADV7182 automatically enters free-run mode if the input
signal cannot be decoded. The user can prevent this operation
by setting the DEF_VAL_AUTO_EN to 0. When the DEF_VAL_
AUTO_EN bit is 0, the ADV7182 outputs noise if it cannot
decode the input video. It is recommended that the user keep
DEF_VAL_AUTO_EN set to 1.
Table 31. DEF_VAL_AUTO_EN Function
DEF_VAL_AUTO_EN Description
0
The ADV7182 outputs noise if it loses
lock with the inputted video signal.
1 (default)
The ADV7182 enters free-run mode if it
loses lock with the inputted video signal.
The user can force free-run mode by setting the DEF_VAL_EN
bit to 1. This can be a useful tool in debugging system level issues.
DEF_VAL_EN, Default Value Enable, Address 0x0C[0]
This bit forces free-run mode.
The user can set which video standard is output in free-run
mode with the VS_COAST_MODE bits.
Table 32. DEF_VAL_EN Function
The user can also specify which data is output in free-run mode
with the FREE_RUN_PAT_SEL bits. The following test patterns
can be set using this function:
DEF_VAL_EN
Description
0 (default)
Do not force free-run mode (that is, free-run
mode dependent on DEF_VAL_AUTO_EN)
1
Force free-run mode
•
•
•
•
Single color
Color bars
Luma ramp
Boundary box
FREE_RUN_PAT_SEL[2:0], Free Run Pattern Select,
Address 0x14[2:0]
This function selects what data is output in free-run mode.
Single Color Test Pattern
Table 33. FREE_FUN_PAT_SEL Function
FREE_RUN_PAT_SEL Description
In this mode, the ADV7182 device can be set to output the
default luma and chroma data stored in DEF_Y and DEF_C
(see the Color Controls section).
000 (default)
Single color set by DEF_C and DEF_Y
controls; see Color Controls section
Color Bars Test Pattern
001
010
100% color bars
In this mode, the ADV7182 device outputs the 100% color bars
pattern.
Luma ramp. Note that in order to display
properly, the DEF_C register should be
set to 0x88. See Color Controls section
Luma Ramp Test Pattern
101
Boundary box
In this mode, the ADV7182 device outputs a series of vertical
bars. Each vertical bar is progressively brighter than the vertical
bar to its left.
VS_COAST_MODE[1:0], Address 0xF9[3:2]
If no video source is connected, then this function can set the
video output standard during free-run mode.
Boundary Box Test Pattern
In this mode, the ADV7182 device outputs a black screen with
a 1-pixel depth white border (see Figure 14).
If a valid input video source is connected to the ADV7182 and
free-run mode is forced, the VS_COAST_MODE bits are
ignored. The free-run standard will be the same as the valid
inputted video standard.
Table 34. VS_COAST_MODE Function
VS_COAST_MODE Description
00 (default)
The ADV7182 outputs in the same
standard as it did before it entered free-run
mode. If no valid standard was output
before entering free-run mode, the
ADV7182 outputs a 576i 50 Hz signal in
free-run mode.
Figure 14. Boundary Box Free-Run Test Pattern
01
10
11
Outputs a 576i 50 Hz signal in free-run mode.
Outputs a 480i 60 Hz signal in free-run mode.
Reserved.
Rev. A | Page 24 of 96
Data Sheet
ADV7182
The primary task of the analog clamping circuits is to ensure that
the video signal stays within the valid 1.0 V ADC input window
so that the analog-to-digital conversion can take place. The current
sources in Figure 15 correct the dc level of the ac-coupled input
video signal before it is fed into the ADC. The digitized data from
the ADC is then fed into the video processor. The digital fine
clamp block within the video processor corrects for any remaining
variation in the dc level. The video processor also sends clamp
control signals to the current sources. This feedback loop fine
tunes the current clamp operation and compensates for any noise
on the inputted video signal. This maintains the dc level of the
video signal during normal operation.
CLAMP OPERATION
The input video is ac-coupled into the ADV7182. This has the
advantage of protecting the ADV7182 from short-to-battery events.
However, the dc value of the input video needs to be restored. This
process is referred to as clamping the video. This section explains
the general process of clamping on the ADV7182 in both single-
ended and differential modes. This section also shows the different
ways in which a user can configure clamp operation behavior.
Single-Ended CVBS Clamp Operation
The ADV7182 uses a combination of current sources and a
digital processing block for clamping, as shown in Figure 15.
The analog processing channel shown is replicated three times
inside the IC. Whereas only a single channel is needed for a
single-ended CVBS signal, two independent channels are needed
for Y/C (SVHS) type signals, and three independent channels
are needed to allow component signals (YPrPb) to be processed.
Differential CVBS Clamping Operation
The differential clamping operation works in a similar manner to
the single-ended clamping operation (see Single-Ended CVBS
Clamp Operation section). In differential mode, a coarse clamp
pulls the positive and negative video input to a common-mode
voltage VCML (see Figure 16). The feedback loop between the
current clamps and the video processor fine tune this coarse dc
offset and make the clamping robust to noise on the video input.
The clamping can be divided into two sections:
Clamping before the ADC (analog domain): current
sources and voltage sources.
Clamping after the ADC (digital domain): digital
processing block.
Note that the current clamps are controlled within a feedback loop
between the AFE and the video processor, and the coarse clamps
are not.
ADV7182
ANALOG FRONT END (AFE)
DIGITAL CORE
EXTERNAL AC
COUPLING
CLAMP CONTROL
CAPACITOR
VIDEO PROCESSOR
WITH DIGITAL
DATA PRE-
PROCESSOR
ADC
FINE CLAMP
CURRENT
SOURCE
CLAMPS
SINGLE-ENDED
ANALOG
VIDEO INPUT
Figure 15. Single-Ended Clamping Overview
ADV7182
ANALOG FRONT END (AFE)
DIGITAL CORE
EXTERNAL AC
COUPLING
CAPACITOR
CLAMP CONTROL
COARSE
CLAMP
VIDEO PROCESSOR
WITH DIGITAL
DATA PRE-
PROCESSOR
ADC
FINE CLAMP
CURRENT
SOURCE
CLAMPS
POSITIVE
DIFFERENTIAL ANALOG
VIDEO INPUT
V
CML
NEGATIVE
DIFFERENTIAL ANALOG
VIDEO INPUT
CURRENT
SOURCE
CLAMPS
EXTERNAL AC
COUPLING
CAPACITOR
COARSE
CLAMP
CLAMP CONTROL
Figure 16. Differential Clamping Overview
Rev. A | Page 25 of 96
ADV7182
Data Sheet
Clamp Operation Controls
The following sections describe the I2C signals that can be used
to influence the behavior of the clamping block.
LUMA FILTER
Data from the digital fine clamp block is processed by the three
sets of filters that follow. The data format at this point is CVBS
for CVBS input or luma only for Y/C and YPrPb input formats.
CCLEN, Current Clamp Enable, Address 0x14[4]
•
Luma antialias filter (YAA). The ADV7182 receives video at
a rate of 28.6363 MHz. (In the case of 4× oversampled video,
the ADC samples at 57.27 MHz, and the first decimation is
performed inside the DPP filters. Therefore, the data rate
into the ADV7182 is always 28.6363 MHz.) The ITU-R
BT.601 recommends a sampling frequency of 13.5 MHz.
The luma antialias filter decimates the oversampled video
using a high quality linear phase, low-pass filter that preserves
the luma signal while, at the same time, attenuating out-of-
band components. The luma antialias filter (YAA) has a
fixed response.
Luma shaping filters (YSH). The shaping filter block is a
programmable low-pass filter with a wide variety of responses.
It can be used to reduce selectively the luma video signal
bandwidth (needed prior to scaling, for example). For some
video sources that contain high frequency noise, reducing
the bandwidth of the luma signal improves visual picture
quality. If the video is low-pass filtered, a follow-on video
compression stage can work more efficiently.
The ADV7182 has two responses for the shaping filter: one
that is used for good quality composite, component, and SVHS
type sources; and a second for nonstandard CVBS signals.
The YSH filter responses also include a set of notches for
PAL and NTSC. However, using the comb filters for Y/C
separation is recommended.
Digital resampling filter. This block allows dynamic
resampling of the video signal to alter parameters such as
the time base of a line of video. Fundamentally, the resampler
is a set of low-pass filters. The actual response is chosen by the
system with no requirement for user intervention.
The current clamp enable bit allows the user to switch off all the
current sources in the AFE simultaneously. This may be useful
if the incoming analog video signal is clamped externally.
When CCLEN is 0, the current sources are switched off.
When CCLEN is 1 (default), the current sources are enabled.
DCT[1:0], Digital Clamp Timing, Address 0x15[6:5]
The clamp timing register determines the time constant of the
digital fine clamp circuitry. Note that the digital fine clamp reacts
quickly because it immediately corrects any residual dc level error
for the active line. The time constant from the digital fine clamp
must be much quicker than the one from the analog blocks.
•
By default, the time constant of the digital fine clamp is adjusted
dynamically to suit the currently connected input signal.
Table 35. DCT Function
DCT[1:0]
Description
00 (default)
Slow (TC = 1 sec)
Medium (TC = 0.5 sec)
Fast (TC = 0.1 sec)
Determined by ADV7182, depending on the
input video parameters
01
10
11
DCFE, Digital Clamp Freeze Enable, Address 0x15[4]
This register bit allows users to freeze the digital clamp loop at
any time (do their own clamping). Users can disable the current
sources for analog clamping via the appropriate register bits,
wait until the digital clamp loop settles, and then freeze it via
the DCFE bit.
•
When DCFE is set to 0 (default), the digital clamp is operational.
When DCFE is 1, the digital clamp loop is frozen.
Figure 18 through Figure 21 show the overall response of all filters
together. Unless otherwise noted, the filters are set into a typical
wideband mode.
Rev. A | Page 26 of 96
Data Sheet
ADV7182
In automatic mode, the system preserves the maximum possible
bandwidth for good CVBS sources (because they can be successfully
combed) as well as for luma components of YPrPb and Y/C
sources (because they need not be combed). For poor quality
signals, the system selects from a set of proprietary shaping
filter responses that complements comb filter operation to
reduce visual artifacts.
Y Shaping Filter
For input signals in CVBS format, the luma shaping filters play
an essential role in removing the chroma component from a
composite signal. Y/C separation must aim for best possible
crosstalk reduction while still retaining as much bandwidth
(especially on the luma component) as possible. High quality
Y/C separation can be achieved by using the internal comb
filters of the ADV7182. Comb filtering, however, relies on the
frequency relationship of the luma component (multiples of the
video line rate) and the color subcarrier (fSC). For good quality
CVBS signals, this relationship is known; the comb filter algorithms
can be used to separate luma and chroma with high accuracy.
The decisions of the control logic are shown in Figure 17.
YSFM[4:0], Y Shaping Filter Mode, Address 0x17[4:0]
The Y shaping filter mode bits allow the user to select from
a wide range of low-pass and notch filters. When switched in
automatic mode, the filter selection is based on other register
selections, such as detected video standard, as well as properties
extracted from the incoming video itself, such as quality and time
base stability. The automatic selection always selects the widest
possible bandwidth for the video input encountered. (See Table 36.)
In the case of nonstandard video signals, the frequency relationship
may be disturbed, and the comb filters may not be able to remove
all crosstalk artifacts in the best fashion without the assistance
of the shaping filter block.
An automatic mode is provided that allows the ADV7182 to
evaluate the quality of the incoming video signal and select the
filter responses in accordance with the signal quality and video
standard. YFSM, WYSFMOVR, and WYSFM allow the user to
manually override the automatic decisions in part or in full.
The Y-shaping filter mode operates as follows:
•
•
If the YSFM settings specify a filter (that is, YSFM is set to
values other than 00000 or 00001), the chosen filter is
applied to all video, regardless of its quality.
In automatic selection mode, the notch filters are only used
for bad quality video signals. For all other video signals,
wideband filters are used.
The luma shaping filter has the following control bits.
•
YSFM[4:0] allows the user to manually select a shaping
filter mode (applied to all video signals) or to enable an
automatic selection (depending on video quality and video
standard).
WYSFMOVR, Wideband Y Shaping Filter Override,
Address 0x18[7]
•
•
WYSFMOVR allows the user to manually override the
WYSFM decision.
WYSFM[4:0] allows the user to select a different shaping
filter mode for good quality composite (CVBS), component
(YPrPb), and SVHS (Y/C) input signals.
Setting the WYSFMOVR bit enables the use of the WYSFM[4:0]
settings for good quality video signals. For more information on
luma shaping filters, see the Y Shaping Filter section and the
flowchart shown in Figure 17.
When WYSFMOVR is set to 0, the shaping filter for good quality
video signals is selected automatically.
Setting WYSFMOVR is set to 1 (default), it enables manual
override via WYSFM[4:0].
SET YSFM
YSFM IN AUTO MODE?
00000 OR 00001
YES
NO
VIDEO
QUALITY
BAD
GOOD
USE YSFM SELECTED
FILTER REGARDLESS OF
VIDEO QUALITY
AUTO SELECT LUMA
SHAPING FILTER TO
COMPLEMENT COMB
WYSFMOVR
1
0
SELECT WIDEBAND
FILTER AS PER
WYSFM[4:0]
SELECT AUTOMATIC
WIDEBAND FILTER
Figure 17. YSFM and WYSFM Control Flowchart
Rev. A | Page 27 of 96
ADV7182
Data Sheet
Table 36. YSFM Function
Table 37. WYSFM Function
WYSFM[4:0]
00000
YSFM[4:0]
Description
Description
00000
Automatic selection including a wide notch
response (PAL/NTSC/SECAM)
Reserved, do not use
Reserved, do not use
SVHS 1
SVHS 2
SVHS 3
SVHS 4
SVHS 5
SVHS 6
SVHS 7
SVHS 8
SVHS 9
SVHS 10
SVHS 11
SVHS 12
SVHS 13
SVHS 14
SVHS 15
00001
00001 (default) Automatic selection including a narrow notch
response (PAL/NTSC/SECAM)
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
SVHS 1
SVHS 2
SVHS 3
SVHS 4
SVHS 5
SVHS 6
SVHS 7
SVHS 8
SVHS 9
SVHS 10
SVHS 11
SVHS 12
SVHS 13
SVHS 14
SVHS 15
SVHS 16
SVHS 17
SVHS 18 (CCIR 601)
PAL NN1
PAL NN2
PAL NN3
PAL WN1
PAL WN2
NTSC NN1
NTSC NN2
NTSC NN3
NTSC WN1
NTSC WN2
NTSC WN3
Reserved
SVHS 16
SVHS 17
SVHS 18 (CCIR 601)
Reserved, do not use
10010
10011 (default)
10100 to 11111
The filter plots in Figure 18 show the SVHS 1 (narrowest) to
SVHS 18 (widest) shaping filter settings. Figure 20 shows the PAL
notch filter responses. The NTSC notch filter responses are shown
in Figure 21.
COMBINED Y ANTIALIAS, SVHS LOW-PASS FILTERS,
Y RESAMPLE
0
–10
–20
–30
–40
–50
–60
–70
WYSFM[4:0], Wideband Y Shaping Filter Mode,
Address 0x18[4:0]
The WYSFM[4:0] bits allow the user to manually select a shaping
filter for good quality video signals, for example, CVBS with
stable time base, luma component of YPrPb, and luma component
of Y/C. The WYSFM bits are active only if the WYSFMOVR bit
is set to 1. See the general discussion of the shaping filter settings in
the Y Shaping Filter section.
0
2
4
6
8
10
12
FREQUENCY (MHz)
Figure 18. Y SVHS Combined Responses
Rev. A | Page 28 of 96
Data Sheet
ADV7182
COMBINED Y ANTIALIAS, NTSC NOTCH FILTERS,
Y RESAMPLE
CHROMA FILTER
Data from the digital fine clamp block is processed by the three
sets of filters that follow. The data format at this point is CVBS for
CVBS inputs, chroma only for Y/C, or U/V interleaved for YPrPb
input formats.
0
–10
–20
–30
–40
–50
–60
–70
•
Chroma antialias filter (CAA). The ADV7182 oversamples the
CVBS by a factor of 4 and the chroma/YPrPb by a factor of 2.
A decimating filter (CAA) is used to preserve the active video
band and to remove any out-of-band components. The
CAA filter has a fixed response.
•
•
Chroma shaping filters (CSH). The shaping filter block
(CSH) can be programmed to perform a variety of low-pass
responses. It can be used to selectively reduce the bandwidth
of the chroma signal for scaling or compression.
Digital resampling filter. This block allows dynamic
resampling of the video signal to alter parameters such as
the time base of a line of video. Fundamentally, the resampler
is a set of low-pass filters. The actual response is chosen by
the system without user intervention.
0
2
4
6
8
10
12
FREQUENCY (MHz)
Figure 21. Combined Y Antialias Filter, NTSC Notch Filters
COMBINED C ANTIALIAS, C SHAPING FILTER,
C RESAMPLER
0
–10
Figure 22 shows the overall response of all filters together.
–20
–30
–40
–50
–60
COMBINED Y ANTIALIAS, CCIR MODE SHAPING FILTER,
Y RESAMPLE
0
–20
–40
–60
0
1
2
3
4
5
6
FREQUENCY (MHz)
–80
Figure 22. Chroma Shaping Filter Responses
–100
–120
CSFM[2:0], C Shaping Filter Mode, Address 0x17[7:5]
The C shaping filter mode bits allow the user to select from a
range of low-pass filters for the chrominance signal. When
switched in automatic mode, the widest filter is selected based
on the video standard/format and user choice (see the 000 and
001 settings in Table 38).
0
2
4
6
8
10
12
FREQUENCY (MHz)
Figure 19. Combined Y Antialias, CCIR Mode Shaping Filter
COMBINED Y ANTIALIAS, PAL NOTCH FILTERS,
Y RESAMPLE
0
Table 38. CSFM Function
CSFM[2:0]
000 (default)
001
010
011
100
101
110
111
Description
–10
Autoselection 1.5 MHz bandwidth
Autoselection 2.17 MHz bandwidth
SH1
SH2
SH3
SH4
SH5
–20
–30
–40
–50
–60
–70
Wideband mode
Figure 22 shows the responses of SH1 (narrowest) to SH5
(widest) in addition to the wideband mode (shown in red).
0
2
4
6
8
10
12
FREQUENCY (MHz)
Figure 20. Combined Y Antialias, PAL Notch Filters
Rev. A | Page 29 of 96
ADV7182
Data Sheet
The minimum supported amplitude of the input video is
determined by the ability of the ADV7182 to retrieve horizontal
and vertical timing and to lock to the color burst, if present.
GAIN OPERATION
The gain control within the ADV7182 is done on a purely digital
basis. The input ADC supports a 10-bit range mapped into a 1.0 V
analog voltage range. Gain correction takes place after the
digitization in the form of a digital multiplier.
There are separate gain control units for luma and chroma data.
Both can operate independently of each other. The chroma unit,
however, can also take its gain value from the luma path.
Advantages of this architecture over the commonly used
programmable gain amplifier (PGA) before the ADC include
the fact that the gain is now completely independent of supply,
temperature, and process variations.
The possible AGC modes are shown in Table 39.
Table 39. AGC Modes
Input Video Type Luma Gain
Chroma Gain
As shown in Figure 25, the ADV7182 can decode a video signal
as long as it fits into the ADC window. The components for this
are the amplitude of the input signal and the dc level it resides on.
The dc level is set by the clamping circuitry (see the Clamp
Operation section).
Any
Manual gain luma
Manual gain chroma
CVBS
Dependent on
Dependent on color-
horizontal sync depth burst amplitude
taken from luma path
Dependent on color-
Peak white
burst amplitude
taken from luma path
If the amplitude of the analog video signal is too high, clipping
may occur, resulting in visual artifacts. The analog input range
of the ADC, together with the clamp level, determines the
maximum supported amplitude of the video signal.
Y/C
Dependent on
Dependent on color-
horizontal sync depth burst amplitude
taken from luma path
Dependent on color-
Peak white
Figure 23 and Figure 24 show the typical voltage divider networks
required to keep the input video signal within the allowed range of
the ADC, 0 V t o 1 V. Place the circuit in Figure 23 before all the
single-ended analog inputs to the ADV7182, and place the circuit
in Figure 24 before all the differential inputs to the ADV7182.
ANALOG VIDEO
burst amplitude
YPrPb
Dependent on
horizontal sync depth
Taken from luma path
It is possible to freeze the automatic gain control loops. This causes
the loops to stop updating and the AGC determined gain at the
time of the freeze to stay active until the loop is either unfrozen
or the gain mode of operation is changed.
INPUT
100nF
AIN OF ADV7182
24Ω
51Ω
The currently active gain from any of the modes can be read
back. Refer to the description of the dual-function manual gain
registers, LG[11:0] luma gain and CG[11:0] chroma gain, in the
Luma Gain and Chroma Gain sections.
Figure 23. Single-Ended Input Voltage Divider Network
ANALOG_INPUT
CVBS_1P
0.1µF
1.3kΩ
A
X
IN
430Ω
430Ω
75Ω
ANALOG_INPUT
CVBS_1N
0.1µF
1.3kΩ
A
X
IN
Figure 24. Differential Input Voltage Divider Network
ANALOG VOLTAGE RANGE SUPPORTED BY ADC
(1V RANGE FOR ADV7182)
MAXIMUM
VOLTAGE
VIDEO PROCESSOR
(GAIN SELECTION ONLY)
DATA PRE-
PROCESSOR
(DPP)
ADC
GAIN
CONTROL
MINIMUM
VOLTAGE
CLAMP
LEVEL
Figure 25. Gain Control Overview
Rev. A | Page 30 of 96
Data Sheet
ADV7182
Luma Gain
LG[11:0], Luma Gain, Address 0x2F[3:0], Address 0x30[7:0]
LAGC[2:0], Luma Automatic Gain Control,
Address 0x2C[6:4]
LMG[11:0], Luma Manual Gain, Address 0x2F[3:0],
Address 0x30[7:0]
The luma automatic gain control mode bits select the operating
mode for the gain control in the luma path.
Luma gain[11:0] is a dual-function register. If all these bits are
written to, a desired manual luma gain can be programmed.
This gain becomes active if the LAGC[2:0] mode is switched to
manual fixed gain. Equation 1 shows how to calculate a desired gain.
There are internal parameters (Analog Devices proprietary
algorithms) to customize the peak white gain control. Contact
local Analog Devices field applications engineers or a local
Analog Devices distributor for more information.
If read back, this register returns the current gain value.
Depending on the setting in the LAGC[2:0] bits, the value is
one of the following:
Table 40. LAGC Function
•
Luma manual gain value (LAGC[2:0] set to luma manual
gain mode)
LAGC[2:0]
Description
000
001
Manual fixed gain (use LMG[11:0])
AGC (blank level to sync tip), peak white algorithm off
•
Luma automatic gain value (LAGC[2:0] set to either of the
automatic modes)
010 (default) AGC (blank level to sync tip), peak white algorithm on
011
100
101
110
111
Reserved
Reserved
Reserved
Reserved
Freeze gain
Table 42. LG/LMG Function
LG[11:0]/LMG[11:0] Read/Write Description
LMG[11:0] = x
LG[11:0] = x
Write
Read
Manual gain for luma path
Actual used gain
LMG[11: 0]
Luma Calibration Factor
LAGT[1:0], Luma Automatic Gain Timing,
Address 0x2F[7:6]
Luma Gain ≅
(1)
where LMG[11:0] is a decimal value between 1024 and 4095.
The luma automatic gain timing register allows the user to
influence the tracking speed of the luminance automatic gain
control. This register has an effect only if the LAGC[2:0] register is
set to 001 or 010 (automatic gain control modes).
Calculation of the Luma Calibration Factor
1. Using a video source, set the content to a gray field and
apply as a standard CVBS signal to the CVBS input of
the board.
2. Using an oscilloscope, measure the signal at the CVBS input
to ensure that its sync depth, color burst, and luma are at
the standard levels.
3. Connect the output parallel pixel bus of the ADV7182 to a
backend system that has unity gain and monitor the output
voltage.
4. Measure the luma level correctly from the black level. Turn
off the luma AGC and manually change the value of the luma
manual gain control register, LMG[11:0], until the output
luma level matches the input measured in Step 2.
If peak white AGC is enabled and active (see the Status 1[7:0],
Address 0x10[7:0] section), the actual gain update speed is dictated
by the peak white AGC loop and, as a result, the LAGT settings
have no effect. As soon as the part leaves peak white AGC, LAGT
becomes relevant again.
The update speed for the peak white algorithm can be customized
by the use of internal parameters. Contact Analog Devices local
field engineers for more information.
Table 41. LAGT Function
LAGT[1:0]
Description
00
01
10
Slow (TC = 2 sec)
Medium (TC = 1 sec)
Fast (TC = 0.2 sec)
Adaptive
This value, in decimal, is the luma calibration factor.
11 (default)
Rev. A | Page 31 of 96
ADV7182
Data Sheet
Chroma Gain
BETACAM, Enable Betacam Levels, Address 0x01[5]
CAGC[1:0], Chroma Automatic Gain Control,
Address 0x2C[1:0]
If YPrPb data is routed through the ADV7182, the automatic
gain control modes can target different video input levels, as
outlined in Table 46. The BETACAM bit is valid only if the input
mode is YPrPb (component). The BETACAM bit sets the target
value for AGC operation.
The two bits of the color automatic gain control mode select the
basic mode of operation for the automatic gain control in the
chroma path.
A review of the following sections is useful:
Table 43. CAGC Function
•
•
The MAN_MUX_EN, Manual Input Muxing Enable,
Address 0xC4[7] section for how component video
(YPrPb) can be routed through the ADV7182.
The Video Standard Selection section to select the various
standards, for example, with and without pedestal.
CAGC[1:0]
Description
00
01
Manual fixed gain (use CMG[11:0])
Use Luma gain for chroma
Automatic gain (based on color burst)
Freeze chroma gain
10 (default)
11
CAGT[1:0], Chroma Automatic Gain Timing,
Address 0x2D[7:6]
The AGC algorithms adjust the levels based on the setting of
the BETACAM bit (see Table 45).
The chroma automatic gain timing register allows the user to
influence the tracking speed of the chroma automatic gain
control. This register has an effect only if the CAGC[1:0] bits
are set to 10 (automatic gain).
PW_UPD, Peak White Update, Address 0x2B[0]
The peak white and average video algorithms determine the
gain based on measurements taken from the active video. The
PW_UPD bit determines the rate of gain change. LAGC[2:0] must
be set to the appropriate mode to enable the peak white or average
video mode in the first place. For more information, see the
LAGC[2:0], Luma Automatic Gain Control, Address 0x2C[6:4]
section.
Table 44. CAGT Function
CAGT[1:0]
Description
Slow (TC = 2 sec)
Medium (TC = 1 sec)
Reserved
00
01
10
Setting PW_UPD to 0 updates the gain once per video line.
Setting PW_UPD to 1 (default) updates the gain once per field.
11 (default)
Adaptive
Table 45. BETACAM Function
BETACAM
Description
0 (default)
Assuming YPrPb is selected as input format:
Selecting PAL with pedestal selects MII.
Selecting PAL without pedestal selects SMPTE.
Selecting NTSC with pedestal selects MII.
Selecting NTSC without pedestal selects SMPTE.
Assuming YPrPb is selected as input format:
Selecting PAL with pedestal selects BETACAM.
1
Selecting PAL without pedestal selects BETACAM variant.
Selecting NTSC with pedestal selects BETACAM.
Selecting NTSC without pedestal selects BETACAM variant.
Table 46. BETACAM Levels
Name
BETACAM (mV)
0 to +714 (including 7.5% pedestal)
−467 to +467
BETACAM Variant (mV)
0 to +714
−505 to +505
+286
SMPTE (mV)
0 to +700
−350 to +350
+300
MII (mV)
Y
0 to +700 (including 7.5% pedestal)
−324 to +324
+300
Pb and Pr
Sync Depth
+286
Rev. A | Page 32 of 96
Data Sheet
ADV7182
CG[11:0], Chroma Gain, Address 0x2D[3:0],
Address 0x2E[7:0]; CMG[11:0], Chroma Manual Gain,
Address 0x2D[3:0], Address 0x2E[7:0]
CKE, Color Kill Enable, Address 0x2B[6]
The color kill enable bit allows the optional color kill function
to be switched on or off.
Chroma gain[11:0] is a dual-function register. If written to, a
desired manual chroma gain can be programmed. This gain
becomes active if the CAGC[1:0] function is switched to manual
fixed gain. See Equation 2 for calculating a desired gain.
For QAM-based video standards (PAL and NTSC), as well as
FM-based systems (SECAM), the threshold for the color kill
decision is selectable via the CKILLTHR[2:0] bits.
If color kill is enabled and the color carrier of the incoming
video signal is less than the threshold for 128 consecutive video
lines, color processing is switched off (black and white output).
To switch the color processing back on, another 128 consecutive
lines with a color burst greater than the threshold are required.
If read back, this register returns the current gain value. Depending
on the setting in the CAGC[1:0] bits, this is either:
•
The chroma manual gain value (CAGC[1:0] set to chroma
manual gain mode).
•
The chroma automatic gain value (CAGC[1:0] set to either
of the automatic modes).
The color kill option works only for input signals with a modulated
chroma part. For component input (YPrPb), there is no color kill.
Set CKE to 0 to disable color kill.
Table 47. CG/CMG Function
CG[11:0]/CMG[11:0] Read/Write Description
Set CKE to 1 (default) to enable color kill.
CKILLTHR[2:0], Color Kill Threshold, Address 0x3D[6:4]
CMG[11:0]
CG[11:0]
Write
Read
Manual gain for chroma path
Currently active gain
The CKILLTHR[2:0] bits allow the user to select a threshold for
the color kill function. The threshold applies only to QAM-based
(NTSC and PAL) or FM-modulated (SECAM) video standards.
CMG[11: 0]decimal
ChromaCalibrationFactor
Chroma_Gain
(2)
≅
where ChromaCalibrationFactor is a decimal value between 0
and 4095.
To enable the color kill function, the CKE bit must be set. For the
000, 001, 010, and 011 settings, chroma demodulation inside
the ADV7182 may not work satisfactorily for poor input video
signals.
Calculation of Chroma Calibration Factor
Take the following steps to calculate the chroma calibration factor:
Table 48. CKILLTHR Function
1. Apply a CVBS signal with the color bars/SMPTE bars test
pattern content directly to the measurement equipment.
2. Ensure correct termination of 75 Ω on the measurement
equipment. Measure chroma output levels.
3. Reconnect the source to the CVBS input of the ADV7182
system that has a back end gain of 1. Repeat the measurement
of chroma levels.
4. Turn off the chroma AGC and manually change the
chroma gain control register, CMG[11:0], until the chroma
level matches that measured directly from the source.
Description
CKILLTHR[2:0] NTSC, PAL
SECAM
000
001
010 (default)
011
Kill at <0.5%
Kill at <1.5%
Kill at <2.5%
Kill at <4%
No color kill
Kill at <5%
Kill at <7%
Kill at <8%
Kill at <9.5%
Kill at <15%
Kill at <32%
100
101
110
Kill at <8.5%
Kill at <16%
Kill at <32%
111
Reserved for Analog Devices internal use only;
do not select
This value, in decimal, is the chroma calibration factor.
Rev. A | Page 33 of 96
ADV7182
Data Sheet
CTI_AB_EN, Chroma Transient Improvement Alpha
CHROMA TRANSIENT IMPROVEMENT (CTI)
Blend Enable, Address 0x4D[1]
The signal bandwidth allocated for chroma is typically much
smaller than that for luminance. In the past, this was a valid way
to fit a color video signal into a given overall bandwidth because
the human eye is less sensitive to chrominance than to luminance.
The CTI_AB_EN bit enables an alpha blend function within
the CTI block. If set to 1, the alpha blender mixes the transient
improved chroma with the original signal. The sharpness of the
alpha blending can be configured via the CTI_AB[1:0] bits.
The uneven bandwidth, however, may lead to visual artifacts in
sharp color transitions. At the border of two bars of color, both
components (luma and chroma) change at the same time (see
Figure 26). Due to the higher bandwidth, the signal transition
of the luma component is usually much sharper than that of the
chroma component. The color edge is not sharp, and in the
worst case, it can be blurred over several pixels.
For the alpha blender to be active, the CTI block must be enabled
via the CTI_EN bit.
Set CTI_AB_EN to 0 to disable the CTI alpha blender.
Set CTI_AB_EN to 1 (default) to enable the CTI alpha-blend
mixing function.
CTI_AB[1:0], Chroma Transient Improvement Alpha
Blend, Address 0x4D[3:2]
LUMA SIGNAL WITH A
TRANSITION, ACCOMPANIED
The CTI_AB[1:0] controls the behavior of alpha-blend circuitry
that mixes the sharpened chroma signal with the original one. It
thereby controls the visual impact of CTI on the output data.
LUMA SIGNAL
BY A CHROMA TRANSITION
For CTI_AB[1:0] to become active, the CTI block must be
enabled via the CTI_EN bit, and the alpha blender must be
switched on via CTI_AB_EN.
ORIGINAL, SLOW CHROMA
TRANSITION PRIOR TO CTI
DEMODULATED
CHROMA SIGNAL
SHARPENED CHROMA
TRANSITION AT THE
OUTPUT OF CTI
Sharp blending maximizes the effect of CTI on the picture;
however, it may also increase the visual impact of small amplitude,
high frequency chroma noise.
Figure 26. CTI Luma/Chroma Transition
The chroma transient improvement block examines the input video
data. It detects transitions of chroma and can be programmed to
create steeper chroma edges in an attempt to artificially restore lost
color bandwidth. The CTI block, however, operates only on edges
above a certain threshold to ensure that noise is not emphasized.
Care was taken to ensure that edge ringing and undesirable
saturation or hue distortion are avoided.
Table 49. CTI_AB Function
CTI_AB[1:0]
Description
00
Sharpest mixing between sharpened and
original chroma signal
01
Sharp mixing
10
Smooth mixing
Chroma transient improvements are needed primarily for signals
that have severe chroma bandwidth limitations. For those types
of signals, it is strongly recommended to enable the CTI block
via CTI_EN.
11 (default)
Smoothest mixing between sharpened and
original chroma signal
CTI_C_TH[7:0], CTI Chroma Threshold, Address 0x4E[7:0]
The CTI_C_TH[7:0] value is an unsigned, 8-bit number specifying
how big the amplitude step in a chroma transition must be if it
is going to be steepened by the CTI block. Programming a small
value into this register causes even smaller edges to be steepened by
the CTI block. Making CTI_C_TH[7:0] a large value causes the
block to improve large transitions only.
CTI_EN, Chroma Transient Improvement (CTI) Enable,
Address 0x4D[0]
Set CTI_EN to 0 to disable the CTI block.
Set CTI_EN to 1 (default) to enable the CTI block.
The default value for CTI_C_TH[7:0] is 0x08.
Rev. A | Page 34 of 96
Data Sheet
ADV7182
PEAKING_GAIN[7:0], Luma Peaking Gain,
Address 0xFB[7:0]
DIGITAL NOISE REDUCTION (DNR) AND LUMA
PEAKING FILTER
Digital noise reduction is based on the assumption that high
frequency signals with low amplitude are probably noise and that
their removal, therefore, improves picture quality. The two DNR
blocks in the ADV7182 are the DNR1 block before the luma
peaking filter and the DNR2 block after the luma peaking filter,
as shown in Figure 27.
This filter can be manually enabled. The user can select to boost
or to attenuate the midregion of the Y spectrum around 3 MHz.
The peaking filter can visually improve the picture by showing
more definition on the picture details that contain frequency
components around 3 MHz. The default value on this register
passes through the luma data unaltered. A lower value attenuates
the signal, and a higher value gains the luma signal. A plot of
the responses of the filter is shown in Figure 28.
Table 52. PEAKING_GAIN[7:0] Function
LUMA
PEAKING
FILTER
LUMA
SIGNAL
LUMA
OUTPUT
DNR1
DNR2
Setting
Description
0x40 (default)
0 dB response
PEAKING GAIN USING BP FILTER
15
10
5
Figure 27. DNR and Peaking Block Diagram
DNR_EN, Digital Noise Reduction Enable, Address 0x4D[5]
The DNR_EN bit enables the DNR block or bypasses it.
0
Table 50. DNR_EN Function
–5
–10
–15
Setting
Description
0
Bypasses the DNR block (disable)
Enables the DNR block
1 (default)
DNR_TH[7:0], DNR Noise Threshold 1, Address 0x50[7:0]
–20
0
The DNR1 block is positioned before the luma peaking block.
The DNR_TH[7:0] value is an unsigned, 8-bit number used to
determine the maximum edge that is interpreted as noise and,
therefore, blanked from the luma data. Programming a large value
into DNR_TH[7:0] causes the DNR block to interpret even large
transients as noise and remove them. As a result, the effect on
the video data is more visible. Programming a small value causes
only small transients to be seen as noise and to be removed.
1
2
3
4
5
6
7
FREQUENCY (MHz)
Figure 28. Peaking Filter Responses
DNR_TH2[7:0], DNR Noise Threshold 2, Address 0xFC[7:0]
The DNR2 block is positioned after the luma peaking block
and, therefore, affects the gained luma signal. It operates in the
same way as the DNR1 block; however, there is an independent
threshold control, DNR_TH2[7:0], for this block. This value is
an unsigned, 8-bit number used to determine the maximum
edge that is interpreted as noise and, therefore, blanked from
the luma data. Programming a large value into DNR_TH2[7:0]
causes the DNR block to interpret even large transients as noise
and remove them. As a result, the effect on the video data is more
visible. Programming a small value causes only small transients
to be seen as noise and to be removed.
Table 51. DNR_TH[7:0] Function
Setting
Description
0x08 (default) Threshold for maximum luma edges to be
interpreted as noise
Table 53. DNR_TH2[7:0] Function
Setting
Description
0x04 (default)
Threshold for maximum luma edges to be
interpreted as noise
Rev. A | Page 35 of 96
ADV7182
Data Sheet
CCMN[2:0], Chroma Comb Mode, NTSC, Address 0x38[5:3]
COMB FILTERS
The comb filters of the ADV7182 can automatically handle
video of all types, standards, and levels of quality. The NTSC
and PAL configuration registers allow the user to customize the
comb filter operation depending on which video standard is
detected (by autodetection) or selected (by manual programming).
In addition to the bits listed in this section, there are some other
internal controls (based on Analog Devices proprietary algorithms);
contact local Analog Devices field engineers for more information.
Table 56. CCMN Function
CCMN[2:0] Description
Configuration
000
Adaptive comb mode
Three-line adaptive
chroma comb for
CTAPSN = 01
Four-line adaptive
chroma comb for
CTAPSN = 10
Five-line adaptive
chroma comb for
CTAPSN = 11
(default)
NTSC Comb Filter Settings
These settings are used for NTSC M/NTSC J CVBS inputs.
NSFSEL[1:0], Split Filter Selection, NTSC, Address 0x19[3:2]
100
101
Disable chroma comb
Fixed chroma comb
(top lines of line
memory)
Fixed two-line chroma
comb for CTAPSN = 01
The NSFSEL[1:0] control selects how much of the overall signal
bandwidth is fed to the combs. A narrow split filter selection
results in better performance on diagonal lines but more dot
crawl in the final output image. The opposite is true for selecting
a wide bandwidth split filter.
Fixed three-line chroma
comb for CTAPSN = 10
Fixed four-line chroma
comb for CTAPSN = 11
Table 54. NSFSEL Function
NSFSEL[1:0]
00 (default)
01
10
11
110
111
Fixed chroma comb (all Fixed three-line chroma
lines of line memory)
comb for CTAPSN = 01
Description
Narrow
Medium
Medium
Wide
Fixed four-line chroma
comb for CTAPSN = 10
Fixed five-line chroma
comb for CTAPSN = 11
Fixed chroma comb
(bottom lines of line
memory)
Fixed two-line chroma
comb for CTAPSN = 01
CTAPSN[1:0], Chroma Comb Taps, NTSC,
Address 0x38[7:6]
Fixed three-line chroma
comb for CTAPSN = 10
Fixed four-line chroma
comb for CTAPSN = 11
Table 55. CTAPSN Function
CTAPSN[1:0] Description
00
Do not use
01
NTSC chroma comb adapts three lines to two lines
NTSC chroma comb adapts five lines to three lines
NTSC chroma comb adapts five lines to four lines
10 (default)
11
Rev. A | Page 36 of 96
Data Sheet
ADV7182
YCMN[2:0], Luma Comb Mode, NTSC, Address 0x38[2:0]
CCMP[2:0], Chroma Comb Mode, PAL, Address 0x39[5:3]
Table 57. YCMN Function
Table 60. CCMP Function
YCMN[2:0]
Description
Configuration
CCMP[2:0]
Description
Configuration
000 (default) Adaptive comb mode Adaptive three-lines
(three taps) luma comb
000 (default)
Adaptive comb mode
Adaptive three-line
chroma comb for
CTAPSN = 01
Adaptive four-line
chroma comb for
CTAPSN = 10
Adaptive five-line
chroma comb for
CTAPSN = 11
100
Disable luma comb
Use low-pass/notch
filter; see the Y Shaping
Filter section
101
110
111
Fixed luma comb (top Fixed luma comb two-
lines of line memory)
line (two taps)
Fixed luma comb (all
lines of line memory)
Fixed luma comb three-
line (three taps)
100
101
Disable chroma comb
Fixed luma comb
(bottom lines of line
memory)
Fixed luma comb two-
line (two taps)
Fixed chroma comb
(top lines of line
memory)
Fixed two-line chroma
comb for CTAPSN = 01
PAL Comb Filter Settings
Fixed three-line chroma
comb for CTAPSN = 10
Fixed four-line chroma
comb for CTAPSN = 11
These settings are used for PAL B/PAL G/PAL H/PAL I/PAL D,
PAL M, PAL Combinational N, PAL 60, and NTSC 4.43 CVBS
inputs.
110
111
Fixed chroma comb (all Fixed three-line chroma
lines of line memory)
PSFSEL[1:0], Split Filter Selection, PAL, Address 0x19[1:0]
comb for CTAPSN = 01
Fixed four-line chroma
comb for CTAPSN = 10
Fixed five-line chroma
comb for CTAPSN = 11
The PSFSEL[1:0] control selects how much of the overall signal
bandwidth is fed to the combs. A wide split filter selection
eliminates dot crawl but shows imperfections on diagonal lines.
The opposite is true for selecting a narrow bandwidth split filter.
Fixed chroma comb
(bottom lines of line
memory)
Fixed two-line chroma
comb for CTAPSN = 01
Table 58. PSFSEL Function
PSFSEL[1:0] Description
Fixed three-line chroma
comb for CTAPSN = 10
Fixed four-line chroma
comb for CTAPSN = 11
00
Narrow
Medium
Wide
01 (default)
10
11
Widest
YCMP[2:0], Luma Comb Mode, PAL, Address 0x39[2:0]
Table 61. YCMP Function
CTAPSP[1:0], Chroma Comb Taps, PAL, Address 0x39[7:6]
Table 59. CTAPSP Function
YCMP[2:0]
Description
Configuration
CTAPSP[1:0] Description
000 (default) Adaptive comb mode
Adaptive five lines (three
taps) luma comb
Use low-pass/notch filter;
see the Y Shaping Filter
section
Fixed three lines (two
taps) luma comb
Fixed five lines (three taps)
luma comb
00
01
Do not use
100
Disable luma comb
PAL chroma comb adapts five lines (three taps)
to three lines (two taps); cancels cross luma only
10
PAL chroma comb adapts five lines (five taps) to
three lines (three taps); cancels cross luma and
hue error less well
101
110
111
Fixed luma comb (top
lines of line memory)
Fixed luma comb (all
lines of line memory)
Fixed luma comb
(bottom lines of line
memory)
11 (default)
PAL chroma comb adapts five lines (five taps) to
four lines (four taps); cancels cross luma and hue
error well
Fixed three lines (two
taps) luma comb
Rev. A | Page 37 of 96
ADV7182
Data Sheet
IF FILTER COMPENSATION
ADAPTIVE CONTRAST ENHANCEMENT (ACE)
IFFILTSEL[2:0], IF Filter Select, Address 0xF8[2:0]
ACE allows for the contrast of an image to be increased, depending
on the content of the picture. Normally, this allows bright areas
to be made brighter and dark areas to be made darker. However,
the ADV7182 ACE feature also allows for the contrast within
dark areas to be increased without significantly affecting bright
areas. This is particularly useful in automotive applications where it
can be important to be able to discern objects in shaded areas.
The IFFILTSEL[2:0] register allows the user to compensate for
SAW filter characteristics on a composite input, as would be
observed on tuner outputs. Figure 29 and Figure 30 show IF
filter compensation for NTSC and PAL, respectively.
The options for this feature are as follows:
•
•
•
Bypass mode
NTSC, consisting of three filter characteristics
PAL, consisting of three filter characteristics
The ACE feature works by sampling the chroma and luma levels
in the inputted image. This information is then histogrammed,
and the resulting correction is applied to the entire image. This
correction is done in a nonlinear fashion so that more correction
can be applied to dark areas if required.
See Table 95 for programming details.
IF COMP FILTERS NTSC ZOOMED AROUND FSC
6
4
For normal use, the luma and chroma gain controls can be
used; however, in automotive applications, where dark areas
may need to be further enhanced, also use the gamma gain
controls.
2
0
The reaction time of the ACE function can be set using the
ACE_RESPONSE_SPEED[7:4] bits (see Table 96). The corrected
image is faded over the original image using alpha blending,
giving a gradual change in contrast with scene changes. The ACE_
RESPONSE_SPEED[7:4] bits determine the duration of the
transition from the original to the corrected image. A larger value
for these bits results in a faster transition time; however, a smaller
value gives more stability to rapid scene changes.
–2
–4
–6
–8
–10
–12
2.0
2.5
3.0
3.5
4.0
4.5
5.0
The ACE_CHROMA_MAX[7:4] bits are used to set a
maximum value that clips the chroma gain regardless of
the ACE_CHROMA_GAIN[3:0] settings.
FREQUENCY (MHz)
Figure 29. NTSC IF Filter Compensation
IF COMP FILTERS PAL ZOOMED AROUND fSC
6
4
The ACE_GAMMA_GAIN[3:0] bits are particularly useful in
automotive applications because they allow dramatic image
enhancement in dark regions by stretching the contrast of pixels
at the low (dark) values of the image histogram. The luma and
chroma gain controls are normally used; however, the
2
0
ACE_GAMMA_GAIN[3:0] bits should be used when further
stretching of the contrast in the dark areas of an image is needed.
–2
–4
–6
–8
ACE_ENABLE, User Sub Map 2, Address 0x80[7]
Enables ACE.
Table 62. ACE_ENABLE Function
ACE_ENABLE
0 (default)
1
Description
Disable ACE
Enable ACE
3.0
3.5
4.0
4.5
5.0
5.5
6.0
FREQUENCY (MHz)
Figure 30. PAL IF Filter Compensation
Rev. A | Page 38 of 96
Data Sheet
ADV7182
ACE_LUMA_GAIN[4:0], User Sub Map 2, Address 0x83[4:0]
ACE_CHROMA_MAX[3:0], User Sub Map 2,
Address 0x84[7:4]
A control to set the auto-contrast level for the luma channel when
ACE_ENABLE is 1.
This control sets a maximum threshold value that clips the
chroma gain regardless of the ACE_CHROMA_GAIN[3:0]
settings.
Table 63. ACE_LUMA_GAIN Function
ACE_LUMA_GAIN[4:0] Description
Table 66. ACE_CHROMA_MAX Function
ACE_CHROMA_MAX[3:0] Description
Set ACE luma auto-contrast level to
minimum value
00000
Set ACE luma auto-contrast level to
default value
Set ACE luma auto-contrast level to
maximum value
Set maximum threshold for ACE
color auto-saturation level to
01101 (default)
0000
11111
minimum value
Set maximum threshold for ACE
color auto-saturation level to
default value
Set maximum threshold for ACE
1000 (default)
ACE_RESPONSE_SPEED[3:0], User Sub Map 2,
Address 0x85[7:4]
1111
Sets the reaction time of the ACE function.
color auto-saturation level to
maximum value
Table 64. ACE_RESPONSE_SPEED Function
ACE_ RESPONSE_SPEED[3:0]
Description
ACE_GAMMA_GAIN[3:0], User Sub Map 2,
Address 0x85[3:0]
0000
Set speed of ACE response to
slowest value
This control provides further contrast enhancement to the luma
and chroma gain controls and is particularly effective in the darker
areas of an image.
1111 (default)
Set speed of ACE response to
fastest value
ACE_CHROMA_GAIN[3:0], User Sub Map 2,
Address 0x84[3:0]
Table 67. ACE_GAMMA_GAIN[3:0] Function
ACE_GAMMA_GAIN[3:0] Description
This control sets the color-saturation level for the color channels
when ACE_ENABLE is 1.
0000
Set further contrast enhancement
to minimum value
Table 65. ACE_CHROMA_GAIN Function
ACE_CHROMA_GAIN[3:0] Description
1000 (default)
1111
Set further contrast enhancements
to default value
Set further contrast enhancement
to maximum value
0000
Set ACE color auto-saturation level
to minimum value
DITHER FUNCTION
1000 (default)
1111
Set ACE color auto-saturation level
The dither function converts the digital output of the ADV7182
from 8-bit pixel data down to 6-bit pixel data. This function makes
it easier for the ADV7182 to communicate with some LCD panels.
The dither function is turned off by default. It is activated by the
BR_DITHER_MODE bit.
to default value
Set ACE color auto-saturation level
to maximum value
BR_DITHER_MODE, User Sub Map 2, Address 0x92[0]
Table 68. BR_DITHER_MODE Function
BR_DITHER_MODE
Description
0 (default)
1
8-bit to 6-bit down dither disabled
8-bit to 6-bit down dither enabled
Rev. A | Page 39 of 96
ADV7182
Data Sheet
Range, Range Selection, Address 0x04[0]
AV CODE INSERTION AND CONTROLS
This section describes the I2C-based controls that affect the
following:
AV codes (as per ITU-R BT.656, formerly known as CCIR-656)
consist of a fixed header made up of 0xFF and 0x00 values.
These two values are reserved and, therefore, are not to be used
for active video. Additionally, the ITU specifies that the nominal
range for video should be restricted to values between 16 and
235 for luma and 16 and 240 for chroma.
•
•
•
•
Insertion of AV codes into the data stream
Data blanking during the vertical blank interval (VBI)
The range of data values permitted in the output data stream
The relative delay of luma vs. chroma signals
The range bit allows the user to limit the range of values output
by the ADV7182 to the recommended value range. In any case,
it ensures that the reserved values of 255d (0xFF) and 00d (0x00)
are not presented on the output pins unless they are part of an
AV code header.
BT.656-4, ITU-R BT.656-3/ITU-R BT.656-4 Enable,
Address 0x04[7]
Between Revision 3 and Revision 4 of the ITU-R BT.656 standards,
the ITU has changed the toggling position for the V bit within
the SAV EAV codes for NTSC. The ITU-R BT.656-4 standard
bit allows the user to select an output mode that is compliant
with either the ITU-R BT.656-3 standard or ITU-R BT.656-4
standard. For further information, visit the International
Telecommunication Union website.
Table 69. Range Function
Range
Description
0
16 ≤ Y ≤ 235, 16 ≤ C/P ≤ 240
1 ≤ Y ≤ 254, 1 ≤ C/P ≤ 254
1 (default)
AUTO_PDC_EN, Automatic Programmed Delay Control,
Address 0x27[6]
Note that the standard change affects only NTSC and has no
bearing on PAL.
Enabling AUTO_PDC_EN activates a function within the
ADV7182 that automatically programs the LTA[1:0] and CTA[2:0]
registers to have the chroma and luma data match delays for all
modes of operation. If AUTO_PDC_EN is 1, the LTA[1:0] and
CTA[2:0] manual registers are not used. If the automatic mode
is disabled (by setting the AUTO_PDC_EN bit to 0), the values
programmed into the LTA[1:0] and CTA[2:0] registers become
active.
When ITU-R BT.656-4 is set to 0 (default), the ITU-R BT.656-3
specification is used. The V bit goes low at EAV of Line 10
and Line 273.
When ITU-R BT.656-4 is 1, the ITU-R BT.656-4 specification is
used. The V bit goes low at EAV of Line 20 and Line 283.
VBI_EN, Vertical Blanking Interval Data Enable,
Address 0x03[7]
The VBI enable bit allows data such as intercast and closed
caption data to be passed through the luma channel of the decoder
with a minimal amount of filtering. All data for Line 1 to Line 21 is
passed through and available at the output port. The ADV7182
does not blank the luma data and automatically switches all filters
along the luma data path into their widest bandwidth. For active
video, the filter settings for YSH and YPK are restored.
When AUTO_PDC_EN is set to 0, the ADV7182 uses the
LTA[1:0] and CTA[2:0] values for delaying luma and chroma
samples. See the LTA[1:0], Luma Timing Adjust, Address
0x27[1:0] section and the CTA[2:0], Chroma Timing Adjust,
Address 0x27[5:3] section.
When AUTO_PDC_EN is 1 (default), the ADV7182 automatically
determines the LTA and CTA values to have luma and chroma
aligned at the output.
See the BL_C_VBI, Blank Chroma During VBI, Address
0x04[2] section for information on the chroma path.
LTA[1:0], Luma Timing Adjust, Address 0x27[1:0]
When VBI_EN is set to 0 (default), all video lines are
filtered/scaled.
The luma timing adjust bits allow the user to specify a timing
difference between chroma and luma samples.
When VBI_EN is 1, only the active video region is filtered/scaled.
There is a functionality overlap with the CTA[2:0] register. For
manual programming, use the following defaults:
BL_C_VBI, Blank Chroma During VBI, Address 0x04[2]
Setting BL_C_VBI to 1 blanks the Cr and Cb values of all VBI
lines. This is done so any data that may arrive during VBI is not
decoded as color and is output through Cr and Cb. As a result,
it is possible to send VBI lines into the decoder and then output
them through an encoder again, undistorted. Without this
blanking, any color that is incorrectly decoded is encoded by the
video encoder, thus distorting the VBI lines.
•
•
•
CVBS input LTA[1:0] = 00
Y/C input LTA[1:0] = 01
YPrPb input LTA[1:0] = 01
Table 70. LTA Function
LTA[1:0]
Description
00 (default)
No delay
01
10
11
Luma one clock (37 ns) late
Luma two clock (74 ns) early
Luma one clock (37 ns) early
Setting BL_C_VBI to 0 decodes and outputs color during VBI.
Setting BL_C_VBI to 1 (default) blanks Cr and Cb values
during VBI.
Rev. A | Page 40 of 96
Data Sheet
ADV7182
pixel units from the falling edge of HSYNC. Using both values,
the user can program both the position and length of the HSYNC
output signal.
CTA[2:0], Chroma Timing Adjust, Address 0x27[5:3]
The chroma timing adjust register allows the user to specify a
timing difference between chroma and luma samples. This can
be used to compensate for external filter group delay differences
in the luma vs. chroma path and to allow a different number of
pipeline delays while processing the video downstream. Review
this functionality together with the LTA[1:0] bits.
The chroma can be delayed or advanced only in chroma pixel
steps. One chroma pixel step is equal to two luma pixels. The
programmable delay occurs after demodulation, where delay
cannot be made by luma pixel steps.
HSB[10:0], HSYNC Begin, Address 0x34[6:4],
Address 0x35[7:0]
The position of this edge is controlled by placing a binary
number into HSB[10:0]. The number applied offsets the edge
with respect to an internal counter that is reset to 0 immediately
after EAV Code FF, 00, 00, XY (see Figure 31). HSB is set to
00000000010b, which is two LLC clock cycles from count [0].
The default value of HSB[10:0] is 0x02, indicating that the
HSYNC pulse starts two pixels after the falling edge of HSYNC.
For manual programming, use the following defaults:
•
•
•
CVBS input CTA[2:0] = 011
Y/C input CTA[2:0] = 101
YPrPb input CTA[2:0] = 110
HSE[10:0], HSYNC End, Address 0x34[2:0], Address 0x36[7:0]
The position of this edge is controlled by placing a binary
number into HSE[10:0]. The number applied offsets the edge
with respect to an internal counter that is reset to 0 immediately
after EAV Code FF, 00, 00, XY (see Figure 31). HSE is set to
00000000000b, which is 0 LLC clock cycles from count [0].
Table 71. CTA Function
CTA[2:0]
Description
000
Reserved
001
010
011 (default)
100
101
Chroma + two pixels (early)
Chroma + one pixel (early)
No delay
Chroma − one pixel (late)
Chroma − two pixels (late)
Chroma − three pixels (late)
Reserved
The default value of HSE[10:0] is 00, indicating that the HSYNC
pulse ends 0 pixels after the falling edge of HSYNC.
For example,
•
To shift the HSYNC toward active video by 20 LLCs, add
20 LLCs to both HSB and HSE, that is, HSB[10:0] =
[00000010110], HSE[10:0] = [00000010100].
To shift the HSYNC away from active video by 20 LLCs,
add 1696 LLCs to both HSB and HSE (for NTSC), that is,
HSB[10:0] = [11010100010], HSE[10:0] = [11010100000].
Therefore, 1696 is derived from the NTSC total number of
pixels, 1716.
110
111
•
SYNCHRONIZATION OUTPUT SIGNALS
HSYNC Configuration
The following controls allow the user to configure the behavior
of the HSYNC output signal only:
•
To move 20 LLCs away from active video, subtract 20 from
1716 and add the result in binary to both HSB[10:0] and
HSE[10:0].
•
•
•
Beginning of HSYNC signal via HSB[10:0]
End of HSYNC signal via HSE[10:0]
Polarity of HSYNC using PHS
PHS, HSYNC Polarity, Address 0x37[7]
The polarity of the HSYNC signal can be inverted using the
PHS bit.
When PHS is 0 (default), HSYNC is active low.
When PHS is 1, HSYNC is active high.
The HSYNC signal can be output on the VS/FIELD/SFL pin or
the HS pin (see the Global Pin Control section.)
The HSYNC begin (HSB) and HSYNC end (HSE) registers allow
the user to freely position the HSYNC signal within the video
line. The values in HSB[10:0] and HSE[10:0] are measured in
Table 72. HS Timing Parameters
Characteristic
HS to Active Video,
LLC Clock Cycles, C
in Figure 31 (Default)
HS Begin Adjust,
Standard HSB[10:0] (Default)
HS End Adjust,
HSE[10:0] (Default)
Active Video Samples/
Line, D in Figure 31
Total LLC Clock
Cycles, E in Figure 31
NTSC
PAL
00000000010b
00000000010b
00000000000b
00000000000b
272
284
720Y + 720C = 1440
720Y + 720C = 1440
1716
1728
LLC
PIXEL
BUS
Cr
Y
FF
00
EAV
00
XY 80
10
80
10
80
10
FF
00
00
SAV
XY Cb
Y
Cr
Y
Cb
Y
Cr
ACTIVE
VIDEO
H BLANK
ACTIVE VIDEO
HS
HSE[10:0]
4 LLC
HSB[10:0]
C
D
D
E
E
Figure 31. HSYNC Timing
Rev. A | Page 41 of 96
ADV7182
Data Sheet
VSYNC and FIELD Configuration
VSEHO, VSYNC End Horizontal Position Odd,
Address 0x33[7]
The following controls allow the user to configure the behavior of
the VSYNC and FIELD output signals, as well as the generation
of embedded AV codes. Note that the VSYNC and FIELD signals
can be output on the VS/FIELD/SFL pin or the HS pin (see the
Global Pin Control section).
The VSEHO and VSEHE bits select the position within a line at
which the VSYNC signal (not the bit in the AV code) becomes
active. Some follow-on chips require the VSYNC signal to
change state only when HSYNC is high or low.
NEWAVMODE, New AV Mode, Address 0x31[4]
When VSEHO is 0 (default), the VSYNC signal goes low
(inactive) in the middle of a line of video (odd field).
When NEWAVMODE is 0, EAV/SAV codes are generated to
suit Analog Devices encoders. No adjustments are possible.
When VSEHO is 1, the VSYNC signal changes state at the start
of a line (odd field).
When NEWAVMODE is 1 (default), it enables the manual position
of the VSYNC, FIELD, and AV codes using Register 0x32 to
Register 0x33 and Register 0xE5 to Register 0xEA. Default register
settings are CCIR656 (BT.565-4) compliant; see Figure 32,
Figure 33 for NTSC and Figure 37, Figure 38 for PAL
VSEHE, VSYNC End Horizontal Position Even,
Address 0x33[6]
The VSEHO and VSEHE bits select the position within a line at
which the VSYNC signal (not the bit in the AV code) becomes
active. Some follow-on chips require the VSYNC signal to
change state only when HS is high or low.
HVSTIM, Horizontal VSYNC Timing, Address 0x31[3]
The HVSTIM bit allows the user to select where the VSYNC
signal is asserted within a line of video. Some interface circuitry
may require VSYNC to go low while HSYNC is low.
When VSEHE is 0 (default), the VSYNC signal goes low
(inactive) in the middle of a line of video (even field).
When HVSTIM is 0 (default), the start of the line is relative to HSE.
When HVSTIM is 1, the start of the line is relative to HSB.
When VSEHE is 1, the VSYNC signal changes state at the start
of a line (even field).
PVS, VSYNC Polarity, Address 0x37[5]
VSBHO, VSYNC Begin Horizontal Position Odd,
Address 0x32[7]
The polarity of the VSYNC signal can be inverted using the PVS
bit.
The VSBHO and VSBHE bits select the position within a line at
which the VSYNC signal (not the bit in the AV code) becomes
active. Some follow-on chips require the VSYNC signal to
change state only when HSYNC is high or low.
When PVS is 0 (default), VSYNC is active high.
When PVS is 1, VSYNC is active low.
PF, FIELD Polarity, Address 0x37[3]
When VSBHO is 0 (default), the VSYNC signal goes high in the
middle of a line of video (odd field).
The FIELD pin can be inverted using the PHS bit.
When PHS is 0 (default), FIELD pin is active high.
When PHS is 1, FIELD pin is active low.
When VSBHO is 1, the VSYNC signal changes state at the start
of a line (odd field).
VSBHE, VSYNC Begin Horizontal Position Even,
Address 0x32[6]
The VSBHO and VSBHE bits select the position within a line at
which the VSYNC signal (not the bit in the AV code) becomes
active. Some follow-on chips require the VSYNC signal to
change state only when HS is high or low.
When VSBHE is 0 (default), the VSYNC signal goes high in the
middle of a line of video (even field).
When VSBHE is 1, the VSYNC signal changes state at the start
of a line (even field).
Rev. A | Page 42 of 96
Data Sheet
ADV7182
FIELD 1
4
525
1
2
3
5
6
7
8
9
10
11
12
13
19
20
21
22
OUTPUT
VIDEO
H
V
1
NVBEG[4:0] = 0x05
NVEND[4:0] = 0x04
BT.656-4
REG 0x04, BIT 7 = 1
F
NFTOG[4:0] = 0x03
FIELD 2
262
263
264
265
266
267
268
269
270
271
272
273
274
275 276
283
284
285
OUTPUT
VIDEO
H
V
1
BT.656-4
REG 0x04, BIT 7 = 1
NVBEG[4:0] = 0x05
NVEND[4:0] = 0x04
F
NFTOG[4:0] = 0x03
APPLIES IF NEWAVMODE = 0:
1
MUST BE MANUALLY SHIFTED IF NEWAVMODE = 1.
Figure 32. NTSC Default, ITU-R BT.656 (Polarity of H, V, and F Embedded in Data)
FIELD 1
525
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
21
22
OUTPUT
VIDEO
HS
OUTPUT
VS
OUTPUT
NVBEG[4:0] = 0x01
NVEND[4:0] = 0x04
FIELD
OUTPUT
NFTOG[4:0] = 0x06
FIELD 2
267
262
263
264
265
266
268
269
270
271
272
273
274
275
276 277
284
285
OUTPUT
VIDEO
HS
OUTPUT
VS
OUTPUT
NVBEG[4:0] = 0x01
NVEND[4:0] = 0x04
FIELD
OUTPUT
NFTOG[4:0] = 0x06
Figure 33. NTSC Typical VS/FIELD Positions
Rev. A | Page 43 of 96
ADV7182
Data Sheet
1
NVBEGSIGN
0
1
NVENDSIGN
0
ADVANCE BEGIN OF
VSYNC BY NVBEG[4:0]
DELAY BEGIN OF
VSYNC BY NVBEG[4:0]
ADVANCE END OF
VSYNC BY NVEND[4:0]
DELAY END OF VSYNC
BY NVEND[4:0]
NOT VALID FOR USER
PROGRAMMING
NOT VALID FOR USER
PROGRAMMING
ODD FIELD?
ODD FIELD?
YES
NO
YES
NO
NVBEGDELO
1
NVBEGDELE
1
NVENDDELO
1
NVENDDELE
1
0
0
0
0
ADDITIONAL
DELAY BY
1 LINE
ADDITIONAL
DELAY BY
1 LINE
ADDITIONAL
DELAY BY
1 LINE
ADDITIONAL
DELAY BY
1 LINE
VSBHO
1
VSBHE
1
VSEHO
1
VSEHE
1
0
0
0
0
ADVANCE BY
0.5 LINE
ADVANCE BY
0.5 LINE
ADVANCE BY
0.5 LINE
ADVANCE BY
0.5 LINE
VSYNC BEGIN
VSYNC END
Figure 34. NTSC VSYNC Begin
Figure 35. NTSC VSYNC End
NVBEGDELO, NTSC VSYNC Begin Delay on Odd Field,
Address 0xE5[7]
NVENDDELO, NTSC VSYNC End Delay on Odd Field,
Address 0xE6[7]
When NVBEGDELO is 0 (default), there is no delay.
When NVENDDELO is 0 (default), there is no delay.
Setting NVBEGDELO to 1 delays VSYNC going high by one
line relative to NVBEG (odd field).
Setting NVENDDELO to 1 delays VSYNC going low by one
line relative to NVEND (odd field).
NVBEGDELE, NTSC VSYNC Begin Delay on Even Field,
Address 0xE5[6]
NVENDDELE, NTSC VSYNC End Delay on Even Field,
Address 0xE6[6]
When NVBEGDELE is 0 (default), there is no delay.
When NVENDDELE is 0 (default), there is no delay.
Setting NVBEGDELE to 1 delays VSYNC going high by one
line relative to NVBEG (even field).
Setting NVENDDELE to 1 delays VSYNC going low by a line
relative to NVEND (even field).
NVBEGSIGN, NTSC VSYNC Begin Sign, Address 0xE5[5]
NVENDSIGN, NTSC VSYNC End Sign, Address 0xE6[5]
Setting NVBEGSIGN to 0 delays the start of VSYNC; sets to low
when manual programming.
Setting NVENDSIGN to 0 (default) delays the end of VSYNC;
sets to low when manual programming.
Setting NVBEGSIGN to 1 (default) advances the start of
VSYNC; however, it is not suitable for user programming.
Setting NVENDSIGN to 1 advances the end of VSYNC;
however, it is not suitable for user programming.
NVBEG[4:0], NTSC VSYNC Begin, Address 0xE5[4:0]
NVEND[4:0], NTSC VSYNC End, Address 0xE6[4:0]
The default value of NVBEG is 00101, indicating the NTSC
VSYNC begin position. For all NTSC/PAL VSYNC timing
controls, both the V bit in the AV code and the VSYNC signal
are modified.
The default value of NVEND is 00100, indicating the NTSC
VSYNC end position.
For all NTSC/PAL VSYNC timing controls, both the V bit in
the AV code and the VSYNC signal are modified.
Rev. A | Page 44 of 96
Data Sheet
ADV7182
NFTOGDELO, NTSC FIELD Toggle Delay on Odd Field,
Address 0xE7[7]
1
NFTOGSIGN
0
When NFTOGDELO is 0 (default), there is no delay.
ADVANCE TOGGLE OF
FIELD BY NFTOG[4:0]
DELAY TOGGLE OF
FIELD BY NFTOG[4:0]
Setting NFTOGDELO to 1 delays the FIELD toggle/transition
by one line relative to NFTOG (odd field).
NOT VALID FOR USER
PROGRAMMING
NFTOGDELE, NTSC FIELD Toggle Delay on Even Field,
Address 0xE7[6]
ODD FIELD?
YES
NO
When NFTOGDELE is 0, there is no delay.
Setting NFTOGDELE to 1 (default) delays the FIELD toggle/
transition by one line relative to NFTOG (even field).
NFTOGDELO
1
NFTOGDELE
1
NFTOGSIGN, NTSC FIELD Toggle Sign, Address 0xE7[5]
0
0
Setting NFTOGSIGN to 0 delays the FIELD toggle/transition;
sets to low when manual programming.
ADDITIONAL
DELAY BY
1 LINE
ADDITIONAL
DELAY BY
1 LINE
Setting NFTOGSIGN to 1 (default) advances the FIELD
toggle/transition; however, it is not not suitable for user
programming.
FIELD
TOGGLE
NFTOG[4:0], NTSC FIELD Toggle, Address 0xE7[4:0]
Figure 36. NTSC FIELD Toggle
The default value of NFTOG is 00011, indicating the NTSC
field toggle position.
For all NTSC/PAL field timing controls, both the F bit in the
AV code and the field signal are modified.
FIELD 1
1
622
623
624
625
2
3
4
5
6
7
8
9
10
22
23
24
OUTPUT
VIDEO
H
V
PVBEG[4:0] = 0x05
PVEND[4:0] = 0x04
F
PFTOG[4:0] = 0x03
FIELD 2
314
310
311
312
313
315
316
317
318
319
320
321 322
335
336
337
OUTPUT
VIDEO
H
V
PVBEG[4:0] = 0x05
PVEND[4:0] = 0x04
F
PFTOG[4:0] = 0x03
Figure 37. PAL Default, ITU-R BT.656 (Polarity of H, V, and F Embedded in Data)
Rev. A | Page 45 of 96
ADV7182
Data Sheet
FIELD 1
1
622
623 624
2
3
4
5
6
7
8
9
10
11
23
24
625
OUTPUT
VIDEO
HS
OUTPUT
VS
OUTPUT
PVBEG[4:0] = 0x01
PVEND[4:0] = 0x04
FIELD
OUTPUT
PFTOG[4:0] = 0x06
FIELD 2
314
310
311
312
315
316
317
318
319
320
321
322
323
336
337
313
OUTPUT
VIDEO
HS
OUTPUT
VS
OUTPUT
PVBEG[4:0] = 0x01
PVEND[4:0] = 0x04
FIELD
OUTPUT
PFTOG[4:0] = 0x06
Figure 38. PAL Typical VS/FIELD Positions
Rev. A | Page 46 of 96
Data Sheet
ADV7182
1
PVBEGSIGN
0
1
PVENDSIGN
0
ADVANCE BEGIN OF
VSYNC BY PVBEG[4:0]
DELAY BEGIN OF
VSYNC BY PVBEG[4:0]
ADVANCE END OF
VSYNC BY PVEND[4:0]
DELAY END OF VSYNC
BY PVEND[4:0]
NOT VALID FOR USER
PROGRAMMING
NOT VALID FOR USER
PROGRAMMING
ODD FIELD?
ODD FIELD?
YES
NO
YES
NO
PVBEGDELO
1
PVBEGDELE
1
PVENDDELO
1
PVENDDELE
1
0
0
0
0
ADDITIONAL
DELAY BY
1 LINE
ADDITIONAL
DELAY BY
1 LINE
ADDITIONAL
DELAY BY
1 LINE
ADDITIONAL
DELAY BY
1 LINE
VSBHO
1
VSBHE
1
VSEHO
1
VSEHE
1
0
0
0
0
ADVANCE BY
0.5 LINE
ADVANCE BY
0.5 LINE
ADVANCE BY
0.5 LINE
ADVANCE BY
0.5 LINE
VSYNC BEGIN
VSYNC END
Figure 39. PAL VSYNC Begin
Figure 40. PAL VSYNC End
PVBEGDELO, PAL VSYNC Begin Delay on Odd Field,
Address 0xE8[7]
PVENDDELO, PAL VSYNC End Delay on Odd Field,
Address 0xE9[7]
When PVBEGDELO is 0 (default), there is no delay.
When PVENDDELO is 0 (default), there is no delay.
Setting PVBEGDELO to 1 delays VSYNC going high by one
line relative to PVBEG (odd field).
Setting PVENDDELO to 1 delays VSYNC going low by one line
relative to PVEND (odd field).
PVBEGDELE, PAL VSYNC Begin Delay on Even Field,
Address 0xE8[6]
PVENDDELE, PAL VSYNC End Delay on Even Field,
Address 0xE9[6]
When PVBEGDELE is 0, there is no delay.
When PVENDDELE is 0 (default), there is no delay.
Setting PVBEGDELE to 1 (default) delays VSYNC going high
by one line relative to PVBEG (even field).
Setting PVENDDELE to 1 delays VSYNC going low by one line
relative to PVEND (even field).
PVBEGSIGN, PAL VSYNC Begin Sign, Address 0xE8[5]
PVENDSIGN, PAL VSYNC End Sign, Address 0xE9[5]
Setting PVBEGSIGN to 0 delays the beginning of VSYNC; sets
to low when manual programming.
Setting PVENDSIGN to 0 (default) delays the end of VSYNC;
sets to low when manual programming.
Setting PVBEGSIGN to 1 (default) advances the beginning of
VSYNC; however, it is not suitable for user programming.
Setting PVENDSIGN to 1 advances the end of VSYNC ;
however, it is not suitable for user programming.
PVBEG[4:0], PAL VSYNC Begin, Address 0xE8[4:0]
PVEND[4:0], PAL VSYNC End, Address 0xE9[4:0]
The default value of PVBEG is 00101, indicating the PAL VSYNC
begin position. For all NTSC/PAL VSYNC timing controls, the V
bit in the AV code and the VSYNC signal are modified.
The default value of PVEND is 10100, indicating the PAL
VSYNC end position.
For all NTSC/PAL VSYNC timing controls, both the V bit in
the AV code and the VSYNC signal are modified.
Rev. A | Page 47 of 96
ADV7182
Data Sheet
SYNC PROCESSING
1
PFTOGSIGN
0
The ADV7182 has two additional sync processing blocks that
postprocess the raw synchronization information extracted
from the digitized input video. If desired, the blocks can be
disabled via the following two I2C bits: ENHSPLL and
ENVSPROC.
ADVANCE TOGGLE OF
FIELD BY PFTOG[4:0]
DELAY TOGGLE OF
FIELD BY PFTOG[4:0]
NOT VALID FOR USER
PROGRAMMING
ENHSPLL, Enable HSYNC Processor, Address 0x01[6]
ODD FIELD?
YES
NO
The HSYNC processor is designed to filter incoming HSYNCs that
have been corrupted by noise, providing improved performance
for video signals with stable time bases but poor SNR.
PFTOGDELO
1
PFTOGDELE
1
Setting ENHSPLL to 0 disables the HSYNC processor.
0
0
Setting ENHSPLL to 1 (default) enables the HSYNC processor.
ENVSPROC, Enable VSYNC Processor, Address 0x01[3]
ADDITIONAL
DELAY BY
1 LINE
ADDITIONAL
DELAY BY
1 LINE
This block provides extra filtering of the detected VSYNCs to
improve vertical lock.
Setting ENVSPROC to 0 disables the VSYNC processor.
Setting ENVSPROC to 1 (default) enables the VSYNC processor.
VBI DATA DECODE
FIELD
TOGGLE
Figure 41. PAL FIELD Toggle
The VBI data processor (VDP) on the ADV7182 can slice both
low bandwidth standards and high bandwidth standards such as
teletext.
PFTOGDELO, PAL FIELD Toggle Delay on Odd Field,
Address 0xEA[7]
When PFTOGDELO is 0 (default), there is no delay.
The VDP is capable of slicing multiple VBI data standards on
SD video. It decodes the VBI data on the incoming CVBS and
Y/C or YUV data. The decoded results are available as ancillary
data in output 656 data stream. For low data rate VBI standards
like CC/WSS/CGMS, the decoded data bytes can be read from
the I2C registers.
Setting PFTOGDELO to 1 delays the FIELD toggle/transition
by one line relative to PFTOG (odd field).
PFTOGDELE, PAL FIELD Toggle Delay on Even Field,
Address 0xEA[6]
When PFTOGDELE is 0, there is no delay.
The VBI data standards that can be decoded by the VDP are
listed in Table 73 and Table 74.
Setting PFTOGDELE to 1 (default) delays the FIELD
toggle/transition by one line relative to PFTOG (even field).
PFTOGSIGN, PAL FIELD Toggle Sign, Address 0xEA[5]
Table 73. PAL
Feature
Standard
Setting PFTOGSIGN to 0 delays the field transition and set to
low when manual programming.
Teletext System A, Teletext System C, or
Teletext System D
Teletext System B/ Teletext System WST
Wide Screen Signaling (WSS)
ITU-R BT.653
Setting PFTOGSIGN to 1 (default) advances the field transition;
however, it is not suitable for user programming.
ITU-R BT.653
ITU-R BT.1119-1/
ETSI EN.300294
PFTOG, PAL FIELD Toggle, Address 0xEA[4:0]
Closed Captioning (CCAP)
Not applicable
The default value of PFTOG is 00011, indicating the PAL field
toggle position.
Table 74. NTSC
Feature
Standard
For all NTSC/PAL field timing controls, the F bit in the AV
code and the FIELD signal are modified.
Teletext System B and Teletext System D
Teletext System C/ Teletext System NABTS
ITU-R BT.653
ITU-R BT.653/
EIA-516
Copy Generation Management System (CGMS)
Closed Captioning (CCAP)
EIA-J CPR-1204/
IEC 61880
EIA-608
Rev. A | Page 48 of 96
Data Sheet
ADV7182
The VBI data standard that the VDP decodes on a particular line of
incoming video has been set by default as described in Table 75.
This can be overridden manually and any VBI data can be decoded
on any line. The details of manual programming are described in
Table 76.
When MAN_LINE_PGM is set to 0 (default), the VDP decodes
default standards on lines, as shown in Table 75.
When MAN_LINE_PGM is set to 1, the VBI standards to be
decoded are manually programmed.
VBI_DATA_Px_Ny[3:0], VBI_DATA_Px[3:0], VBI Standard
to be Decoded on Line X for PAL, Line Y for NTSC,
Address 0x64 to Address 0x77, Interrupt/VDP Map
VDP Default Configuration
The VDP can decode different VBI data standards on a line-to-
line basis. The various standards supported by default on different
lines of VBI are explained in Table 75.
These are related 4-bit clusters in Register 0x64 to Register 0x77
of the Interrupt/VDP Map Details (see Table 94). These 4-bit, line
programming registers, VBI_DATA_Px_Ny and VBI_DATA_Px,
identify the VBI data standard that is decoded on Line X in PAL
mode or on Line Y in NTSC mode. The different types of VBI
standards decoded by VBI_DATA_Px_Ny and VBI_DATA_Px
are shown in Table 76. Note that the X or Y value depends on
whether the ADV7182 is in PAL or NTSC mode.
VDP Manual Configuration
MAN_LINE_PGM, Enable Manual Line Programming of
VBI Standards, Address 0x64[7], Interrupt/VDP Map
The user can configure the VDP to decode different standards on
a line-to-line basis through manual line programming. For this, set
the MAN_LINE_PGM bit. The user must write into all the line
programming registers, VBI_DATA_Px_Ny and VBI_DATA_Px
(see Register 0x64 to Register 0x77 in Table 97).
Table 75. Default Standards on Lines for PAL and NTSC
PAL—625/50
NTSC—525/60
Default VBI
Data Decoded
WST
WST
WST
WST
WST
WST
WST
WST
WST
WST
Reserved
Reserved
Reserved
Reserved
WST
Default VBI
Data Decoded
Reserved
WST
WST
WST
WST
WST
WST
WST
WST
WST
WST
Reserved
Reserved
WST
WST
CCAP
Default VBI
Data Decoded
Reserved
Reserved
Reserved
NABTS
NABTS
NABTS
NABTS
Reserved
NABTS
Reserved
NABTS
NABTS
NABTS
CGMS
Default VBI
Data Decoded
Reserved
Reserved
Reserved
NABTS
NABTS
NABTS
NABTS
NABTS
Reserved
NABTS
Reserved
NABTS
NABTS
NABTS
Line No.
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
Line No.
318
319
320
321
322
323
324
325
326
327
328
329
332
333
334
335
Line No.
23
24
25
10
11
12
13
14
15
16
17
18
19
20
21
Line No.
286
287
288
272
273
274
275
276
277
278
279
280
281
282
283
284
CCAP
NABTS
CGMS
CCAP
WST
22 + full
odd field
Reserved
22
23
CCAP
WSS
WST
336
WST
Reserved
Reserved
Reserved
285 + full
even field
Reserved
NABTS
337 + full
even field
Reserved
WST
Reserved
Reserved
Reserved
Reserved
24 + full
Reserved
Reserved
odd field
Table 76. VBI Data Standards for Manual Configuration
VBI_DATA_Px_Ny
PAL—625/50
NTSC—525/60
0000
Disable VDP
Disable VDP
0001
Teletext system identified by VDP_TTXT_TYPE
Teletext system identified by VDP_TTXT_TYPE
0010
Reserved
Reserved
0011
Reserved
Reserved
0100
0101
0110
0111
WSS ITU-R BT.1119-1/ETSI.EN.300294
CGMS EIA-J CPR-1204/IEC 61880
Reserved
Reserved
CCAP EIA-608
Reserved
Reserved
Reserved
CCAP
1000 to 1111
Reserved
Rev. A | Page 49 of 96
ADV7182
Data Sheet
Table 77.VBI Data Standards to be Decoded on Line Px (PAL) or Line Ny (NTSC)
Signal Name
Bit Location
Dec Address
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
Hex Address
0x65
0x66
0x67
0x68
0x69
0x6A
0x6B
0x6C
0x6D
0x6E
0x6F
0x70
0x71
0x72
0x73
0x74
0x75
0x76
0x77
0x64
0x65
0x66
0x67
0x68
0x69
0x6A
0x6B
0x6C
0x6D
0x6E
0x6F
0x70
0x71
0x72
0x73
0x74
0x75
0x76
0x77
VBI_DATA_P6_N23
VBI_DATA_P7_N24
VBI_DATA_P8_N25
VBI_DATA_P9
VBI_DATA_P10
VBI_DATA_P11
VBI_DATA_P12_N10
VBI_DATA_P13_N11
VBI_DATA_P14_N12
VBI_DATA_P15_N13
VBI_DATA_P16_N14
VBI_DATA_P17_N15
VBI_DATA_P18_N16
VBI_DATA_P19_N17
VBI_DATA_P20_N18
VBI_DATA_P21_N19
VBI_DATA_P22_N20
VBI_DATA_P23_N21
VBI_DATA_P24_N22
VBI_DATA_P318
VDP_LINE_00F[7:4]
VDP_LINE_010[7:4]
VDP_LINE_011[7:4]
VDP_LINE_012[7:4]
VDP_LINE_013[7:4]
VDP_LINE_014[7:4]
VDP_LINE_015[7:4]
VDP_LINE_016[7:4]
VDP_LINE_017[7:4]
VDP_LINE_018[7:4]
VDP_LINE_019[7:4]
VDP_LINE_01A[7:4]
VDP_LINE_01B[7:4]
VDP_LINE_01C[7:4]
VDP_LINE_01D[7:4]
VDP_LINE_01E[7:4]
VDP_LINE_01F[7:4]
VDP_LINE_020[7:4]
VDP_LINE_021[7:4]
VDP_LINE_00E[3:0]
VDP_LINE_00F[3:0]
VDP_LINE_010[3:0]
VDP_LINE_011[3:0]
VDP_LINE_012[3:0]
VDP_LINE_013[3:0]
VDP_LINE_014[3:0]
VDP_LINE_015[3:0]
VDP_LINE_016[3:0]
VDP_LINE_017[3:0]
VDP_LINE_018[3:0]
VDP_LINE_019[3:0]
VDP_LINE_01A[3:0]
VDP_LINE_01B[3:0]
VDP_LINE_01C[3:0]
VDP_LINE_01D[3:0]
VDP_LINE_01E[3:0]
VDP_LINE_01F[3:0]
VDP_LINE_020[3:0]
VDP_LINE_021[3:0]
VBI_DATA_P319_N286
VBI_DATA_P320_N287
VBI_DATA_P321_N288
VBI_DATA_P322
VBI_DATA_P323
VBI_DATA_P324_N272
VBI_DATA_P325_N273
VBI_DATA_P326_N274
VBI_DATA_P327_N275
VBI_DATA_P328_N276
VBI_DATA_P329_N277
VBI_DATA_P330_N278
VBI_DATA_P331_N279
VBI_DATA_P332_N280
VBI_DATA_P333_N281
VBI_DATA_P334_N282
VBI_DATA_P335_N283
VBI_DATA_P336_N284
VBI_DATA_P337_N285
Full field detection (lines other than VBI lines) of any standard can
also be enabled by writing to the VBI_DATA_P24_N22[3:0] and
VBI_DATA_P337_N285[3:0] bits. So, if VBI_DATA_P24_N22[3:0]
is programmed with any teletext standard, teletext is decoded
off for the entire odd field. The corresponding register for the
even field is VBI_DATA_P337_N285[3:0].
To program the VDP_TTXT_TYPE_MAN bit, the
VDP_TTXT_TYPE_MAN_ENABLE bit must be set to 1.
VDP_TTXT_TYPE_MAN_ENABLE, Enable Manual
Selection of Teletext Type, Address 0x60[2],
Interrupt/VDP Map
Setting VDP_TTXT_TYPE_MAN_ENABLE to 0 (default),
disables manual programming of the teletext type.
For teletext system identification, VDP assumes that if teletext
is present in a video channel, all the teletext lines comply with a
single standard system. Therefore, the line programming using
the VBI_DATA_Px_Ny and VBI_DATA_Px registers identifies
whether the data in line is teletext; the actual standard is identified
by the VDP_TTXT_TYPE_MAN bit.
Setting VDP_TTXT_TYPE_MAN_ENABLE to 1, enables
manual programming of the teletext type.
Rev. A | Page 50 of 96
Data Sheet
ADV7182
VDP_TTXT_TYPE_MAN[1:0], Specify the Teletext Type,
Address 0x60[1:0], Interrupt/VDP Map
ADF_DID[4:0], User-Specified Data ID Word in
Ancillary Data, Address 0x62[4:0], Interrupt/VDP Map
These bits specify the teletext type to be decoded. These bits are
functional only if VDP_TTXT_TYPE_MAN_ENABLE is set to 1.
These bits select the data ID word to be inserted into the ancillary
data stream with the data decoded by the VDP.
The default value of ADF_DID[4:0] is 10101.
Table 78. VDP_TTXT_TYPE_MAN Function
ADF_SDID[5:0], User-Specified Secondary Data ID Word
in Ancillary Data, Address 0x63[5:0], Interrupt/VDP Map
VDP_TTXT_
TYPE_MAN[1:0] 625/50 (PAL)
525/60 (NTSC)
Teletext-ITU-BT.653- Reserved
625/50-A
Teletext-ITU-BT.653- Teletext-ITU-BT.653-
625/50-B (WST) 525/60-B
Teletext-ITU-BT.653- Teletext-ITU-BT.653-
00 (default)
These bits select the secondary data ID word to be inserted in
the ancillary data stream with the data decoded by the VDP.
01
10
The default value of ADF_SDID[5:0] is 101010.
DUPLICATE_ADF, Enable Duplication/Spreading of
Ancillary Data over Y and C Buses, Address 0x63[7],
Interrupt/VDP Map
625/50-C
525/60-C or EIA516
(NABTS)
11
Teletext-ITU-BT.653- Teletext-ITU-BT.653-
625/50-D 525/60-D
This bit determines whether the ancillary data is duplicated over
both Y and C buses or if the data packets are spread between
the two channels.
VDP Ancillary Data Output
Reading the data back via I2C may not be feasible for VBI data
standards with high data rates (for example, teletext). An alternative
is to place the sliced data in a packet in the line blanking of the
digital output CCIR656 stream. This is available for all standards
sliced by the VDP module.
When DUPLICATE_ADF to 0 (default) is set, the ancillary data
packet is spread across the Y and C data streams.
When DUPLICATE_ADF to 1 is set, the ancillary data packet is
duplicated on the Y and C data streams.
When data is sliced on a given line, the corresponding ancillary
data packet is placed immediately after the next EAV code that
occurs at the output (that is, data sliced from multiple lines are
not buffered up and then emitted in a burst). Note that, due to
the vertical delay through the comb filters, the line number on
which the packet is placed differs from the line number on
which the data was sliced.
ADF_MODE[1:0], Determine the Ancillary Data Output
Mode, Address 0x62[6:5], Interrupt/VDP Map
These bits determine whether the ancillary data output mode is
in byte mode or nibble mode.
Table 79. ADF_MODE
ADF_MODE[1:0] Description
The user can enable or disable the insertion of VDP results that
have been decoded into the 656 ancillary streams by using the
ADF_ENABLE bit.
00 (default)
01
10
Nibble mode
Byte mode, no code restrictions
Byte mode, but 0x00 and 0xFF prevented
(0x00 replaced by 0x01, 0xFF replaced by 0xFE)
Reserved
ADF_ENABLE, Enable Ancillary Data Output Through
656 Stream, Address 0x62[7], User Sub Map 2
11
Setting ADF_ENABLE to 0 (default) disables the insertion of
VBI decoded data into the ancillary 656 stream.
Setting ADF_ENABLE to 1 enables the insertion of VBI
decoded data into the ancillary 656 stream.
The user may select the data identification word (DID) and the
secondary data identification word (SDID) through programming
the ADF_DID[4:0] and ADF_SDID[5:0] bits, respectively.
Rev. A | Page 51 of 96
ADV7182
Data Sheet
The ancillary data packet sequence is explained in Table 80 and
Table 81. The nibble output mode is the default mode of output
from the ancillary stream when ancillary stream output is
enabled. This format is in compliance with ITU-R BT.1364.
EP
•
•
—The MSB, B9, is the inverse of EP. This ensures that
restricted Code 0x00 and Code 0xFF do not occur.
LINE_NUMBER[9:0]—The line number of the line that
immediately precedes the ancillary data packet. The line
number is from the numbering system in ITU-R BT.470.
The line number runs from 1 to 625 in a 625-line system
and from 1 to 263 in a 525-line system. Note that, due to
the vertical delay through the comb filters, the line number
on which the packet is output differs from the line number
on which the VBI data was sliced.
Data count—The data count specifies the number of UDWs
in the ancillary stream for the standard. The total number
of user data-words is four times the data count. Padding
words can be introduced to make the total number of UDWs
divisible by 4.
The following abbreviations are used in Table 80 and Table 81:
•
•
EP—Even parity for Bit B8 to Bit B2. The parity bit’s EP is
set so that an even number of 1s are in Bit B8 to Bit B2,
including the parity bit, B8.
CS—Checksum word. The CS word is used to increase
confidence of the integrity of the ancillary data packet
from the DID, SDID, and dc through user data-words
(UDWs). It consists of 10 bits that include the following:
a 9-bit calculated value and B9 as the inverse of B8. The
checksum value B8 to B0 is equal to the nine LSBs of the
sum of the nine LSBs of the DID, SDID, and dc, and all
UDWs in the packet. Prior to the start of the checksum
count cycle, all checksum and carry bits are preset to 0.
Any carry resulting from the checksum count cycle is
ignored.
•
Table 80. Ancillary Data in Nibble Output Format
Byte
B9
B8
B7
B6
B5
0
B4
0
B3
B2
0
B1
0
B0
0
Description
0
1
2
3
0
0
0
0
0
1
1
Ancillary data preamble
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
EP
EP
0
I2C_DID6_2[4:0]
0
0
DID (data identification
word)
4
EP
EP
I2C_SDID7_2[5:0]
0
0
SDID (secondary data
identification word)
5
EP
EP
EP
EP
EP
EP
EP
EP
EP
EP
EP
EP
EP
EP
EP
EP
EP
EP
EP
EP
0
0
DC[4:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Data count
6
Padding[1:0]
VBI_DATA_STD[3:0]
LINE_NUMBER[9:5]
LINE_NUMBER[4:0]
ID0 (User Data-Word 1)
ID1 (User Data-Word 2)
ID2 (User Data-Word 3)
ID3 (User Data-Word 4)
ID4 (User Data-Word 5)
ID5 (User Data-Word 6)
ID6 (User Data-Word 7)
ID7 (User Data-Word 8)
ID8 (User Data-Word 9)
7
8
EVEN_FIELD
9
0
0
0
0
0
0
0
0
0
0
0
0
0
0
VDP_TTXT_TYPE[1:0]
VBI_WORD_1[7:4]
10
11
12
13
14
VBI_WORD_1[3:0]
VBI_WORD_2[7:4]
VBI_WORD_2[3:0]
VBI_WORD_3[7:4]
Pad 0x200; these
padding words may be
present, depending on
ancillary data type; user
data-word
n − 3
n − 2
n − 1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
B8
Checksum (CS)
CS (checksum word)
Rev. A | Page 52 of 96
Data Sheet
ADV7182
Table 81. Ancillary Data in Byte Output Format1
Byte
B9
B8
B7
B6
B5
0
B4
0
B3
0
B2
0
B1
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
B0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
Description
0
0
0
0
0
Ancillary data preamble
1
1
1
1
1
1
1
1
1
2
1
1
1
1
1
1
1
1
3
EP
EP
EP
EP
EP
EP
EP
0
I2C_DID6_2[4:0]
I2C_SDID7_2[5:0]
DC[4:0]
DID
EP
EP
EP
EP
EP
EP
EP
4
SDID
5
0
0
Data count
6
Padding[1:0]
VBI_DATA_STD[3:0]
LINE_NUMBER[9:5]
LINE_NUMBER[4:0]
ID0 (User Data-Word 1)
ID1 (User Data-Word 2)
ID2 (User Data-Word 3)
ID3 (User Data-Word 4)
ID4 (User Data-Word 5)
ID5 (User Data-Word 6)
ID6 (User Data-Word 7)
ID7 (User Data-Word 8)
ID8 (User Data-Word 9)
7
8
EVEN_FIELD
0
9
0
0
0
VDP_TTXT_TYPE[1:0]
10
11
12
13
14
VBI_WORD_1[7:0]
VBI_WORD_2[7:0]
VBI_WORD_3[7:0]
VBI_WORD_4[7:0]
VBI_WORD_5[7:0]
Pad 0x200; these
padding words may be
present, depending on
ancillary data type; user
data-word
n − 3
n − 2
n − 1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
B8
Checksum
CS (checksum word)
1 This mode does not fully comply with ITU-R BT.1364.
Example
Structure of VBI Words in the Ancillary Data Stream
For teletext (B-WST), the framing code byte is 11100100 (0xE4),
with bits shown in the order of transmission. VBI_WORD_1 =
0x27, VBI_WORD_2 = 0x00, and VBI_WORD_3 = 0x00
translated into UDWs in the ancillary data stream for nibble
mode are as follows:
Each VBI data standard has been split into a clock-run-in
(CRI), a framing code (FC), and a number of data bytes (n).
The data packet in the ancillary stream includes only the FC
and data bytes. Table 82 shows the format of VBI_WORD_x in
the ancillary data stream.
UDW5[5:2] = 0010
Table 82. Structure of VBI Data-Words in the Ancillary Stream
UDW6[5:2] = 0111
Ancillary Data Byte No.
VBI_WORD_1
VBI_WORD_2
VBI_WORD_3
VBI_WORD_4
…
Byte Type
Description
UDW7[5:2] = 0000 (undefined bits set to 0)
UDW8[5:2] = 0000 (undefined bits set to 0)
UDW9[5:2] = 0000 (undefined bits set to 0)
UDW10[5:2] = 0000 (undefined bits set to 0)
For byte mode,
FC0
FC1
FC2
DB1
Framing Code[23:16]
Framing Code[15:8]
Framing Code[7:0]
First data byte
…
…
VBI_WORD_N + 3
DBn
Last (nth) data byte
UDW5[9:2] = 0010_0111
VDP Framing Code
The length of the actual framing code depends on the VBI data
standard. For uniformity, the length of the framing code reported
in the ancillary data stream is always 24 bits. For standards with
a smaller framing code length, the extra LSB bits are set to 0.
The valid length of the framing code can be decoded from the
VBI_DATA_STD bits available in ID0 (UDW 1). The framing
code is always reported in the inverse-transmission order.
UDW6[9:2] = 0000_0000 (undefined bits set to 0)
UDW7[9:2] = 0000_0000 (undefined bits set to 0)
Table 83 shows the framing code and its valid length for VBI
data standards supported by VDP.
Rev. A | Page 53 of 96
ADV7182
Data Sheet
The data bytes in the ancillary data stream are as follows:
Data Bytes
VBI_WORD_4 = Byte 1[7:0]
VBI_WORD_5 = Byte 2[7:0]
VBI_WORD_4 to VBI_WORD_N + 3 contain the data-words
that were decoded by the VDP in the transmission order. The
position of bits in bytes is in the inverse transmission order.
The number of VBI_WORDS for each VBI data standard and
the total number of UDWs in the ancillary data stream is shown
in Table 84.
For example, closed captioning has two user data bytes, as
shown in Table 88.
Table 83. Framing Code Sequence for Different VBI Standards
Error-Free Framing Code Bits
(in Order of Transmission)
Error-Free Framing Code Reported by
VDP (in Reverse Order of Transmission)
VBI Standard
Length in Bits
TTXT_SYSTEM_A (PAL)
TTXT_SYSTEM_B (PAL)
TTXT_SYSTEM_B (NTSC)
TTXT_SYSTEM_C (PAL and NTSC)
TTXT_SYSTEM_D (PAL and NTSC)
WSS (PAL)
8
8
8
8
8
24
3
11100111
11100100
11100100
11100111
11100101
000111100011110000011111
001
0
11100111
00100111
00100111
11100111
10100111
111110000011110001111000
100
0
CCAP (NTSC and PAL)
CGMS (NTSC)
1
Table 84. Total User Data-Words for Different VBI Standards1
VBI Standard
ADF Mode
Framing Code UDWs VBI Data-Words No. of Padding Words Total UDWs
TTXT_SYSTEM_A (PAL)
00 (nibble mode)
01, 10 (byte mode)
00 (nibble mode)
01, 10 (byte mode)
00 (nibble mode)
01, 10 (byte mode)
6
3
6
3
6
3
6
3
6
3
6
3
6
3
6
3
74
37
84
42
68
34
66
33
68
34
4
0
0
2
3
2
3
0
2
2
3
2
3
2
3
0
2
84
44
96
52
80
44
76
42
80
44
16
12
16
12
16
12
TTXT_SYSTEM_B (PAL)
TTXT_SYSTEM_B (NTSC)
TTXT_SYSTEM_C (PAL and NTSC) 00 (nibble mode)
01, 10 (byte mode)
TTXT_SYSTEM_D (PAL and NTSC) 00 (nibble mode)
01, 10 (byte mode)
WSS (PAL)
00 (nibble mode)
01, 10 (byte mode)
00 (nibble mode)
01, 10 (byte mode)
00 (nibble mode)
01, 10 (byte mode)
2
4
2
6
CCAP (NTSC and PAL)
CGMS (NTSC)
3 + 3
1 The first four UDWs are always the ID.
Rev. A | Page 54 of 96
Data Sheet
ADV7182
I2C Interface
WSS_CGMS_CB_CHANGE, Enable Content-Based
Dedicated I2C readback registers are available for CCAP, CGMS,
and WSS. Because teletext is a high data rate standard, data
extraction is supported only through the ancillary data packet.
User Interface for I2C Readback Registers
Updating for WSS/CGMS, Address 0x9C[4],
Interrupt/VDP Map
Setting WSS_CGMS_CB_CHANGE to 0 disables content-based
updating.
Setting WSS_CGMS_CB_CHANGE to 1 (default) enables
content-based updating.
VDP—Interrupt-Based Reading of VDP I2C Registers
The VDP decodes all enabled VBI data standards in real-time.
Because the I2C access speed is much lower than the decoded
rate, when the registers are accessed, they may be updated with
data from the next line. To avoid this, VDP has a self-clearing
clear bit and an available (AVL) status bit accompanying all I2C
readback registers.
The user must clear the I2C readback register by writing a high to
the clear bit. This resets the state of the available bit to low and
indicates that the data in the associated readback registers is not
valid. After the VDP decodes the next line of the corresponding
VBI data, the decoded data is placed into the I2C readback register,
and the available bit is set to high to indicate that valid data is
now available.
Some VDP status bits are also linked to the interrupt request
controller so that the user does not have to poll the available status
bit. The user can configure the video decoder to trigger an
INTRQ
interrupt request on the
pin in response to the valid
data available in the I2C registers. This function is available for
the following data types: CGMS or WSS. The user can select
either triggering an interrupt request each time sliced data is
available or triggering an interrupt request only when the sliced
data has changed. Selection is made via the WSS_CGMS_CB_
CHANGE bit.
The sequence for the interrupt-based reading of the VDP I2C data
registers is as follows for the CCAP standard:
Though the VDP decodes this VBI data in subsequent lines, if
present, the decoded data is not updated to the readback registers
until the clear bit is set high again. However, this data is
available through the 656 ancillary data packets.
1. The user unmasks the CCAP interrupt mask bit (Register 0x50,
Bit 0, Interrupt/VDP Map = 1). CCAP data occurs on the
incoming video. VDP slices CCAP data and places it into
the VDP readback registers.
2. The VDP CCAP available bit, VDP_CCAPD_Q, goes high,
and the VDP module signals to the interrupt controller to
stimulate an interrupt request (for CCAP in this case).
3. The user reads the interrupt status bits (Interrupt/VDP
Map) and sees that new CCAP data is available (Register
0x4E, Bit 0, Interrupt/VDP Map = 1).
The clear and available bits are in the VDP_STATUS_CLEAR
(0x78, Interrupt/VDP Map, write only) and VDP_STATUS
(0x78, Interrupt/VDP Map, read only) registers, respectively.
VDP—Content-Based Data Update
For certain standards such as WSS and CGMS, the information
content in the signal transmitted remains the same over numerous
lines, and the user may want to be notified only when there is a
change in the information content or loss of the information
content. The user must enable content-based updating for the
required standard through the WSS_CGMS_CB_CHANGE bit.
This bit shows the availability of WSS and CGMS information
only when its content has changed.
4. The user writes 1 to the CCAP interrupt clear bit (Register 0x4F,
Bit 0, Interrupt/VDP Map = 1) in the interrupt I2C space (this
INTRQ
is a self-clearing bit). This clears the interrupt on the
pin but does not have an effect in the VDP I2C area.
5. The user reads the CCAP data from the VDP I2C area.
6. The user writes to Bit CC_CLEAR in the
VDP_STATUS_CLEAR register, (Register 0x78, Bit 0,
User Sub Map 2 = 1) to signify that the CCAP data has
been read (therefore the VDP CCAP can be updated at the
next occurrence of CCAP).
Content-based updating also applies to lines with lost data.
Therefore, for standards like CGMS and WSS, if no data arrives in
the next four lines programmed, the corresponding available bit
in the VDP_STATUS register is set high, and the content in the
I2C registers for that standard is set to 0. The user must write
high to the corresponding clear bit so that when a valid line is
decoded after some time, the decoded results are available in the
I2C registers, with the available status bit set high.
7. The user goes back to Step 2.
If content-based updating is enabled, the available bit is set high
(assuming the clear bit was written) in the following cases:
•
•
The data contents have changed.
Data was being decoded and four lines with no data have
been detected.
•
No data was being decoded, and new data is now being
decoded.
Rev. A | Page 55 of 96
ADV7182
Data Sheet
I2C READBACK REGISTERS
Interrupt Mask Register Details
The following bits set the interrupt mask on the signal from the
VDP VBI data slicer.
Teletext
Because teletext is a high data rate standard, the decoded bytes
are available only as ancillary data. However, a TTXT_AVL bit
has been provided in I2C so that the user can check whether the
VDP has detected teletext. Note that the TTXT_AVL bit is a
plain status bit and does not use the protocol identified in the
I2C Interface section.
VDP_CCAPD_MSK
, Address 0x50[0], Interrupt/VDP Map
VDP_CCAPD_MSK
Setting
to 0 (default) masks (disables) the
interrupt on the VDP_CCAPD_Q signal.
VDP_CCAPD_MSK
Setting
to 1 unmasks (enables) the
interrupt on the VDP_CCAPD_Q signal.
TTXT_AVL, Teletext Detected Status, Address 0x78[7],
Interrupt/VDP Map, Read Only
VDP_CGMS_WSS_CHNGD_MSK
Interrupt/VDP Map
, Address 0x50[2],
When TTXT_AVL is 0, teletext was not detected.
When TTXT_AVL is 1, teletext was detected.
WST Packet Decoding
VDP_CGMS_WSS_CHNGD_MSK
Setting
to 0 (default) masks
(disables) the interrupt on the VDP_CGMS_WSS_ CHNGD_Q
signal.
For WST only, the VDP decodes the magazine and row address
of teletext packets and further decodes the packet’s 8 × 4
hamming coded words. This feature can be disabled using the
WST_PKT_DECODE_DISABLE bit (Bit 3, Register 0x60, user
sub map). This feature is valid for WST only.
VDP_CGMS_WSS_CHNGD_MSK
(enables) the interrupt on the VDP_CGMS_WSS_CHNGD_Q
signal.
Setting
to 1 unmasks
Interrupt Status Register Details
The following read-only bits contain data detection information
from the VDP module since the status bit was last cleared or
unmasked.
WST_PKT_DECODE_DISABLE, Disable Hamming
Decoding of Bytes in WST, Address 0x60[3],
Interrupt/VDP Map
VDP_CCAPD_Q, Address 0x4E[0], Interrupt/VDP Map
Setting WST_PKT_DECODE_DISABLE to 0 enables hamming
decoding of WST packets.
When VDP_CCAPD_Q is 0 (default), CCAP data has not been
detected.
Setting WST_PKT_DECODE_DISABLE to 1 (default) disables
hamming decoding of WST packets.
When VDP_CCAPD_Q is 1, CCAP data has been detected.
For hamming-coded bytes, the de-hammed nibbles are output
along with some error information from the hamming decoder
as follows:
VDP_CGMS_WSS_CHNGD_Q, Address 0x4E[2],
Interrupt/VDP Map
When VDP_CGMS_WSS_CHNGD_Q is 0 (default), CGMS or
WSS data has not been detected.
•
Input hamming coded byte: {D3, P3, D2, P2, D1, P1, D0, P0}
(bits in decoded order)
VDP_CGMS_WSS_CHNGD_Q is also 0 if the CGMS or WSS
data state has not changed since last cleared (see Interrupt
Status Clear Register Details).
•
Output dehammed byte: {E1, E0, 0, 0, D3', D2', D1', D0'}
(Di' – corrected bits, Ei error information).
When VDP_CGMS_WSS_CHNGD_Q is 1, CGM or WSS data
has been detected.
Table 85. Error Bits in the Dehammed Output Byte
Output Data Bits
in Nibble
E[1:0] Error Information
Interrupt Status Clear Register Details
00
01
10
11
No errors detected
Error in P4
Double error
Okay
Okay
Bad
It is not necessary to write 0 to these write-only bits because
they automatically reset after they have been set to 1 (self-clearing).
VDP_CCAPD_CLR, Address 0x4F[0],
Interrupt/VDP Map
Single error found and corrected
Okay
Table 86 describes the WST packets that are decoded.
Setting VDP_CCAPD_CLR to 1 clears the VDP_CCAP_Q bit.
VDP_CGMS_WSS_CHNGD_CLR, Address 0x4F[2],
Interrupt/VDP Map
Setting VDP_CGMS_WSS_CHNGD_CLR to 1 clears the
VDP_CGMS_WSS_CHNGD_Q bit.
Rev. A | Page 56 of 96
Data Sheet
ADV7182
Table 86. WST Packet Description
Packet
Byte
Description
Header Packet (X/00)
1st
2nd
3rd
4th
5th to 10th
11th to 42nd
1st
2nd
3rd to 42nd
1st
2nd
3rd
4th to 10th
11th to 23rd
24th to 42nd
1st
2nd
3rd
4th to 10th
11th to 23rd
24th to 42nd
1st
Magazine number—Dehammed Byte 4
Row number—Dehammed Byte 5
Page number—Dehammed Byte 6
Page number—Dehammed Byte 7
Control bytes—Dehammed Byte 8 to Byte 13
Raw data bytes
Text Packets (X/01 to X/25)
Magazine number—Dehammed Byte 4
Row number—Dehammed Byte 5
Raw data bytes
8/30 (Format 1) Packet
Design Code = 0000 or 0001
UTC
Magazine number—Dehammed Byte 4
Row number—Dehammed Byte 5
Design code—Dehammed Byte 6
De-hammed initial teletext page, Byte 7 to Byte 12
UTC bytes—Dehammed Byte 13 to Byte 25
Raw status bytes
8/30 (Format 2) Packet
Design Code = 0010 or 0011
PDC
Magazine number—Dehammed Byte 4
Row number—Dehammed Byte 5
Design code—Dehammed Byte 6
Dehammed initial teletext page, Byte 7 to Byte 12
PDC bytes—Dehammed Byte 13 to Byte 25
Raw status bytes
X/26, X/27, X/28, X/29, X/30, X/311
Magazine number—Dehammed Byte 4
Row number—Dehammed Byte 5
Design code—Dehammed Byte 6
Raw data bytes
2nd
3rd
4th to 42nd
1 For X/26, X/28, and X/29, further decoding needs 24 × 18 hamming decoding. Not supported at present.
VDP_CGMS_WSS_
VDP_CGMS_WSS_DATA_2 DATA_1[5:0]
0
1
2
3
4
5
6
7
0
1
2
3
4
5
RUN-IN
SEQUENCE
START
CODE
ACTIVE
VIDEO
11.0µs
38.4µs
42.5µs
Figure 42. WSS Waveform
CGMS and WSS
CGMS_WSS_AVL, CGMS/WSS Available, Address 0x78[2],
User Sub Map, Read Only
The CGMS and WSS data packets convey the same type of
information for different video standards. WSS is for PAL and
CGMS is for NTSC; therefore, the CGMS and WSS readback
registers are shared. WSS is biphase coded; the VDP performs a
biphase decoding to produce the 14 raw WSS bits in the CGMS/
WSS readback I2C registers and to set the CGMS_WSS_AVL bit.
When CGMS_WSS_AVL is 0, CGMS/WSS was not detected.
When CGMS_WSS_AVL is 1, CGMS/WSS was detected.
VDP_CGMS_WSS_DATA_0[3:0], Address 0x7D[3:0];
VDP_CGMS_WSS_DATA_1[7:0], Address 0x7E[7:0];
CGMS_WSS_CLEAR, CGMS/WSS Clear, Address 0x78[2],
Interrupt/VDP Map, Write Only, Self-Clearing
VDP_CGMS_WSS_DATA_2[7:0], Address 0x7F[7:0];
Interrupt/VDP Map, Read Only
Setting CGMS_WSS_CLEAR to 0 does not reinitialize the
CGMS/WSS readback registers.
These bits hold the decoded CGMS or WSS data.
Refer to Figure 42 and Figure 43 for the I2C-to-WSS and I2C-to-
CGMS bit mapping.
Setting CGMS_WSS_CLEAR to 1 reinitializes the CGMS/WSS
readback registers.
Rev. A | Page 57 of 96
ADV7182
Data Sheet
+100 IRE
VDP_CGMS_WSS_
DATA_0[3:0]
REF
VDP_CGMS_WSS_DATA_2
VDP_CGMS_WSS_DATA_1
+70 IRE
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
0 IRE
49.1µs ± 0.5µs
–40 IRE
11.2µs
CRC SEQUENCE
2.235µs ± 20ns
Figure 43. CGMS Waveform
Table 87. CGMS Readback Registers (These registers are readback registers; default value does not apply.)
Signal Name
Register Location
Dec
125
126
127
Hex
CGMS_WSS_DATA_0[3:0]
CGMS_WSS_DATA_1[7:0]
CGMS_WSS_DATA_2[7:0]
VDP_CGMS_WSS_DATA_0[3:0]
VDP_CGMS_WSS_DATA_1[7:0]
VDP_CGMS_WSS_DATA_2[7:0]
0x7D
0x7E
0x7F
10.5µs ± 0.25µs
12.91µs
7 CYCLES
OF 0.5035MHz
(CLOCK RUN-IN)
0 1 2 3 4 5 6
7
0 1 2 3 4
5
6
7
S
T
A
R
T
P
A
R
I
T
Y
P
A
R
I
T
Y
50 IRE
40 IRE
VDP_CCAP_DATA_0
VDP_CCAP_DATA_1
REFERENCE COLOR BURST
(9 CYCLES)
FREQUENCY = f = 3.579545MHz
SC
AMPLITUDE = 40 IRE
10.003µs
27.382µs
33.764µs
Figure 44. CCAP Waveform and Decoded Data Correlation
Table 88. CCAP Readback Registers (These registers are readback registers; default value does not apply.)
Signal Name
Register Location
Dec
121
122
Hex
CCAP_BYTE_1[7:0]
CCAP_BYTE_2[7:0]
VDP_CCAP_DATA_0[7:0]
VDP_CCAP_DATA_1[7:0]
0x79
0x7A
CCAP
CC_EVEN_FIELD, Address 0x78[1], Interrupt/VDP Map,
Read Only
Two bytes of decoded closed caption data are available in the
I2C registers. The field information of the decoded CCAP data
can be obtained from the CC_EVEN_FIELD bit (Register 0x78).
Identifies the field from which the CCAP data was decoded.
When CC_EVEN_FIELD is 0, closed captioning was detected
from an odd field.
CC_CLEAR, Closed Caption Clear, Address 0x78[0],
Interrupt/VDP Map, Write Only, Self-Clearing
When CC_EVEN_FIELD is 1, closed captioning was detected
from an even field.
Setting CC_CLEAR to 0 does not reinitializes the CCAP
readback registers.
VDP_CCAP_DATA_0, Address 0x79[7:0], Interrupt/VDP
Map, Read Only
Setting CC_CLEAR to 1 reinitializes the CCAP readback
registers.
Decoded Byte 1 of CCAP data.
CC_AVL, Closed Caption Available, Address 0x78[0],
Interrupt/VDP Map, Read Only
VDP_CCAP_DATA_1, Address 0x7A[7:0], Interrupt/VDP
Map, Read Only
When CC_AVL is 0, closed captioning is not detected.
When CC_AVL is 1, closed captioning is detected.
Decoded Byte 2 of CCAP data.
Rev. A | Page 58 of 96
Data Sheet
ADV7182
Letterbox Detection
LB_LCT[7:0], Letterbox Line Count Top, Address 0x9B[7:0];
LB_LCM[7:0], Letterbox Line Count Mid, Address 0x9C[7:0];
LB_LCB[7:0], Letterbox Line Count Bottom, Address 0x9D[7:0]
Incoming video signals may conform to different aspect ratios
(16:9 wide screen or 4:3 standard). For certain transmissions in
the wide-screen format, a digital sequence (WSS) is transmitted
with the video signal. If a WSS sequence is provided, the aspect
ratio of the video can be derived from the digitally decoded bits
that WSS contains.
Table 89. LB_LCx Access Information
Signal Name
LB_LCT[7:0]
LB_LCM[7:0]
LB_LCB[7:0]
Address
0x9B
0x9C
0x9D
In the absence of a WSS sequence, letterbox detection can be
used to find wide-screen signals. The detection algorithm examines
the active video content of lines at the start and end of a field. If
black lines are detected, this may indicate that the currently
shown picture is in wide-screen format.
LB_TH[4:0], Letterbox Threshold Control,
Address 0xDC[4:0]
Table 90. LB_TH Function
The active video content (luminance magnitude) over a line of
video is summed together. At the end of a line, this accumulated
value is compared with a threshold, and a decision is made as to
whether or not a particular line is black. The threshold value
needed may depend on the type of input signal; some control is
provided via LB_TH[4:0].
LB_TH[4:0]
Description
01100 (default)
01101 to 10000
Default threshold for detection of black lines
Increase threshold (need larger active video
content before identifying nonblack lines)
Decrease threshold (even small noise levels
can cause the detection of nonblack lines)
00000 to 01011
Detection at the Start of a Field
LB_SL[3:0], Letterbox Start Line, Address 0xDD[7:4]
The ADV7182 expects a section of at least six consecutive black
lines of video at the top of a field. After those lines are detected,
LB_LCT[7:0] reports the number of black lines that were actually
found. By default, the ADV7182 starts looking for those black
lines in sync with the beginning of active video, for example,
immediately after the last VBI video line. LB_SL[3:0] allows the
user to set the start of letterbox detection from the beginning of
a frame on a line-by-line basis. The detection window closes in
the middle of the field.
The LB_SL[3:0] bits are set at 1100 by default. For an NTSC
signal, this window is from Line 31 to Line 294.
By changing the bits to 0100, the detection window starts on
Line 23 and ends on Line 286.
LB_EL[3:0], Letterbox End Line, Address 0xDD[3:0]
The LB_EL[3:0] bits are set at 1100 by default. This means that the
letterbox window ends with the last active video line. For an NTSC
signal, this window is from Line 261 to Line 524.
Detection at the End of a Field
By changing the bits to 1101, the detection window starts on
Line 262 and ends on Line 255.
The ADV7182 expects at least six continuous lines of black video
at the bottom of a field before reporting the number of lines
actually found via the LB_LCB[7:0] value. The activity window
for letterbox detection (end of field) starts in the middle of an
active field. Its end is programmable via LB_EL[3:0].
Detection at the Midrange
Some transmissions of wide-screen video include subtitles
within the lower black box. If the ADV7182 finds at least two
black lines followed by some more nonblack video, for example, the
subtitle followed by the remainder of the bottom black block, it
reports a midcount via LB_LCM[7:0]. If no subtitles are found,
LB_LCM[7:0] reports the same number as LB_LCB[7:0].
There is a two-field delay in reporting any line count parameter.
There is no letterbox detected bit. Read the LB_LCT[7:0] and
LB_LCB[7:0] register values to determine whether the letterbox-
type video is present in the software.
Rev. A | Page 59 of 96
ADV7182
Data Sheet
PIXEL PORT CONFIGURATION
The ADV7182 has a very flexible pixel port that can be configured
in a variety of formats to accommodate downstream ICs. The
ordering of components, for example, Cr vs. Cb can be changed.
See the SWPC, Swap Pixel Cr/Cb, Address 0x27[7] section.
LLC_PAD_SEL[2:0] LLC Output Selection,
Address 0x8F[6:4]
The following I2C write allows the user to select between LLC
(nominally at 27 MHz) and LLC (nominally at 13.5 MHz).
SWPC, Swap Pixel Cr/Cb, Address 0x27[7]
The LLC signal is useful for LLC-compatible wide bus (16-bit)
output modes. The LLC signal and data on the data bus are
synchronized. By default, the rising edge of LLC/LLC is aligned
with the Y data; the falling edge occurs when the data bus holds
C data. The polarity of the clock, and therefore the Y/C
assignments to the clock edges, can be altered by using the
polarity LLC pin.
This bit allows Cr and Cb samples to be swapped.
When SWPC is 0 (default), no swapping is allowed. When SWPC
is 1, the Cr and Cb values can be swapped.
When LLC_PAD_SEL is 000, the output is nominally 27 MHz
LLC on the LLC pin (default).
When LLC_PAD_SEL is 101, the output is nominally 13.5 MHz
LLC on the LLC pin.
Rev. A | Page 60 of 96
Data Sheet
ADV7182
MPU PORT DESCRIPTION
The ADV7182 supports a 2-wire (I2C-compatible) serial interface.
Two inputs, serial data (SDATA) and serial clock (SCLK), carry
information between the ADV7182 and the system I2C master
controller. Each slave device is recognized by a unique address.
The ADV7182 I2C port allows the user to set up and configure
the decoder and to read back the captured VBI data. The
ADV7182 has four possible slave addresses for both read and
write operations, depending on the logic level of the ALSB pin.
The four unique addresses are shown in Table 91. The ADV7182
ALSB pin controls Bit 1 of the slave address. By altering the
ALSB, it is possible to control two ADV7182s in an application
without the conflict of using the same slave address. The LSB
(Bit 0) sets either a read or write operation. Logic 1 corresponds to
a read operation, and Logic 0 corresponds to a write operation.
bit determines the direction of the data. Logic 0 on the LSB of
the first byte means that the master writes information to the
peripheral. Logic 1 on the LSB of the first byte means that the
master reads information from the peripheral.
The ADV7182 acts as a standard slave device on the bus. The
data on the SDATA pin is eight bits long, supporting the 7-bit
W
address plus the R/ bit. The device has subaddresses to enable
access to the internal registers. It, therefore, interprets the first
byte as the device address and the second byte as the starting
subaddress. The subaddresses auto-increment, allowing data to
be written to or read from the starting subaddress. A data transfer
is always terminated by a stop condition. The user can also
access any unique subaddress register on a one-by-one basis
without updating all the registers.
Table 91. I2C Address for ADV7182
Stop and start conditions can be detected at any stage during the
data transfer. If these conditions are asserted out of sequence with
normal read and write operations, they cause an immediate jump
to the idle condition. During a given SCLK high period, only issue
one start condition, one stop condition, or a single stop condition
followed by a single start condition. If an invalid subaddress is
issued, the ADV7182 does not issue an acknowledge and returns to
the idle condition.
R/W
ALSB
Slave Address
0x40
0x41
0x42
0x43
0
0
1
1
0
1
0
1
To control the device on the bus, a specific protocol must be
followed. First, the master initiates a data transfer by establishing a
start condition, which is defined by a high-to-low transition on
SDATA while SCLK remains high. This indicates that an address/
data stream follows. All peripherals respond to the start condition
In autoincrement mode, if the user exceeds the highest subaddress,
the following action is taken:
In read mode, the highest subaddress register contents
continue to be output until the master device issues a
no acknowledge. This indicates the end of a read. A no
acknowledge condition occurs when the SDATA line is
not pulled low on the ninth pulse.
W
and shift the next eight bits (the 7-bit address plus the R/ bit).
The bits are transferred from MSB down to LSB. The peripheral
that recognizes the transmitted address responds by pulling the
data line low during the ninth clock pulse; this is known as an
acknowledge bit. All other devices withdraw from the bus at
this point and maintain an idle condition. The idle condition is
where the device monitors the SDATA and SCLK lines for the
In write mode, the data for the invalid byte is not loaded
into any subaddress register. A no acknowledge is issued by
the ADV7182, and the part returns to the idle condition.
W
start condition and the correct transmitted address. The R/
SDATA
SCLK
S
P
1–7
8
9
1–7
8
9
1–7
DATA
8
9
START ADDR R/W ACK SUBADDRESS ACK
ACK
STOP
Figure 45. Bus Data Transfer
WRITE
S
S
SLAVE ADDR A(S) SUB ADDR
LSB = 0
A(S)
DATA
A(S)
DATA
A(M)
A(S) P
SEQUENCE
LSB = 1
READ
SEQUENCE
SLAVE ADDR A(S) SUB ADDR
A(S)
S
SLAVE ADDR A(S)
DATA
DATA
A(M) P
S = START BIT
P = STOP BIT
A(S) = ACKNOWLEDGE BY SLAVE
A(M) = ACKNOWLEDGE BY MASTER
A(S) = NO ACKNOWLEDGE BY SLAVE
A(M) = NO ACKNOWLEDGE BY MASTER
Figure 46. Read and Write Sequence
Rev. A | Page 61 of 96
ADV7182
Data Sheet
Register Select (SR7 to SR0)
REGISTER ACCESS
These bits are set up to point to the required starting address.
I2C SEQUENCER
The MPU can write to or read from all of the ADV7182 registers
except the subaddress register, which is write only. The subaddress
register determines which register the next read or write operation
accesses. All communications with the part through the bus
start with an access to the subaddress register. A read/write
operation is then performed from or to the target address, which
increments to the next address until a stop command on the bus
is performed. Note that only the registers listed in the I2C Register
Maps section are supported.
An I2C sequencer is used when a parameter exceeds eight bits
and is, therefore, distributed over two or more I2C registers, for
example, HSB[10:0].
When such a parameter is changed using two or more I2C write
operations, the parameter can hold an invalid value for the time
between the first I2C being completed and the last I2C being
completed. In other words, the top bits of the parameter may
hold the new value while the remaining bits of the parameter still
hold the previous value.
To avoid this problem, the I2C sequencer holds the updated bits
of the parameter in local memory, and all bits of the parameter
are updated together once the last register write operation has
completed.
REGISTER PROGRAMMING
The following sections describe the configuration for each
register. The communication register is an 8-bit, write-only
register. After the part is accessed over the bus and a read/write
operation is selected, the subaddress is set up. The subaddress
register determines to or from which register the operation
takes place.
The correct operation of the I2C sequencer relies on the following:
SUB_USR_EN, Address 0x0E[6:5]
•
All I2C registers for the parameter in question must be
written to in order of ascending addresses. For example, for
HSB[10:0], write to Address 0x34 first, followed by 0x35,
and so on.
The ADV7182 has three I2C maps. The main register map (see
Table 92) is the map that is available by default. The other two
maps are accessed using the SUB_USR_EN bit (Address 0x0E).
When programming of these maps is completed, it is necessary
to write to the SUB_USR_EN bit to return to the main register
map (see Table 92).
•
No other I2C can take place between the two (or more) I2C
writes for the sequence. For example, for HSB[10:0], write to
Address 0x34 first, immediately followed by 0x35, and so on.
0x0E[6:5] = 00b
0x0E[6:5] = 01b
0x0E[6:5] = 10b
MAIN REGISTER
MAP
INTERRUPT/VDP
MAP
USER SUB MAP
2
Figure 47. Register Access—Main Register Map, Interrupt/VDP Map, and User
Sub Map 2
Rev. A | Page 62 of 96
Data Sheet
ADV7182
I2C REGISTER MAPS
To access all the registers listed in Table 92, SUB_USR_EN in Register Address 0x0E must be programmed to 00b. All read only registers
are left blank.
Table 92. Main Register Map Details
Address
Reset
Value
Dec Hex Register Name
RW
RW
RW
7
6
5
4
3
2
1
0
(Hex)
0
00 Input control
INSEL[4]
INSEL[3]
ENVSPROC
INSEL[2]
INSEL[1]
INSEL[0]
00001110 0E
11001000 C8
00000100 04
01001100 4C
00110101 35
1
01 Video Selection 1
02 Video Selection 2
03 Output control
ENHSPLL
VID_SEL[2]
TOD
BETACAM
VID_SEL[1]
2
RW VID_SEL[3]
RW VBI_EN
VID_SEL[0]
3
4
04 Extended output control RW BT.656-4
05 Reserved
TIM_OE
BL_C_VBI
EN_SFL_PIN
Range
5
6
06 Reserved
7
07 Autodetect enable
08 Contrast
RW AD_SEC525_EN AD_SECAM_EN
AD_N443_EN
CON[5]
AD_P60_EN
CON[4]
AD_PALN_EN
CON[3]
AD_PALM_EN AD_NTSC_EN
AD_PAL_EN
CON[0]
01111111 7F
10000000 80
8
RW CON[7]
CON[6]
CON[2]
CON[1]
9
09 Reserved
10
11
12
0A Brightness Adjust
0B Hue Adjust
RW BRI[7]
BRI[6]
BRI[5]
BRI[4]
BRI[3]
BRI[2]
BRI[1]
BRI[0]
00000000 00
00000000 00
00110110 36
RW HUE[7]
RW DEF_Y[5]
HUE[6]
DEF_Y[4]
HUE[5]
DEF_Y[3]
HUE[4]
DEF_Y[2]
HUE[3]
DEF_Y[1]
HUE[2]
DEF_Y[0]
HUE[1]
HUE[0]
0C Default Value Y
DEF_VAL_
AUTO_EN
DEF_VAL_EN
13
14
15
16
17
18
19
20
0D Default Value C
0E ADI Control 1
0F Power management
10 Status 1
RW DEF_C[7]
RW
DEF_C[6]
DEF_C[5]
DEF_C[4]
DEF_C[3]
DEF_C[2]
DEF_C[1]
DEF_C[0]
01111100 7C
00000000 00
00100000 20
SUB_USR_EN[1]
SUB_USR_EN[0]
PWRDWN
RW Reset
R
COL_KILL
IDENT[7]
AD_RESULT[2]
IDENT[6]
AD_RESULT[1] AD_RESULT[0]
FOLLOW_PW
IDENT[3]
FSC_LOCK
IDENT[2]
LOST_LOCK
IDENT[1]
IN_LOCK
11 IDENT
R
IDENT[5]
IDENT[4]
IDENT[0]
00011100 1C
12 Status 2
R
FSC NSTD
STD FLD LEN
LL NSTD
MV AGC DET
Reserved
MV PS DET
SD_OP_50Hz
MVCS T3
Reserved
MVCS DET
INST_HLOCK
13 Status 3
R
PAL_SW_LOCK Interlaced
DCT[1]
FREE_RUN_ACT
CCLEN
14 Analog clamp control
RW
FREE_RUN_
PAT_SEL.2
FREE_RUN_
PAT_SEL.1
FREE_RUN_
PAT_SEL.0
00010000 10
0000xxxx 00
21
22
23
24
25
29
39
43
44
45
45
46
46
47
47
48
48
49
50
51
52
53
54
55
56
57
58
15 Digital Clamp Control 1 RW
16 Reserved
DCT[0]
DCFE
17 Shaping Filter Control 1 RW CSFM[2]
18 Shaping Filter Control 2 RW WYSFMOVR
CSFM[1]
CSFM[0]
YSFM[4]
YSFM[3]
YSFM[2]
YSFM[1]
YSFM[0]
00000001 01
10010011 93
11110001 F1
11000xxx C0
01011000 58
11100001 E1
10101110 AE
11110100 F4
WYSFM[4]
WYSFM[3]
NSFSEL[1]
WYSFM[2]
NSFSEL[0]
WYSFM[1]
PSFSEL[1]
WYSFM[0]
PSFSEL[0]
19 Comb filter control
1D ADI Control 2
RW
RW TRI_LLC
RW SWPC
RW
27 Pixel delay control
2B Misc gain control
2C AGC mode control
2D Chroma Gain Control 1
2D Chroma Gain 1
AUTO_PDC_EN
CKE
CTA[2]
CTA[1]
CTA[0]
LTA[1]
LTA[0]
PW_UPD
CAGC[0]
CMG[8]
CG[8]
RW
LAGC[2]
CAGT[0]
LAGC[1]
LAGC[0]
CAGC[1]
CMG[9]
CG[9]
W
R
CAGT[1]
CMG[11]
CG[11]
CMG[3]
CG[3]
CMG[10]
CG[10]
CMG[2]
CG[2]
2E Chroma Gain Control 2
2E Chroma Gain 2
W
R
CMG[7]
CG[7]
CMG[6]
CG[6]
CMG[5]
CG[5]
CMG[4]
CG[4]
CMG[1]
CG[1]
CMG[0]
CG[0]
00000000 00
1111xxxx F0
xxxxxxxx 00
2F Luma Gain Control 1
2F Luma Gain 1
W
R
LAGT[1]
LAGT[0]
LMG[11]
LG[11]
LMG[3]
LG[3]
LMG[10]
LG[10]
LMG[2]
LG[2]
LMG[9]
LG[9]
LMG[8]
LG[8]
30 Luma Gain Control 2
30 Luma Gain 2
W
R
LMG[7]
LG[7]
LMG[6]
LG[6]
LMG[5]
LG[5]
LMG[4]
LMG[1]
LG[1]
LMG[0]
LG[0]
LG[4]
31 VS/FIELD Control 1
32 VS/FIELD Control 2
33 VS/FIELD Control 3
34 HS Position Control 1
35 HS Position Control 2
36 HS Position Control 3
37 Polarity
RW
NEWAVMODE
HVSTIM
00000010 02
01000001 41
10000100 84
00000000 00
00000010 02
00000000 00
00010001 09
10000000 80
11000000 C0
RW VSBHO
RW VSEHO
RW
VSBHE
VSEHE
HSB[10]
HSB[6]
HSE[6]
HSB[9]
HSB[5]
HSE[5]
PVS
HSB[8]
HSB[4]
HSE[4]
HSE[10]
HSB[2]
HSE[2]
HSE[9]
HSB[1]
HSE[1]
HSE[8]
HSB[0]
HSE[0]
PCLK
RW HSB[7]
RW HSE[7]
RW PHS
HSB[3]
HSE[3]
PF
38 NTSC comb control
39 PAL comb control
3A ADC control
RW CTAPSN[1]
RW CTAPSP[1]
RW
CTAPSN[0]
CTAPSP[0]
CCMN[2]
CCMP[2]
CCMN[1]
CCMP[1]
CCMN[0]
CCMP[0]
YCMN[2]
YCMP[2]
YCMN[1]
YCMP[1]
YCMN[0]
YCMP[0]
PWRDWN_MUX_0 PWRDWN_MUX PWRDWN_MUX MUX PDN override 00000000 00
_1
_2
61
65
77
78
80
81
96
3D Manual window control RW
CKILLTHR[2]
SFL_INV
CKILLTHR[1]
CKILLTHR[0]
00100010 22
00000001 01
11101111 EF
00001000 08
00001000 08
00100100 24
00010000 10
00000000 00
00010010 12
00000000 00
41 Resample control
4D CTI DNR Control 1
4E CTI DNR Control 2
RW
RW
DNR_EN
CTI_AB[1]
CTI_C_TH[3]
DNR_TH[3]
COL[0]
CTI_AB[0]
CTI_C_TH[2]
DNR_TH[2]
CIL[2]
CTI_AB_EN
CTI_C_TH[1]
DNR_TH[1]
CIL[1]
CTI_EN
RW CTI_C_TH[7]
CTI_C_TH[6]
DNR_TH[6]
SRLS
CTI_C_TH[5]
DNR_TH[5]
COL[2]
CTI_C_TH[4]
DNR_TH[4]
COL[1]
CTI_C_TH[0]
DNR_TH[0]
CIL[0]
50 DNR Noise Threshold 1 RW DNR_TH[7]
51 Lock count
RW FSCLE
60 ADC Switch 3
RW
RW
RW
W
MUX3[2]
MUX3[1]
MUX3[0]
106 6A Output Sync Select 1
107 6B Output Sync Select 2
143 8F Free-Run Line Length 1
HS_OUT_SEL[2] HS_OUT_SEL[1] HS_OUT_SEL[0]
FLD_OUT_SEL[2]
LLC_PAD_SEL[2]
FLD_OUT_SEL[1] FLD_OUT_SEL[0]
LLC_PAD_
SEL[1]
LLC_PAD_
SEL[0]
153 99 CCAP1
R
CCAP1[7]
CCAP1[6]
CCAP1[5]
CCAP1[4]
CCAP1[3]
CCAP1[2]
CCAP1[1]
CCAP1[0]
Rev. A | Page 63 of 96
ADV7182
Data Sheet
Address
Reset
Dec Hex Register Name
154 9A CCAP2
RW
R
7
6
5
4
3
2
1
0
Value
(Hex)
CCAP2[7]
LB_LCT[7]
LB_LCM[7]
LB_LCB[7]
CCAP2[6]
LB_LCT[6]
LB_LCM[6]
LB_LCB[6]
CCAP2[5]
LB_LCT[5]
LB_LCM[5]
LB_LCB[5]
CCAP2[4]
LB_LCT[4]
LB_LCM[4]
LB_LCB[4]
CCAP2[3]
LB_LCT[3]
LB_LCM[3]
LB_LCB[3]
CCAP2[2]
LB_LCT[2]
LB_LCM[2]
LB_LCB[2]
CRC_ENABLE
MUX0[2]
CCAP2[1]
LB_LCT[1]
LB_LCM[1]
LB_LCB[1]
CCAP2[0]
LB_LCT[0]
LB_LCM[0]
LB_LCB[0]
155 9B Letterbox 1
R
156 9C Letterbox 2
R
157 9D Letterbox 3
R
178 B2 CRC enable
W
00011100 1C
xxxxxxxx 00
0xxxxxxx 00
10101100 AC
01001100 4C
195 C3 ADC Switch 1
196 C4 ADC Switch 2
220 DC Letterbox Control 1
221 DD Letterbox Control 2
222 DE ST Noise Readback 1
223 DF ST Noise Readback 2
225 E1 SD offset Cb channel
226 E2 SD offset Cr channel
RW Reserved
MUX1[2]
MUX1[1]
MUX1[0]
Reserved
MUX0[1]
MUX0[0]
RW MAN_MUX_EN
Reserved
MUX2[2]
MUX2[1]
MUX2[0]
RW
LB_TH[4]
LB_SL[0]
LB_TH[3]
LB_TH[2]
LB_EL[2]
LB_TH[1]
LB_TH[0]
RW LB_SL[3]
R
LB_SL[2]
LB_SL[1]
LB_EL[3]
LB_EL[1]
LB_EL[0]
ST_NOISE_VLD
ST_NOISE[3]
SD_OFF_Cb[3]
SD_OFF_Cr[3]
SD_SAT_Cb[3]
SD_SAT_Cr[3]
NVBEG[3]
ST_NOISE[10]
ST_NOISE[2]
ST_NOISE[9]
ST_NOISE[1]
ST_NOISE[8]
ST_NOISE[0]
R
ST_NOISE[7]
ST_NOISE[6]
ST_NOISE[5]
ST_NOISE[4]
RW SD_OFF_Cb[7] SD_OFF_Cb[6]
RW SD_OFF_Cr[7] SD_OFF_Cr[6]
SD_OFF_Cb[5] SD_OFF_Cb[4]
SD_OFF_Cr[5] SD_OFF_Cr[4]
SD_SAT_Cb[5] SD_SAT_Cb[4]
SD_OFF_Cb[2] SD_OFF_Cb[1] SD_OFF_Cb[0]
SD_OFF_Cr[2] SD_OFF_Cr[1] SD_OFF_Cr[0]
SD_SAT_Cb[2] SD_SAT_Cb[1] SD_SAT_Cb[0]
10000000 80
10000000 80
10000000 80
10000000 80
00100101 25
00000100 04
01100011 63
01100101 65
00010100 14
01100011 63
01010101 55
01010101 55
00000000 00
227 E3 SD saturation Cb channel RW SD_SAT_Cb[7] SD_SAT_Cb[6]
228 E4 SD saturation Cr channel RW SD_SAT_Cr[7]
SD_SAT_Cr[6]
NVBEGDELE
NVENDDELE
NFTOGDELE
PVBEGDELE
PVENDDELE
PFTOGDELE
NVBIOLCM[0]
NVBIOCCM[0]
SD_SAT_Cr[5]
NVBEGSIGN
NVENDSIGN
NFTOGSIGN
PVBEGSIGN
PVENDSIGN
PFTOGSIGN
NVBIELCM[1]
NVBIECCM[1]
SD_SAT_Cr[4]
NVBEG[4]
SD_SAT_Cr[2]
NVBEG[2]
SD_SAT_Cr[1]
NVBEG[1]
SD_SAT_Cr[0]
NVBEG[0]
229 E5 NTSC V bit begin
230 E6 NTSC V bit end
231 E7 NTSC F bit toggle
232 E8 PAL V bit begin
233 E9 PAL V bit end
234 EA PAL F bit toggle
235 EB Vblank Control 1
236 EC Vblank Control 2
243 F3 AFE_CONTROL 1
RW NVBEGDELO
RW NVENDDELO
RW NFTOGDELO
RW PVBEGDELO
RW PVENDDELO
RW PFTOGDELO
RW NVBIOLCM[1]
RW NVBIOCCM[1]
RW
NVEND[4]
NFTOG[4]
NVEND[3]
NVEND[2]
NFTOG[2]
NVEND[1]
NFTOG[1]
NVEND[0]
NFTOG[0]
NFTOG[3]
PVBEG[4]
PVBEG[3]
PVBEG[2]
PVBEG[1]
PVBEG[0]
PVEND[4]
PVEND[3]
PVEND[2]
PVEND[1]
PVEND[0]
PFTOG[4]
PFTOG[3]
PFTOG[2]
PFTOG[1]
PFTOG[0]
NVBIELCM[0]
NVBIECCM[0]
PVBIOLCM[1]
PVBIOCCM[1]
AA_FILT_EN[3]
PVBIOLCM[0]
PVBIOCCM[0]
PVBIELCM[1]
PVBIECCM[1]
PVBIELCM[0]
PVBIECCM[0]
AA_FILT_MAN_
OVR
AA_FILT_EN[2] AA_FILT_EN[1] AA_FILT_EN[0]
244 F4 Drive strength
RW GLITCH_FILT_
BYP
DR_STR[1]
DR_STR[0]
DR_STR_C[1]
DR_STR_C[0]
DR_STR_S[1]
DR_STR_S[0]
0x010101 15
248 F8 IF comp control
249 F9 VS mode control
RW
RW
IFFILTSEL[2]
IFFILTSEL[1]
IFFILTSEL[0]
00000000 00
00000011 03
VS_COAST_
MODE[1]
VS_COAST_
MODE[0]
EXTEND_VS_
MIN_FREQ
EXTEND_VS_
MAX_FREQ
251 FB Peaking gain
RW PEAKING_
GAIN[7]
PEAKING_
GAIN[6]
PEAKING_
GAIN[5]
PEAKING_
GAIN[4]
PEAKING_
GAIN[3]
PEAKING_
GAIN[2]
PEAKING_
GAIN[1]
PEAKING_
GAIN[0]
01000000 40
252 FC DNR Noise Threshold 2 RW DNR_TH2[7]
254 FE CSI Tx slave address
DNR_TH2[6]
DNR_TH2[5]
DNR_TH2[4]
DNR_TH2[3]
DNR_TH2[2]
DNR_TH2[1]
DNR_TH2[0]
00000100 04
00000000 00
RW CSI_TX_SLAVE_ CSI_TX_SLAVE_
ADDR[6] ADDR[5]
CSI_TX_SLAVE_ CSI_TX_SLAVE_
ADDR[4]
CSI_TX_SLAVE_
ADDR[2]
CSI_TX_SLAVE_ CSI_TX_SLAVE_
ADDR[1] ADDR[0]
ADDR[3]
Rev. A | Page 64 of 96
Data Sheet
ADV7182
To access the registers listed in Table 93, SUB_USR_EN in Register Address 0x0E must be programmed to 10b. All read only registers are
left blank.
Table 93. User Sub Map 2 Register Map Details
Address
Reset
Value
Dec Hex Register Name
128 80 ACE Control 1
131 83 ACE Control 4
RW
7
6
5
4
3
2
1
0
(Hex)
RW ACE_ENABLE
RW
00000000 00
00001101 0D
ACE_LUMA_
GAIN[4]
ACE_LUMA_GAIN ACE_LUMA_
[3]
ACE_LUMA_
GAIN[1]
ACE_LUMA_
GAIN[0]
GAIN[2]
132 84 ACE Control 5
RW ACE_CHROMA_
MAX[3]
ACE_CHROMA_
MAX[2]
ACE_CHROMA_
MAX[1]
ACE_CHROMA_ ACE_CHROMA_
GAIN[3]
ACE_CHROMA_
GAIN[2]
ACE_CHROMA_ ACE_CHROMA_ 10001000 88
GAIN[1] GAIN[0]
MAX[0]
133 85 ACE Control 6
146 92 Dither control
217 D9 Min Max 0
218 DA Min Max 1
219 DB Min Max 2
220 DC Min Max 3
221 DD Min Max 4
222 DE Min Max 5
RW ACE_RESPONSE_ ACE_RESPONSE_ ACE_RESPONSE_ ACE_RESPONSE ACE_GAMMA_
SPEED[3] SPEED[2] SPEED[2] _SPEED[1] GAIN[3]
ACE_GAMMA_
GAIN[2]
ACE_GAMMA_ ACE_GAMMA_ 11111000 F8
GAIN[1]
GAIN[0]
RW
BR_DITHER_MO 00000000 00
DE
RW MIN_THRESH_Y[7] MIN_THRESH_Y[6] MIN_THRESH_Y[5] MIN_THRESH_ MIN_THRESH_Y[3] MIN_THRESH_Y[2] MIN_THRESH_ MIN_THRESH_ 00000000 00
Y[4] Y[1] Y[0]
RW MAX_THRESH_Y[7] MAX_THRESH_Y[6] MAX_THRESH_Y[5] MAX_THRESH_ MAX_THRESH_Y[3] MAX_THRESH_Y[2] MAX_THRESH_ MAX_THRESH_ 11111111 FF
Y[4] Y[1] Y[0]
RW MIN_THRESH_C[7] MIN_THRESH_C[6] MIN_THRESH_C[5] MIN_THRESH_ MIN_THRESH_C[3] MIN_THRESH_C[2] MIN_THRESH_ MIN_THRESH_ 00000000 00
C[4] C[1] C[0]
RW MAX_THRESH_C[7] MAX_THRESH_C[6] MAX_THRESH_C[5] MAX_THRESH_ MAX_THRESH_C[3] MAX_THRESH_C[2] MAX_THRESH_ MAX_THRESH_ 11111111 FF
C[4]
C[1]
C[0]
RW MIN_SAMPLES_
ALLOWED_Y[3]
MIN_SAMPLES_
ALLOWED_Y[2]
MIN_SAMPLES_
ALLOWED_Y[1]
MIN_SAMPLES_ MAX_SAMPLES_
ALLOWED_Y[0] ALLOWED_Y[3]
MAX_SAMPLES_
ALLOWED_Y[2]
MAX_SAMPLES MAX_SAMPLES 11001100 CC
_ALLOWED_Y[1] _ALLOWED_Y[0]
RW MIN_SAMPLES_
ALLOWED_C[3]
MIN_SAMPLES_
ALLOWED_C[2]
MIN_SAMPLES_
ALLOWED_C[1]
MIN_SAMPLES_ MAX_SAMPLES_
ALLOWED_C[0] ALLOWED_C[3]
MAX_SAMPLES_
ALLOWED_C[2]
MAX_SAMPLES_ MAX_SAMPLES_ 11001100 CC
ALLOWED_C[1] ALLOWED_C[0]
224 E0 FL control
225 E1 Y Average 0
226 E2 Y Average 1
227 E3 Y Average 2
RW
FL_ENABLE
00000000 00
RW LINE_START[8]
RW LINE_END[8]
LINE_START[7]
LINE_END[7]
LINE_START[6]
LINE_END[6]
LINE_START[5] LINE_START[4]
LINE_START[3]
LINE_END[3]
LINE_START[2] LINE_START[1] 0001001 11
LINE_END[5]
LINE_END[4]
LINE_END[2]
LINE_END[1]
10001000 88
00010111 1B
RW SAMPLE_START[9] SAMPLE_START[8] SAMPLE_START[7] SAMPLE_
START[6]
SAMPLE_START[5] SAMPLE_
START[4]
SAMPLE_
START[3]
SAMPLE_
START[2]
228 E4 Y Average 3
229 E5 Y Average 4
RW SAMPLE_END[9]
RW SAMPLE_END[1]
SAMPLE_END[8]
SAMPLE_END[0]
SAMPLE_END[7]
SAMPLE_END[6] SAMPLE_END[5]
SAMPLE_END[4]
SAMPLE_END[3] SAMPLE_END[2] 11010111 D7
LINE_END[0] LINE_START[0] 00100011 23
SAMPLE_START[1] SAMPLE_
START[0]
230 E6 Y Average 5
RW
Y_AVG_TIME_ Y_AVG_TIME_
CONST[2] CONST[1]
Y_AVG_TIME_
CONST[0]
Y_AVG_FILT_EN CAPTURE_
VALUE
00010000 10
231 E7 Y average data MSB
232 E8 Y average data LSB
R
R
Y_AVERAGE[9]
Y_AVERAGE[8]
Y_AVERAGE[7]
Y_AVERAGE[6] Y_AVERAGE[5]
Y_AVERAGE[4]
Y_AVERAGE[3] Y_AVERAGE[2]
Y_AVERAGE[1] Y_AVERAGE[0]
Rev. A | Page 65 of 96
ADV7182
Data Sheet
To access the registers listed in Table 94, SUB_USR_EN in Register Address 0x0E must be programmed to 01b. All read only registers are
left blank.
Table 94. Interrupt/VDP Map Details1
Address
Dec
Hex
Register Name
RW
7
6
5
4
3
2
1
0
Reset Value (Hex)
64
40
Interrupt
Configuration 1
RW
INTRQ_DUR_
SEL[1]
INTRQ_DUR_
SEL[0]
MV_INTRQ_
SEL[1]
MV_INTRQ_
SEL[0]
MPU_STIM_
INTRQ
INTRQ_OP_
SEL[1]
INTRQ_OP_SEL[0] 0001x000
10
66
67
42
43
Interrupt Status 1
Interrupt Clear 1
R
MV_PS_CS_Q
SD_FR_CHNG_Q
SD_UNLOCK_Q SD_LOCK_Q
W
MV_PS_CS_CLR SD_FR_CHNG_
CLR
SD_UNLOCK_
CLR
SD_LOCK_CLR
x0000000
00
00
68
69
70
71
72
44
45
46
47
48
Interrupt Mask 1
Raw Status 2
RW
R
MV_PS_CS_
MSKB2
SD_FR_CHNG_
MSKB2
SD_UNLOCK_
MSKB2
SD_LOCK_MSKB2 x0000000
CCAPD
MPU_STIM_
INTRQ
CHX_MIN_MAX_ EVEN_FIELD
INTRQ
Interrupt Status 2
Interrupt Clear 2
Interrupt Mask 2
R
MPU_STIM_
INTRQ_Q
SD_FIELD_
CHNGD_Q
CCAPD_Q
W
RW
MPU_STIM_
INTRQ_CLR
CHX_MIN_MAX_ SD_FIELD_
INTRQ_CLR
CCAPD_CLR
0xx00000
00
00
CHNGD_CLR
MPU_STIM_
CHX_MIN_MAX_ SD_FIELD_
CCAPD_MSKB2 0xx00000
INTRQ_MSKB2
INTRQ_MSKB2
CHNGD_MSKB2
73
74
49
4A
Raw Status 3
R
R
SCM_LOCK
SD_H_LOCK
SD_V_LOCK
SD_OP_50Hz
Interrupt Status 3
PAL_SW_LK_
CHNG_Q
SCM_LOCK_
CHNG_Q
SD_AD_CHNG_Q SD_H_LOCK_
CHNG_Q
SD_V_LOCK_
CHNG_Q
SD_OP_CHNG_Q
75
76
78
79
4B
4C
4E
4F
Interrupt Clear 3
Interrupt Mask 3
Interrupt Status 4
Interrupt Clear 4
W
RW
R
PAL_SW_LK_
CHNG_CLR
SCM_LOCK_
CHNG_CLR
SD_AD_CHNG_ SD_H_LOCK_
SD_V_LOCK_
CHNG_CLR
SD_OP_CHNG_ xx000000
CLR
00
00
CLR
CHNG_CLR
PAL_SW_LK_
CHNG_MSKB2
SCM_LOCK_
SD_AD_CHNG_ SD_H_LOCK_
SD_V_LOCK_
CHNG_MSKB2
SD_OP_CHNG_ xx000000
MSKB2
CHNG_MSKB2
MSKB2
CHNG_MSKB2
VDP_CGMS_
WSS_CHNGD_Q
VDP_CCAPD_Q
W
VDP_CGMS_
WSS_CHNGD_
CLR
VDP_CCAPD_CLR 00x0x0x0
00
00
80
50
Interrupt Mask 4
RW
VDP_CGMS_
WSS_CHNGD_
MSKB2
VDP_CCAPD_
MSKB2
00x0x0x0
81
96
51
60
Interrupt Latch 0
VDP_CONFIG_1
R
Y_CHANNEL_
Y_CHANNEL_
CB_CHANNEL_ CB_CHANNEL_ CR_CHANNEL_ CR_CHANNEL_
MIN_VIOLATION MAX_VIOLATION MIN_VIOLATION MAX_VIOLATION MIN_VIOLATION MAX_VIOLATION
RW
WST_PKT_
DECODE_
DISABLE
VDP_TTXT_
TYPE_MAN_
ENABLE
VDP_TTXT_
TYPE_MAN[1]
VDP_TTXT_
TYPE_MAN[0]
10001000
88
98
62
63
64
65
66
67
68
69
6A
6B
6C
6D
6E
6F
70
71
72
73
74
VDP_ADF_CONFIG RW
_1
ADF_ENABLE
ADF_MODE[1]
ADF_MODE[0]
ADF_SDID[5]
ADF_DID[4]
ADF_SDID[4]
ADF_DID[3]
ADF_DID[2]
ADF_DID[1]
ADF_SDID[1]
ADF_DID[0]
ADF_SDID[0]
00010101
0x101010
0xxx0000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
15
2A
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
99
VDP_ADF_CONFIG RW
_2
DUPLICATE_ADF
MAN_LINE_PGM
ADF_SDID[3]
ADF_SDID[2]
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
VDP_LINE_00E
VDP_LINE_00F
VDP_LINE_010
VDP_LINE_011
VDP_LINE_012
VDP_LINE_013
VDP_LINE_014
VDP_LINE_015
VDP_LINE_016
VDP_LINE_017
VDP_LINE_018
VDP_LINE_019
VDP_LINE_01A
VDP_LINE_01B
VDP_LINE_01C
VDP_LINE_01D
VDP_LINE_01E
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
VBI_DATA_
P318[3]
VBI_DATA_
P318[2]
VBI_DATA_
P318[1]
VBI_DATA_
P318[0]
VBI_DATA_
P6_N23[3]
VBI_DATA_
P6_N23[2]
VBI_DATA_
P6_N23[1]
VBI_DATA_
P6_N23[0]
VBI_DATA_
P319_N286[3]
VBI_DATA_
P319_N286[2]
VBI_DATA_
P319_N286[1]
VBI_DATA_
P319_N286[0]
VBI_DATA_
P7_N24[3]
VBI_DATA_
P7_N24[2]
VBI_DATA_
P7_N24[1]
VBI_DATA_
P7_N24[0]
VBI_DATA_
P320_N287[3]
VBI_DATA_
P320_N287[2]
VBI_DATA_
P320_N287[1]
VBI_DATA_
P320_N287[0]
VBI_DATA_
P8_N25[3]
VBI_DATA_
P8_N25[2]
VBI_DATA_
P8_N25[1]
VBI_DATA_
P8_N25[0]
VBI_DATA_
P321_N288[3]
VBI_DATA_
P321_N288[2]
VBI_DATA_
P321_N288[1]
VBI_DATA_
P321_N288[0]
VBI_DATA_
P9[3]
VBI_DATA_
P9[2]
VBI_DATA_
P9[1]
VBI_DATA_
P9[0]
VBI_DATA_
P322[3]
VBI_DATA_
P322[2]
VBI_DATA_
P322[1]
VBI_DATA_
P322[0]
VBI_DATA_
P10[3]
VBI_DATA_
P10[2]
VBI_DATA_
P10[1]
VBI_DATA_
P10[0]
VBI_DATA_
P323[3]
VBI_DATA_
P323[2]
VBI_DATA_
P323[1]
VBI_DATA_
P323[0]
VBI_DATA_
P11[3]
VBI_DATA_
P11[2]
VBI_DATA_
P11[1]
VBI_DATA_
P11[0]
VBI_DATA_
P324_N272[3]
VBI_DATA_
P324_N272[2]
VBI_DATA_
P324_N272[1]
VBI_DATA_
P324_N272[0]
VBI_DATA_
P12_N10[3]
VBI_DATA_
P12_N10[2]
VBI_DATA_
P12_N10[1]
VBI_DATA_
P12_N10[0]
VBI_DATA_
P325_N273[3]
VBI_DATA_
P325_N273[2]
VBI_DATA_
P325_N273[1]
VBI_DATA_
P325_N273[0]
VBI_DATA_
P13_N11[3]
VBI_DATA_
P13_N11[2]
VBI_DATA_
P13_N11[1]
VBI_DATA_
P13_N11[0]
VBI_DATA_
P326_N274[3]
VBI_DATA_
P326_N274[2]
VBI_DATA_
P326_N274[1]
VBI_DATA_
P326_N274[0]
VBI_DATA_
P14_N12[3]
VBI_DATA_
P14_N12[2]
VBI_DATA_
P14_N12[1]
VBI_DATA_
P14_N12[0]
VBI_DATA_
P327_N275[3]
VBI_DATA_
P327_N275[2]
VBI_DATA_
P327_N275[1]
VBI_DATA_
P327_N275[0]
VBI_DATA_
P15_N13[3]
VBI_DATA_
P15_N13[2]
VBI_DATA_
P15_N13[1]
VBI_DATA_
P15_N13[0]
VBI_DATA_
P328_N276[3]
VBI_DATA_
P328_N276[2]
VBI_DATA_
P328_N276[1]
VBI_DATA_
P328_N276[0]
VBI_DATA_
P16_N14[3]
VBI_DATA_
P16_N14[2]
VBI_DATA_
P16_N14[1]
VBI_DATA_
P16_N14[0]
VBI_DATA_
P329_N277[3]
VBI_DATA_
P329_N277[2]
VBI_DATA_
P329_N277[1]
VBI_DATA_
P329_N277[0]
VBI_DATA_
P17_N15[3]
VBI_DATA_
P17_N15[2]
VBI_DATA_
P17_N15[1]
VBI_DATA_
P17_N15[0]
VBI_DATA_
P330_N278[3]
VBI_DATA_
P330_N278[2]
VBI_DATA_
P330_N278[1]
VBI_DATA_
P330_N278[0]
VBI_DATA_
P18_N16[3]
VBI_DATA_
P18_N16[2]
VBI_DATA_
P18_N16[1]
VBI_DATA_
P18_N16[0]
VBI_DATA_
P331_N279[3]
VBI_DATA_
P331_N279[2]
VBI_DATA_
P331_N279[1]
VBI_DATA_
P331_N279[0]
VBI_DATA_
P19_N17[3]
VBI_DATA_
P19_N17[2]
VBI_DATA_
P19_N17[1]
VBI_DATA_
P19_N17[0]
VBI_DATA_
P332_N280[3]
VBI_DATA_
P332_N280[2]
VBI_DATA_
P332_N280[1]
VBI_DATA_
P332_N280[0]
VBI_DATA_
P20_N18[3]
VBI_DATA_
P20_N18[2]
VBI_DATA_
P20_N18[1]
VBI_DATA_
P20_N18[0]
VBI_DATA_
P333_N281[3]
VBI_DATA_
P333_N281[2]
VBI_DATA_
P333_N281[1]
VBI_DATA_
P333_N281[0]
VBI_DATA_
P21_N19[3]
VBI_DATA_
P21_N19[2]
VBI_DATA_
P21_N19[1]
VBI_DATA_
P21_N19[0]
VBI_DATA_
P334_N282[3]
VBI_DATA_
P334_N282[2]
VBI_DATA_
P334_N282[1]
VBI_DATA_
P334_N282[0]
Rev. A | Page 66 of 96
Data Sheet
ADV7182
Address
Dec
Hex
Register Name
RW
7
6
5
4
3
2
1
0
Reset Value (Hex)
117
75
VDP_LINE_01F
RW
VBI_DATA_
P22_N20[3]
VBI_DATA_
P22_N20[2]
VBI_DATA_
P22_N20[1]
VBI_DATA_
P22_N20[0]
VBI_DATA_
P335_N283[3]
VBI_DATA_
P335_N283[2]
VBI_DATA_
P335_N283[1]
VBI_DATA_
P335_N283[0]
00000000
00000000
00000000
00
00
00
118
119
76
77
VDP_LINE_020
VDP_LINE_021
VDP_STATUS
RW
RW
VBI_DATA_
P23_N21[3]
VBI_DATA_
P23_N21[2]
VBI_DATA_
P23_N21[1]
VBI_DATA_
P23_N21[0]
VBI_DATA_
P336_N284[3]
VBI_DATA_
P336_N284[2]
VBI_DATA_
P336_N284[1]
VBI_DATA_
P336_N284[0]
VBI_DATA_
P24_N22[3]
VBI_DATA_
P24_N22[2]
VBI_DATA_
P24_N22[1]
VBI_DATA_
P24_N22[0]
VBI_DATA_
P337_N285[3]
VBI_DATA_
P337_N285[2]
VBI_DATA_
P337_N285[1]
VBI_DATA_
P337_N285[0]
120
120
78
78
R
TTXT_AVL
CGMS_WSS_AVL CC_EVEN_FIELD CC_AVL
VDP_STATUS_
CLEAR
W
CGMS_WSS_
CLEAR
CC_CLEAR
00000000
00
121
122
125
126
127
156
79
7A
7D
7E
7F
9C
VDP_CCAP_
DATA_0
R
R
R
R
R
CCAP_BYTE_1[7] CCAP_BYTE_1[6] CCAP_BYTE_1[5] CCAP_BYTE_1[4] CCAP_BYTE_1[3] CCAP_BYTE_1[2] CCAP_BYTE_1[1] CCAP_BYTE_1[0]
VDP_CCAP_
DATA_1
CCAP_BYTE_2[7] CCAP_BYTE_2[6] CCAP_BYTE_2[5] CCAP_BYTE_2[4] CCAP_BYTE_2[3] CCAP_BYTE_2[2] CCAP_BYTE_2[1] CCAP_BYTE_2[0]
VDP_CGMS_
WSS_DATA_0
CGMS_CRC[5]
CGMS_CRC[4]
CGMS_CRC[3]
CGMS_CRC[2]
CGMS_WSS[8]
CGMS_WSS[0]
VDP_CGMS_
WSS_DATA_1
CGMS_CRC[1]
CGMS_WSS[7]
CGMS_CRC[0]
CGMS_WSS[6]
CGMS_WSS[13] CGMS_WSS[12] CGMS_WSS[11] CGMS_WSS[10] CGMS_WSS[9]
VDP_CGMS_
WSS_DATA_2
CGMS_WSS[5]
CGMS_WSS[4]
CGMS_WSS[3]
CGMS_WSS[2]
CGMS_WSS[1]
VDP_OUTPUT_SEL RW
WSS_CGMS_CB_
CHANGE
00110000
30
1 x in a reset value indicates do not care.
2 B at the end of the bit name equals an overbar for the whole bit name.
Rev. A | Page 67 of 96
ADV7182
Data Sheet
To access all the registers listed in Table 95, SUB_USR_EN in Register Address 0x0E must be programmed to 00b. The gray shading is the
default.
Table 95. Register Map Descriptions (Main Register Map)1
Bits
(Shading Indicates Default State)
Subaddress
Register
Bit Description
7
6
5
4
0
0
0
0
0
0
0
3
0
0
0
0
1
1
1
2
0
0
0
0
0
0
1
1
0
0
1
1
0
0
0
0
0
1
0
1
0
1
0
Comments
Notes
0x00
Input control
INSEL[4:0]; the INSEL bits allow
the user to select an input
channel and the input format
CVBS input on AIN1
CVBS input on AIN2
CVBS input on AIN3
CVBS input on AIN4
Y input on AIN1, C input on AIN2
Y input on AIN3, C input on AIN4
Y input on AIN1, Pb input on AIN2, Pr
input on AIN3
0
0
1
1
1
1
0
1
1
0
0
1
0
Differential positive on AIN1,
differential negative on AIN2
Differential positive on AIN3,
differential negative on AIN4
0x01
Video
Reserved
Sets to default
Selection 1
ENVSPROC
0
1
Disables VSYNC processor
Enables VSYNC processor
Sets to default
Reserved
0
BETACAM; enables BETACAM
levels
0
1
Standard video input
Betacam input enable
Disables HSYNC processor
Enables HSYNC processor
Sets to default
ENHSPLL
0
1
Reserved
Reserved
1
0
0x02
Video
0
1
0
0
Set to default
Selection 2
VID_SEL[3:0]; the VID_SEL bits
allow the user to select the
input video standard
0
0
0
0
0
1
Autodetects PAL B/PAL G/PAL H/
PAL I/PAL D, NTSC J (no
pedestal), SECAM
0
Autodetects PAL B/PAL G/PAL H/
PAL I/PAL D, NTSC M (pedestal),
SECAM
0
0
0
0
1
1
0
1
Autodetects PAL N (pedestal),
NTSC J (no pedestal), SECAM
Autodetects PAL N (pedestal),
NTSC M (pedestal) SECAM
0
0
0
0
1
1
1
1
1
1
0
0
0
0
1
1
0
0
0
1
0
1
0
1
NTSC J
NTSC M
PAL 60
NTSC 4.43
PAL B/G/H/I/D
PAL N = PAL B/PAL G/PAL H/ PAL
I/PAL D (with pedestal)
1
1
1
1
0
0
1
1
1
1
0
0
0
1
0
1
PAL M (without pedestal)
PAL M
PAL Combination N
PAL Combination N (with
pedestal)
1
1
1
1
1
1
0
0
1
0
SECAM
SECAM
0x03
Output
control
Reserved
1
1
0
0
Reserved
TOD; tristate output drivers; this
bit allows the user to tristate
the output drivers; pixel
0
1
Output driverss enabled
See also TIM_OE and
TRI_LLC
Output drivers tristated
outputs, HS and VS/FIELD/SFL
VBI_EN; vertical blanking
interval data enable; allows VBI
data (Line 1 to Line 21) to be
passed through with only a
minimum amount of filtering
performed
0
1
All lines filtered and scaled
Only active video region filtered
Rev. A | Page 68 of 96
Data Sheet
ADV7182
Bits
(Shading Indicates Default State)
Subaddress
Register
Extended
Bit Description
7
6
5
4
3
2
1
0
0
1
Comments
Notes
0x04
Range; allows the user to select
16 ≤ Y ≤ 235, 16 ≤ C/P ≤ 240
1 ≤ Y ≤ 254, 1 ≤ C/P ≤ 254
ITU-R BT.656
output control the range of output values; can
be ITU-R BT.656 compliant or can
fill the whole accessible number
range
Extended range
EN_SFL_PIN
0
1
Disables SFL output
SFL output enables
encoder and decoder
to be connected
directly
Outputs SFL information on the
SFL pin
BL_C_VBI; blank chroma during
VBI; if set, it enables data in the
VBI region to be passed
through the decoder
0
1
Decode and output color during
VBI
during VBI
Blank Cr and Cb values during
VBI
undistorted
TIM_OE; enables timing signals
output
0
1
HS, VS, FIELD tristated
Controlled by TOD
HS, VS, FIELD forced active
Reserved
0
1
1
BT.656-4; allows the user to select
an output mode compatible
with ITU-R BT.656-3/-4
0
1
ITU-R BT.656-3 compatible
ITU-R BT.656-4 compatible
0x07
Autodetect
enable
AD_PAL_EN; PAL B/PAL D/PAL I/
PAL G/PAL H autodetect enable
0
1
Disables
Enables
Disables
Enables
Disables
Enables
Disables
Enables
Disables
Enables
Disables
Enables
Disables
Enables
Disables
Enables
Luma gain = 1
AD_NTSC_EN; NTSC autodetect
enable
0
1
AD_PALM_EN; PAL M
autodetect enable
0
1
AD_PALN_EN; PAL N
autodetect enable
0
1
AD_P60_EN; PAL 60 autodetect
enable
0
1
AD_N443_EN; NTSC 4.43
autodetect enable
0
1
AD_SECAM_EN; SECAM
autodetect enable
0
1
AD_SEC525_EN; SECAM 525
autodetect enable
0
1
1
0x08
0x0A
0x0B
0x0C
Contrast
CON[7:0]; contrast adjust; this is
the user control for contrast
adjustment
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0x00 gain = 0,
0x80 gain = 1,
0xFF gain = 2
Brightness
Adjust
BRI[7:0]; this register controls
the brightness of the video signal
0
0
0x00 = 0 IRE,
0x7F = +30 IRE,
0x80 = −30 IRE
Hue Adjust
HUE[7:0]; this register contains
the value for the color hue
adjustment
Hue range = −90° to
+90°
Default Value Y
DEF_VAL_EN; default value
enable
0
1
Free-run mode dependent
on DEF_VAL_AUTO_EN
Forces free-run mode on
DEF_VAL_AUTO_EN; default
value automatic enable
0
1
Disables free-run mode
When lock is lost, free-
run mode can be
enabled to output
stable timing, clock,
and a set color
Enables automatic free-run mode
DEF_Y[5:0]; default value is Y; this
register holds the Y default value
0
0
0
1
1
1
1
1
0
1
1
1
Y[7:0] = {DEF_Y[5:0], 0, 0}
Default Y value output
in free-run mode
0x0D
Default
Value C
DEF_C[7:0]; default value is C;
the Cr and Cb default values are
defined in this register
0
0
Cr[3:0] = {DEF_C[7:4]},
Cb[3:0] = {DEF_C[3:0]}
Default Cb/Cr value
output in free-run
mode; default values
give blue screen
output
Rev. A | Page 69 of 96
ADV7182
Data Sheet
Bits
(Shading Indicates Default State)
Subaddress
Register
Bit Description
7
6
5
4
3
2
1
0
Comments
Notes
0x0E
ADI Control 1
Reserved
0
0
0
0
0
Sets as default
SUB_USR_EN[1:0]; enables user to
access the interrupt/VDP map
and User Sub Map 2
0
0
0
1
Accesses main register space
See Figure 47
Accesses interrupt/VDP register
space
1
0
0
Accesses User Sub Map 2
Sets as default
Reserved
Reserved
Reserved
0
0x0F
Power
management
0
0
Sets to default
0
0
Sets to default
PWRDWN; power-down places
the decoder into a full power-
down mode
0
1
System functional
Powered down
Reserved
Sets to default
Reset; chip reset, loads all I2C
bits with default values
0
1
Normal operation
Starts reset sequence
Executing reset takes
approximately 2 ms;
this bit is self-clearing
0x10
Status 1
(read only)
IN_LOCK
x
1 = in lock (now)
1 = lost lock (since last read)
1 = fSC lock (now)
1 = peak white AGC mode active
NTSC M/NTSC J
NTSC 4.43
Provides info about
the internal status of
the decoder
LOST_LOCK
FSC_LOCK
FOLLOW_PW
x
x
x
AD_RESULT[2:0]; autodetection
result reports the standard of
the input video
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Detected standard
PAL M
PAL 60
PAL B/PAL G/PAL H/PAL I/PAL D
SECAM
PAL Combination N
SECAM 525
COL_KILL
x
1 = color kill is active
Color kill
0x11
0x12
IDENT
(read only)
IDENT[7:0]; provides ID on the
revision of the part
0
0
0
1
1
x
1
x
0
x
0
x
Power-up value =
0x1C
Status 2
(read only)
MVCS DET
MVCS T3
MV color striping detected
MV color striping type
1 = detected
0 = Type 2, 1 = Type 3
1 = detected
MV PS DET
MV AGC DET
LL NSTD
MV pseudosync detected
MV AGC pulses detected
Nonstandard line length
fSC frequency nonstandard
1 = detected
x
1 = detected
FSC NSTD
Reserved
x
1 = detected
x
x
0x13
Status 3
(read only)
INST_HLOCK
Reserved
x
1 = horizontal lock achieved
Reserved
Unfiltered
x
SD_OP_50Hz
0
1
SD 60 Hz detected
SD 50 Hz detected
SD field rate detect
Reserved
x
FREE_RUN_ACT
STD FLD LEN
x
1 = free-run mode active
1 = field length standard
x
Correct field length
found
Interlaced
x
1 = interlaced video detected
1 = swinging burst detected
Field sequence
found
PAL_SW_LOCK
x
Reliable swinging
burst sequence
Rev. A | Page 70 of 96
Data Sheet
ADV7182
Bits
(Shading Indicates Default State)
Subaddress
Register
Bit Description
7
6
5
4
3
2
1
0
Comments
Notes
0x14
Analog clamp
control
FREE_RUN_PAT_SEL[2:0]
0
0
0
Single color set by DEF_C and
DEF_Y; see Color Controls section
0
0
1
0
1
0
1
0
1
100% color bars
Luma ramp
Boundary box
Reserved
0
x
Sets to default
CCLEN; current clamp enable
allows the user to switch off the
current sources in the analog
front
0
1
Current sources switched off
Current sources enabled
Reserved
Reserved
0
0
0
Sets to default
0x15
Digital Clamp
Control 1
x
x
x
Sets to default
DCFE; digital clamp freeze
enable
0
1
Digital clamp on
Digital clamp off
Slow (TC = 1 sec)
Medium (TC = 0.5 sec)
Fast (TC = 0.1 sec)
TC dependent on video
Set to default
DCT[1:0]; digital clamp timing
determines the time constant of
the digital fine clamp circuitry
0
0
1
1
0
1
0
1
Reserved
0
0x17
Shaping Filter
Control 1
YSFM[4:0]; selects Y shaping filter
mode in CVBS-only mode; allows
the user to select a wide range
of low-pass/notch filters; if
either auto mode is selected, the
decoder selects the optimum
Y filter depending on the CVBS
video source quality (good vs.
poor)
0
0
0
0
0
0
0
0
0
1
Autowide notch for poor quality
sources or wideband filter with
comb for good quality input
Autonarrow notch for poor
quality sources or wideband filter
with comb for good quality input
SVHS 1
SVHS 2
SVHS 3
SVHS 4
SVHS 5
SVHS 6
SVHS 7
SVHS 8
Decoder selects
optimum Y shaping
filter depending on
CVBS quality
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
If one of these
modes is selected,
the decoder does
not change filter
modes; depending
on video quality, a
fixed filter response
(the one selected) is
used for good and
bad quality video
SVHS 9
SVHS 10
SVHS 11
SVHS 12
SVHS 13
SVHS 14
SVHS 15
SVHS 16
SVHS 17
SVHS 18 (CCIR 601)
PAL NN1
PAL NN2
PAL NN3
PAL WN1
PAL WN2
NTSC NN1
NTSC NN2
NTSC NN3
NTSC WN1
NTSC WN2
NTSC WN3
Reserved
Rev. A | Page 71 of 96
ADV7182
Data Sheet
Bits
(Shading Indicates Default State)
Subaddress
Register
Bit Description
7
0
0
6
0
0
5
0
1
4
3
2
1
0
Comments
Notes
CSFM[2:0]: C shaping filter mode
allows selection from a range of
low-pass chrominance filters; if
either auto mode is selected,
the decoder selects the optimum
C filter depending on the CVBS
video source quality (good vs.
bad); nonauto settings force a C
filter for all standards and quality
of CVBS video
Autoselection 1.5 MHz
Autoselection 2.17 MHz
Automatically
selects a C filter
based on video
standard and quality
0
0
1
1
1
1
1
1
0
0
1
1
0
1
0
1
0
1
SH1
Selects a C filter for
all video standards
and for good and
bad video
SH2
SH3
SH4
SH5
Wideband mode
Reserved, do not use
Reserved, do not use
SVHS 1
0x18
Shaping Filter
Control 2
WYSFM[4:0]; wideband Y shaping
filter mode allows the user to
select which Y shaping filter is
used for the Y component of
Y/C, YPrPb, B/W input signals; it
is also used when a good quality
input CVBS signal is detected;
for all other inputs, the Y shaping
filter chosen is controlled by
YSFM[4:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
~
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
~
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
~
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
~
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
~
1
SVHS 2
SVHS 3
SVHS 4
SVHS 5
SVHS 6
SVHS 7
SVHS 8
SVHS 9
SVHS 10
SVHS 11
SVHS 12
SVHS 13
SVHS 14
SVHS 15
SVHS 16
SVHS 17
SVHS 18 (CCIR 601)
Reserved, do not use
Reserved, do not use
Reserved, do not use
Set to default
Autoselection of best filter
Reserved
0
0
WYSFMOVR; enables use of the
automatic WYSFM filter
0
1
Manual select filter using
WYSFM[4:0]
0x19
Comb filter
control
PSFSEL[1:0]; controls the signal
bandwidth that is fed to the
comb filters (PAL)
0
0
1
1
0
1
0
1
Narrow
Medium
Wide
Widest
Narrow
Medium
Medium
Wide
NSFSEL[1:0]; controls the signal
bandwidth that is fed to the
comb filters (NTSC)
0
0
1
1
0
1
0
1
Reserved
Reserved
Reserved
1
1
1
1
0
1
0
0x1D
ADI Control 2
0
x
x
x
TRI_LLC; tristate LLC driver
0
1
LLC pin active
LLC pin tristated
Rev. A | Page 72 of 96
Data Sheet
ADV7182
Bits
(Shading Indicates Default State)
Subaddress
Register
Bit Description
7
6
5
4
3
2
1
0
0
0
0
1
Comments
Notes
0x27
Pixel delay
control
LTA[1:0]; luma timing adjust
allows the user to specify a
timing difference between
chroma and luma samples
No delay
CVBS mode,
LTA[1:0] = 00b,
Y/C mode,
LTA[1:0] = 01b,
YPrPb mode,
LTA[1:0] = 01b
Luma one clock (37 ns) late
1
1
0
1
Luma two clocks (74 ns) early
Luma one clock (37 ns) early
Reserved
0
Sets to 0
CTA[2:0]; chroma timing adjust
allows a specified timing
difference between the luma
and chroma samples
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Reserved
CVBS mode
CTA[2:0] = 011b,
Y/C mode,
CTA[2:0] =101b,
YPrPb mode,
CTA[2:0] = 110b
Chroma + two pixels (early)
Chroma + one pixel (early)
No delay
Chroma − one pixel (late)
Chroma − two pixels (late)
Chroma − three pixels (late)
Reserved
AUTO_PDC_EN; automatic
programmed delay control.
automatically programs the
LTA/CTA values so that luma and
chroma are aligned at the output
for all modes of operation
0
1
Use values in LTA[1:0] and
CTA[2:0] for delaying
luma/chroma
LTA and CTA values determined
automatically
SWPC; allows the Cr and Cb
samples to be swapped
0
1
No swapping
Swaps the Cr and Cb output
samples
0x2B
Misc gain
control
PW_UPD; peak white update
determines the rate of gain
0
1
Updates once per video line
Updates once per field
Peak white must be
enabled; see
LAGC[2:0]
Reserved
1
0
0
0
0
Sets to default
CKE; color kill enable allows the
color kill function to be switched
on and off
0
1
Color kill disabled
Color kill enabled
For SECAM color kill,
the threshold is set
at 8%; see
CKILLTHR[2:0]
Reserved
1
Sets to default
Manual fixed gain
Uses luma gain for chroma
Automatic gain
Freeze chroma gain
Sets to 1
0x2C
AGC mode
control
CAGC[1:0]; chroma automatic
gain control selects the basic
mode of operation for the AGC
in the chroma path
0
0
1
1
0
1
0
1
Use CMG[11:0]
Based on color burst
Reserved
1
1
LAGC[2:0]; luma automatic gain
control selects the mode of
operation for the gain control in
the luma path
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Manual fixed gain
AGC peak white algorithm off
AGC peak white algorithm on
Reserved
Uses LMG[11:0]
Blank level to sync tip
Blank level to sync tip
Reserved
Reserved
Reserved
Freeze gain
Reserved
1
Sets to 1
0x2D
Chroma Gain
Control 1,
Chroma
CMG[11:8]/CG[11:8]; in manual
mode, the chroma gain control
can be used to program a desired
manual chroma gain; in auto
mode, it can be used to read back
the current gain value
0
1
0
0
CAGC[1:0] settings
decide in which
mode CMG[11:0]
operates
Gain 1 (CG)
Reserved
1
0
1
0
Set to 1
Has an effect only if
CAGC[1:0] is set to
autogain (10)
CAGT[1:0]; chroma automatic
gain timing allows adjustment
of the chroma AGC tracking
speed
0
0
1
1
0
0
1
0
1
0
Slow (TC = 2 sec)
Medium (TC = 1 sec)
Reserved
Adaptive
0x2E
Chroma Gain
Control 2,
Chroma
CMG[7:0]/CG[7:0]; chroma
manual gain lower eight bits; see
CMG[11:8]/CG[11:8] for
description
0
0
0
0
CMG[11:0] = see the CMG section
Minimum value =
0d,
maximum value =
4095d
Gain 2 (CG)
Rev. A | Page 73 of 96
ADV7182
Data Sheet
Bits
(Shading Indicates Default State)
Subaddress
Register
Bit Description
7
6
5
4
3
2
1
0
Comments
Notes
0x2F
Luma Gain
Control 1,
Luma Gain 1
(LG)
LMG[11:8]/LG[11:8]; in manual
mode, luma gain control can be
used to program a desired
manual luma gain; in auto mode,
it can be used to read back the
actual gain value used
x
x
x
x
LAGC[1:0] settings decide in
which mode LMG[11:0] operates
Reserved
1
x
1
x
Sets to 1
LAGT[1:0]; luma automatic gain
timing allows adjustment of the
luma AGC tracking speed
0
0
1
1
x
0
1
0
1
x
Slow (TC = 2 sec)
Medium (TC = 1 sec)
Fast (TC = 0.2 sec)
Adaptive
Has an effect only if
LAGC[1:0] is set to
autogain (001, 010)
LMG[7:0]/LG[7:0]; luma manual
gain/ luma gain lower eight bits;
see LMG[11:8]/LG[11:8] for
description
x
x
x
x
LMG[7:0]/LG[7:0]; luma manual
gain/luma gain lower eight bits;
see LMG[11:8]/LG[11:8] for
description
Minimum value =
1024d,
Maximum value =
4095d
0x30
0x31
Luma Gain
Control 2,
Luma Gain 2
(LG)
Reserved
0
1
0
Sets to default
VS/FIELD
Control 1
HVSTIM; horizontal VSYNC timing;
selects where within a line of
video the VSYNC signal is asserted
0
1
Start of line relative to HSE
Start of line relative to HSB
HSE = HSYNC end
HSB = HSYNC begin
NEWAVMODE; sets the EAV/SAV
mode
0
1
EAV/SAV codes generated to suit
Analog Devices encoders
Manual VS/FIELD position
controlled by the Register 0x32,
Register 0x33, and Register 0xE5 to
Register 0xEA
Reserved
Reserved
VSBHE
0
0
0
0
Sets to default
Sets to default
NEWAVMODE bit
must be set high
0x32
0x33
0x34
VS/FIELD
Control 2
0
0
0
1
0
0
0
0
1
0
0
0
1
VSYNC signal goes high in the
middle of the line (even field)
VSYNC signal changes state at the
start of the line (even field)
VSBHO
0
1
VSYNC signal goes high in the
middle of the line (odd field)
VSYNC signal changes state at the
start of the line (odd field)
Reserved
VSEHE
0
0
0
Sets to default
VS/FIELD
Control 3
0
1
VSYNC signal goes low in the
middle of the line (even field)
NEWAVMODE bit
must be set high
VSYNC signal changes state at the
start of the line (even field)
VSEHO
0
1
VSYNC signal goes low in the
middle of the line (odd field)
VSYNC signal changes state at the
start of the line odd field
HSE[10:8]; HSYNC end allows
positioning of the HSYNC
output within the video line
HSYNC output ends HSE[10:0]
pixels after the falling edge of
HSYNC
Using HSB and HSE,
the position/length of
the output HSYNC
HS Position
Control 1
can be programmed
Reserved
0
Sets to 0
HSB[10:8]; HSYNC begin allows
positioning of the HSYNC
0
0
0
HS output starts HSB[10:0] pixels
after the falling edge of HSYNC
output within the video line
Reserved
0
0
Sets to 0
0x35
0x36
HS Position
Control 2
HSB[7:0]; see Address 0x34, using
HSB[10:0] and HSE[10:0], users can
program the position and length
of the HSYNC output signal
0
0
0
0
0
0
0
0
0
0
1
0
0
0
HS Position
Control 3
HSE[7:0]; see Address 0x35
description
0
Rev. A | Page 74 of 96
Data Sheet
ADV7182
Bits
(Shading Indicates Default State)
Subaddress
Register
Bit Description
7
6
5
4
3
2
1
0
0
1
Comments
Notes
0x37
Polarity
PCLK; sets polarity of LLC
Inverts polarity
Normal polarity as per the timing
diagrams
Reserved
0
0
Set to 0
PF; sets the FIELD polarity
0
1
Reserved
0
PVS; sets the VSYNC polarity
0
1
Active high
Active low
Sets to 0
Reserved
0
PHS; sets HSYNC polarity
0
1
0
1
Active high
Active low
YCMN[2:0]; luma comb mode,
NTSC
0
0
0
Adaptive three-line, three-tap
luma comb
0x38
NTSC comb
control
1
1
0
0
0
1
Uses low-pass/notch filter
Fixed luma comb two-line (two
taps)
Top lines of memory
All lines of memory
1
1
1
1
0
1
Fixed luma comb three-line (three
taps)
Fixed luma comb two-line (two
taps)
Bottom lines of
memory
CCMN[2:0]; chroma comb
mode, NTSC
0
0
0
Three-line adaptive for CTAPSN = 01,
four-line adaptive for CTAPSN = 10,
five-line adaptive for CTAPSN = 11
1
1
0
0
0
1
Disables chroma comb
Fixed two-line for CTAPSN = 01,
fixed three-line for CTAPSN = 10,
fixed four-line for CTAPSN = 11
Top lines of memory
All lines of memory
1
1
1
1
0
1
Fixed three-line for CTAPSN = 01,
fixed four-line for CTAPSN = 10,
fixed five-line for CTAPSN = 11
Fixed two-line for CTAPSN = 01,
fixed three-line for CTAPSN = 10,
fixed four-line for CTAPSN = 11
Bottom lines of
memory
CTAPSN[1:0]; chroma comb
taps, NTSC
0
0
1
1
0
1
0
1
Not used
Adapts three lines to two lines
Adapts five lines to three lines
Adapts five lines to four lines
0x39
PAL comb
control
YCMP[2:0]; luma comb mode,
PAL
0
0
0
Adaptive five-line, three-tap
luma comb
1
1
1
1
0
0
1
1
0
1
0
1
Use low-pass notch filter
Fixed luma comb (three-line)
Fixed luma comb (five-line)
Fixed luma comb (three-line)
Top lines of memory
All lines of memory
Bottom lines of
memory
CCMP[2:0]; chroma comb
mode, PAL
0
0
0
Three-line adaptive for CTAPSN = 01,
four-line adaptive for CTAPSN = 10,
five-line adaptive for CTAPSN = 11
1
1
0
0
0
1
Disable chroma comb
Fixed two-line for CTAPSN = 01,
fixed three-line for CTAPSN = 10,
fixed four-line for CTAPSN = 11
Fixed three-line for CTAPSN = 01,
fixed four-line for CTAPSN = 10,
fixed five-line for CTAPSN = 11
Fixed two-line for CTAPSN = 01,
fixed three-line for CTAPSN = 10,
fixed four-line for CTAPSN = 11
Top lines of memory
All lines of memory
1
1
1
1
0
1
Bottom lines of
memory
Rev. A | Page 75 of 96
ADV7182
Data Sheet
Bits
(Shading Indicates Default State)
Subaddress
Register
Bit Description
7
0
0
6
0
1
5
4
3
2
1
0
Comments
Notes
CTAPSP[1:0]; chroma comb taps,
PAL
Not used
Adapts five lines to three lines
(two taps)
1
1
0
1
Adapts five lines to three lines
(three taps)
Adapts five lines to four lines
(four taps)
0x3A
ADC control
MUX PDN override; mux power-
down override
0
1
No control over
power-down for
muxes and
associated channel
circuit
Allows power-down
of MUX0/MUX1/
MUX2 and associated
channel circuit; when
INSEL[4:0] is used,
unused channels are
automatically
powered down
PWRDWN_MUX_2; enables
power-down of MUX2 and
associated channel clamp and
buffer
0
1
MUX2 and associated channel in
normal operation
Power down MUX2 and
associated channel operation
MUX PDN override =
1
PWRDWN_MUX_1; enables
power-down of MUX1 and
associated channel clamp and
buffer
0
1
MUX1 and associated channel in
normal operation
Power down MUX1 and
associated channel operation
MUX PDN override =
1
PWRDWN_MUX_0; enables
power-down of MUX0 and
associated channel clamp and
buffer
0
1
MUX0 and associated channel in
normal operation
Power down MUX0 and
associated channel operation
MUX PDN override =
1
Reserved
Reserved
0
0
0
0
Sets as default
Sets to default
0x3D
Manual
window
control
0
0
1
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
NTSC, PAL color kill at <0.5%,
SECAM no color kill
CKE = 1 enables the
color kill function
and must be
enabled for
CKILLTHR[2:0] to
take effect
CKILLTHR[2:0]; color kill
threshold
NTSC, PAL color kill at <1.5%,
SECAM color kill at <5%
NTSC, PAL color kill at <2.5%,
SECAM color kill at <7%
NTSC, PAL color kill at <4%,
SECAM color kill at <8%
NTSC, PAL color kill at <8.5%,
SECAM color kill at <9.5%
NTSC, PAL color kill at <16%,
SECAM color kill at <15%
NTSC, PAL color kill at <32%,
SECAM color kill at <32%
Reserved
Reserved
Reserved
0
0
Sets to default
Sets to default
0x41
Resample
control
0
0
0
0
0
1
SFL_INV; controls the behavior
of the PAL switch bit
0
1
SFL-compatible with the ADV717x
and ADV73xx video encoders
SFL-compatible with older video
encoders such as the ADV7194.
Set to default
Reserved
Rev. A | Page 76 of 96
Data Sheet
ADV7182
Bits
(Shading Indicates Default State)
Subaddress
Register
Bit Description
7
6
5
4
3
2
1
0
0
1
Comments
Notes
0x4D
CTI DNR
Control 1
CTI_EN; CTI enable
Disables CTI
Enables CTI
CTI_AB_EN; enables the mixing
of the transient improved
chroma with the original signal
0
1
Disables CTI alpha blender
Enables CTI alpha blender
CTI_AB[1:0]; controls the
behavior of the alpha-blend
circuitry
0
0
1
1
0
1
0
1
Sharpest mixing between
sharpened/original chroma signal
Sharp mixing between sharpened
and original chroma signal
Smooth mixing between
sharpened/original chroma signal
Smoothest mixing between
sharpened and original chroma
signal
Reserved
0
Sets to default
DNR_EN; enables or bypasses
the DNR block
0
1
Bypasses the DNR block
Enables the DNR block
Sets to default
Reserved
1
0
1
0
0x4E
0x50
CTI DNR
Control 2
CTI_C_TH[7:0]; specifies how
big the amplitude step must be
to be steepened by the CTI block
0
0
0
0
1
1
0
0
0
0
0
0
DNR Noise
DNR_TH[7:0]; specifies the
maximum luma edge that is
interpreted as noise and is
therefore blanked
0
0
Threshold 1
0x51
Lock count
CIL[2:0]; count into lock
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
One line of video
determines the number of lines
the system must remain in lock
before showing a locked status
Two lines of video
Five lines of video
10 lines of video
100 lines of video
500 lines of video
1000 lines of video
100,000 lines of video
One line of video
Two lines of video
Five lines of video
10 lines of video
100 lines of video
500 lines of video
1000 lines of video
100,000 lines of video
Over field with vertical info
Line-to-line evaluation
COL[2:0]; count out of lock
determines the number of lines
the system must remain out-of-
lock before showing a lost-
locked status
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
SRLS; select raw lock signal and
selects the determination of the
lock status
0
1
FSCLE; fSC lock enable
0
1
Lock status set only by horizontal
lock
Lock status set by horizontal lock
and subcarrier lock
0x60
0x6A
ADC Switch 3
MUX3[2:0]
0
0
0
0
0
0
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
No connect
No connect
AIN2
No connect
AIN4
Reserved
0
0
0
0
0
0
1
0
Output Sync
Select 1
HS_OUT_SEL[2:0] selects which
sync comes out on the HS pin
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
HSYNC
VSYNC
FIELD
DE
SFL
Reserved
0
Rev. A | Page 77 of 96
ADV7182
Data Sheet
Bits
(Shading Indicates Default State)
Subaddress
Register
Bit Description
7
6
5
4
3
2
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
Comments
HSYNC
Notes
0x6B
Output Sync
Select 2
FLD_OUT_SEL[2:0] selects
which sync comes out on the
VS/FIELD/SFL pin
VSYNC
FIELD
DE
SFL
Reserved
Reserved
0
0
0
1
0
0
Set as default
Set as default
0x8F
Free-Run Line
Length 1
0
0
0
LLC_PAD_SEL[2:0]; enables
manual selection of the clock
for the LLC pin
0
1
0
0
0
1
LLC (nominal 27 MHz) selected
out on LLC pin
LLC (nominal 13.5 MHz) selected
out on LLC pin
Reserved
0
x
Sets to default
0x99
0x9A
0x9B
CCAP1
(read only)
CCAP1[7:0]; closed caption data
register
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
CCAP1[7] contains parity bit for
Byte 0
CCAP2
(read only)
CCAP2[7:0]; closed caption data
register
x
x
CCAP2[7] contains parity bit for
Byte 0
Letterbox 1
(read only)
LB_LCT[7:0]; letterbox data
register
Reports the number of black
lines detected at the top of active examines the active
This feature
video
video at the start
and end of each
field; it enables
format detection
even if the video is
not accompanied by
a CGMS or WSS
sequence
0x9C
Letterbox 2
(read only)
LB_LCM[7:0]; letterbox data
register
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Reports the number of black
lines detected in the middle half
of active video if subtitles are
detected
0x9D
0xB2
Letterbox 3
(read only)
LB_LCB[7:0]; letterbox data
register
x
x
Reports the number of black
lines detected at the bottom of
active video
CRC enable
(write only)
Reserved
0
0
Sets as default
CRC_ENABLE; enable CRC
checksum decoded from FMS
packet to validate CGMSD
0
1
Turns off CRC check
CGMSD goes high with valid
checksum
Reserved
0
0
0
1
1
0
Sets as default
No connect
AIN1
0xC3
ADC Switch 1
MUX0[2:0]; manual muxing
control for MUX0; this setting
controls which input is routed
to the ADC for processing
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
MAN_MUX_EN = 1
AIN2
AIN3
AIN4
Reserved
MUX1[2:0]; manual muxing
control for MUX1; this setting
controls which input is routed
to the ADC for processing
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
No connect
No connect
AIN2
No connect
AIN4
Reserved
0
0xC4
ADC Switch 2
MUX2[2:0]; manual muxing
control for MUX2; this setting
controls which input is routed
to the ADC for processing
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
No connect
No connect
AIN2
MAN_MUX_EN = 1
AIN3
No connect
Reserved
0
0
0
0
0
1
MAN_MUX_EN; enable manual
setting of input signal muxing
0
1
Disables
Enables
This bit must be set to
1 for manual muxing
0xDC
Letterbox
Control 1
LB_TH[4:0]; sets the threshold
value that determines if a line is
black
1
0
0
Default threshold for the
detection of black lines
01101 to 10000—increase
threshold,
00000 to 01011—decrease
threshold
Reserved
1
0
1
Sets as default
Rev. A | Page 78 of 96
Data Sheet
ADV7182
Bits
(Shading Indicates Default State)
Subaddress
Register
Bit Description
7
6
5
4
3
2
1
0
Comments
Notes
0xDD
Letterbox
Control 2
LB_EL[3:0]; programs the end
line of the activity window for
LB detection (end of field)
1
1
0
0
LB detection ends with the last
line of active video on a field,
1100b: 262/525
LB_SL[3:0]; programs the start
line of the activity window for
LB detection (start of field)
1
1
0
0
Letterbox detection aligned with
the start of active video, 0100b:
23/286 NTSC
0xDE
0xDF
0xE1
ST Noise
Readback 1
(read only)
ST_NOISE[10:8]
ST_NOISE_VLD
x
x
x
x
x
x
ST noise[10:0]
measures the noise
on the horizontal
sync tip of video
source
x
x
When = 1, ST_NOISE[10:0] is valid
ST Noise
Readback 2
(read only)
ST_NOISE[7:0]
x
x
x
x
SD offset Cb
channel
SD_OFF_Cb[7:0]; adjusts the
hue by selecting the offset for
the Cb channel
0
1
1
0
1
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
−312 mV offset applied to the Cb
channel
0 mV offset applied to the Cb
channel
+312 mV offset applied to the Cb
channel
0xE2
SD offset Cr
channel
SD_OFF_Cr[7:0]; adjusts the hue
by selecting the offset for the Cr
channel
−312 mV offset applied to the Cr
channel
0 mV offset applied to the Cr
channel
+312 mV offset applied to the Cr
channel
0xE3
0xE4
0xE5
SD saturation
Cb channel
SD_SAT_Cb[7:0]; adjusts the
saturation by affecting gain on
the Cb channel
0
1
1
0
1
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
0
1
0
0
1
0
0
0
1
0
0
1
1
0
0
1
0
0
1
0
0
0
1
0
0
1
1
Gain on Cb channel = −42 dB
Gain on Cb channel = 0 dB
Gain on Cb channel = +6 dB
Gain on Cr channel = −42 dB
Gain on Cr channel = 0 dB
Gain on Cr channel = +6 dB
NTSC default (ITU-R BT.656)
SD saturation
Cr channel
SD_SAT_Cr[7:0]; adjusts the
saturation by affecting gain on
the Cr channel
NTSC VSYNC
begin
NVBEG[4:0]; number of lines
after lCOUNT rollover to set V high
NVBEGSIGN
0
1
Sets to low when manual
programming
Not suitable for user programming
No delay
NVBEGDELE; delay V bit going
high by one line relative to
NVBEG (even field)
0
1
Additional delay by one line
NVBEGDELO; delay V bit going
high by one line relative to
NVBEG (odd field)
0
1
No delay
Additional delay by one line
0xE6
NTSC VSYNC
end
NVEND[4:0]; number of lines
after lCOUNT rollover to set V low
0
0
1
0
0
NTSC default (ITU-R BT.656)
NVENDSIGN
0
1
Sets to low when manual
programming
Not suitable for user programming
No delay
NVENDDELE; delay V bit going
low by one line relative to
NVEND (even field)
0
1
Additional delay by one line
NVENDDELO; delay V bit going
low by one line relative to
NVEND (odd field)
0
1
No delay
Additional delay by one line
0xE7
NTSC FIELD
toggle
NFTOG[4:0]; number of lines after
lCOUNT rollover to toggle F signal
0
0
0
1
1
NTSC default
NFTOGSIGN
0
1
Sets to low when manual
programming
Not suitable for user programming
No delay
NFTOGDELE; delay F transition
by one line relative to NFTOG
(even field)
0
1
Additional delay by one line
NFTOGDELO; delay F transition
by one line relative to NFTOG
(odd field)
0
1
No delay
Additional delay by one line
Rev. A | Page 79 of 96
ADV7182
Data Sheet
Bits
(Shading Indicates Default State)
Subaddress
Register
Bit Description
7
6
5
4
3
2
1
0
Comments
Notes
0xE8
PAL VSYNC
begin
PVBEG[4:0]; number of lines
after lCOUNT rollover to set V high
0
0
1
0
1
PAL default (ITU-R BT.656)
PVBEGSIGN
0
1
Sets to low when manual
programming
Not suitable for user
programming
PVBEGDELE; delay V bit going
high by one line relative to
PVBEG (even field)
0
1
No delay
Additional delay by one line
PVBEGDELO; delay V bit going
high by one line relative to
PVBEG (odd field)
0
1
No delay
Additional delay by one line
0xE9
0xEA
0xEB
PAL VSYNC
end
PVEND[4:0]; number of lines
after lCOUNT rollover to set V low.
1
0
1
0
1
0
0
1
0
PAL default (ITU-R BT.656)
PVENDSIGN
0
1
Sets to low when manual
programming
Not suitable for user
programming
PVENDDELE; delay V bit going
low by one line relative to
PVEND (even field)
0
1
No delay
Additional delay by one line
PVENDDELO; delay V bit going
low by one line relative to
PVEND (odd field)
0
1
No delay
Additional delay by one line
PAL FIELD
toggle
PFTOG[4:0]; number of lines after
lCOUNT rollover to toggle F signal
0
0
0
PAL default (ITU-R BT.656)
PFTOGSIGN
0
1
Sets to low when manual
programming
Not suitable for user
programming
PFTOGDELE; delay F transition
by one line relative to PFTOG
(even field)
0
1
No delay
Additional delay by one line
PFTOGDELO; delay F transition
by one line relative to PFTOG
(odd field)
0
1
No delay
Additional delay by one line
Vblank
Control 1
PVBIELCM[1:0]; PAL VBI even
field line control
VBI ends one line earlier (Line 335)
Controls position of
first active (comb
filtered) line after VBI
on even field in PAL
0
1
1
1
0
1
ITU-R BT.470 compliant (Line 336)
VBI ends one line later (Line 337)
VBI ends two lines later (Line 338)
VBI ends one line earlier (Line 22)
ITU-R BT.470 compliant (Line 23)
VBI ends one line later (Line 24)
VBI ends two lines later (Line 25)
VBI ends one line earlier (Line 282)
ITU-R BT.470 compliant (Line 283)
VBI ends one line later (Line 284)
VBI ends two lines later (Line 285)
VBI ends one line earlier (Line 20)
ITU-R BT.470 compliant (Line 21)
VBI ends one line later (Line 22)
VBI ends two lines later (Line 23)
PVBIOLCM[1:0]; PAL VBI odd field
line control
0
0
1
1
0
1
0
1
Controls position of
first active (comb
filtered) line after VBI
on odd field in PAL
NVBIELCM[1:0]; NTSC VBI even
field line control
0
0
1
1
0
1
0
1
Controls position of
first active (comb
filtered) line after VBI
on even field in NTSC
NVBIOLCM[1:0]; NTSC VBI odd
field line control
0
0
1
1
0
1
0
1
Controls position of
first active (comb
filtered) line after VBI
on odd field in NTSC
Rev. A | Page 80 of 96
Data Sheet
ADV7182
Bits
(Shading Indicates Default State)
Subaddress
Register
Bit Description
7
6
5
4
3
2
1
0
0
0
0
1
Comments
Notes
0xEC
Vblank
Control 2
PVBIECCM[1:0]; PAL VBI even
field color control
Color output beginning Line 335
Controls the position
of first line that
outputs color after
VBI on even field in
PAL
ITU-R BT.470 compliant color
output beginning Line 336
1
1
0
1
Color output beginning Line 337
Color output beginning Line 338
Color output beginning Line 22
PVBIOCCM[1:0]; PAL VBI odd
field color control
0
0
0
1
Controls the position
of first line that
outputs color after
VBI on odd field in
PAL
ITU-R BT.470-compliant color
output beginning Line 23
1
1
0
1
Color output beginning Line 24
Color output beginning Line 25
Color output beginning Line 282
NVBIECCM[1:0]; NTSC VBI even
field color control
0
0
0
1
Controls the position
of first line that
outputs color after
VBI on even field in
NTSC
ITU-R BT.470-compliant color
output beginning Line 283
1
1
0
1
VBI ends one line later (Line 284)
Color output beginning Line 285
Color output beginning Line 20
NVBIOCCM[1:0]; NTSC VBI odd
field color control
0
0
0
1
Controls the position
of first line that
outputs color after
VBI on odd field in
NTSC
ITU-R BT.470 compliant color
output beginning Line 21
1
1
0
1
Color output beginning Line 22
Color output beginning Line 23
Antialiasing Filter 1 disabled
0xF3
AFE_
CONTROL 1
AA_FILT_EN[3:0] antialiasing
filter enable
0
1
AA_FILT_MAN_OVR
must be enabled to
change settings
defined by
INSEL[4:0]
Antialiasing Filter 1 enabled
Antialiasing Filter 2 disabled
Antialiasing Filter 2 enabled
Antialiasing Filter 3 disabled
Antialiasing Filter 3 enabled
Antialiasing Filter 4 enabled
Antialiasing Filter 4 enabled
Override disabled
0
1
0
1
0
1
AA_FILT_MAN_OVR;
antialiasing filter override
0
1
Override enabled
Reserved
0
0
0
0xF4
Drive strength
DR_STR_S[1:0]; selects the drive
strength for the sync output
signals
0
0
1
1
0
1
0
1
Low drive strength (1×)
Medium low drive strength (2×)
Medium high drive strength (3×)
High drive strength (4×)
DR_STR_C[1:0]; selects the drive
strength for the clock output
signal
0
0
1
1
0
1
0
1
Low drive strength (1×)
Medium low drive strength (2×)
Medium high drive strength (3×)
High drive strength (4×)
DR_STR[1:0]; selects the drive
strength for the data output
signals; can be increased or
decreased for EMC or crosstalk
reasons
0
0
1
1
0
1
0
1
Low drive strength (1×)
Medium low drive strength (2×)
Medium high drive strength (3×)
High drive strength (4×)
Reserved
x
GLITCH_FILT_BYP
0
1
Rev. A | Page 81 of 96
ADV7182
Data Sheet
Bits
(Shading Indicates Default State)
Subaddress
Register
Bit Description
7
6
5
4
3
2
1
0
Comments
Notes
0xF8
IF comp
control
IFFILTSEL[2:0]; IF filter selection
for PAL and NTSC
0
0
0
Bypass mode
0 dB
2 MHz NTSC Filters
−3 dB
0
0
0
1
0
1
1
0
1
0
1
0
−6 dB
−10 dB
Reserved
3 MHz PAL Filters
−2 dB
1
1
1
0
1
1
1
0
1
−5 dB
−7 dB
Reserved
0
0
0
0
0
0xF9
VS mode
control
EXTEND_VS_MAX_FREQ
0
1
Limits maximum VSYNC
frequency to 66.25 Hz
(475 lines/frame)
Limits maximum VSYNC
frequency to 70.09 Hz
(449 lines/frame)
EXTEND_VS_MIN_FREQ
VS_COAST_MODE[1:0]
0
1
Limits minimum VSYNC
frequency to 42.75 Hz
(731 lines/frame)
Limits minimum VSYNC
frequency to 39.51 Hz
(791 lines/frame)
0
0
1
1
0
1
0
1
Autocoast mode
576i 50 Hz coast mode
480i 60 Hz coast mode
Reserved
This value forces the
video standard
output during free-
run mode
Reserved
0
0
0
1
0
0
0
0
0xFB
0xFC
0xFE
Peaking gain
PEAKING_GAIN[7:0]
0
0
0
1
0
0
0
0
0
Increases/decreases the gain for
high frequency portions of the
video signal
DNR Noise
Threshold 2
DNR_TH2[7:0]
0
0
0
0
0
0
0
0
Specifies the maximum luma edge
that is interpreted as noise and
therefore blanked
CSI Tx slave
address
Reserved
Reserved
Programs the I2C address of the
MIPI CSI TX
CSI_TX_SLAVE_ADDR[6:0]
0
0
0
1 x indicates a bit that keeps the last written value.
Rev. A | Page 82 of 96
Data Sheet
ADV7182
To access the registers listed in Table 96, SUB_USR_EN in Register Address 0x0E must be programmed to 10b. The gray shading is the
default.
Table 96. Register Map Descriptions User Sub Map 2
Bits
(Shading Indicates Default State)
Subaddress
Register
Bit Description
Reserved
7
6
5
4
3
2
1
0
Comments
Reserved.
Notes
0x80
ACE Control 1
0
0
0
0
0
0
0
ACE_ENABLE
0
1
Disable ACE.
Enable ACE.
0x83
0x84
ACE Control 4
ACE Control 5
ACE_LUMA_GAIN[4:0]
0
1
1
1
0
0
0
1
0
Set ACE luma auto-contrast level to
default value.
5b’00000 minimum value
…
When ACE_ ENABLE
is set to 1
5b’11111 maximum value
Reserved
0
1
0
0
0
0
ACE_CHROMA_GAIN[3:0]
Set ACE color auto-saturation level
4b’0000 minimum value
…
4b’1111 maximum value
ACE_CHROMA_MAX[3:0]
0
Set maximum threshold for ACE color
color-saturation level
4b’0000 = minimum value
…
4b’1111 = maximum value
0x85
ACE Control 6
ACE_GAMMA_GAIN[3:0]
ACE_RESPONSE_SPEED[3:0]
BR_DITHER_MODE
1
0
0
0
Set further contrast enhancement
4b’0000 = minimum value
…
4b’1111 = maximum value
1
1
1
1
Sets speed of ACE response
4b’0000 slowest value
…
4b’1111 fastest value
0x92
Dither control
0
1
8-bit to 6-bit down dither disabled
8-bit to 6-bit down dither enabled
Reserved
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0xD9
0xDA
0xDB
0xDC
0xDD
Min Max 0
Min Max 1
Min Max 2
Min Max 3
Min Max 4
MIN_THRESH_Y[7:0]
0
1
0
1
0
Selects the minimum threshold for the
incoming luma video signal.
MAX_THRESH_Y[7:0]
MIN_THRESH_C[7:0]
MAX_THRESH_C[7:0]
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
1
0
1
1
1
0
1
0
Selects the maximum threshold for the
incoming luma video signal.
Selects the minimum threshold for the
incoming chroma video signal.
Selects the maximum threshold for the
incoming chroma video signal.
MAX_SAMPLES_ALLOWED_
Y[3:0]
Selects the number of maximum luma
samples allowed in a given window
before an interrupt is triggered.
MIN_SAMPLES_ALLOWED_
Y[3:0]
1
1
1
1
0
0
0
0
Selects the number of minimum luma
samples allowed in a given window
before an interrupt is triggered.
0xDE
Min Max 5
MAX_SAMPLES_ALLOWED_
C[3:0]
1
1
0
0
Selects the number of maximum
chroma samples allowed in a given
window before an interrupt is
triggered.
MIN_SAMPLES_ALLOWED_
C[3:0]
Selects the number of minimum
chroma samples allowed in a given
window before an interrupt is
triggered.
0xE0
FL Control
FL_ENABLE
0
1
Enables fast lock.
Reserved
0
0
1
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
1
0
0
0
0
1
0
0
0
1
0xE1
0xE2
0xE3
Y Average 0
Y Average 1
Y Average 2
LINE_START[8:1]
LINE_END[8:1]
SAMPLE_START[9:2]
1
0
1
Selects starting line for field averaging.
Selects end line for field averaging.
See Subaddress
0xE5 for least
significant bits
Selects starting sample for line
averaging.
0xE4
Y Average 3
SAMPLE_END[9:2]
1
1
0
1
0
1
1
1
Selects end sample for line averaging.
Rev. A | Page 83 of 96
ADV7182
Data Sheet
Bits
(Shading Indicates Default State)
Subaddress
Register
Bit Description
LINE_START[0]
LINE_END[0]
7
6
5
4
3
2
1
0
Comments
Notes
0xE5
Y Average 4
1
1
Reserved
0
0
SAMPLE_START[1:0]
SAMPLE_END[1:0]
CAPTURE_VALUE
1
0
0
0
0xE6
Y Average 5
0
Trigger used to store the readback
value.
Y_AVG_FILT_EN
0
Enable low pass filtering of the
y_averaged signal.
Y_AVG_TIME_CONST[2:0]
1
x
0
x
0
x
Selects the filter cutoff to be used for
filtering the y averaged data.
3’b1xx = least filtered.
3’b000 = next least.
…
3’b011 = heavily filtered.
Reserved
0
x
0
x
0
x
0xE7
0xE8
Y Average Data
MSB
Y_AVERAGE[9:2]
x
x
x
x
Contains the averaged video data.
Note these are read
only registers
Y Average Data
LSB
Y_AVERAGE[1:0]
Rev. A | Page 84 of 96
Data Sheet
ADV7182
To access the registers listed in Table 97, SUB_USR_EN in Register Address 0x0E must be programmed to 01b. The gray shading is the default.
Table 97. Interrupt/VDP Map Descriptions1
Bit (Shading Indicates
Interrupt/VDP Map
Bit Description
Default State)
Address Register
7
6
5
4
3
2
1
0
0
1
1
0
0
1
0
1
Comments
Notes
0x40
Interrupt Configuration 1 INTRQ_OP_SEL[1:0]; interrupt
drive level select
Open drain
Drive low when active
Drive high when active
Reserved
MPU_STIM_INTRQ; manual
interrupt set mode
0
1
Manual interrupt mode
disabled
Manual interrupt mode
enabled
Reserved
x
Not used
MV_INTRQ_SEL[1:0]; Macrovision
interrupt select
0
0
1
1
0
1
0
1
Reserved
Pseudo sync only
Color stripe only
Pseudo sync or color stripe
Three XTAL periods
15 XTAL periods
63 XTAL periods
Active until cleared
No change
INTRQ_DUR_SEL[1:0]; interrupt
duration select
0
0
1
1
0
1
0
1
0x42
Interrupt Status 1
(read only)
SD_LOCK_Q
0
1
These bits can be cleared or
masked in Register 0x43 and
Register 0x44, respectively
SD input has caused the
decoder to go
from an unlocked state to a
locked state
SD_UNLOCK_Q
0
1
No change
SD input has caused the
decoder to go
from a locked state to an
unlocked state
Reserved
x
x
x
SD_FR_CHNG_Q
0
1
No change
Denotes a change in the free-
run status
MV_PS_CS_Q
0
1
No change
Pseudo sync/color striping
detected;
see Register 0x40
MV_INTRQ_SEL[1:0]
for selection
Reserved
x
x
x
0x43
Interrupt Clear 1
(write only)
SD_LOCK_CLR
0
1
Do not clear
Clears SD_LOCK_Q bit
Do not clear
SD_UNLOCK_CLR
0
1
Clears SD_UNLOCK_Q bit
Not used
Reserved
0 0 0
SD_FR_CHNG_CLR
0
1
Do not clear
Clears SD_FR_CHNG_Q bit
Do not clear
MV_PS_CS_CLR
0
1
Clears MV_PS_CS_Q bit
Not used
Reserved
0x44
Interrupt Mask 1
(read/write)
SD_LOCK_MSK
0
1
Masks SD_LOCK_Q bit
Unmasks SD_LOCK_Q bit
Masks SD_UNLOCK_Q bit
Unmasks SD_UNLOCK_Q bit
Not used
SD_UNLOCK_MSK
0
1
Reserved
0 0 0
SD_FR_CHNG_MSK
0
1
Masks SD_FR_CHNG_Q bit
Unmasks SD_FR_CHNG_Q bit
Masks MV_PS_CS_Q bit
Unmasks MV_PS_CS_Q bit
Not used
MV_PS_CS_MSK
Reserved
0
1
Rev. A | Page 85 of 96
ADV7182
Data Sheet
Bit (Shading Indicates
Default State)
Interrupt/VDP Map
Bit Description
Address Register
7
6
5
4
3
2
1
0
Comments
Notes
0x45
Raw Status 2
CCAPD
0
No CCAPD data detected— VBI These bits are status bits only;
(read only)
System 2
they cannot be cleared or
masked; Register 0x46 is used for
this purpose
1
CCAPD data detected—VBI
System 2
Reserved
x
x
x
EVEN_FIELD
0
1
Current SD field is odd
numbered
Current SD field is even
numbered
CHX_MIN_MAX_INTRQ
0
1
If the input to the ADC is
within the correct range this is
0
If the input to the ADC is
outside the range this is set to
1. The range is set by User Sub
Map 2
Reserved
x
Not used
MPU_STIM_INTRQ
0
1
MPU_STIM_INTRQ = 0
MPU_STIM_INTRQ = 1
0x46
Interrupt Status 2
(read only)
CCAPD_Q
0
1
Closed captioning not
detected in the input video
signal—VBI System 2
These bits can be cleared or
masked by Register 0x47 and
Register 0x48, respectively; note
that the interrupt in Register
0x46 for the CCAP, CGMS, and
WSS data uses the Mode 1 data
slicer
Closed captioning data
detected in the video input
signal—VBI System 2
Reserved
x
Not used
Not used
Reserved
x x
SD_FIELD_CHNGD_Q
0
1
SD signal has not changed
field from odd to even or vice
versa
SD signal has changed Field
from odd to even or vice versa
Reserved
x
x
Not used
MPU_STIM_INTRQ_Q
0
1
Manual interrupt not set
Manual interrupt set
Do not clear—VBI System 2
0x47
Interrupt Clear 2
(write only)
CCAPD_CLR
0
1
Note that interrupt in Register
0x46 for the CCAP, CGMS, and
WSS data uses the Mode 1 data
slicer
Clears CCAPD_Q bit—VBI
System 2
Reserved
x
Not used
Reserved
x x
SD_FIELD_CHNGD_CLR
0
1
Do not clear
Clears SD_FIELD_CHNGD_Q
bit
CHX_MIN_MAX_INTRQ_CLR
0
1
Do not clear
Clears CHX_MIN_MAX_INTRQ
bit
Reserved
x
Not used
MPU_STIM_INTRQ_CLR
0
1
Do not clear
Clears MPU_STIM_INTRQ_Q bit
Rev. A | Page 86 of 96
Data Sheet
ADV7182
Bit (Shading Indicates
Default State)
Interrupt/VDP Map
Bit Description
Address Register
7
6
5
4
3
2
1
0
Comments
Notes
0x48
Interrupt Mask 2
(read/write)
CCAPD_MSK
0
Masks CCAPD_Q bit—VBI
System 2
Note that interrupt in Register
0x46 for the CCAP, CGMS, and
WSS data uses the Mode 1 data
slicer
1
Unmasks CCAPD_Q bit—VBI
System 2
Reserved
0
Not used
Not used
Reserved
0
0
SD_FIELD_CHNGD_MSK
0
1
Masks SD_FIELD_CHNGD_Q
bit
Unmasks SD_FIELD_CHNGD_Q
bit
CHX_MIN_MAX_INTRQ_MSKB
0
1
Masks CHX_MIN_MAX_INTRQ
bit
Unmasks
CHX_MIN_MAX_INTRQ bit
Reserved
0
Not used
MPU_STIM_INTRQ_MSK
0
1
Masks MPU_STIM_INTRQ_Q bit
Unmasks MPU_STIM_INTRQ_Q
bit
0x49
Raw Status 3 (read only)
SD_OP_50Hz; SD 60 Hz/50 Hz
frame rate at output
0
1
SD 60 Hz signal output
SD 50 Hz signal output
These bits are status bits only;
they cannot be cleared or masked;
Register 0x4A is used for this
purpose
SD_V_LOCK
0
1
SD vertical sync lock is not
established
SD vertical sync lock
established
SD_H_LOCK
0
1
SD horizontal sync lock is not
established
SD horizontal sync lock
established
Reserved
x
Not used
SCM_LOCK
0
1
SECAM lock is not established
SECAM lock established
Not used
Reserved
x
x
x
0x4A
Interrupt Status 3
(read only)
SD_OP_CHNG_Q; SD 60 Hz/50 Hz
frame rate at output
0
1
No change in SD signal
standard detected at the
output
These bits can be cleared and
masked by Register 0x4B and
Register 0x4C, respectively
A change in SD signal standard
is detected at the output
SD_V_LOCK_CHNG_Q
SD_H_LOCK_CHNG_Q
0
1
No change in SD VSYNC lock
status
SD VSYNC lock status has
changed
0
1
No change in HSYNC lock
status
SD HSYNC lock status has
changed
SD_AD_CHNG_Q; SD autodetect
changed
0
1
No change in AD_RESULT[2:0]
bits in Status 1 register
AD_RESULT[2:0] bits in Status 1
register have changed
SCM_LOCK_CHNG_Q; SECAM lock
PAL_SW_LK_CHNG_Q
Reserved
0
1
No change in SECAM lock
status
SECAM lock status has
changed
0
1
No change in PAL swinging
burst lock status
PAL swinging burst lock status
has changed
x
x
Not used
Rev. A | Page 87 of 96
ADV7182
Data Sheet
Bit (Shading Indicates
Default State)
Interrupt/VDP Map
Bit Description
Address Register
7
6
5
4
3
2
1
0
0
1
Comments
Notes
0x4B
Interrupt Clear 3
SD_OP_CHNG_CLR
Do not clear
(write only)
Clears SD_OP_CHNG_Q bit
Do not clear
SD_V_LOCK_CHNG_CLR
0
1
Clears SD_V_LOCK_CHNG_Q
bit
SD_H_LOCK_CHNG_CLR
0
1
Do not clear
Clears SD_H_LOCK_CHNG_Q
bit
SD_AD_CHNG_CLR
0
1
Do not clear
Clears SD_AD_CHNG_Q bit
Do not clear
SCM_LOCK_CHNG_CLR
0
1
Clears SCM_LOCK_CHNG_Q
bit
PAL_SW_LK_CHNG_CLR
0
1
Do not clear
Clears PAL_SW_LK_CHNG_Q
bit
Reserved
x
x
Not used
0x4C
Interrupt Mask 3
(read/write)
SD_OP_CHNG_MSK
0
1
Masks SD_OP_CHNG_Q bit
Unmasks SD_OP_CHNG_Q bit
SD_V_LOCK_CHNG_MSK
SD_H_LOCK_CHNG_MSK
0
1
Masks SD_V_LOCK_CHNG_Q
bit
Unmasks
SD_V_LOCK_CHNG_Q bit
0
1
Masks SD_H_LOCK_CHNG_Q
bit
Unmasks
SD_H_LOCK_CHNG_Q bit
SD_AD_CHNG_MSK
0
1
Masks SD_AD_CHNG_Q bit
Unmasks SD_AD_CHNG_Q bit
SCM_LOCK_CHNG_MSK
0
1
Masks SCM_LOCK_CHNG_Q
bit
Unmasks SCM_LOCK_CHNG_Q
bit
PAL_SW_LK_CHNG_MSK
0
1
Masks PAL_SW_LK_CHNG_Q
bit
Unmasks
PAL_SW_LK_CHNG_Q bit
Reserved
x
x
Not used
0x4E
Interrupt Status 4
(read only)
VDP_CCAPD_Q
0
1
Closed captioning not
detected
These bits can be cleared and
masked by Register 0x4F and
Register 0x50, respectively; note
that an interrupt in Register 0x4E
for the CCAP, CGMS, and WSS
data uses the VDP data slicer
Closed captioning detected
Reserved
x
VDP_CGMS_WSS_CHNGD_Q;
see Address 0x9C, Bit 4, of User Sub
Map to determine whether
interrupt is issued for a change in
detected data or for when data is
detected, regardless of content
0
1
CGMS/WSS data is not
changed/not available
CGMS/WSS data is
changed/available
Reserved
Reserved
Reserved
Reserved
Reserved
x
x
x
x
x
Rev. A | Page 88 of 96
Data Sheet
ADV7182
Bit (Shading Indicates
Default State)
Interrupt/VDP Map
Bit Description
Address Register
7
6
5
4
3
2
1
0
0
1
Comments
Notes
0x4F
Interrupt Clear 4
(write only)
VDP_CCAPD_CLR
Do not clear
In Register 0x4E, CCAP/CGMS/
WSS data uses VDP data slicer
Clears VDP_CCAPD_Q
Reserved
0
VDP_CGMS_WSS_CHNGD_CLR
0
1
Do not clear
Clears
VDP_CGMS_WSS_CHNGD_Q
Reserved
0
Reserved
0
Reserved
0
Reserved
0
Do not clear
Reserved
0
VDP_CCAPD_CLR
VDP_CCAPD_MSK
0
0
1
Do not clear
0x50
Interrupt Mask 4
Masks VDP_CCAPD_Q
Unmasks VDP_CCAPD_Q
Note that an interrupt in Register
0x4E for the CCAP, CGMS, and
WSS data uses the VDP data
slicer
Reserved
0
VDP_CGMS_WSS_CHNGD_MSK
0
1
Masks
VDP_CGMS_WSS_CHNGD_Q
Unmasks
VDP_CGMS_WSS_CHNGD_Q
Reserved
0
Reserved
0
Reserved
0
Reserved
0
Reserved
0
0x51
Interrupt Latch 0
(read only)
CR_CHANNEL_MAX_VIOLATION
0
1
Cr value is below programmed This register is cleared by
maximum value
CHX_MIN_MAX_INTRQ_CLR
Cr value is above programmed
maximum value
CR_CHANNEL_MIN_VIOLATION
CB_CHANNEL_MAX_VIOLATION
CB_CHANNEL_MIN_VIOLATION
Y_CHANNEL_MAX_VIOLATION
Y_CHANNEL_MIN_VIOLATION
Reserved
0
1
Cr value is above programmed
minimum value
Cr value is below programmed
minimum value
0
1
Cb value is below
programmed maximum value
Cb value is above
programmed maximum value
0
1
Cb value is above
programmed minimum value
Cb value is below
programmed minimum value
0
1
Y value is below programmed
maximum value
Y value is above programmed
maximum value
0
1
Y value is above programmed
minimum value
Y value is below programmed
minimum value
0
0
Rev. A | Page 89 of 96
ADV7182
Data Sheet
Bit (Shading Indicates
Default State)
Interrupt/VDP Map
Bit Description
Address Register
7
6
5
4
3
2
1
0
Comments
Notes
0x60
VDP_CONFIG_1
VDP_TTXT_TYPE_MAN[1:0]
0
0
PAL: Teletext-ITU-BT.653-
625/50-A,
NTSC: reserved
0
1
1
0
PAL: Teletext-ITU-BT.653-625/50-
B (WST),
NTSC: Teletext-ITU-BT.653-
525/60-B
PAL: Teletext-ITU-BT.653-
625/50-C,
NTSC: Teletext-ITU-BT.653-
525/60-C, or
EIA516 (NABTS)
1
1
PAL: Teletext-ITU-BT.653-
625/50-D,
NTSC: Teletext-ITU-BT.653-
525/60-D
VDP_TTXT_TYPE_MAN_ENABLE
WST_PKT_DECODE_DISABLE
0
1
User programming of teletext
type disabled
User programming of teletext
type enabled
0
1
Enables hamming decoding of
WST packets
Disables hamming decoding
of WST packets
Reserved
1
0
0
0
1
0x62
VDP_ADF_CONFIG_1
ADF_DID[4:0]
0
1
0
1
User-specified DID sent in the
ancillary data stream with VDP
decoded data
ADF_MODE[1:0]
0
0
0
1
Nibble mode
Sets whether ancillary data output
mode in byte mode or nibble
mode
Byte mode, no code
restrictions
1
1
0
1
Byte mode with 0x00 and 0xFF
prevented
Reserved
ADF_ENABLE
0
1
Disables insertion of VBI
decoded data into ancillary
656 stream
Enables insertion of VBI
decoded data into ancillary
656 stream
0x63
VDP_ADF_CONFIG_2
ADF_SDID[5:0]
1
0
1
0
1
0
User-specified SDID sent in the
ancillary data stream with VDP
decoded data
Reserved
x
DUPLICATE_ADF
0
1
Ancillary data packet is spread
across the Y and C data
streams
Ancillary data packet is
duplicated on the Y and C data
streams
0x64
VDP_LINE_00E
VBI_DATA_P318[3:0]
0
0
0
0
Sets VBI standard to be
decoded from Line 318 (PAL),
NTSC—not applicable
Reserved
0 0 0
MAN_LINE_PGM
0
1
Decode default standards on
the lines indicated in Table 75
Manually program the VBI
standard to be decoded on
each line; see Table 76
If set to 1, all VBI_DATA_Px_Ny
bits can be set as desired
0x65
VDP_LINE_00F
VBI_DATA_P319_N286[3:0]
VBI_DATA_P6_N23[3:0]
0
0
0
0
Sets VBI standard to be
decoded from Line 319 (PAL), for these bits to be effective
Line 286 (NTSC)
MAN_LINE_PGM must be set to 1
0
0
0
0
Sets VBI standard to be
decoded from Line 6 (PAL),
Line 23 (NTSC)
Rev. A | Page 90 of 96
Data Sheet
ADV7182
Bit (Shading Indicates
Default State)
Interrupt/VDP Map
Bit Description
Address Register
7
6
5
4
3
2
1
0
Comments
Notes
MAN_LINE_PGM must be set to 1
0x66
0x67
0x68
0x69
0x6A
0x6B
0x6C
0x6D
0x6E
0x6F
VDP_LINE_010
VDP_LINE_011
VDP_LINE_012
VDP_LINE_013
VDP_LINE_014
VDP_LINE_015
VDP_LINE_016
VDP_LINE_017
VDP_LINE_018
VDP_LINE_019
VBI_DATA_P320_N287[3:0]
VBI_DATA_P7_N24[3:0]
VBI_DATA_P321_N288[3:0]
VBI_DATA_P8_N25[3:0]
VBI_DATA_P322[3:0]
0
0
0
0
Sets VBI standard to be
decoded from Line 320 (PAL), for these bits to be effective
Line 287 (NTSC)
0
0
0
0
Sets VBI standard to be
decoded from Line 7 (PAL),
Line 24 (NTSC)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Sets VBI standard to be
decoded from Line 321 (PAL), for these bits to be effective
Line 288 (NTSC)
MAN_LINE_PGM must be set to 1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Sets VBI standard to be
decoded from Line 8 (PAL),
Line 25 (NTSC)
Sets VBI standard to be
decoded from Line 322 (PAL), for these bits to be effective
NTSC—not applicable
MAN_LINE_PGM must be set to 1
VBI_DATA_P9[3:0]
Sets VBI standard to be
decoded from Line 9 (PAL),
NTSC—not applicable
VBI_DATA_P323[3:0]
Sets VBI standard to be
decoded from Line 323 (PAL), for these bits to be effective
NTSC—not applicable
MAN_LINE_PGM must be set to 1
VBI_DATA_P10[3:0]
Sets VBI standard to be
decoded from Line 10 (PAL),
NTSC—not applicable
VBI_DATA_P324_N272[3:0]
VBI_DATA_P11[3:0]
Sets VBI standard to be
decoded from Line 324 (PAL), for these bits to be effective
Line 272 (NTSC)
MAN_LINE_PGM must be set to 1
Sets VBI standard to be
decoded from Line 11 (PAL);
NTSC—not applicable
VBI_DATA_P325_N273[3:0]
VBI_DATA_P12_N10[3:0]
VBI_DATA_P326_N274[3:0]
VBI_DATA_P13_N11[3:0]
VBI_DATA_P327_N275[3:0]
VBI_DATA_P14_N12[3:0]
VBI_DATA_P328_N276[3:0]
VBI_DATA_P15_N13[3:0]
VBI_DATA_P329_N277[3:0]
VBI_DATA_P16_N14[3:0]
Sets VBI standard to be
decoded from Line 325 (PAL), for these bits to be effective
Line 273 (NTSC)
MAN_LINE_PGM must be set to 1
Sets VBI standard to be
decoded from Line 12 (PAL),
Line 10 (NTSC)
Sets VBI standard to be
decoded from Line 326 (PAL), for these bits to be effective
Line 274 (NTSC)
MAN_LINE_PGM must be set to 1
Sets VBI standard to be
decoded from Line 13 (PAL),
Line 11 (NTSC)
Sets VBI standard to be
decoded from Line 327 (PAL), for these bits to be effective
Line 275 (NTSC)
MAN_LINE_PGM must be set to 1
Sets VBI standard to be
decoded from Line 14 (PAL),
Line 12 (NTSC)
Sets VBI standard to be
decoded from Line 328 (PAL), for these bits to be effective
Line 276 (NTSC)
MAN_LINE_PGM must be set to 1
Sets VBI standard to be
decoded from Line 15 (PAL),
Line 13 (NTSC)
Sets VBI standard to be
decoded from Line 329 (PAL), for these bits to be effective
Line 277 (NTSC)
MAN_LINE_PGM must be set to 1
Sets VBI standard to be
decoded from Line 16 (PAL),
Line 14 (NTSC)
Rev. A | Page 91 of 96
ADV7182
Data Sheet
Bit (Shading Indicates
Default State)
Interrupt/VDP Map
Bit Description
Address Register
7
6
5
4
3
2
1
0
Comments
Notes
MAN_LINE_PGM must be set to 1
0x70
0x71
0x72
0x73
0x74
0x75
0x76
0x77
VDP_LINE_01A
VBI_DATA_P330_N278[3:0]
VBI_DATA_P17_N15[3:0]
VBI_DATA_P331_N279[3:0]
VBI_DATA_P18_N16[3:0]
VBI_DATA_P332_N280[3:0]
VBI_DATA_P19_N17[3:0]
VBI_DATA_P333_N281[3:0]
VBI_DATA_P20_N18[3:0]
VBI_DATA_P334_N282[3:0]
VBI_DATA_P21_N19[3:0]
VBI_DATA_P335_N283[3:0]
VBI_DATA_P22_N20[3:0]
VBI_DATA_P336_N284[3:0]
VBI_DATA_P23_N21[3:0]
VBI_DATA_P337_N285[3:0]
VBI_DATA_P24_N22[3:0]
0
0
0
0
Sets VBI standard to be
decoded from Line 330 (PAL), for these bits to be effective
Line 278 (NTSC)
0
0
0
0
Sets VBI standard to be
decoded from Line 17 (PAL),
Line 15 (NTSC)
VDP_LINE_01B
VDP_LINE_01C
VDP_LINE_01D
VDP_LINE_01E
VDP_LINE_01F
VDP_LINE_020
VDP_LINE_021
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Sets VBI standard to be
MAN_LINE_PGM must be set to 1
decoded from Line 331 (PAL), for these bits to be effective
Line 279 (NTSC)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Sets VBI standard to be
decoded from Line 18 (PAL),
Line 16 (NTSC)
Sets VBI standard to be
MAN_LINE_PGM must be set to 1
decoded from Line 332 (PAL), for these bits to be effective
Line 280 (NTSC)
Sets VBI standard to be
decoded from Line 19 (PAL),
Line 17 (NTSC)
Sets VBI standard to be
MAN_LINE_PGM must be set to 1
decoded from Line 333 (PAL), for these bits to be effective
Line 281 (NTSC)
Sets VBI standard to be
decoded from Line 20 (PAL),
Line 18 (NTSC)
Sets VBI standard to be
MAN_LINE_PGM must be set to 1
decoded from Line 334 (PAL), for these bits to be effective
Line 282 (NTSC)
Sets VBI standard to be
decoded from Line 21 (PAL),
Line 19 (NTSC)
Sets VBI standard to be
MAN_LINE_PGM must be set to 1
decoded from Line 335 (PAL), for these bits to be effective
Line 283 (NTSC)
Sets VBI standard to be
decoded from Line 22 (PAL),
Line 20 (NTSC)
Sets VBI standard to be
MAN_LINE_PGM must be set to 1
decoded from Line 336 (PAL), for these bits to be effective
Line 284 (NTSC)
Sets VBI standard to be
decoded from Line 23 (PAL),
Line 21 (NTSC)
Sets VBI standard to be
MAN_LINE_PGM must be set to 1
decoded from Line 337 (PAL), for these bits to be effective
Line 285 (NTSC)
Sets VBI standard to be
decoded from Line 24 (PAL),
Line 22 (NTSC)
Rev. A | Page 92 of 96
Data Sheet
ADV7182
Bit (Shading Indicates
Default State)
Interrupt/VDP Map
Bit Description
Address Register
7
6
5
4
3
2
1
0
Comments
Notes
0x78
VDP_STATUS (read only)
CC_AVL
0
Closed captioning not
detected
CC_CLEAR resets the CC_AVL bit
1
Closed captioning is detected
CC_EVEN_FIELD
0
1
Closed captioning decoded
from odd field
Closed captioning decoded
from even field
CGMS_WSS_AVL
0
1
CGMS/WSS is not detected
CGMS/WSS detected
CGMS_WSS_CLEAR resets the
CGMS_WSS_AVL bit
Reserved
0
0
0
0
TTXT_AVL
0
1
Teletext not detected
Teletext detected
VDP_STATUS_CLEAR
(write only)
CC_CLEAR
0
1
Does not reinitialize the CCAP
readback registers
This is a self-clearing bit
This is a self-clearing bit
Reinitializes the CCAP
readback registers
Reserved
0
CGMS_WSS_CLEAR
0
1
Does not reinitialize the
CGMS/WSS readback registers
Reinitializes the CGMS/WSS
readback registers
Reserved
0
x
0
x
0
x
0
x
0
x
0x79
0x7A
0x7D
VDP_CCAP_DATA_0
(read only)
VDP_CCAP_DATA_1
(read only)
VDP_CGMS_WSS_DATA_0 CGMS_CRC[5:2]
(read only)
CCAP_BYTE_1[7:0]
x
x
x
x
x
x
x
x
x
Decoded Byte 1 of CCAP
Decoded Byte 2 of CCAP
CCAP_BYTE_2[7:0]
x
x
x
x
x
x
Decoded CRC sequence for
CGMS
Reserved
0
0
0
x
0
x
0x7E
VDP_CGMS_WSS_DATA_1 CGMS_WSS[13:8]
x
x
x
x
Decoded CGMS/WSS data
Decoded CRC sequence for
CGMS
(read only)
CGMS_CRC[1:0]
x
x
x
x
0x7F
0x9C
VDP_CGMS_WSS_DATA_2 CGMS_WSS[7:0]
(read only)
VDP_OUTPUT_SEL
x
x
x
x
x
x
Decoded CGMS/WSS data
Reserved
0
0
0
0
WSS_CGMS_CB_CHANGE
0
1
Disable content-based
updating of CGMS and WSS
data
Enable content-based
updating of CGMS and WSS
data
The available bit shows the
availability of data only when its
content has changed
Reserved
0
0
0
1 x indicates a bit that keeps the last written value.
Rev. A | Page 93 of 96
ADV7182
Data Sheet
PCB LAYOUT RECOMMENDATIONS
VREFN AND VREFP
The ADV7182 is a high precision, high speed, mixed-signal device.
To achieve the maximum performance from the part, it is
important to have a well laid out PCB. The following is a guide
for designing a board using the ADV7182.
Place the circuit associated with theVREFN and VREFP pins as
close as possible and on the same side of the PCB as the
ADV7182.
ANALOG INTERFACE INPUTS
DIGITAL OUTPUTS (BOTH DATA AND CLOCKS)
Take care when routing the inputs on the PCB. Keep track
lengths to a minimum and use 75 Ω trace impedances when
possible because trace impedances other than 75 Ω increase the
chance of reflections.
Try to minimize the trace length that the digital outputs have to
drive. Longer traces have higher capacitance, requiring more
current and, in turn, causing more internal digital noise. Shorter
traces reduce the possibility of reflections.
Adding a 30 Ω to 50 Ω series resistor can suppress reflections,
reduce EMI, and reduce the current spikes inside the ADV7182.
If series resistors are used, place them as close as possible to the
ADV7182 pins. However, try not to add vias or extra length to
the output trace to place the resistors closer.
POWER SUPPLY DECOUPLING
It is recommended that each power supply pin be decoupled
with 0.1 µF and 10 nF capacitors. The fundamental idea is to
have a decoupling capacitor within about 0.5 cm of each power
pin. In addition, avoid placing the capacitor on the opposite
side of the PCB from the ADV7182 because doing so interposes
inductive vias in the path. Locate the decoupling capacitors
between the power plane and the power pin. Flow current from
the power plane to the capacitor and then to the power pin. Do
not apply the power connection between the capacitor and the
power pin. Placing a via underneath the 100 nF capacitor pads,
down to the power plane, is the best approach (see Figure 48).
If possible, limit the capacitance that each of the digital outputs
drives to less than 15 pF. This can be accomplished easily by
keeping traces short and by connecting the outputs to only one
device. Loading the outputs with excessive capacitance increases
the current transients inside the ADV7182, creating more digital
noise on its power supplies.
The ADV7182 has an exposed metal paddle on the bottom of
the package. This paddle must be soldered to PCB ground for
proper heat dissipation and for noise and mechanical strength
benefits.
SUPPLY
VIA TO SUPPLY
10nF
100nF
GROUND
VIA TO GND
DIGITAL INPUTS
The digital inputs on the ADV7182 are designed to work with
1.8 V to 3.3 V signals and are not tolerant of 5 V signals. Extra
components are needed if 5 V logic signals are required to be
applied to the decoder.
Figure 48. Recommended Power Supply Decoupling
It is particularly important to maintain low noise and good
stability of PVDD. Pay careful attention to regulation, filtering,
and decoupling. It is highly desirable to provide separate regulated
supplies for each of the analog circuitry groups (AVDD, DVDD,
DVDDIO, and PVDD).
Some graphic controllers use substantially different levels of
power when active (during active picture time) and when idle
(during horizontal and vertical sync periods). This can result in
a measurable change in the voltage supplied to the analog supply
regulator, which can in turn produce changes in the regulated
analog supply voltage. This can be mitigated by regulating the
analog supply, or at least PVDD, from a different, cleaner power
source, for example, from a 12 V supply.
Using a single ground plane for the entire board is also
recommended.
Experience has repeatedly shown that the noise performance is
the same or better with a single ground plane. Using multiple
ground planes can be detrimental because each separate ground
plane is smaller, and long ground loops can result.
Rev. A | Page 94 of 96
Data Sheet
ADV7182
TYPICAL CIRCUIT CONNECTION
Figure 49 provides an example of how to connect the ADV7182. For a detailed schematic of the ADV7182 evaluation boards, contact a
local Analog Devices field applications engineer or Analog Devices distributor.
0.1µF
1.3kΩ
A
1
IN
430Ω
DIFF CVBS
INPUT
75Ω
430Ω
0.1µF
D
_1.8V
0.1µF
D
_3.3V
10nF
A
VDD
_1.8V
10nF
VDD
VDDIO
1.3kΩ
A
A
A
2
3
4
IN
IN
IN
0.1µF
0.1µF
10nF 0.1µF
10nF
SINGLE-ENDED
INPUT EXAMPLE
0.1µF
51Ω
P
_1.8V
10nF
VDD
24Ω
D
_3.3V
VDDIO
D
_1.8V
VDD
0.1µF
A
_1.8V
VDD
SINGLE-ENDED
INPUT EXAMPLE
0.1µF
51Ω
24Ω
P[0:7]
17
18
A
1
2
A
A
1
2
IN
IN
A
12
P0
P1
P2
P3
P4
P5
P6
P7
IN
IN
P0
P1
P2
P3
P4
P5
P6
P7
11
10
9
8
7
YCrCb
22
23
A
A
3
4
A
A
3
4
8-BIT
IN
IN
656 DATA
IN
IN
6
5
ADV7182WBCPZ
LFCSP-32
19
20
VREFP
VREFN
0.1µF
32
24
LLC
LLC
INTRQ
INTRQ
LOCATE CLOSE TO, AND ON THE
SAME SIDE AS, THE ADV7182.
14
15
XTALP
XTALN
29
30
47pF
VS/FIELD/SFL
HS
VS/FIELD/SFL
HS
28.63636MHz
47pF
D
VDDIO
4kΩ
26
ALSB
2
2
ALSB TIED HI ≥ I C ADDRESS = 42h
ALSB TIED LOW ≥ I C ADDRESS = 40h
31
25
28
27
PWRDWN
RESET
SCLK
PWRDWN
RESET
SCLK
SDATA
SDATA
Figure 49. ADV7182 Typical Connection Diagram
Rev. A | Page 95 of 96
ADV7182
Data Sheet
OUTLINE DIMENSIONS
5.10
5.00 SQ
4.90
0.30
0.25
0.18
PIN 1
INDICATOR
PIN 1
INDICATOR
25
32
24
1
0.50
BSC
*
3.75
EXPOSED
PAD
3.60 SQ
3.55
17
8
16
9
0.50
0.40
0.30
0.25 MIN
TOP VIEW
BOTTOM VIEW
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.80
0.75
0.70
0.05 MAX
0.02 NOM
SECTION OF THIS DATA SHEET.
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
*
COMPLIANT TO JEDEC STANDARDS MO-220-WHHD-5
WITH EXCEPTION TO EXPOSED PAD DIMENSION.
Figure 50. 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
5 mm × 5 mm Body, Very Very Thin Quad
(CP-32-12)
Dimensions shown in millimeters
ORDERING GUIDE
Model1, 2
Temperature Range
−40°C to +105°C
−40°C to +105°C
Package Description
Package Option
CP-32-12
CP-32-12
ADV7182WBCPZ
ADV7182WBCPZ-RL
EVAL-ADV7182EBZ
32-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
32-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
Evaluation Board for the 32-Lead LFCSP
1 Z = RoHS Compliant Part.
2 W = Qualified for Automotive Applications.
AUTOMOTIVE PRODUCTS
The ADV7182W models are available with controlled manufacturing to support the quality and reliability requirements of automotive
applications. Note that these automotive models may have specifications that differ from the commercial models; therefore, designers
should review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for use in
automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to
obtain the specific Automotive Reliability reports for these models.
I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).
©2013 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D11001-0-3/13(A)
Rev. A | Page 96 of 96
相关型号：
ADV7183
ADV7183: Advanced Video Decoder with 10-Bit ADC and Component Input Support Data Sheet (Rev. 0. 5/02)
ETC
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