ADV7181WBSTZ [ADI]
10-Bit, Integrated, Multiformat SDTV Video Decoder and RGB Graphics Digitizer; 10位，集成，多格式SDTV视频解码器和RGB图形数字化仪
| 型号： | ADV7181WBSTZ |
| 厂家： | 
ADI |
| 描述： | 10-Bit, Integrated, Multiformat SDTV Video Decoder and RGB Graphics Digitizer |
| 文件： | 总20页 (文件大小：455K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
10-Bit, Integrated, Multiformat SDTV
Video Decoder and RGB Graphics Digitizer
ADV7181C
FEATURES
GENERAL DESCRIPTION
Four 10-bit ADCs sampling up to 110 MHz
6 analog input channels
SCART fast blank support
Internal antialias filters
NTSC, PAL, SECAM color standards support
The ADV7181C is a high quality, single-chip, multiformat
video decoder and graphics digitizer. This multiformat decoder
supports the conversion of PAL, NTSC, and SECAM standards
in the form of composite or S-Video into a digital ITU-R BT.656
format. The ADV7181C also supports the decoding of a com-
525p/625p component progressive scan support
720p/1080i component HDTV support
Digitizes RGB graphics up to 1280 × 1024 at 60 Hz (SXGA)
3 × 3 color space conversion matrix
Industrial temperature range: −40°C to +85°C
12-bit 4:4:4 DDR, 8-/10-/16-/20-bit SDR pixel output interface
Programmable interrupt request output pin
Small package
ponent RGB/YPrPb video signal into a digital YCrCb or RGB
DDR pixel output stream. The support for component video
includes standards such as 525i, 625i, 525p, 625p, 720p, 1080i,
and many other HD and SMPTE standards. Graphics digitization
is also supported by the ADV7181C; it is capable of digitizing
RGB graphics signals from VGA to SXGA rates and converting
them into a digital DDR RGB or YCrCb pixel output stream.
SCART and overlay functionality are enabled by the ability of
the ADV7181C to process simultaneously CVBS and standard
definition RGB signals. The mixing of these signals is controlled
by the fast blank pin.
Low pin count
Single front end for video and graphics
APPLICATIONS
The ADV7181C contains two main processing sections. The
first section is the standard definition processor (SDP), which
processes all PAL, NTSC, and SECAM signal types. The second
section is the component processor (CP), which processes YPrPb
and RGB component formats, including RGB graphics.
Automotive entertainment
HDTVs
LCD/DLP projectors
HDTV STBs with PVR
DVD recorders with progressive scan input support
AVR receivers
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2008 Analog Devices, Inc. All rights reserved.
ADV7181C
TABLE OF CONTENTS
Features .............................................................................................. 1
SDP Pixel Data Output Modes ................................................. 11
CP Pixel Data Output Modes ................................................... 11
Composite and S-Video Processing......................................... 11
Component Video Processing.................................................. 12
RGB Graphics Processing ......................................................... 12
General Features......................................................................... 12
Detailed Description...................................................................... 13
Analog Front End....................................................................... 13
Standard Definition Processor (SDP)...................................... 13
Component Processor (CP)...................................................... 13
Analog Input Muxing ................................................................ 14
Pixel Output Formatting................................................................ 16
Recommended External Loop Filter Components.................... 17
Typical Connection Diagram ....................................................... 18
Outline Dimensions....................................................................... 19
Ordering Guide .......................................................................... 19
Applications....................................................................................... 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Functional Block Diagram .............................................................. 3
Specifications..................................................................................... 4
Electrical Characteristics............................................................. 4
Video Specifications..................................................................... 5
Timing Characteristics ................................................................ 6
Analog Specifications................................................................... 7
Absolute Maximum Ratings............................................................ 8
Package Thermal Performance................................................... 8
Thermal Specifications ................................................................ 8
ESD Caution.................................................................................. 8
Pin Configuration and Function Descriptions............................. 9
Detailed Functionality ................................................................... 11
Analog Front End....................................................................... 11
REVISION HISTORY
8/08—Revision 0: Initial Version
Rev. 0 | Page 2 of 20
ADV7181C
FUNCTIONAL BLOCK DIAGRAM
0 0 1 3 - 5 1 0 7
R E T A T R M O F A N O D F I F U P T U T O
Figure 1.
Rev. 0 | Page 3 of 20
ADV7181C
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
AVDD = 3.15 V to 3.45 V, DVDD = 1.65 V to 2.0 V, DVDDIO = 3.0 V to 3.6 V, PVDD = 1.71 V to 1.89 V, nominal input range 1.6 V.
TMIN to TMAX = −40°C to +85°C, unless otherwise noted.
Table 1.
Parameter1, 2
Symbol
Test Conditions
Min
Typ
Max
Unit
STATIC PERFORMANCE3, 4
Resolution (each ADC)
Integral Nonlinearity
N
10
Bits
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
INL
BSL at 27 MHz (10-bit level)
BSL at 54 MHz (10-bit level)
BSL at 74 MHz (10-bit level)
BSL at 110 MHz (8-bit level)
At 27 MHz (10-bit level)
At 54 MHz (10-bit level)
At 74 MHz (10-bit level)
At 110 MHz (8-bit level)
0.6
2.5
−0.6/+0.7
1.4
0.9
Differential Nonlinearity
DNL
−0.2/+0.25
−0.2/+0.25
0.9
−0.99/+2.5
−0.2/+1.5
DIGITAL INPUTS5
Input High Voltage6
VIH
VIL
2
V
HS_IN, VS_IN low trigger mode
HS_IN, VS_IN low trigger mode
0.7
V
Input Low Voltage7
0.8
0.3
+10
10
V
V
Input Current
Input Capacitance5
IIN
−10
2.4
μA
pF
CIN
DIGITAL OUTPUTS
Output High Voltage8
Output Low Voltage8
High Impedance Leakage Current
VOH
VOL
ISOURCE = 0.4 mA
ISINK = 3.2 mA
Pin 1
V
0.4
60
10
20
V
ILEAK
μA
μA
pF
All other output pins
Output Capacitance5
POWER REQUIREMENTS5
Digital Core Power Supply
Digital I/O Power Supply
PLL Power Supply
COUT
DVDD
DVDDIO
PVDD
1.65
3.0
1.8
3.3
1.8
3.3
105
113
106
4
2
V
3.6
1.89
3.45
V
1.71
3.15
V
Analog Power Supply
Digital Core Supply Current
AVDD
V
IDVDD
CVBS input sampling at 54 MHz
Graphics RGB sampling at 110 MHz
SCART RGB FB sampling at 54 MHz
CVBS input sampling at 54 MHz
Graphics RGB sampling at 110 MHz
CVBS input sampling at 54 MHz
Graphics RGB sampling at 110 MHz
CVBS input sampling at 54 MHz
Graphics RGB sampling at 110 MHz
SCART RGB FB sampling at 54 MHz
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
ms
Digital I/O Supply Current
PLL Supply Current
IDVDDIO
IPVDD
16
11
12
Analog Supply Current9
IAVDD
99
198
269
2.25
16
Power-Down Current
Green Mode Power-Down
Power-Up Time
IPWRDN
IPWRDNG
TPWRUP
Synchronization bypass function
20
1 The minimum/maximum specifications are guaranteed over this range.
2 All specifications are obtained using the Analog Devices, Inc., recommended programming scripts.
3 All ADC linearity tests performed at input range of full scale – 12.5%, and at zero scale + 12.5%.
4 Maximum INL and DNL specifications obtained with part configured for component video input.
5 Guaranteed by characterization.
6 To obtain specified VIH level on Pin 22, program Register 0x13 (WO) with a value of 0x04. If Register 0x13 is programmed with a value of 0x00, then VIH on Pin 22 is 1.2 V.
7 To obtain specified VIL level on Pin 22, program Register 0x13 (WO) with a value of 0x04. If Register 0x13 is programmed with a value of 0x00, then VIL on Pin 22 is 0.4 V.
8 VOH and VOL levels obtained using default drive strength value (0xD5) in Register Subaddress 0xF4.
9 For CVBS current measurement only, ADC0 is powered up. For RGB current measurements only, ADC0, ADC1, and ADC2 are powered up. For SCART FB current
measurements, all ADCs are powered up.
Rev. 0 | Page 4 of 20
ADV7181C
VIDEO SPECIFICATIONS
AVDD = 3.15 V to 3.45 V, DVDD = 1.65 V to 2.0 V, DVDDIO = 3.0 V to 3.6 V, PVDD = 1.71 V to 1.89 V. TMIN to TMAX = −40°C to +85°C,
unless otherwise noted.
Table 2.
Parameter1, 2
Symbol
Test Conditions
Min
Typ
Max
Unit
NONLINEAR SPECIFICATIONS
Differential Phase
Differential Gain
Luma Nonlinearity
NOISE SPECIFICATIONS
SNR Unweighted
DP
DG
LNL
CVBS input, modulated 5 step
CVBS input, modulated 5 step
CVBS input, 5 step
0.5
0.5
0.5
Degrees
%
%
Luma ramp
54
58
56
60
60
dB
dB
dB
SNR Unweighted
Analog Front-End Crosstalk
Luma flat field
LOCK TIME SPECIFICATIONS
Horizontal Lock Range
Vertical Lock Range
−5
40
+5
70
%
Hz
FSC Subcarrier Lock Range
Color Lock in Time
1.3
60
kHz
Lines
%
Sync Depth Range3
20
5
200
200
Color Burst Range
%
Vertical Lock Time
2
100
Fields
Lines
Horizontal Lock Time
CHROMA SPECIFICATIONS
Hue Accuracy
Color Saturation Accuracy
Color AGC Range
HUE
CL_AC
1
1
Degrees
%
%
5
400
Chroma Amplitude Error
Chroma Phase Error
Chroma Luma Intermodulation
0.5
0.4
0.2
%
Degrees
%
LUMA SPECIFICATIONS
Luma Brightness Accuracy
Luma Contrast Accuracy
CVBS, 1 V input
CVBS, 1 V input
1
1
%
%
1 The minimum/maximum specifications are guaranteed over this range.
2 Guaranteed by characterization.
3 Nominal synchronization depth is 300 mV at 100% synchronization depth range.
Rev. 0 | Page 5 of 20
ADV7181C
TIMING CHARACTERISTICS
AVDD = 3.15 V to 3.45 V, DVDD = 1.65 V to 2.0 V, DVDDIO = 3.0 V to 3.6 V, PVDD = 1.71 V to 1.89 V. TMIN to TMAX = −40°C to +85°C,
unless otherwise noted.
Table 3.
Parameter1, 2
Symbol Test Conditions
Min
Typ
Max
Unit
SYSTEM CLOCK AND CRYSTAL
Crystal Nominal Frequency
Crystal Frequency Stability
LLC Frequency Range3
I2C PORT4
28.63636
MHz
ppm
MHz
50
110
12.825
SCLK Frequency
400
kHz
μs
μs
μs
μs
ns
ns
ns
μs
SCLK Min Pulse Width High
SCLK Min Pulse Width Low
Hold Time (Start Condition)
Setup Time (Start Condition)
SDA Setup Time
SCLK and SDA Rise Time
SCLK and SDA Fall Time
Setup Time for Stop Condition
RESET FEATURE
t1
t2
t3
t4
t5
t6
t7
t8
0.6
1.3
0.6
0.6
100
300
300
0.6
Reset Pulse Width
5
ms
CLOCK OUTPUTS
LLC Mark Space Ratio
DATA and CONTROL OUTPUTS
Data Output Transition Time SDR (SDP)5
t9:t10
45:55
55:45 % duty cycle
t11
t12
t13
t14
t15
t16
t17
t18
Negative clock edge
to start of valid data
End of valid data to
negative clock edge
End of valid data to
negative clock edge
Negative clock edge
to start of valid data
3.6
2.4
2.8
0.1
ns
ns
ns
ns
ns
ns
ns
ns
Data Output Transition Time SDR (SDP)5
Data Output Transition Time SDR (CP)6
Data Output Transition Time SDR (CP)6
Data Output Transition Time DDR (CP)6, 7
Data Output Transition Time DDR (CP)6, 7
Data Output Transition Time DDR (CP)6, 7
Data Output Transition Time DDR (CP)6, 7
Positive clock edge to −4 + TLLC/4
end of valid data
Positive clock edge to 0.25 + TLLC/4
start of valid data
Negative clock edge
to end of valid data
Negative clock edge
to start of valid data
−2.95 + TLLC/4
−0.5 + TLLC/4
1 The minimum/maximum specifications are guaranteed over this range.
2 Guaranteed by characterization.
3 Maximum LLC frequency is 110 MHz.
4 TTL input values are 0 V to 3 V, with rise/fall times of ≤3 ns, measured between the 10% and 90% points.
5 SDP timing figures obtained using default drive strength value (0xD5) in Register Subaddress 0xF4.
6 CP timing figures obtained using maximum drive strength value (0xFF) in Register Subaddress 0xF4.
7 DDR timing specifications dependent on LLC output pixel clock; TLCC/4 = 9.25 ns at LLC = 27 MHz.
Rev. 0 | Page 6 of 20
ADV7181C
ANALOG SPECIFICATIONS
AVDD = 3.1.5 V to 3.45 V, DVDD = 1.65 V to 2.0 V, DVDDIO = 3.0 V to 3.6 V, PVDD = 1.71 V to 1.89 V. TMIN to TMAX = −40°C to +85°C,
unless otherwise noted. Recommended analog input video signal range: 0.5 V to 1.6 V, typically 1 V p-p.
Table 4.
Parameter1, 2
Test Conditions
Min
Typ
Max
Unit
CLAMP CIRCUITRY
External Clamp Capacitor
Input Impedance; Except Pin 34 (FB)
Input Impedance of Pin 34 (FB)
CML
0.1
10
20
1.86
μF
MΩ
kΩ
V
Clamps switched off
ADC Full-Scale Level
ADC Zero-Scale level
ADC Dynamic Range
Clamp Level (When Locked)
CML + 0.8 V
CML − 0.8 V
1.6
CML – 0.292 V
CML – 0.4 V
CML – 0.292 V
CML – 0 V
CML – 0.3 V
CML – 0.3 V
0.75
V
V
V
V
V
V
V
V
CVBS input
SCART RGB input (R, G, B signals)
S-Video input (Y signal)
S-Video input (C signal)
Component input (Y, Pr, Pb signals)
PC RGB input (R, G, B signals)
SDP only
SDP only
SDP only
SDP only
V
Large Clamp Source Current
Large Clamp Sink Current
Fine Clamp Source Current
Fine Clamp Sink Current
mA
mA
μA
μA
0.9
17
17
1 The minimum/maximum specifications are guaranteed over this range.
2 Guaranteed by characterization.
Rev. 0 | Page 7 of 20
ADV7181C
ABSOLUTE MAXIMUM RATINGS
Table 5.
PACKAGE THERMAL PERFORMANCE
To reduce power consumption when using the part the user is
advised to turn off any unused ADCs.
Parameter
Rating
AVDD to AGND
4 V
It is imperative that the recommended scripts be used for the
following high current modes: SCART, 720p, 1080i, and all
RGB graphic standards. Using the recommended scripts ensures
correct thermal performance. These scripts are available from
a local FAE.
DVDD to DGND
PVDD to AGND
DVDDIO to DGND
DVDDIO to AVDD
PVDD to DVDD
DVDDIO to PVDD
DVDDIO to DVDD
AVDD to PVDD
2.2 V
2.2 V
4 V
−0.3 V to +0.3 V
−0.3 V to +0.3 V
−0.3 V to +2 V
−0.3 V to +2 V
−0.3 V to +2 V
−0.3 V to +2 V
DGND − 0.3 V to
DVDDIO + 0.3 V
DGND − 0.3 V to
DVDDIO + 0.3 V
The junction temperature must always stay below the
maximum junction temperature (TJ MAX) of 125°C. Using
the following equation, calculate the junction temperature:
AVDD to DVDD
Digital Inputs Voltage to DGND
TJ = TA MAX + (θJA × WMAX
where:
A MAX = 85°C.
θJA = 45.5°C/W.
MAX = ((AVDD × IAVDD) + (DVDD × IDVDD) + (DVDDIO ×
)
Digital Outputs Voltage to DGND
Analog Inputs to AGND
T
AGND − 0.3 V to
AVDD + 0.3 V
−40°C to +85°C
125°C
W
IDVDDIO) + (PVDD × IPVDD)).
Operating Temperature
Maximum Junction Temperature (TJ MAX
THERMAL SPECIFICATIONS
)
Storage Temperature Range
Infrared Reflow Soldering (20 sec)
−65°C to +150°C
260°C
Table 6.
Package Type
1
2
θJA
θJC
Unit
°C/W
°C/W
64-Lead LQFP
45.5
20.3
9.2
1.2
64-Lead LFCSP_VQ
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
1 4-layer PCB with solid ground plane (still air).
2 4-layer PCB with solid ground plane.
ESD CAUTION
Rev. 0 | Page 8 of 20
ADV7181C
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
INT
A
A
A
5
4
3
IN
IN
IN
PIN 1
2
3
HS/CS
DGND
4
DVDDIO
NC
5
P15
CAPC2
AGND
CML
6
P14
7
P13
ADV7181C
8
P12
REFOUT
AVDD
TOP VIEW
(Not to Scale)
9
SFL/SYNC_OUT
10
11
12
13
14
15
16
DGND
DVDDIO
P11
CAPY2
CAPY1
AGND
P10
A
A
2
1
IN
IN
P9
P8
FB
NC
P7
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
NOTES
1. NC = NO CONNECT.
2. THE LFCSP_VQ HAS AN EXPOSED PADDLE THAT MUST BE CONNECTED TO GND.
Figure 2. Pin Configuration
Table 7. Pin Function Descriptions
Pin No.
Mnemonic
Type1 Description
3, 10, 24, 57
32, 37, 43
4, 11
23, 58
40
31
34
DGND
AGND
DVDDIO
DVDD
AVDD
PVDD
FB
AIN1 to AIN6
P0 to P19
G
G
P
P
P
P
I
Digital Ground.
Analog Ground.
Digital I/O Supply Voltage (3.3 V).
Digital Core Supply Voltage (1.8 V).
Analog Supply Voltage (3.3 V).
PLL Supply Voltage (1.8 V).
Fast Switch Overlay Input. This pin switches between CVBS and RGB analog signals.
Analog Video Input Channels.
35, 36, 46, 47, 48, 49
28 to 25, 19 to 12,
8 to 5, 62 to 59
I
O
Video Pixel Output Port. Refer to Table 10 for output configuration modes.
1
INT
O
O
Interrupt. This pin can be active low or active high. When SDP/CP status bits
change, this pin is triggered. The set of events that triggers an interrupt is
under user control.
HS: Horizontal Synchronization Output Signal (SDP and CP Modes).
CS: Digital Composite Synchronization Signal (CP Mode).
2
HS/CS
64
63
VS
FIELD/DE
O
O
Vertical Synchronization Output Signal (SDP and CP Modes).
Field Synchronization Output Signal (All Interlaced Video Modes). This pin also
can be enabled as an data enable signal (DE) in CP mode to allow direct
connection to a HDMI/DVI Tx IC.
I2C Port Serial Data Input/Output Pin.
I2C Port Serial Clock Input. Maximum clock rate of 400 kHz.
This pin selects the I2C address for the ADV7181C control and VBI readback
ports. ALSB set to Logic 0 sets the address for a write to Control Port 0x40 and
the readback address for VBI Port 0x21. ALSB set to a Logic 1 sets the address
for a write to Control Port 0x42 and the readback address for VBI Port 0x23.
53
54
52
SDATA
SCLK
ALSB
I/O
I
I
Rev. 0 | Page 9 of 20
ADV7181C
Pin No.
Mnemonic
Type1 Description
51
RESET
I
System Reset Input, Active Low. A minimum low reset pulse width of 5 ms is
required to reset the ADV7181C circuitry.
20
22
21
LLC
O
I
Line-Locked Output Clock. This pin is for the pixel data (the range is
12.825 MHz to 110 MHz).
Input pin for 28.63636 MHz crystal, or can be overdriven by an external 3.3 V,
28.63636 MHz clock oscillator source to clock the ADV7181C.
This pin should be connected to the 28.63636 MHz crystal or left as a no connect if
an external 3.3 V, 28.63636 MHz clock oscillator source is used to clock the
ADV7181C. In crystal mode, the crystal must be a fundamental crystal.
XTAL
XTAL1
O
30
9
ELPF
SFL/SYNC_OUT
O
O
The recommended external loop filter must be connected to this ELPF pin.
SFL: Subcarrier Frequency Lock. This pin contains a serial output stream that
can be used to lock the subcarrier frequency when this decoder is connected
to any Analog Devices digital video encoder.
SYNC_OUT: Sliced Synchronization Output Signal Available Only in CP Mode.
41
REFOUT
O
O
I
Internal Voltage Reference Output. See Figure 5 for a recommended capacitor
network for this pin.
Common-Mode Level Pin (CML) for the Internal ADCs. See Figure 5 for a
recommended capacitor network for this pin.
ADC Capacitor Network. See Figure 5 for a recommended capacitor network for
this pin.
ADC Capacitor Network. See Figure 5 for a recommended capacitor network for
this pin.
42
CML
38, 39
44
CAPY1, CAPY2
CAPC2
I
56
HS_IN/CS_IN
I
This pin can be configured in CP mode to be either a digital HS input signal or a
digital CS input signal used to extract timing in a 5-wire or 4-wire RGB mode.
55
50
29
VS_IN
I
I
I
VS Input Signal. Used in CP mode for 5-wire timing mode.
SOG/SOY
PWRDWN
NC
Sync on Green/Sync on Luma Input. Used in embedded synchronization mode.
A Logic 0 on this pin places the ADV7181C in a power-down mode.
No Connect. These pins are not connected internally.
33, 45
1 G = ground, I = input, O = output, I/O = input/output.
Rev. 0 | Page 10 of 20
ADV7181C
DETAILED FUNCTIONALITY
ANALOG FRONT END
COMPOSITE AND S-VIDEO PROCESSING
The analog front-end section contains four high quality 10-bit
ADCs, and the six analog input channel mux enables multisource
connection without the requirement of an external mux. It also
contains
Composite and S-Video processing features offer support for
NTSC M/J, NTSC 4.43, PAL B/D/I/G/H, PAL60, PAL M, PAL
N, and SECAM (B, D, G, K, and L) standards in the form of
CVBS and S-Video as well as super-adaptive, 2D, 5-line comb
filters for NTSC and PAL give superior chrominance and
luminance separation for composite video. They also include
full automatic detection and autoswitching of all worldwide
standards (PAL, NTSC, and SECAM) and automatic gain
control with white peak mode to ensure the video is always
processed without loss of the video processing range. Other
features are
•
•
•
Four current and voltage clamp control loops to ensure
that any dc offsets are removed from the video signal
SCART functionality and SD RGB overlay on CVBS that
are controlled by fast blank input
Four internal antialias filters to remove out-of-band noise
on standard definition input video signals
SDP PIXEL DATA OUTPUT MODES
•
•
Adaptive Digital Line Length Tracking (ADLLT™)
Proprietary architecture for locking to weak, noisy, and
unstable sources from VCRs and tuners
IF filter block to compensate for high frequency luma
attenuation due to tuner SAW filter
•
8-/10-bit ITU-R BT.656 4:2:2 YCrCb with embedded time
codes and/or HS, S, and FIELD
•
16-/20-bit YCrCb with embedded time codes and/or HS,
VS, and FIELD
•
•
•
•
Chroma transient improvement (CTI)
CP PIXEL DATA OUTPUT MODES
Luminance digital noise reduction (DNR)
Color controls including hue, brightness, saturation,
contrast, and Cr and Cb offset controls
Certified Macrovision® copy protection detection on
composite and S-Video for all worldwide formats
(PAL/NTSC/SECAM)
CP pixel data output modes include single data rate (SDR) and
double data rate (DDR) as follows:
•
•
•
•
SDR 8-/10-bit 4:2:2 YCrCb for 525i, 625i
SDR 16-/20-bit 4:2:2 YCrCb for all standards
DDR 8-/10-bit 4:2:2 YCrCb for all standards
DDR 12-bit 4:4:4 RGB for graphics inputs
•
•
4× oversampling (54 MHz) for CVBS, S-Video, and
YUV modes
•
•
•
Line-locked clock output (LLC)
Letterbox detection support
Free-run output mode to provide stable timing when no
video input is present
•
Vertical blanking interval data processor, including teletext,
video programming system (VPS), vertical interval time
codes (VITC), closed captioning (CC) and extended data
service (EDS), wide screen signaling (WSS), copy genera-
tion management system (CGMS), and compatibility with
GemStar™ 1×/2× electronic program guide
Clocked from a single 28.63636 MHz crystal
Subcarrier frequency lock (SFL) output for downstream
video encoder
•
•
•
•
Differential gain typically 0.5%
Differential phase typically 0.5°
Rev. 0 | Page 11 of 20
ADV7181C
COMPONENT VIDEO PROCESSING
GENERAL FEATURES
Component video processing supports formats including 525i,
625i, 525p, 625p, 720p, 1080i, and many other HDTV formats,
as well as automatic adjustments that include gain (contrast)
and offset (brightness), and manual adjustment controls. Other
features supported by component video processing are
General features of the ADV7181C include HS/CS, VS, and
FIELD/DE output signals with programmable position, polarity,
and width as well as a programmable interrupt request output
INT
pin,
, that signals SDP/CP status changes. Other features are
•
Low power consumption: 1.8 V digital core, 3.3 V analog
and digital I/O, low power, power-down mode, and green
PC mode
•
•
•
•
Analog component YPrPb/RGB video formats with
embedded synchronization or with separate HS, VS, or CS
Color space conversion matrix to support YCrCb-to-DDR
RGB and RGB-to-YCrCb
Standard identification (STDI) enables system level
component format detection
Synchronization source polarity detector (SSPD) to determine
the source and polarity of the synchronization signals that
accompany the input video
•
•
•
Industrial temperature range of −40°C to +85°C
64-lead, 10 mm × 10 mm, Pb-free LQFP
3.3 V ADCs giving enhanced dynamic range and
performance
•
•
•
Certified Macrovision copy protection detection on
component formats (525i, 625i, 525p, and 625p)
Free-run output mode to provide stable timing when no
video input is present
Arbitrary pixel sampling support for nonstandard video
sources
RGB GRAPHICS PROCESSING
RGB graphics processing offers a 110 MSPS conversion rate
that supports RGB input resolutions up to 1280 × 1024 at 60 Hz
(SXGA), automatic or manual clamp and gain controls for
graphics modes, and contrast and brightness controls. Other
features include
•
•
32-phase DLL to allow optimum pixel clock sampling
Automatic detection of synchronization source and
polarity by SSPD block
•
•
Standard identification enabled by the STDI block
RGB that can be color space converted to YCrCb and
decimated to a 4:2:2 format for video centric back-end
IC interfacing
•
•
•
Data enable (DE) output signal supplied for direct
connection to HDMI/DVI Tx IC
Arbitrary pixel sampling support for nonstandard
video sources
RGB graphics supported on 12-bit DDR format
Rev. 0 | Page 12 of 20
ADV7181C
DETAILED DESCRIPTION
such as VCRs, noisy sources from tuner outputs, VCD players,
and camcorders. The SDP also contains a chroma transient
improvement (CTI) processor. This processor increases the
edge rate on chroma transitions, resulting in a sharper
video image.
ANALOG FRONT END
The ADV7181C analog front end comprises four 10-bit ADCs
that digitize the analog video signal before applying it to the
SDP or CP. The analog front end uses differential channels to
each ADC to ensure high performance in a mixed-signal
application.
The SDP can process a variety of VBI data services, such as
teletext, closed captioning (CC), wide screen signaling (WSS),
video programming system (VPS), vertical interval time codes
(VITC), copy generation management system (CGMS), GemStar
1×/2×, and extended data service (XDS). The ADV7181C SDP
section has a Macrovision 7.1 detection circuit that allows it
to detect Type I, Type II, and Type III protection levels. The
decoder is also fully robust to all Macrovision signal inputs.
The front end also includes a 6-channel input mux that enables
multiple video signals to be applied to the ADV7181C. Current
and voltage clamps are positioned in front of each ADC to ensure
that the video signal remains within the range of the converter.
Fine clamping of the video signals is performed downstream by
digital fine clamping in either the CP or SDP.
Optional antialiasing filters are positioned in front of each ADC.
These filters can be used to band-limit standard definition
video signals, removing spurious out-of-band noise.
COMPONENT PROCESSOR (CP)
The CP section is capable of decoding/digitizing a wide range of
component video formats in any color space. Component video
standards supported by the CP are 525i, 625i, 525p, 625p, 720p,
1080i, graphics up to SXGA at 60 Hz, and many other standards.
The ADCs are configured to run in 4× oversampling mode
when decoding composite and S-Video inputs; 2× oversampling
is performed for component 525i, 625i, 525p, and 625p sources.
All other video standards are 1× oversampled. Oversampling
the video signals reduces the cost and complexity of external
antialiasing filters with the benefit of an increased signal-to-
noise ratio (SNR).
The CP section of the ADV7181C contains an AGC block.
When no embedded synchronization is present, the video
gain can be set manually. The AGC section is followed by a
digital clamp circuit that ensures the video signal is clamped to
the correct blanking level. Automatic adjustments within the
CP include gain (contrast) and offset (brightness); manual
adjustment controls are also supported.
The ADV7181C can support simultaneous processing of CVBS
and RGB standard definition signals to enable SCART compati-
bility and overlay functionality. A combination of CVBS and
RGB inputs can be mixed and output under the control of the
I2C registers and the fast blank pin.
A fixed mode graphics RGB to component output is available.
A color space conversion matrix is placed between the analog
front end and the CP section. This enables YPrPb-to-DDR RGB
and RGB-to-YCrCb conversions. Many other standards of color
space can be implemented using the color space converter.
STANDARD DEFINITION PROCESSOR (SDP)
The SDP section is capable of decoding a large selection of
baseband video signals in composite S-Video and YUV
formats. The video standards supported by the SDP include
PAL B/D/I/G/H, PAL60, PAL M, PAL N, NTSC M/J, NTSC
4.43, and SECAM B/D/G/K/L. The ADV7181C automatically
detects the video standard and processes it accordingly.
The output section of the CP is highly flexible. It can be confi-
gured in SDR mode with one data packet per clock cycle or in
a DDR mode where data is presented on the rising and falling
edges of the clock. In SDR mode, a 20-bit 4:2:2 is possible. In
these modes, HS/CS, VS, and FIELD/DE (where applicable)
timing reference signals are provided. In DDR mode, the
ADV7181C can be configured in an 8-bit 4:2:2 YCrCb or
12-bit 4:4:4 RGB pixel output interface with corresponding
timing signals.
The SDP has a 5-line super adaptive 2D comb filter that gives
superior chrominance and luminance separation when decoding a
composite video signal. This highly adaptive filter automatically
adjusts its processing mode according to video standards and
signal quality with no user intervention required. The SDP has
an IF filter block that compensates for attenuation in the high
frequency luma spectrum due to the tuner SAW filter.
The CP section contains circuitry to enable the detection of
Macrovision encoded YPrPb signals for 525i, 625i, 525p, and
625p. It is designed to be fully robust when decoding these
types of signals.
The SDP has specific luminance and chrominance parameter
control for brightness, contrast, saturation, and hue.
VBI extraction of component data is performed by the CP
section of the ADV7181C for interlaced, progressive, and high
definition scanning rates. The data extracted can be read back
over the I2C interface.
The ADV7181C implements a patented Adaptive-Digital-Line-
Length-Tracking (ADLLT) algorithm to track varying video
line lengths from sources such as a VCR. ADLLT enables the
ADV7181C to track and decode poor quality video sources
Rev. 0 | Page 13 of 20
ADV7181C
ANALOG INPUT MUXING
The ADV7181C has an integrated analog muxing section that allows more than one source of video signal to be connected to the decoder.
Figure 3 outlines the overall structure of the input muxing provided in the ADV7181C.
ADC_SW_MAN_EN
1
ADC0_SW[3:0]
A
A
A
1
2
IN
IN
3
4
IN
IN
ADC0
A
A
A
5
6
IN
IN
1
ADC1_SW[3:0]
A
A
3
4
IN
IN
A
A
5
6
IN
ADC1
IN
1
ADC2_SW[3:0]
A
A
2
4
IN
IN
A
A
5
6
IN
ADC2
IN
1
ADC3_SW[3:0]
A
4
IN
ADC3
Figure 3. ADV7181C Internal Pin Connections
Rev. 0 | Page 14 of 20
ADV7181C
On the ADV7181C, it is recommended to use the ADC mapping shown in Table 8.
Table 8. Recommended ADC Mapping
Mode
Required ADC Mapping
AIN Channel Core Configuration1
CVBS
ADC0
CVBS = AIN1
SD
SD
SD
CP
SD
CP
INSEL[3:0] = 0000
SDM_SEL[1:0] = 00
PRIM_MODE[3:0] = 0000
VID_STD[3:0] = 0010
INSEL[3:0] = 0000
SDM_SEL[1:0] = 11
PRIM_MODE[3:0] = 0000
VID_STD[3:0] = 0010
INSEL[3:0] = 1001
SDM_SEL[1:0] = 00
PRIM_MODE[3:0] = 0000
VID_STD[3:0] = 0010
INSEL[3:0] = 0000
SDM_SEL[1:0] = 00
PRIM_MODE[3:0] = 0000
VID_STD[3:0] = 1010
INSEL[3:0] = 0000
SDM_SEL[1:0] = 00
PRIM_MODE[3:0] = 0000
VID_STD[3:0] = 0010
INSEL[3:0] = 0000
SDM_SEL[1:0] = 00
PRIM_MODE[3:0] = 0001
VID_STD[3:0] = 1100
YC/YC auto
Y = ADC0
C = ADC1
Y = AIN2
C = AIN3
Component YUV
Component YUV
SCART RGB
Y = ADC0
U = ADC2
V = ADC1
Y = AIN6
U = AIN4
V = AIN5
Y = ADC0
U = ADC2
V = ADC1
Y = AIN6
U = AIN4
V = AIN5
CBVS = ADC0
G = ADC1
B = ADC3
R = ADC2
G = ADC0
B = ADC2
R = ADC1
CVBS = AIN2
G = AIN6
B = AIN4
R = AIN5
G = AIN6
B = AIN4
R = AIN5
Graphics
RGB Mode
1 Configuration to format follow-on blocks in correct format.
Table 9. Manual MUX Settings for All ADCs
ADC_SWITCH_MAN to 1
ADC1
ADC1_SW_SEL[3:0] Connection
ADC0
ADC2
ADC3
ADC0_SW_SEL[3:0] Connection
ADC2_SW_SEL[3:0] Connection
ADC3_SW_SEL[3:0] Connection
0001
0010
0100
0101
0110
1100
AIN1
AIN2
AIN4
AIN5
AIN6
AIN3
0001
0010
0100
0101
0110
1100
N/A
N/A
AIN4
AIN5
AIN6
AIN3
0001
0010
0100
0101
0110
1100
N/A
AIN2
AIN4
AIN5
AIN6
N/A
0001
0010
0100
0101
0110
1100
N/A
N/A
AIN4
N/A
N/A
N/A
The analog input muxes of the ADV7181C must be controlled
directly. This is referred to as manual input muxing. The manual
muxing is activated by setting the ADC_SWITCH_MAN bit
(see Table 9). It affects only the analog switches in front of the
ADCs. INSEL, SDM_SEL, PRIM_MODE, and VID_STD still
have to be set so that the follow-on blocks process the video
data in the correct format.
Table 9 explains the ADC mapping configuration for the
following:
•
•
•
•
•
ADC_SWITCH_MAN, manual input muxing enable,
IO map, Address 0C[7]
ADC0_SW[3:0], ADC0 mux configuration, IO map,
Address 0D[3:0]
ADC1_SW[3:0], ADC1 mux configuration, IO map,
Address 0D[7:4]
ADC2_SW[3:0], ADC2 mux configuration, IO map,
Address 0E[3:0]
Not every input pin can be routed to any ADC. There are
restrictions in the channel routing imposed by the analog
signal routing inside the IC. See Table 9 for an overview of
the routing capabilities inside the chip. The three mux
sections can be controlled by the reserved control signal
buses ADC0_SW[3:0]/ ADC1_SW[3:0]/ADC2_SW[3:0].
ADC3_SW[3:0], ADC3 mux configuration, IO map,
Address 0E[7:4]
Rev. 0 | Page 15 of 20
ADV7181C
PIXEL OUTPUT FORMATTING
Table 10. Pixel Output Formats
Pixel Port Pins P[19:0]
Processor, Format,
and Mode
19 18 17 16
15
14
13
12
11 10
9
8
7
6
5
4
3
2
1
0
Video output
8-bit 4:2:2
SDP
SDP
SDP
SDP
YCrCb[7:0]
YCrCb[9:0]
Y[7:0]
Video output
10-bit 4:2:2
Video output
16-bit 4:2:2
CrCb[7:0]
CrCb[7:0]
Video output
20-bit 4:2:2
Y[9:0]
D71 D61 D51 D41 D31 D21 D11 D01
B[7]↑ B[6]↑ B[5]↑ B[4]↑ B[3]↑ B[2]↑ B[1]↑ B[0]↑
R[3]↓ R[2]↓ R[1]↓ R[0]↓ G[7]↓ G[6]↓ G[5]↓ G[4]↓
D111 D101 D91 D81
G[3]↑ G[2]↑ G[1]↑ G[0]↑
R[7]↓ R[6]↓ R[5]↓ R[4]↓
Video output
12-bit 4:4:4
RGB DDR
CP
Video output
16-bit 4:2:2
CP
CP
CHA[7:0] (for example, Y[7:0])
CHA[9:0] (for example, Y[9:0])
CHB/C[7:0] (for example, Cr/Cb[7:0])
CHB/C[9:0] (for example, Cr/Cb[9:0])
Video output
20-bit 4:2:2
1 ↑ indicates data clocked on the rising edge of LLC, ↓ indicates data clocked on the falling edge of LLC.
Rev. 0 | Page 16 of 20
ADV7181C
RECOMMENDED EXTERNAL LOOP FILTER COMPONENTS
The external loop filter components for the ELPF pin should be placed as close as possible to the respective pins. Figure 4 shows the
recommended component values.
30
ELPF
1.69kΩ
10nF
82nF
PVDD = 1.8V
Figure 4. ELPF Components
Rev. 0 | Page 17 of 20
ADV7181C
TYPICAL CONNECTION DIAGRAM
5
0 0 3 - 5 1 0 7
Figure 5. ADV7181C Typical Connection
Rev. 0 | Page 18 of 20
ADV7181C
OUTLINE DIMENSIONS
12.20
12.00 SQ
11.80
0.75
0.60
0.45
1.60
MAX
64
49
1
48
PIN 1
10.20
10.00 SQ
9.80
TOP VIEW
(PINS DOWN)
1.45
1.40
1.35
0.20
0.09
7°
3.5°
0°
0.08
COPLANARITY
16
33
0.15
0.05
SEATING
17
32
PLANE
VIEW A
0.27
0.22
0.17
0.50
BSC
LEAD PITCH
VIEW A
ROTATED 90° CCW
COMPLIANT TO JEDEC STANDARDS MS-026-BCD
Figure 6. 64-Lead Low Profile Quad Flat Package [LQFP]
(ST-64)
Dimensions shown in millimeters
0.60 MAX
9.00
BSC SQ
0.60
MAX
PIN 1
INDICATOR
64
49
48
1
PIN 1
INDICATOR
0.50
BSC
7.25
7.10 SQ
6.95
8.75
BSC SQ
TOP VIEW
EXPOSED PAD
(BOTTOM VIEW)
0.50
0.40
0.30
16
17
33
32
0.25 MIN
7.50
REF
0.80 MAX
0.65 TYP
12° MAX
1.00
0.85
0.80
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.05 MAX
0.02 NOM
SECTION OF THIS DATA SHEET.
0.30
0.23
0.18
SEATING
PLANE
0.20 REF
COMPLIANT TO JEDEC STANDARDS MO-220-VMMD-4
Figure 7. 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
9 mm × 9 mm Body, Very Thin Quad (CP-64-3)
Dimensions shown in millimeters
ORDERING GUIDE
Model
Temperature Range
Package Description
64–Lead LFCSP_VQ
64-Lead LFCSP_VQ
64 –Lead LQFP
Package Option
ADV7181CBCPZ1
ADV7181CBCPZ-REEL1
ADV7181CBSTZ1
ADV7181CBSTZ-REEL1
ADV7181WBCPZ1
ADV7181WBCPZ-REEL1
ADV7181WBSTZ1
ADV7181WBSTZ_REEL1
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
CP-64-3
CP-64-3
ST-64
64–Lead LQFP
ST-64
64-Lead LFCSP_VQ
64-Lead LFCSP_VQ
64–Lead LQFP
CP-64-3
CP-64-3
ST-64
64 –Lead LQFP
ST-64
1 Z = RoHS Compliant Part.
Rev. 0 | Page 19 of 20
ADV7181C
Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent
Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
©2008 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07513-0-8/08(0)
Rev. 0 | Page 20 of 20
相关型号：
ADV7183
ADV7183: Advanced Video Decoder with 10-Bit ADC and Component Input Support Data Sheet (Rev. 0. 5/02)
ETC
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