ADV7324KSTZ_技术文档

Multiformat 216 MHz

Video Encoder with Six NSV^®14-Bit DACs

ADV7324

Programmable DAC gain control

Sync outputs in all modes

FEATURES

High definition (HD) input formats

16-/20-, 24-/30-bit (4:2:2, 4:4:4) parallel YCrCb

Fully compliant with:

SMPTE 274M (1080i, 1080p @ 74.25 MHz)

SMPTE 296M (720p)

SMPTE 240M (1035i)

RGB in 3-bit × 10-bit 4:4:4 input format

HDTV RGB supported:

On-board voltage reference

Six 14-bit NSV (noise shaped video) precision video DACs

2-wire serial I²C® interface, open-drain configuration

Dual I/O supply 2.5 V/3.3 V operation

Analog and digital supply 2.5 V

On-board PLL

64-lead LQFP package

Lead (Pb) free product

RGB, RGBHV

APPLICATIONS

Other HD formats using async

timing mode

Enhanced definition (ED) input formats

8-/10-, 16-/20-, 24-/30-bit (4:2:2, 4:4:4) parallel YCrCb

SMPTE 293M (525p)

BTA T-1004 EDTV2 (525p)

EVD (enhanced versatile disk) players

High-end SD/PS DVD recorders/players

SD/PS/HDTV display devices

SD/HDTV set top boxes

Professional video systems

ITU-R BT.1358 (625p/525p)

ITU-R BT.1362 (625p/525p)

RGB in 3-bit × 10-bit 4:4:4 input format

Standard definition (SD) input formats

CCIR-656 4:2:2 8-/10-bit or 16-/20-bit parallel input

HD output formats

YPrPb HDTV (EIA 770.3)

RGB, RGBHV

CGMS-A (720p/1080i)

ED output formats

Macrovision Rev 1.2 (525p/625p)

CGMS-A (525p/625p)

YPrPb progressive scan (PS) (EIA-770.1, EIA-770.2)

RGB, RGBHV

SD output formats

Composite NTSC M/N

SD

ADV7324

CONTROL BLOCK

COLOR CONTROL

BRIGHTNESS

DNR

14-BIT

DAC

GAMMA

PROGRAMMABLE

FILTERS

14-BIT

DAC

O

V

E

R

S

A

M

P

L

SD TEST PATTERN

D

E

M

U

X

14-BIT

DAC

Y9–Y0

C9–C0

S9–S0

PROGRAMMABLE

RGB MATRIX

14-BIT

DAC

I

N

G

HD

14-BIT

DAC

CONTROL BLOCK

HD TEST PATTERN

14-BIT

DAC

COLOR CONTROL

ADAPTIVE FILTER CTRL

SHARPNESS FILTER

HSYNC

VSYNC

BLANK

TIMING

GENERATOR

2

I C

INTERFACE

CLKIN_A

CLKIN_B

PLL

Composite PAL M/N/B/D/G/H/I, PAL-60

SMPTE 170M NTSC-compatible composite video

ITU-R BT.470 PAL-compatible composite video

S-video (Y/C)

Figure 1. Simplified Functional Block Diagram

GENERAL DESCRIPTION

The ADV®7324 is a high speed, digital-to-analog encoder on a

single monolithic chip. It includes six high speed NSV video

DACs with TTL-compatible inputs. It has separate 8-/10-,

16-/20-, and 24-/30-bit input ports that accept data in high

definition (HD) and/or standard definition (SD) video format.

For all standards, external horizontal, vertical, and blanking

signals, or EAV/SAV timing codes, control the insertion of

appropriate synchronization signals into the digital data stream

and, therefore, the output signal.

EuroScart RGB

Component YPrPb (Betacam, MII, SMPTE/EBU N10)

Macrovision Rev 7.1.L1

CGMS/WSS

Closed captioning

GENERAL FEATURES

Simultaneous SD/HD or PS/SD inputs and outputs

Oversampling up to 216 MHz

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable.

However, no responsibility is assumed by Analog Devices for its use, nor for any

infringements of patents or other rights of third parties that may result from its use.

Specifications subject to change without notice. No license is granted by implication

or otherwise under any patent or patent rights of Analog Devices. Trademarks and

registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.326.8703

www.analog.com

ADV7324

TABLE OF CONTENTS

Specifications..................................................................................... 6

Gamma Correction.................................................................... 53

HD Sharpness Filter and Adaptive Filter Controls................ 55

Dynamic Specifications ............................................................... 7

Timing Specifications .................................................................. 8

Timing Diagrams.............................................................................. 9

Absolute Maximum Ratings.......................................................... 16

Thermal Characteristics ............................................................ 16

ESD Caution................................................................................ 16

Pin Configuration and Function Descriptions........................... 17

Typical Performance Characteristics ........................................... 19

MPU Port Description................................................................... 23

Register Access................................................................................ 25

Register Programming............................................................... 25

Subaddress Registers (SR7 to SR0)........................................... 25

Input Configuration ....................................................................... 38

SD Only........................................................................................ 38

PS Only or HDTV Only ............................................................ 38

Simultaneous SD/PS or SD/HDTV.......................................... 38

PS at 27 MHz (Dual Edge) or 54 MHz.................................... 39

Features ............................................................................................ 41

Output Configuration................................................................ 41

HD Async Timing Mode........................................................... 42

HD Timing Reset........................................................................ 43

HD Sharpness Filter and Adaptive Filter

Application Examples ................................................................ 56

SD Digital Noise Reduction...................................................... 57

Coring Gain Border ................................................................... 58

Coring Gain Data....................................................................... 58

DNR Threshold .......................................................................... 58

Border Area................................................................................. 58

Block Size Control...................................................................... 58

DNR Input Select Control......................................................... 58

DNR Mode Control ................................................................... 59

Block Offset Control.................................................................. 59

SD Active Video Edge................................................................ 59

SAV/EAV Step-Edge Control ................................................... 59

Hsync/Vsync Output Control .................................................. 61

Board Design and Layout.............................................................. 62

DAC Termination and Layout Considerations ...................... 62

Video Output Buffer and Optional Output Filter.................. 62

PCB Board Layout...................................................................... 63

Appendix 1—Copy Generation Management System .............. 65

PS CGMS..................................................................................... 65

HD CGMS................................................................................... 65

SD CGMS .................................................................................... 65

CGMS Functionality.................................................................. 65

Appendix 2—SD Wide-Screen Signaling.................................... 68

Appendix 3—SD Closed Captioning........................................... 70

Appendix 4—Test Patterns............................................................ 71

Appendix 5—SD Timing Modes.................................................. 74

SD Real-Time Control, Subcarrier Reset, and

Timing Reset ............................................................................... 43

Reset Sequence............................................................................ 45

SD VCR FF/RW Sync................................................................. 45

Vertical Blanking Interval ......................................................... 46

Subcarrier Frequency Registers................................................ 46

Square Pixel Timing Mode........................................................ 47

Filters............................................................................................ 48

Color Controls and RGB Matrix .............................................. 49

Programmable DAC Gain Control .......................................... 53

Mode 0 (CCIR-656)—Slave Option

(Timing Register 0 TR0 = X X X X X 0 0 0) ........................... 74

Mode 0 (CCIR-656)—Master Option

(Timing Register 0 TR0 = X X X X X 0 0 1) ........................... 75

Rev. 0 | Page 2 of 92

ADV7324

Mode 1—Slave Option

(Timing Register 0 TR0 = X X X X X 0 1 0) ............................77

Appendix 6—HD Timing ..............................................................82

Appendix 7—Video Output Levels...............................................83

HD YPrPb Output Levels ..........................................................83

RGB Output Levels .....................................................................84

YPrPb Levels—SMPTE/EBU N10............................................85

Appendix 8—Video Standards......................................................87

Outline Dimensions........................................................................89

Ordering Guide ...........................................................................89

Mode 1—Master Option

(Timing Register 0 TR0 = X X X X X 0 1 1) ............................78

Mode 2— Slave Option

(Timing Register 0 TR0 = X X X X X 1 0 0) ............................79

Mode 2—Master Option

(Timing Register 0 TR0 = X X X X X 1 0 1) ............................80

Mode 3—Master/Slave Option

(Timing Register 0 TR0 = X X X X X 1 1 0 or X X X X X 1 1 1)

.......................................................................................................81

REVISION HISTORY

11/04—Revision 0: Initial Version

Rev. 0 | Page 3 of 92

ADV7324

Table 1. Standards Directly Supported¹

DETAILED FEATURES

Frame

Clock

Input

(MHz)

HD programmable features (720p/1080i/1035i)

2× oversampling (148.5 MHz)

Internal test pattern generator

Color hatch, black bar, flat field/frame

Fully programmable YCrCb to RGB matrix

Gamma correction

Programmable adaptive filter control

Programmable sharpness filter control

CGMS-A (720p/1080i)

ED programmable features (525p/625p)

8× oversampling (216 MHz output)

Internal test pattern generator

Color hatch, black bar, flat frame

Individual Y and PrPb output delay

Gamma correction

Interlace/ Rate

Resolution

PS

(Hz)

Standard

720 × 480

I

29.97

27

ITU-R

BT.656

720 × 576

720 × 480

25

27

ITU-R

BT.656

29.97

24.54

NTSC

Square

Pixel

720 × 576

720 × 483

I

25

29.5

27

PAL Square

Pixel

SMPTE

293M

P

59.94

720 × 483

P

59.94

27

BTA T-1004

ITU-R

BT.1358

Programmable adaptive filter control

Fully programmable YCrCb to RGB matrix

Undershoot limiter

Macrovision Rev 1.2 (525p/625p)

CGMS-A (525p/625p)

720 × 576

720 × 483

720 × 576

1920 × 1035

P

I

50

27

ITU-R

BT.1358

ITU-R

BT.1362

ITU-R

BT.1362

SMPTE

240M

59.94

50

SD programmable features

30

29.97

60, 50,

30, 25, 24

74.25

74.1758

74.25

16× oversampling (216 MHz)

Internal test pattern generator

Color bars, black bar

1280 × 720

P

SMPTE

296M

Controlled edge rates for start and end of active video

Individual Y and PrPb output delay

Undershoot limiter

23.97,

59.94,

29.97

74.1758

1920 × 1080

I

30, 25

29.97

30, 25, 24 74.25

23.98,

29.97

74.25

74.1758

SMPTE

274M

Gamma correction

Digital noise reduction (DNR)

Multiple chroma and luma filters

Luma-SSAF™ filter with programmable gain/attenuation

PrPb SSAF™

P

SMPTE

274M

74.1758

Separate pedestal control on component and

composite/S-video output

¹Other standards are supported in async timing mode.

VCR FF/RW sync mode

Macrovision Rev 7.1.L1

CGMS/WSS

Closed captioning

Rev. 0 | Page 4 of 92

ADV7324

HD PIXEL

INPUT

SHARPNESS

AND

Y

CR

CB

Y COLOR

CR COLOR

CB COLOR

DE-

TEST

DAC

4:2:2

TO

4:4:4

INTER-

LEAVE

ADAPTIVE

FILTER

PS 8×

PATTERN

HDTV 2×

CLKIN_B

CONTROL

P_HSYNC

P_VSYNC

P_BLANK

TIMING

GENERATOR

CLOCK

CONTROL

AND PLL

U

V

UV SSAF

S_HSYNC

S_VSYNC

S_BLANK

RGB

TIMING

GENERATOR

MATRIX

SD 16×

CLKIN_A

CB

CR

Y

DE-

INTER-

LEAVE

LUMA

AND

F

TEST

PATTERN

DNR

GAMMA

COLOR

CONTROL

SYNC

INSERTION

SC

2× OVER-

SAMPLING

CGMS

WSS

MODU-

LATION

CHROMA

FILTERS

SD PIXEL

INPUT

Figure 2. Detailed Functional Block Diagram

TERMINOLOGY

HDTV: high definition television video, conforming to

SMPTE 274M, or SMPTE 296M and SMPTE 240M.

SD: standard definition video, conforming to

ITU-R BT.601/ITU-R BT.656.

YCrCb SD, PS, or HD component: digital video.

YPrPb SD, PS, or HD component: analog video.

HD: high definition video, i.e., 720p/1080i/1035i.

EDTV: enhanced definition television (525p/625p).

PS: progressive scan video, conforming to SMPTE 293M,

ITU-R BT.1358, BTA T-1004 EDTV2, or ITU-R BT.13621362.

Rev. 0 | Page 5 of 92

ADV7324

SPECIFICATIONS

V_AA= 2.375 V to 2.625 V, V_DD= 2.375 V to 2.625 V, V_{DD_IO}= 2.375 V to 3.6 V, V_REF= 1.235 V, R_SET= 3040 Ω, R_LOAD= 150 Ω. All

specifications T_MINto T_MAX(0°C to 70°C), unless otherwise noted.

Table 2.

Parameter

STATIC PERFORMANCE¹

Min

Typ

Max

Unit

Test Conditions

Resolution

Integral Nonlinearity

Differential Nonlinearity,²+ve

Differential Nonlinearity,²−ve

DIGITAL OUTPUTS

Output Low Voltage, V_OL

Output High Voltage, V_OH

Three-State Leakage Current

Three-State Output Capacitance

DIGITAL AND CONTROL INPUTS

Input High Voltage, V_IH

Input Low Voltage, V_IL

Input Leakage Current

Input Capacitance, C_IN

ANALOG OUTPUTS

14

Bits

LSB

2.0

1.0

3.0

0.4 [0.4]³

V

µA

pF

I_SINK= 3.2 mA

I_SOURCE= 400 µA

V_IN= 0.4 V, 2.4 V

2.4 [2.0]³

1.0

2

V

µA

pF

0.8

10

2

V_IN= 2.4 V

Full-Scale Output Current

Output Current Range

DAC-to-DAC Matching

Output Compliance Range, V_OC

Output Capacitance, C_OUT

VOLTAGE REFERENCE

Internal Reference Range, V_REF

External Reference Range, V_REF

V_REFCurrent⁴

4.1

4.33

1.0

7

4.6

mA

%

V

pF

0

1.4

1.15

1.235

10

1.3

V

µA

POWER REQUIREMENTS

Normal Power Mode

5

I_DD

137

78

73

140

1.0

37

mA

SD only (16×)

PS only (8×)

HDTV only (2×)

SD (16×, 10-bit) + PS (8×, 20-bit)

190⁶

45

I_{DD_IO}

7, 8

I_AA

Sleep Mode

I_DD

80

µA

I_AA

7

µA

I_{DD_IO}

250

0.01

µA

POWER SUPPLY REJECTION RATIO

%/%

¹Oversampling disabled. Static DAC performance improves with increased oversampling ratios.

²DNL measures the deviation of the actual DAC output voltage step from the ideal. For +ve DNL, the actual step value lies above the ideal step value; for −ve DNL, the

actual step value lies below the ideal step value.

³For values in brackets, V_{DD_IO}= 2.375 V to 2.75 V.

⁴External current required to overdrive internal V_REF

.

⁵I_DD, the circuit current, is the continuous current required to drive the digital core.

⁶Guaranteed maximum by characterization.

⁷All DACs on.

⁸I_AAis the total current required to supply all DACs, including the V_REFcircuitry and the PLL circuitry.

Rev. 0 | Page 6 of 92

ADV7324

DYNAMIC SPECIFICATIONS

V_AA= 2.375 V to 2.625 V, V_DD= 2.375 V to 2.625 V, V_{DD_IO}= 2.375 V to 3.6 V, V_REF= 1.235 V, R_SET= 3040 Ω, R_LOAD= 150 Ω. All

specifications T_MINto T_MAX(0°C to 70°C), unless otherwise noted.

Table 3.

Parameter

Min

Typ

Max

Unit

Test Conditions

PS MODE

Luma Bandwidth

Chroma Bandwidth

SNR

12.5

5.8

65.6

72

MHz

dB

Luma ramp unweighted

Flat field full bandwidth

dB

HDTV MODE

Luma Bandwidth

Chroma Bandwidth

SD MODE

30

13.75

MHz

Hue Accuracy

0.44

0.20

0.84

−0.2

0

97.5

0

0.1

Degrees

%

Degrees

%

ns

%

dB

%

Degrees

dB

Color Saturation Accuracy

Chroma Nonlinear Gain

Chroma Nonlinear Phase

Chroma/Luma Intermodulation

Chroma/Luma Gain Inequality

Chroma/Luma Delay Inequality

Luminance Nonlinearity

Chroma AM Noise

Chroma PM Noise

Referenced to 40 IRE

84

75.3

0.09

0.12

63.5

77.7

Differential Gain

Differential Phase

SNR

NTSC

Luma ramp

Flat field full bandwidth

Rev. 0 | Page 7 of 92

ADV7324

TIMING SPECIFICATIONS

V_AA= 2.375 V to 2.625 V, V_DD= 2.375 V to 2.625 V, V_{DD_IO}= 2.375 V to 3.6 V, V_REF= 1.235 V, R_SET= 3040 Ω, R_LOAD= 150 Ω. All

specifications T_MINto T_MAX(0°C to 70°C), unless otherwise noted.

Table 4.

Parameter

Min Typ Max Unit

Test Conditions

MPU PORT¹

SCLOCK Frequency

0

400

kHz

µs

SCLOCK High Pulse Width, t₁

SCLOCK Low Pulse Width, t₂

Hold Time (Start Condition), t₃

0.6

1.3

0.6

µs

First clock generated after this period relevant for

repeated start condition

Setup Time (Start Condition), t₄

Data Setup Time, t₅

SDATA, SCLOCK Rise Time, t₆

SDATA, SCLOCK Fall Time, t₇

Setup Time (Stop Condition), t₈

0.6

100

µs

ns

µs

ns

300

0.6

100

Low Time

RESET

ANALOG OUTPUTS

Analog Output Delay²

Output Skew

7

1

ns

CLOCK CONTROL AND PIXEL PORT³

f_CLK

29.5 MHz

MHz

SD PAL square pixel mode

PS/HD async mode

81

Clock High Time, t₉

Clock Low Time, t₁₀

40

2.0

% of one clock cycle

ns

1

Data Setup Time, t₁₁

1

Data Hold Time, t₁₂

SD Output Access Time, t₁₃

SD Output Hold Time, t₁₄

HD Output Access Time, t₁₃

HD Output Hold Time, t₁₄

PIPELINE DELAY⁴

15

14

ns

5.0

63

76

35

41

36

Clock cycles

SD (2×, 16×)

SD component mode (16×)

PS (1×)

PS (8×)

HD (2×, 1×)

¹Guaranteed by characterization.

²Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of DAC output full-scale transition.

3

P_HSYNC P_VSYNC P_BLANK S_HSYNC S_VSYNC S_BLANK

Data: C[9:0]; Y[9:0], S[9:0]; Control:

⁴SD, PS = 27 MHz, HD = 74.25 MHz.

,

.

Rev. 0 | Page 8 of 92

ADV7324

TIMING DIAGRAMS

CLKIN_A

t₉

t

10

t₁₂

P_HSYNC,

P_VSYNC,

P_BLANK

CONTROL

INPUTS

Y9–Y0

C9–C0

Y0

Y1

Y2

Y3

Y4

Y5

Cr0

t₁₁

Cr4

Cb0

Cb4

Cb2

Cr2

t₁₃

CONTROL

OUTPUTS

t₁₄

t₉= CLOCK HIGH TIME

t₁₀= CLOCK LOW TIME

t₁₁= DATA SETUP TIME

t₁₂= DATA HOLD TIME

Figure 3. HD Only 4:2:2 Input Mode (Input Mode 010); PS Only 4:2:2 Input Mode (Input Mode 001)

CLKIN_A

t₉

t₁₂

t₁₀

P_HSYNC,

P_VSYNC,

P_BLANK

CONTROL

INPUTS

Y9–Y0

C9–C0

Y0

Y1

Y2

Y3

Y4

Y5

Cb1

t₁₁

Cb2

Cr2

Cb3

Cb4

Cb5

Cb0

Cr1

Cr3

Cr4

Cr5

S9–S0

Cr0

CONTROL

OUTPUTS

t₁₄

t₁₃

t₉= CLOCK HIGH TIME

t₁₀= CLOCK LOW TIME

t₁₁= DATA SETUP TIME

t₁₂= DATA HOLD TIME

Figure 4. HD Only 4:4:4 Input Mode (Input Mode 010); PS Only 4:4:4 Input Mode (Input Mode 001)

Rev. 0 | Page 9 of 92

ADV7324

CLKIN_A

t₉

t₁₂

t₁₀

P_HSYNC,

P_VSYNC,

P_BLANK

CONTROL

INPUTS

Y9–Y0

C9–C0

G0

B0

G1

B1

G2

G3

B3

G4

B4

G5

B5

B2

R2

t₁₁

R1

S9–S0

R0

R3

R4

R5

CONTROL

OUTPUTS

t₁₄

t₁₃

t₉= CLOCK HIGH TIME

t₁₀= CLOCK LOW TIME

t₁₁= DATA SETUP TIME

t₁₂= DATA HOLD TIME

Figure 5. HD RGB 4:4:4 Input Mode (Input Mode 010)

CLKIN_B*

t

9

t₁₀

P_HSYNC,

P_VSYNC,

P_BLANK

CONTROL

INPUTS

Crxxx

Yxxx

Y9–Y0

Cb0

t₁₂

Y0

Cr0

Y1

t₁₂

t₁₁

t₁₃

CONTROL

OUTPUTS

t₁₄

t₉= CLOCK HIGH TIME

t₁₀= CLOCK LOW TIME

t₁₁= DATA SETUP TIME

t₁₂= DATA HOLD TIME

*CLKIN_B MUST BE USED IN THIS PS MODE

HSYNC VSYNC

/

Figure 6. PS 4:2:2 10-Bit Interleaved at 27 MHz

Input Mode (Input Mode 100)

CLKIN_A

t₁₀

t₉

P_VSYNC,

P_HSYNC,

P_BLANK

CONTROL

INPUTS

Crxxx

Cb0

Y1

Y0

Cr0

Yxxx

Y9–Y0

t₁₂

t₁₃

t₁₄

t₁₁

CONTROL

OUTPUTS

t₉= CLOCK HIGH TIME

t₁₀= CLOCK LOW TIME

t₁₁= DATA SETUP TIME

t₁₂= DATA HOLD TIME

HSYNC VSYNC

Input Mode (Input Mode 111)

Figure 7. PS 4:2:2 10-Bit Interleaved at 54 MHz

/

Rev. 0 | Page 10 of 92

ADV7324

CLKIN_B*

Y9–Y0

t₉

t₁₀

3FF

t

00

XY

t₁₂

Cb0

Y0

Cr0

Y1

12

t₁₁

t₁₃

CONTROL

OUTPUTS

t₁₄

t₉= CLOCK HIGH TIME

t₁₀= CLOCK LOW TIME

t₁₁= DATA SETUP TIME

t₁₂= DATA HOLD TIME

*CLKIN_B USED IN THIS PS ONLY MODE

Figure 8. PS Only 4:2:2 10-Bit Interleaved at 27 MHz EAV/SAV Input Mode (Input Mode 100)

CLKIN_A

t₁₀

t₉

Y9–Y0

3FF

00

XY

Cb0

Y0

Y1

Cr0

t₁₂

t₁₃

t₁₄

t₁₁

CONTROL

OUTPUTS

t₉= CLOCK HIGH TIME

t₁₀= CLOCK LOW TIME

t₁₁= DATA SETUP TIME

t₁₂= DATA HOLD TIME

NOTE: Y0, Cb0 SEQUENCE AS PER SUBADDRESS 0x01, BIT 1

Figure 9. PS Only 4:2:2 10-Bit Interleaved at 54 MHz EAV/SAV Input Mode (Input Mode 111)

CLKIN_B

t₁₂

t₁₀

t₉

P_HSYNC,

P_VSYNC,

P_BLANK

CONTROL

INPUTS

HD INPUT

Y9–Y0

C9–C0

Y0

Y1

Y3

Y4

Y5

Y2

Cr0

Cr4

Cb0

Cb2

Cr2

Cb4

t₁₁

CLKIN_A

t₁₂

t₉

t₁₀

S_HSYNC,

S_VSYNC,

S_BLANK

CONTROL

INPUTS

SD INPUT

S9–S0

Cr0

Y1

Cb0

Y0

Cb1

Y2

t₁₁

Figure 10. HD 4:2:2 and SD 10-Bit Simultaneous Input Mode (Input Mode 101: SD Oversampled) (Input Mode 110: HD Oversampled)

Rev. 0 | Page 11 of 92

ADV7324

CLKIN_B

t₁₂

t₁₀

t₉

P_HSYNC,

P_VSYNC,

P_BLANK

CONTROL

INPUTS

PS INPUT

Y9–Y0

C9–C0

Y0

Y1

Y3

Y4

Y5

Y2

Cr0

Cr4

Cb0

Cb2

Cr2

Cb4

t₁₁

CLKIN_A

t₁₂

t₉

t₁₀

S_HSYNC,

S_VSYNC,

S_BLANK

CONTROL

INPUTS

SD INPUT

S9–S0

Cr0

Y1

Cb0

Y0

Cb1

Y2

t₁₁

Figure 11. PS 4:2:2 and SD 10-Bit Simultaneous Input Mode (Input Mode 011)

CLKIN_B

t₉

t₁₀

P_HSYNC,

P_VSYNC,

P_BLANK

CONTROL

INPUTS

PS INPUT

Crxxx

Yxxx

Cr0

Y1

t₁₂

Y9–Y0

Cb0

t₁₂

Y0

t₁₁

CLKIN_A

t₁₂

t₉

t₁₀

S_HSYNC,

S_VSYNC,

S_BLANK

CONTROL

INPUTS

SD INPUT

S9–S0

Cr0

Y1

Cb0

Y0

Cb1

Y2

t₁₁

Figure 12. PS 10-Bit and SD 10-Bit Simultaneous Input Mode (Input Mode 100)

Rev. 0 | Page 12 of 92

ADV7324

CLKIN_A

t₉

t

10

t₁₂

S_HSYNC,

S_VSYNC,

S_BLANK

CONTROL

INPUTS

IN SLAVE MODE

S9–S0/Y9–Y0*

Cb0

Cr0

t₁₁

Cb4

t₁₃

Cr4

Cb2

Cr2

CONTROL

OUTPUTS

IN MASTER/SLAVE MODE

t₁₄

*SELECTED BY ADDRESS 0x01, BIT 7

Figure 13. 10-/8-Bit SD Only Pixel Input Mode (Input Mode 000)

CLKIN_A

t₉

t₁₀

t₁₂

S_HSYNC,

S_VSYNC,

S_BLANK

CONTROL

INPUTS

IN SLAVE MODE

S9–S0/Y9–Y0*

C9–C0

Y0

Y1

Y2

Y3

Cb0

Cr0

Cb2

Cr2

t₁₁

t₁₃

CONTROL

OUTPUTS

IN MASTER/SLAVE MODE

t₁₄

*SELECTED BY ADDRESS 0x01, BIT 7

Figure 14. 20-/16-Bit SD Only Pixel Input Mode (Input Mode 000)

Rev. 0 | Page 13 of 92

ADV7324

Y OUTPUT

c

P_HSYNC

P_VSYNC

a

P_BLANK

Y9–Y0

Y2

Y3

Y0

Y1

Cb0 Cr0 Cr1 Cb1

C9–C0

b

a AND b AS PER RELEVANT STANDARD.

c = PIPELINE DELAY. PLEASE REFER TO RELEVANT PIPELINE DELAY. THIS CAN BE FOUND IN THE TIMING SPECIFICATIONS

SECTION OF THE DATA SHEET.

A FALLING EDGE OF HSYNC INTO THE ENCODER GENERATES A FALLING EDGE OF TRILEVEL SYNC ON THE OUTPUT

AFTER A TIME EQUAL TO THE PIPELINE DELAY.

Figure 15. HD 4:2:2 Input Timing Diagram

P_HSYNC

P_VSYNC

a

P_BLANK

Cr

Y

Y9–Y0

Cb

Y

b

a = 32 CLOCK CYCLES FOR 525p

a = 24 CLOCK CYCLES FOR 625p

AS RECOMMENDED BY STANDARD

b(MIN) = 244 CLOCK CYCLES FOR 525p

b(MIN) = 264 CLOCK CYCLES FOR 625p

Figure 16. PS 4:2:2 10-Bit Interleaved Input Timing Diagram

Rev. 0 | Page 14 of 92

ADV7324

S_HSYNC

S_VSYNC

PAL = 24 CLOCK CYCLES

NTSC = 32 CLOCK CYCLES

S_BLANK

Cr

Y

S9–S0/Y9–Y0*

Cb

Y

PAL = 264 CLOCK CYCLES

NTSC = 244 CLOCK CYCLES

*SELECTED BY ADDRESS 0x01, BIT 7

Figure 17. SD Timing Input for Timing Mode 1

t₃

t₅

t₃

SDA

t₁

t₆

SCLK

t₄

t₂

t₇

t₈

Figure 18. MPU Port Timing Diagram

Rev. 0 | Page 15 of 92

ADV7324

ABSOLUTE MAXIMUM RATINGS

Table 5.

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those listed in the operational sections

of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

Parameter¹

Value

V_AAto AGND

V_DDto DGND

−0.3 V to +3.0 V

−0.3 V to +4.6 V

−0.3 V to V_{DD_IO}+0.3 V

−0.3 V to +0.3 V

V_{DD_IO}to GND_IO

Digital Input Voltage to DGND

V_AAto V_DD

AGND to DGND

DGND to GND_IO

AGND to GND_IO

THERMAL CHARACTERISTICS

Ambient Operating Temperature (T_A) 0°C to 70°C

Storage Temperature (T_S)

Infrared Reflow Soldering (20 s)

–65°C to +150°C

260°C

θ_JC= 11°C/W

θ_JA= 47°C/W

¹Analog output short circuit to any power supply or common can be of

an indefinite duration.

The ADV7324 is a Pb-free, environmentally friendly product. It is

manufactured using the most up-to-date materials and processes.

The coating on the leads of each device is 100% pure Sn electro-

plate. The device is suitable for Pb-free applications and is able

to withstand surface-mount soldering up to 255°C ( 5°C).

In addition, it is backward-compatible with conventional SnPb

soldering processes. This means that the electroplated Sn coating

can be soldered with Sn/Pb solder pastes at conventional reflow

temperatures of 220°C to 235°C.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily

accumulate on the human body and test equipment and can discharge without detection. Although

this product features proprietary ESD protection circuitry, permanent damage may occur on devices

subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are

recommended to avoid performance degradation or loss of functionality.

Rev. 0 | Page 16 of 92

ADV7324

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

1

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

V

S_BLANK

DD_IO

PIN 1

2

3

Y0

R

SET1

REF

Y1

Y2

Y3

Y4

Y5

Y6

Y7

V

4

COMP1

DAC A

DAC B

DAC C

5

6

ADV7324

TOP VIEW

(Not to Scale)

7

8

V

AA

9

AGND

DAC D

DAC E

DAC F

COMP2

10

11

12

13

14

15

16

V

DD

DGND

Y8

Y9

C0

R

SET2

C1

EXT_LF

RESET

C2

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

Figure 19. Pin Configuration

Table 6. Pin Function Descriptions

Pin No.

11, 57

40

32

63

Mnemonic

Input/Output Description

DGND

AGND

CLKIN_A

CLKIN_B

G

I

Digital Ground.

Analog Ground.

Pixel Clock Input for HD Only (74.25 MHz), PS Only (27 MHz), and SD Only (27 MHz).

I

Pixel Clock Input. Requires a 27 MHz reference clock for PS mode or a 74.25 MHz

(74.1758 MHz) reference clock in HDTV mode. This clock is only used in dual modes.

45, 36

44

43

42

39

COMP1, 2

DAC A

DAC B

DAC C

DAC D

O

Compensation Pin for DACs. Connect 0.1 µF capacitor from COMP pin to V_AA.

CVBS/Green/Y/Y Analog Output.

Chroma/Blue/U/Pb Analog Output.

Luma/Red/V/Pr Analog Output.

In SD Only Mode: CVBS/Green/Y Analog Output; in HD Only Mode and Simultaneous HD/SD

Mode: Y/Green [HD] Analog Output.

38

37

DAC E

DAC F

O

In SD Only Mode: Luma/Blue/U Analog Output; in HD Only Mode and Simultaneous HD/SD

Mode: Pr/Red Analog Output.

In SD Only Mode: Chroma/Red/V Analog Output; in HD Only Mode and Simultaneous HD/SD

Mode: Pb/Blue [HD] Analog Output.

23

24

25

48

49

50

P_HSYNC

P_VSYNC

P_BLANK

S_BLANK

S_VSYNC

S_HSYNC

Y9 to Y0

I

Video Horizontal Sync Control Signal for HD in Simultaneous SD/HD Mode and HD Only Mode.

Video Vertical Sync Control Signal for HD in Simultaneous SD/HD Mode and HD Only Mode.

Video Blanking Control Signal for HD in Simultaneous SD/HD Mode and HD Only Mode.

Video Blanking Control Signal for SD Only.

I

I/O

I

Video Vertical Sync Control Signal for SD Only.

Video Horizontal Sync Control Signal for SD Only.

13,12,

9 to 2

SD or PS/HDTV Input Port for Y Data. Input port for interleaved PS data. The LSB is set up on

Pin Y0. For 8-bit data input, LSB is set up on Y2.

30 to 26,

18 to 14

62 to 58,

55 to 51

C9 to C0

S9 to S0

I

PS/HDTV Input Port 4:4:4 Input Mode. This port is used for the Cb[Blue/U] data. The LSB is set

up on Pin C0. For 8-bit data input, LSB is set up on C2.

SD or PS/HDTV Input Port for Cr[Red/V] Data in 4:4:4 Input Mode. LSB is set up on Pin S0. For

8-bit data input, LSB is set up on S2.

Rev. 0 | Page 17 of 92

ADV7324

Pin No.

Mnemonic

Input/Output Description

33

RESET

I

This input resets the on-chip timing generator and sets the ADV7324 to its default register

setting. RESET is an active low signal.

47, 35

R_SET1, R_SET2

I

A 3040 Ω resistor must be connected from this pin to AGND and is used to control the

amplitudes of the DAC outputs.

22

21

20

SCLK

SDA

ALSB

I

I²C Port Serial Interface Clock Input.

I²C Port Serial Data Input/Output.

I/O

I

TTL Address Input. This signal sets up the LSB of the I²C address. When this pin is tied low, the

I²C filter is activated, which reduces noise on the I²C interface.

1

V_{DD_IO}

V_DD

V_AA

P

Power Supply for Digital Inputs and Outputs.

Digital Power Supply.

Analog Power Supply.

10, 56

41

46

34

31

19

V_REF

I/O

Optional External Voltage Reference Input for DACs or Voltage Reference Output (1.235 V).

External Loop Filter for the Internal PLL.

Multifunctional Input. Real-time control (RTC) input, timing reset input, subcarrier reset input.

This input pin must be tied high (V_{DD_IO}) for the ADV7324 to interface over the I²C port.

Digital Input/Output Ground.

EXT_LF

RTC_SCR_TR

I²C

I

64

GND_IO

Rev. 0 | Page 18 of 92

ADV7324

TYPICAL PERFORMANCE CHARACTERISTICS

Y PASS BAND IN PS OVERSAMPLING MODE

PS Pr/Pb RESPONSE. LINEAR INTERP FROM 4:2:2 TO 4:4:4

0

1.0

0.5

–10

–20

–30

–40

–50

–60

–70

–80

0

–0.5

–1.0

–1.5

–2.0

–2.5

–3.0

0

20

40

60

80 100 120 140 160 180 200

FREQUENCY (MHz)

0

2

4

6

8

10

12

FREQUENCY (MHz)

Figure 20. PS—UV 8× Oversampling Filter (Linear)

Figure 23. PS—Y 8× Oversampling Filter (Pass Band)

PS Pr/Pb RESPONSE. SSAF INTERP FROM 4:2:2 TO 4:4:4

Pr/Pb RESPONSE IN HDTV OVERSAMPLING MODE

0

–10

–20

–30

–40

–50

–60

–70

–80

–10

–20

–30

–40

–50

–60

–70

–80

0

20

40

60

80 100 120 140 160 180 200

FREQUENCY (MHz)

0

20

40

60

80

100

120

140

FREQUENCY (MHz)

Figure 21. PS—UV 8× Oversampling Filter (SSAF)

Figure 24. HDTV—UV 2× Oversampling Filter

Y RESPONSE IN PS OVERSAMPLING MODE

Y RESPONSE IN HDTV OVERSAMPLING MODE

0

–10

–20

–30

–40

–50

–60

–70

–80

0

–10

–20

–30

–40

–50

–60

–70

–80

0

20

40

60

80 100 120 140 160 180 200

FREQUENCY (MHz)

0

20

40

60

80

100

120

140

FREQUENCY (MHz)

Figure 22. PS—Y 8× Oversampling Filter

Figure 25. HDTV—Y 2× Oversampling Filter

Rev. 0 | Page 19 of 92

ADV7324

0

–10

–20

–30

–40

–50

–60

0

–10

–20

–30

–40

–50

–60

–70

0

2

4

6

8

10

12

0

2

4

6

8

10

12

FREQUENCY (MHz)

Figure 26. Luma NTSC Low-Pass Filter

Figure 29. Luma PAL Notch Filter

Y RESPONSE IN SD OVERSAMPLING MODE

0

–10

–20

–30

–40

–50

–60

0

–10

–20

–30

–40

–50

–60

–70

–80

–70

0

20

40

60

80 100 120 140 160 180 200

FREQUENCY (MHz)

2

4

6

8

10

12

FREQUENCY (MHz)

Figure 27. Luma PAL Low-Pass Filter

Figure 30. Y—16× Oversampling Filter

0

–10

–20

–30

–40

–50

–60

–70

0

–10

–20

–30

–40

–50

–60

–70

0

2

4

6

8

10

12

2

4

6

8

10

12

FREQUENCY (MHz)

Figure 31. Luma SSAF Filter up to 12 MHz

Figure 28. Luma NTSC Notch Filter

Rev. 0 | Page 20 of 92

ADV7324

4

2

0

–10

–20

–30

–40

–50

–60

–70

0

–2

–4

–6

–8

–10

–12

0

1

2

3

4

6

7

0

2

4

6

8

10

12

5

FREQUENCY (MHz)

Figure 32. Luma SSAF Filter—Programmable Responses

Figure 35. Luma CIF Low-Pass Filter

5

4

3

2

1

0

–10

–20

–30

–40

–50

–60

–70

–1

0

2

4

6

8

10

12

5

6

7

0

1

2

3

4

FREQUENCY (MHz)

Figure 33. Luma SSAF Filter—Programmable Gain

Figure 36. Luma QCIF Low-Pass Filter

1

0

–10

–20

–30

–40

–50

–60

–70

0

–1

–2

–3

–4

–5

0

1

2

3

4

5

6

7

0

2

4

6

8

10

12

FREQUENCY (MHz)

Figure 34. Luma SSAF Filter—Programmable Attenuation

Figure 37. Chroma 3.0 MHz Low-Pass Filter

Rev. 0 | Page 21 of 92

ADV7324

0

–10

–20

–30

–40

–50

–60

0

–10

–20

–30

–40

–50

–60

–70

0

10

12

2

4

6

8

0

2

4

6

8

10

12

FREQUENCY (MHz)

Figure 38. Chroma 2.0 MHz Low-Pass Filter

Figure 41. Chroma 0.65 MHz Low-Pass Filter

0

–10

–20

–30

–40

–50

–60

0

–10

–20

–30

–40

–50

–60

–70

0

2

4

6

8

10

12

0

2

4

6

8

10

12

FREQUENCY (MHz)

Figure 39. Chroma 1.3 MHz Low-Pass Filter

Figure 42. Chroma CIF Low-Pass Filter

0

–10

–20

–30

–40

–50

–60

0

–10

–20

–30

–40

–50

–60

–70

0

10

12

2

4

6

8

0

2

4

6

8

10

12

FREQUENCY (MHz)

Figure 40. Chroma 1.0 MHz Low-Pass Filter

Figure 43. Chroma QCIF Low-Pass Filter

Rev. 0 | Page 22 of 92

ADV7324

MPU PORT DESCRIPTION

The ADV7324 supports a 2-wire serial (I²C-compatible)

microprocessor bus driving multiple peripherals. This port

operates in an open-drain configuration. Two inputs, serial data

(SDA) and serial clock (SCL), carry information between any

device connected to the bus and the ADV7324. Each slave

device is recognized by a unique address. The ADV7324 has

four possible slave addresses for both read and write operations.

These are unique addresses for each device and are illustrated in

Figure 44. The LSB sets either a read or write operation. Logic 1

corresponds to a read operation, while Logic 0 corresponds to a

write operation. A1 is enabled by setting the ALSB pin of the

ADV7324 to Logic 0 or Logic 1. When ALSB is set to 1, there is

greater input bandwidth on the I²C lines, which allows high

speed data transfers on this bus. When ALSB is set to 0, there is

reduced input bandwidth on the I²C lines, which means that

pulses of less than 50 ns will not pass into the I²C internal

controller. This mode is recommended for noisy systems.

The ADV7324 acts as a standard slave device on the bus. The

data on the SDA pin is eight bits long, supporting the 7-bit

address plus the R/ bit. It interprets the first byte as the device

W

address and the second byte as the starting subaddress. There is

a subaddress auto-increment facility. This allows data to be

written to or read from registers in ascending subaddress

sequence, starting at any valid subaddress. A data transfer is

always terminated by a stop condition. The user can also access

any unique subaddress register on a one-by-one basis without

updating all of the registers.

Stop and start conditions can be detected at any stage during

the data transfer. If these conditions are asserted out of

sequence with normal read and write operations, they cause the

device to immediately jump to the idle condition. During a

given SCL high period, the user should only issue a start

condition, a stop condition, or a stop condition followed by a

start condition. If an invalid subaddress is issued by the user,

the ADV7324 does not issue an acknowledge and returns to the

idle condition. If the user utilizes the auto-increment method of

addressing the encoder and exceeds the highest subaddress, the

following actions are taken:

1

0

1

0

1

A1

X

ADDRESS

CONTROL

SET UP BY

ALSB PIN

READ/WRITE

CONTROL

• In read mode, the highest subaddress register contents are

output until the master device issues a no acknowledge. This

indicates the end of a read. A no acknowledge condition is

when the SDA line is not pulled low on the ninth pulse.

0

1

WRITE

READ

Figure 44. ADV7324 Slave Address = 0xD4

• In write mode, the data for the invalid byte is not loaded into

any subaddress register, a no acknowledge is issued by the

ADV7324, and the part returns to the idle condition.

To control the various devices on the bus, the following

protocol must be followed. First, the master initiates a data

transfer by establishing a start condition, defined by a high-to-

low transition on SDA while SCL remains high. This indicates

that an address/data stream will follow. All peripherals respond

to the start condition and shift the next eight bits (7-bit address

Before writing to the subcarrier frequency registers, it is required

to reset ADV7324 at least once after power-up.

The four subcarrier frequency registers must be updated,

starting with Subcarrier Frequency Register 0 and ending with

Subcarrier Frequency Register 3. The subcarrier frequency will

only update after the last subcarrier frequency register byte has

been received by the ADV7324.

+ R/ bit). The bits are transferred from MSB down to LSB.

W

The peripheral that recognizes the transmitted address

responds by pulling the data line low during the ninth clock

pulse. This is known as an acknowledge bit. All other devices

withdraw from the bus at this point and maintain an idle

condition. The idle condition is where the device monitors the

SDA and SCL lines, waiting for the start condition and the

Figure 45 illustrates an example of data transfer for a write

sequence and the start and stop conditions. Figure 46 shows bus

write and read sequences.

correct transmitted address. The R/ bit determines the

W

direction of the data.

Logic 0 on the LSB of the first byte means that the master will

write information to the peripheral. Logic 1 on the LSB of the

first byte means that the master will read information from the

peripheral.

Rev. 0 | Page 23 of 92

ADV7324

SDATA

SCLOCK

S

P

9

1–7

9

1–7

8

1–7

8

START ADRR R/W ACK SUBADDRESS ACK

DATA

ACK

STOP

Figure 45. Bus Data Transfer

WRITE

S

SLAVE ADDR A(S)

LSB = 0

SUBADDR

A(S)

DATA

A(S)

DATA

A(M)

A(S) P

SEQUENCE

LSB = 1

READ

SEQUENCE

SLAVE ADDR A(S)

S

SLAVE ADDR A(S)

DATA

A(M) P

S = START BIT

P = STOP BIT

A(S) = ACKNOWLEDGE BY SLAVE

A(M) = ACKNOWLEDGE BY MASTER

A (S) = NO-ACKNOWLEDGE BY SLAVE

A (M) = NO-ACKNOWLEDGE BY MASTER

Figure 46. Read and Write Sequences

Rev. 0 | Page 24 of 92

ADV7324

REGISTER ACCESS

The MPU can write to or read from all registers of the

REGISTER PROGRAMMING

ADV7324 except the subaddress registers, which are write only

registers. The subaddress register selected determines which

register the next read or write operation will access. All

communication with the part through the bus starts with an

access to the subaddress register. A read/write operation is then

performed from/to the target address, which increments to the

next address until a stop command is performed on the bus.

The following tables describe the functionality of each register. All

registers can be read from and written to, unless otherwise stated.

SUBADDRESS REGISTERS (SR7 TO SR0)

Each subaddress register is an 8-bit, write only register. After the

encoder’s bus is accessed and a read or write operation is selected,

the subaddress is set up. The subaddress register determines to

or from which register the operation takes place.

Table 7. Registers 0x00 to 0x01

SR7–

Reset Value

SR0

0x00

Register

Power

Mode

Bit Description

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0

1

Register Setting

Sleep mode off.

Sleep mode on.

(Shaded)

0xFC

Sleep Mode. With this

control enabled, the

current consumption is

reduced to µA level. All

DACs and the internal

PLL cct are disabled. I²C

registers can be read from

and written to in sleep

mode.

Register

PLL and Oversampling

Control. This control

allows the internal PLL cct

to be powered down and

the oversampling to be

switched off.

0

1

PLL on.

PLL off.

DAC F: Power On/Off.

0

1

DAC F off.

DAC F on.

DAC E off.

DAC E on.

DAC D off.

DAC D on.

DAC C off.

DAC C on.

DAC B off.

DAC B on.

DAC A off.

DAC A on.

Reserved.

DAC E: Power On/Off.

DAC D: Power On/Off.

DAC C: Power On/Off.

DAC B: Power On/Off.

DAC A: Power On/Off.

Reserved.

0

1

0

1

0

1

0

1

0

1

0x01

Mode

0

Select

Register

Clock Edge.

0

1

Cb clocked upon rising

edge.

Y clocked upon rising

edge.

Only for PS

interleaved

input at 27 MHz.

Reserved.

0

Clock Align.

0

1

Must be set if the phase

delay between the two

input clocks is <9.25 ns

or >27.75 ns.

Only if two

input clocks are

used.

Input Mode.

0

1

0

1

0

1

0

1

0

1

SD input only.

PS input only.

HDTV input only.

SD and PS (20-bit).

SD and PS (10-bit).

SD and HDTV

0x38

(SD oversampled).

SD and HDTV

(HDTV oversampled).

PS only (at 54 MHz).

1

0

1

Y/C/S Bus Swap.

0

1

Allows data to be

See Table 21.

applied to data ports in

various configurations

(SD feature only).

Rev. 0 | Page 25 of 92

ADV7324

Table 8. Registers 0x02 to 0x0F

SR7–

SR0

0x02

Register

Mode Register 0

Bit Description

Reserved

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

0

Bit 0

0

Register Setting

Zero must be written to

these bits.

Reset Value

0x20

Test Pattern Black Bar

0

1

Disabled.

Enabled.

0x11, Bit 2 must

also be enabled.

Manual RGB Matrix

Adjust

0

1

Disable manual RGB matrix

adjust.

Enable manual RGB matrix

adjust.

Sync on RGB¹

RGB/YPrPb Output

SD Sync

0

1

No sync.

Sync on all RGB outputs.

RGB component outputs.

YPrPb component outputs.

No sync output.

Output SD syncs on

0

1

0

1

,

S_HSYNC S_VSYNC

pins.

S_BLANK

No sync output.

Output HD, ED, syncs on

HD Sync

0

1

,

.

S_HSYNC S_VSYNC

0x03

0x04

RGB Matrix 0

RGB Matrix 1

x

LSB for GY.

LSB for RV.

0x03

0xF0

x

LSB for BU.

x

LSB for GV.

x

0

x

0

LSB for GU.

0x05

0x06

0x07

0x08

0x09

0x0A

RGB Matrix 2

RGB Matrix 3

RGB Matrix 4

RGB Matrix 5

RGB Matrix 6

DAC A, B, C

x

0

x

0

x

0

x

0

x

0

x

0

Bit 9 to Bit 2 for GY.

Bit 9 to Bit 2 for GU.

Bit 9 to Bit 2 for GV.

Bit 9 to Bit 2 for BU.

Bit 9 to Bit 2 for RV.

0%

0x4E

0x0E

0x24

0x92

0x7C

0x00

Positive Gain to DAC

Output Voltage

Output Level²

0

1

0

…

1

0

+0.018%

+0.036%

…

+7.382%

+7.5%

−7.5%

0

1

0

1

0

1

0

1

0

1

0

1

0

Negative Gain to

0

DAC Output Voltage

1

0

1

0

…

1

0

−7.382%

−7.364%

…

−0.018%

0%

1

0

1

0

1

0

1

0

1

0

1

0

1

0

0x0B

DAC D, E, F

Output Level

Positive Gain to DAC

Output Voltage

0x00

0

1

0

…

1

0

+0.018%

+0.036%

…

+7.382%

+7.5%

−7.5%

0

1

0

1

0

1

0

1

0

1

0

1

0

Negative Gain to

0

DAC Output Voltage

1

0

1

0

…

1

−7.382%

−7.364%

…

1

0

1

0

1

0

1

0

1

0

1

0

1

0

−0.018%

0x0C³

0x0D³

0x0E

0x00

0

Reserved

0x0F

¹For more detail, refer to Appendix 7.

²For more detail on the programmable output levels, refer to the Programmable DAC Gain Control section.

³The register setting value must be written after power-up/reset.

Rev. 0 | Page 26 of 92

ADV7324

Table 9. Registers 0x10 to 0x11

SR7–

Reset

Value

SR0

Register

Bit Description

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Register Setting

Note

0x10

HD Mode

Register 1

HD Output

Standard

0

EIA770.2 output

0x00

0

1

0

EIA770.1 output

Output levels for

full input range

1

Reserved

Input Sync

Format

0

1

,

HSYNC VSYNC

BLANK

EAV/SAV codes

HD/ED Input

Mode

0

SMPTE 293M, ITU-

BT. 1358

525p @

59.94 Hz

0

1

0

Async mode

BTA-1004, ITU-

BT. 1362

525p @

59.94 Hz

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

ITU-BT. 1358

625p @

50 Hz

ITU-BT. 1362

625p @

50 Hz

SMPTE 296M-1, -2

SMPTE 296M-3

SMPTE 296M-4, -5

SMPTE 296M-6

SMPTE 296M-7, -8

SMPTE 240M

720p @

60/59.94 Hz

720p @

50 Hz

720p @

30/29.97 Hz

720p @

25 Hz

720p @

24/23.98 Hz

1035i @

60/59.94 Hz

0

1

0

1

0

1

0

1

Reserved

SMPTE 274M-4, -5

1080i @

30/29.97 Hz

0

1

0

1

0

1

0

1

0

1

SMPTE 274M-6

SMPTE 274M-7, -8

SMPTE 274M-9

1080i @

25 Hz

1080p @

30/29.97 Hz

1080p @

25 Hz

SMPTE 274M-10, -11 1080p @

24/23.98 Hz

10010–11111

Reserved

0x11

HD Mode

Register 2

HD Pixel Data

Valid

0

1

Pixel data valid off

0x00

Pixel data valid on

Reserved

0

HD Test Pattern

Enable

0

1

HD test pattern off

HD test pattern on

Hatch

HD Test Pattern

Hatch/Field

0

1

Field/frame

Disabled

Enabled

HD VBI Open

0

1

HD Undershoot

Limiter

0

Disabled

Only

available in

EDTV

0

1

0

1

−11 IRE

−6 IRE

(525p/625p)

−1.5 IRE

Disabled

Enabled

HD Sharpness

Filter

0

1

Rev. 0 | Page 27 of 92

ADV7324

Table 10. Register 0x12

SR7–

Reset

Value

SR0

Register

Bit Description

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Register Setting

0 clock cycles

1 clock cycles

2 clock cycles

3 clock cycles

4 clock cycles

0 clock cycles

1 clock cycle

2 clock cycles

3 clock cycles

4 clock cycles

Disabled

0x12

HD Mode

Register 3

HD Y Delay with Respect

to Falling Edge of

0

1

0

1

0

1

0

1

0

0x00

HSYNC

HD Color Delay with

Respect to Falling Edge of

HSYNC

0

1

0

1

0

1

0

1

0

HD CGMS

0

1

Enabled

HD CGMS CRC

0

1

Disabled

Enabled

Table 11. Registers 0x13 to 0x14

SR7–

Reset

SR0

Register

Bit Description

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Register Setting

Value

0x13

HD Mode

Register 4

HD Cr/Cb Sequence

0

Cb after falling edge of

.

0x4C

HSYNC

1

Cr after falling edge of

.

HSYNC

Reserved

0

0 must be written to this bit.

8-bit input.

10-bit input.

Disabled.

HD Input Format

0

1

Sinc Filter on DAC D, E, F

0

1

Enabled.

Reserved

0

0 must be written to this bit.

Disabled.

HD Chroma SSAF

0

1

Enabled.

HD Chroma Input

HD Double Buffering

HD Timing Reset

0

1

4:4:4

4:2:2

0

1

Disabled.

Enabled.

0x14

HD Mode

Register 5

x

A low-high-low transition

resets the internal HD timing

counters.

0x00

HD Hsync Generation¹

HD Vsync Generation¹

HD Blank Polarity

0

1

Refer to the

Output Control section.

/

HSYNC VSYNC

0

1

0

1

active high.

active low.

BLANK

HD Macrovision for 525p

and 625p

0

1

Macrovision disabled.

Macrovision enabled.

Reserved

0

0 must be written to these bits.

0 = field input.

HD

/Field Input

VSYNC

0

1

1 =

input.

VSYNC

Horizontal/Vertical

Counters²

0

1

Update field/line counter.

Field/line counter free running.

¹Used in conjunction with HD SYNC in Register 0x02, Bit 7, set to 1.

²When set to 0, the horizontal/vertical counters automatically wrap around at the end of the line/field/frame of the standard selected. When set to 1, the

horizontal/vertical counters are free running and wrap around when external sync signals indicate to do so.

Rev. 0 | Page 28 of 92

ADV7324

Table 12. Register 0x15

SR7–

Reset

Value

SR0

Register

Bit Description

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Register Setting

0x15

HD Mode

Register 6

Reserved

0

0 must be written to this bit.

0x00

HD RGB Input

0

1

Disabled.

Enabled.

HD Sync on PrPb

HD Color DAC Swap

0

1

Disabled.

Enabled.

0

1

DAC E = Pb; DAC F = Pr.

DAC E = Pr; DAC F = Pb.

Gamma Curve A.

Gamma Curve B.

Disabled.

HD Gamma Curve A

HD Gamma Curve B

HD Gamma Curve Enable

0

1

0

1

Enabled.

HD Adaptive Filter Mode

HD Adaptive Filter Enable

0

1

Mode A.

Mode B.

0

1

Disabled.

Enabled.

Rev. 0 | Page 29 of 92

ADV7324

Table 13. Registers 0x16 to 0x37

SR7–

Register

Setting

Reset

Value

SR0

Register

Bit Description

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0x16

0x17

HD Y Level¹

HD Cr Level¹

HD Cb Level¹

x

Y level value

Cr level value

0xA0

0x80

0x18

x

Cb level value

0x80

0x19

0x1A

0x1B

0x1C

0x1D

0x1E

0x1F

0x20

Reserved

0x00

Reserved

HD Sharpness

Filter Gain

HD Sharpness Filter Gain Value A

0

Gain A = 0

0

1

Gain A = +1

…

0

…

1

…

1

…

1

…

Gain A = +7

1

0

Gain A = −8

…

1

…

1

…

1

…

1

…

Gain A = −1

HD Sharpness Filter Gain Value B

0

1

Gain B = 0

0

Gain B = +1

…

0

…

1

…

1

…

1

…

Gain B = +7

1

0

Gain B = −8

…

1

…

1

…

1

…

1

…

Gain B = −1

0x21

0x22

0x23

0x24

0x25

0x26

0x27

0x28

0x29

0x2A

0x2B

0x2C

0x2D

0x2E

0x2F

0x30

0x31

0x32

0x33

0x34

0x35

0x36

0x37

HD CGMS Data 0

HD CGMS Data 1

HD CGMS Data 2

HD Gamma A

HD Gamma B

HD CGMS Data Bits

0

C19

C11

C3

x

C18

C10

C2

x

C17

C9

C1

x

C16

C8

C0

x

CGMS 19 to 16

0x00

HD CGMS Data Bits

C15

C7

x

C14

C6

x

C13

C5

x

C12

C4

x

CGMS 15 to 8

HD CGMS Data Bits

CGMS 7 to 0

HD Gamma Curve A Data Points

HD Gamma Curve B Data Points

A0

A1

A2

A3

A4

A5

A6

A7

A8

A9

B0

B1

B2

B3

B4

B5

B6

B7

B8

B9

x

¹For use with internal test pattern only.

Rev. 0 | Page 30 of 92

ADV7324

Table 14. Registers 0x38 to 0x3D

SR7–

Register

Setting

Reset

Value

SR0

Register

Bit Description

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0x38

HD Adaptive Filter

Gain 1

HD Adaptive Filter

Gain 1, Value A

0

Gain A = 0

0x00

0

1

Gain A = +1

…

0

…

1

…

1

…

1

Gain A = +7

Gain A = −8

…

1

0

…

1

…

1

…

1

…

1

Gain A = −1

Gain B = 0

HD Adaptive Filter

Gain 1, Value B

0

1

Gain B = +1

…

0

…

1

…

1

…

1

Gain B = +7

Gain B = −8

…

1

0

…

1

…

1

…

1

…

1

Gain B = −1

Gain A = 0

0x39

HD Adaptive Filter

Gain 2

HD Adaptive Filter

Gain 2, Value A

0

0x00

0

1

Gain A = +1

…

0

…

1

…

1

…

1

Gain A = +7

Gain A = −8

…

1

0

…

1

…

1

…

1

…

1

Gain A = −1

Gain B = 0

HD Adaptive Filter

Gain 2, Value B

0

1

Gain B = +1

…

0

…

1

…

1

…

1

Gain B = +7

Gain B = −8

…

1

0

…

1

…

1

…

1

…

1

Gain B = −1

Gain A = 0

0x3A

HD Adaptive Filter

Gain 3

HD Adaptive Filter

Gain 3, Value A

0

0x00

0

1

Gain A = +1

…

0

…

1

…

1

…

1

Gain A = +7

Gain A = −8

…

1

0

…

1

…

1

…

1

…

1

Gain A = −1

Gain B = 0

HD Adaptive Filter

Gain 3 Value B

0

1

Gain B = +1

…

0

…

1

…

1

…

1

Gain B = +7

Gain B = −8

…

1

0

…

1

…

1

…

1

…

1

Gain B = −1

Threshold A

0x3B

0x3C

0x3D

HD Adaptive Filter

Threshold A

HD Adaptive Filter

Threshold A

x

0x00

HD Adaptive Filter

Threshold B

HD Adaptive Filter

Threshold B

x

Threshold B

Threshold C

HD Adaptive Filter

Threshold C

HD Adaptive Filter

Threshold C

Rev. 0 | Page 31 of 92

ADV7324

Table 15. Registers 0x3E to 0x43

SR7–

Reset

Value

0x00

SR0

Register

Bit Description

Reserved

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Register Setting

0x3E

0x3F

0x40

Reserved

SD Mode Register 0

SD Standard

0

1

0

1

0

1

NTSC.

PAL B, D, G, H, I.

PAL M.

PAL N.

SD Luma Filter

0

1

0

1

0

1

0

1

0

1

0

1

0

1

LPF NTSC.

LPF PAL.

Notch NTSC.

Notch PAL.

SSAF luma.

Luma CIF.

Luma QCIF.

Reserved.

1.3 MHz.

0.65 MHz.

1.0 MHz.

2.0 MHz.

SD Chroma Filter

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Reserved.

Chroma CIF.

Chroma QCIF.

3.0 MHz.

0x41

0x42

Reserved

SD PrPb SSAF

0x00

0x08

SD Mode Register 1

0

1

Disabled.

Enabled.

SD DAC Output 1

SD DAC Output 2

0

1

Refer to the Output

Configuration section.

0

1

Refer to the Output

Configuration section.

SD Pedestal

0

1

Disabled.

Enabled.

SD Square Pixel

SD VCR FF/RW Sync

SD Pixel Data Valid

0

1

Disabled.

Enabled.

Disabled.

Enabled.

Disabled.

Enabled.

0

1

0

1

SD SAV/EAV Step

Edge Control

0

1

Disabled.

Enabled.

0x43

SD Mode Register 2

SD Pedestal YPrPb

Output

SD Output Levels Y

0

1

No pedestal on YUV.

7.5 IRE pedestal on YUV.

Y = 700 mV/300 mV.

Y = 714 mV/286 mV.

700 mV p-p (PAL);

1000 mV p-p (NTSC).

700 mV p-p.

0x00

0

1

SD Output Levels PrPb

0

1

0

1

1000 mV p-p.

648 mV p-p.

SD VBI Open

0

1

Disabled.

Enabled.

SD CC Field Control

0

1

0

1

0

1

CC disabled.

CC on odd field only.

CC on even field only.

CC on both fields.

Reserved.

Reserved

0

Rev. 0 | Page 32 of 92

ADV7324

Table 16. Registers 0x44 to 0x49

SR7–

Reset

Value

0x00

SR0

Register

SD Mode

Register 3

Bit Description

SD -3H

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0

1

Register Setting

Disabled.

0x44

VSYNC

= 2.5 lines (PAL),

VSYNC

= 3 lines (NTSC).

VSYNC

SD RTC/TR/SCR

0

1

0

1

0

1

Genlock disabled.

Subcarrier Reset.

Timing Reset.

RTC enabled.

720 pixels.

710 (NTSC)/702 (PAL).

Chroma enabled.

Chroma disabled.

Enabled.

SD Active Video Length

SD Chroma

0

1

0

1

SD Burst

0

1

Disabled.

SD Color Bars

SD DAC Swap

0

1

Disabled.

Enabled.

DAC A = luma, DAC B = chroma.

DAC A = chroma, DAC B = luma.

0

1

0x45

0x46

Reserved

SD Mode

Register 4

0x00

0x01

NTSC Color Subcarrier

Adjust (Falling Edge of

HS to Start of Color

Burst)¹

0

1

0

1

0

5.17 μs.

5.31 μs (default).

5.59 μs (must be set for

Macrovision compliance).

Reserved.

Disabled.

Enabled.

1

0

1

0x47

SD Mode

Register 5

SD PrPb Scale

SD Y Scale

0x00

0

1

Disabled.

Enabled.

SD Hue Adjust

SD Brightness

SD Luma SSAF Gain

0

1

Disabled.

Enabled.

Disabled.

Enabled.

Disabled.

Enabled.

0

1

0

1

Reserved

0

0 must be written to this bit.

0

0x48

SD Mode

Register 6

Reserved

SD Double Buffering

0

0x00

0

0 must be written to this bit.

Disabled.

Enabled.

0

1

SD Input Format

0

1

0

1

0

1

8-bit input.

16-bit input.

10-bit input.

20-bit input.

Disabled.

SD Digital Noise

Reduction

0

1

Enabled.

SD Gamma Control

0

1

Disabled.

Enabled.

SD Gamma Curve

0

1

Gamma Curve A.

Gamma Curve B.

Disabled.

−11 IRE.

−6 IRE.

0x49

SD Mode

Register 7

SD Undershoot Limiter

0

1

0

1

0

1

0x00

−1.5 IRE.

Reserved

SD Black Burst Output on

DAC Luma

0

0 must be written to this bit.

Disabled.

Enabled.

0

1

SD Chroma Delay

0

1

0

1

0

1

Disabled.

4 clock cycles.

8 clock cycles.

Reserved.

Reserved

0

0 must be written to this bit.

0

¹NTSC color bar adjust should be set to 10 b for Macrovision compliance.

Rev. 0 | Page 33 of 92

ADV7324

Table 17. Registers 0x4A to 0x58

SR7–

Reset

Value

0x08

SR0

0x4A

Register

SD Timing

Register 0

Bit Description

SD Slave/Master

Mode

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0

1

Register Setting

Slave mode.

Master mode.

Mode 0.

Mode 1.

Mode 2.

SD Timing Mode

0

1

0

1

0

1

Mode 3.

SD BLANK Input

SD Luma Delay

0

1

Enabled.

Disabled.

No delay.

2 clock cycles.

4 clock cycles.

6 clock cycles.

−40 IRE.

0

1

0

1

0

1

SD Min. Luma

Value

SD Timing Reset

0

1

0

−7.5 IRE.

x

0

A low-high-low transition resets

the internal SD timing counters.

T_a= 1 clock cycle.

0x4B

SD Timing

Register 1

SD

Width

0x00

HSYNC

0

1

0

1

T_a= 4 clock cycles.

T_a= 16 clock cycles.

T_a= 128 clock cycles.

T_b= 0 clock cycle.

T_b= 4 clock cycles.

T_b= 8 clock cycles.

T_b= 18 clock cycles.

T_c= T_b.

SD

VSYNC

to

Delay

0

1

0

1

0

1

HSYNC

SD

to

HSYNC VSYNC

x

0

1

T_c= T_b+ 32 µs.

Rising Edge Delay

(Mode 1 Only)

Width

0

1

0

1

0

1

1 clock cycle.

4 clock cycles.

16 clock cycles.

128 clock cycles.

0 clock cycles.

1 clock cycle.

2 clock cycles.

3 clock cycles.

Subcarrier Frequency Bit 7 to Bit 0.

VSYNC

(Mode 2 Only)

to Pixel

Data Adjust

0

1

x

0

1

0

1

x

HSYNC

0x1E¹

0x7C

0xF0

0x21

0x00

0x4C

SD F_SCRegister 0¹

x

0x4D

0x4E

0x4F

0x50

0x51

SD F_SCRegister 1

SD F_SCRegister 2

SD F_SCRegister 3

SD F_SCPhase

SD Closed

x

Subcarrier Frequency Bit 15 to Bit 8.

Subcarrier Frequency Bit 23 to Bit 16.

Subcarrier Frequency Bit 31 to Bit 24.

Subcarrier Phase Bit 9 to Bit 2.

Extended Data Bit 7 to Bit 0.

Extended Data on

Even Fields

Captioning

0x52

0x53

0x54

0x55

SD Closed

Captioning

SD Closed

Captioning

SD Closed

Captioning

SD Pedestal

Register 0

Extended Data on

Even Fields

Data on Odd Fields

x

Extended Data Bit 15 to Bit 8.

Data Bit 7 to Bit 0.

0x00

x

Data on Odd Fields

x

Data Bit 15 to Bit 8.

Pedestal on Odd

Fields

17

16

15

14

13

12

11

10

Setting any of these bits to 1

disables pedestal on the line num-

ber indicated by the bit settings.

0x56

0x57

0x58

SD Pedestal

Register 1

SD Pedestal

Register 2

SD Pedestal

Register 3

Pedestal on Odd

Fields

Pedestal on Even

Fields

Pedestal on Even

Fields

25

17

25

24

16

24

23

15

23

22

14

22

21

13

21

20

12

20

19

11

19

18

10

18

0x00

¹For precise NTSC Fsc, this register should be programmed to 0x1F.

LINE 1

LINE 313

LINE 314

HSYNC

T

a

T

c

T

b

VSYNC

Figure 47. Timing Register 1 in PAL Mode

Rev. 0 | Page 34 of 92

ADV7324

Table 18. Registers 0x59 to 0x64

SR7–

Reset

Value

0x00

SR0

Register

Bit Description

SD CGMS Data

SD CGMS CRC

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

19

Bit 2

18

Bit 1

17

Bit 0

16

Register Setting

CGMS Data Bit C19 to Bit C16

Disabled

Enabled

0x59

SD CGMS/WSS 0

0

1

SD CGMS on Odd

Fields

0

1

Disabled

Enabled

SD CGMS on Even

Fields

0

1

Disabled

Enabled

SD WSS

0

1

Disabled

Enabled

0x5A

SD CGMS/WSS 1

SD CGMS/WSS Data

13

5

12

4

11

3

10

2

9

8

CGMS Data Bit C13 to Bit C8,

or WSS Data Bit C13 to Bit C8

CGMS Data Bit C15 to Bit C14

CGMS/WSS Data Bit C7 to

Bit C0

0x00

15

7

14

6

0x00

0x5B

0x5C

SD CGMS/WSS 2

SD LSB Register

SD CGMS/WSS Data

1

x

0

x

SD LSB for Y Scale

Value

SD Y Scale Bit 1 to Bit 0

SD LSB for Cb Scale

Value

SD LSB for Cr Scale

Value

x

SD Cb Scale Bit 1 to Bit 0

SD Cr Scale Bit 1 to Bit 0

x

SD LSB for F_SCPhase

SD Y Scale Value

x

Subcarrier Phase Bit 1 to Bit 0

SD Y Scale Bit 7 to Bit 2

0x5D

0x5E

0x5F

SD Y Scale

Register

SD Cb Scale

Register

SD Cr Scale

Register

SD Hue Register

SD Brightness/

WSS

x

0x00

SD Cb Scale Value

SD Cr Scale Value

x

SD Cb Scale Bit 7 to Bit 2

SD Cr Scale Bit 7 to Bit 2

0x60

0x61

SD Hue Adjust Value

SD Brightness Value

SD Blank WSS Data

x

SD Hue Adjust Bit 7 to Bit 0

SD Brightness Bit 6 to Bit 0

Disabled

Enabled

−4 dB

0 dB

+4 dB

No gain

+1/16 [–1/8]

+2/16 [–2/8]

+3/16 [–3/8]

+4/16 [–4/8]

+5/16 [–5/8]

+6/16 [–6/8]

+7/16 [–7/8]

+8/16 [–1]

No gain

+1/16 [–1/8]

+2/16 [–2/8]

+3/16 [–3/8]

+4/16 [–4/8]

+5/16 [–5/8]

+6/16 [–6/8]

+7/16 [–7/8]

+8/16 [–1]

0

0x00

Line 23

0

1

0

0x62

0x63

SD Luma SSAF

SD DNR 0

SD Luma SSAF

Gain/Attenuation

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

0x00

Coring Gain Border

0x00

In DNR

mode,

the

values in

brackets

apply.

Coring Gain Data

0

1

0

1

0

1

0

1

0

…

1

0

1

0

1

0

1

0

1

0

…

1

0x64

SD DNR 1

DNR Threshold

0

…

1

0

…

1

0

…

1

0

1

…

0

1

0x00

1

…

62

63

Border Area

0

1

2 pixels

4 pixels

Block Size Control

0

1

8 pixels

16 pixels

Rev. 0 | Page 35 of 92

ADV7324

Table 19. Registers 0x65 to 0x7C

SR7–

Reset

Value

SR0

Register

Bit Description

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Register Setting

0x65

SD DNR 2

DNR Input Select

0

1

0

1

0

1

0

1

0

Filter A

0x00

Filter B

Filter C

Filter D

DNR Mode

0

1

0

1

…

0

1

x

DNR mode

DNR sharpness mode

DNR Block Offset

0

…

1

x

0

…

1

x

0

…

1

x

0 pixel offset

1 pixel offset

…

14 pixel offset

15 pixel offset

0x66

0x67

0x68

0x69

0x6A

0x6B

0x6C

0x6D

0x6E

0x6F

0x70

0x71

0x72

0x73

0x74

0x75

0x76

0x77

0x78

0x79

0x7A

SD Gamma A

SD Gamma B

SD Gamma Curve A Data Points

SD Gamma Curve B Data Points

SD Brightness Value

x

A0

A1

A2

A3

A4

A5

A6

A7

A8

A9

B0

0x00

B1

B2

B3

B4

B5

B6

B7

B8

B9

SD Brightness

Detect

Read only

0x7B

Field Count

Register

Field Count

Reserved

x

Read only

Reserved

Read only

Reserved

0x8x

0

Reserved

0

Reserved

0

Revision Code

Reserved

1

0

0x7C

0x00

Rev. 0 | Page 36 of 92

ADV7324

Table 20. Registers 0x7D to 0x91

SR7-

Reset

Value

SR0

Register

Bit Description

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Register Setting

0x7D

0x7E

0x7F

0x80

0x81

0x82

0x83

0x84

0x85

0x86

0x87

0x88

0x89

0x8A

0x8B

0x8C

0x8D

0x8E

0x8F

0x90

0x91

Reserved

Macrovision

MV Control Bits

MV Control Bit

x

0

x

0

x

0

x

0

x

0

x

0

x

0

x

0x00

Bit 1 to Bit 7 must be 0.

Rev. 0 | Page 37 of 92

ADV7324

INPUT CONFIGURATION

When 10-bit input data is applied, the following bits must be set

to 1:

PS ONLY OR HDTV ONLY

Address[0x01]: Input Mode = 001 or 010, Respectively

Address 0x13, Bit 2 (HD 10-bit enable)

Address 0x48, Bit 4 (SD 10-bit enable)

YCrCb PS, HDTV, or any other HD YCrCb data can be input in

4:2:2 or 4:4:4. In 4:2:2 input format, the Y data is input on Pin Y9

to Pin Y0, and the CrCb data is input on Pin C9 to Pin C0. In

4:4:4 input mode, Y data is input on Pin Y9 to Pin Y0, Cb data is

input on Pin C9 to Pin C0, and Cr data is input on Pin S9 to

Pin S0. If the YCrCb data does not conform to SMPTE 293M

(525p), ITU-R BT.1358M (625p), SMPTE 274M (1080i),

SMPTE 296M (720p), SMPTE 240M (1035i), or BTA-T1004/1362,

the async timing mode must be used. RGB data can only be

input in 4:4:4 format in PS or HDTV input modes when HD RGB

input is enabled. G data is input on Pin Y9 to Pin Y0, R data is

input on Pin S9 to Pin S0, and B data is input on Pin C9 to Pin C0.

The clock signal must be input on Pin CLKIN_A.

Note that the ADV7324 defaults to simultaneous SD and PS

upon power-up (Address[0x01]: Input Mode = 011).

SD ONLY

Address[0x01]: Input Mode = 000

In 8-/10-bit input mode, multiplexed data is input on Pin S9 to

Pin S0 (or Pin Y9 to Pin Y0, depending on Register Address 0x01,

Bit 7), with S0 being the LSB in 10-bit input mode (see Table 21).

Input standards supported are ITU-R BT.601/656. In 16-/20-bit

input mode, the Y pixel data is input on Pin S9 to Pin S2, and

CrCb data is input on Pin Y9 to Pin Y2 (see Table 21).

MPEG2

DECODER

16-/20-Bit Mode Operation

ADV7324

27MHz

When Register 0x01, Bit 7 = 0, CrCb data is input on the Y bus,

and Y data is input on the S bus. When Register 0x01, Bit 7 = 1,

CrCb data is input on the C bus, and Y data is input on Y bus.

YCrCb

CLKIN_A

10

Cb

Cr

Y

C[9:0]

S[9:0]

Y[9:0]

INTERLACED TO

PS

The 27 MHz clock input must be input on Pin CLKIN_A. Input

sync signals are input on the

,

, and

S_VSYNC S_HSYNC

P_VSYNC,

P_HSYNC,

P_BLANK

3

pins.

S_BLANK

Figure 49. PS Input Mode

Table 21. SD 8-/10-Bit and 16-/20-Bit Configurations

Configuration

SIMULTANEOUS SD/PS OR SD/HDTV

Parameter

8-/10-Bit Mode 16-/20-Bit Mode

Register 0x01, Bit 7 = 0

Y Bus

S Bus

C Bus

Address[0x01]: Input Mode 011 (SD 10-Bit, PS 20-Bit), Input

Mode 101 (SD and HD, SD Oversampled), or Input Mode

110 (SD and HD, HD Oversampled)

CrCb

Y

656/601, YCrCb

YCrCb PS and HD data must be input in 4:2:2 format. In 4:2:2

input format, the HD Y data is input on Pin Y9 to Pin Y0, and

the HD CrCb data is input on Pin C9 to Pin C0. If PS 4:2:2 data is

inter-leaved onto a single 10-bit bus, Pin Y9 to Pin Y0 are used

for the input port. The input data is input at 27 MHz, with the

data being clocked upon the rising and falling edges of the input

clock. The input mode register at Address 0x01 is set accordingly.

If the YCrCb data does not conform to SMPTE 293M (525p),

ITU-R BT.1358M (625p), SMPTE 274M (1080i), SMPTE 296M

(720p), SMPTE 240M (1035i), or BTA-T1004, the async timing

mode must be used.

Register 0x01, Bit 7 = 1

Y Bus

S Bus

C Bus

Y

CrCb

ADV7324

S_VSYNC,

S_HSYNC,

S_BLANK

3

MPEG2

DECODER

27MHz

10

CLKIN_A

The 8- or 10-bit SD data must be compliant with ITU-R

BT.601/656 in 4:2:2 format. SD data is input on Pin S9 to Pin S0,

with S0 being the LSB. Using 8-bit input format, the data is

input on Pin S9 to Pin S2. The clock input for SD must be input

on CLKIN_A, and the clock input for HD must be input on

CLKIN_B. Synchronization signals are optional. SD syncs are

YCrCb

S[9:0] OR Y[9:0]*

*SELECTED BY ADDRESS 0x01, BIT 7

Figure 48. SD Only Input Mode

Rev. 0 | Page 38 of 92

ADV7324

S_BLANK

.

, and

P_HSYNC

input on Pin

HD syncs are input on Pin

, Pin

, and Pin

, Pin

S_VSYNC

S_HSYNC

PS AT 27 MHZ (DUAL EDGE)

OR 54 MHZ

P_VSYNC

.

P_BLANK

Address[0x01]: Input Mode 100 or 111, Respectively

ADV7324

YCrCb PS data can be input at 27 MHz or 54 MHz. The input

data is interleaved onto a single 8-/10-bit bus and is input on

Pin Y9 to Pin Y0. When a 27 MHz clock is supplied, the data is

clocked upon the rising and falling edges of the input clock, and

the clock edge bit [Address 0x01, Bit 1] must be set accordingly.

S_VSYNC,

S_HSYNC,

S_BLANK

3

MPEG2

DECODER

27MHz

10

CLKIN_A

S[9:0]

YCrCb

Table 22 provides an overview of all possible input configurations.

Figure 53, Figure 54, and Figure 55 show the possible conditions:

Cb data on the rising edge, and Y data on the rising edge.

CrCb

Y

10

C[9:0]

Y[9:0]

INTERLACED TO

PS

P_VSYNC,

P_HSYNC,

P_BLANK

3

CLKIN_B

27MHz

CLKIN_B

Y9–Y0

3FF

00

XY

Cb0

Y0

Cr0

Y1

Figure 50. Simultaneous SD and PS Input

CLOCK EDGE ADDRESS 0x00, BIT 1, SHOULD BE SET TO 0 IN THIS CASE.

ADV7324

Figure 53. Input Sequence in PS Bit Interleaved Mode (EAV/SAV)

S_VSYNC,

S_HSYNC,

3

S_BLANK

SDTV

DECODER

27MHz

CLKIN_B

CLKIN_A

YCrCb 10

S[9:0]

Y9–Y0

3FF

00

XY

Y0

Cb0

Y1

Cr0

HDTV

DECODER

CrCb 10

C[9:0]

Y[9:0]

1080i

OR

Y

10

3

CLOCK EDGE ADDRESS 0x00, BIT 1, SHOULD BE SET TO 1 IN THIS CASE.

720p

OR

P_VSYNC,

P_HSYNC,

P_BLANK

1035i

Figure 54. Input Sequence in PS Bit Interleaved Mode (EAV/SAV)

74.25MHz

CLKIN_B

Figure 51. Simultaneous SD and HD Input

PIXEL INPUT

3FF

00

XY

Cb0

Y0

Cr0

Y1

DATA

In simultaneous SD/HD input mode, if the two clock phases

differ by less than 9.25 ns or by more than 27.75 ns, the clock

align bit [Address 0x01, Bit 3] must be set accordingly. If the

application uses the same clock source for both SD and PS, the

clock align bit must be set because the phase difference between

both inputs is less than 9.25 ns.

WITH A 54MHz CLOCK, THE DATA IS LATCHED ON EVERY RISING EDGE.

Figure 55. Input Sequence in PS Bit Interleaved Mode (EAV/SAV)

MPEG2

DECODER

CLKIN_A

CLKIN_B

ADV7324

27MHz OR 54MHz

YCrCb

CLKIN_A

t

< 9.25ns OR

> 27.75ns

DELAY

INTERLACED

TO PS

YCrCb

10

Y[9:0]

Figure 52. Clock Phase with Two Input Clocks

P_VSYNC,

P_HSYNC,

P_BLANK

3

Figure 56. 10-Bit PS at 27 MHz or 54 MHz

Rev. 0 | Page 39 of 92

ADV7324

Table 22. Input Configurations

Input Format

Total Bits

Input Video Input Pins

Subaddress Register Setting

ITU-R BT.656 (See Table 21)

8

4:2:2

4:4:4

YCrCb

S9 to S2 (MSB = S9) 0x01

0x00

0x48

S9 to S0 (MSB = S9) 0x01

0x48

S9 to S2 (MSB = S9) 0x01

Y9 to Y2 (MSB = Y9) 0x48

S9 to S0 (MSB = S9) 0x01

Y9 to Y0 (MSB = Y9) 0x48

Y9 to Y2 (MSB = Y9) 0x01

0x48

Y9 to Y0 (MSB = Y9) 0x01

0x48

Y9 to Y2 (MSB = Y9) 0x01

0x13

Y9 to Y0 (MSB = Y9) 0x01

0x13

Y9 to Y2 (MSB = Y9) 0x01

0x13

Y9 to Y0 (MSB = Y9) 0x01

0x13

0x00

0x10

0x00

0x08

0x00

0x18

0x80

0x00

0x80

0x10

0x40

0x10

0x44

0x70

0x40

0x70

0x44

0x10

0x40

0x10

0x44

0x10

0x00

10

YCrCb

16

Y

CrCb

Y

CrCb

YCrCb

20

8

10

YCrCb

PS Only

8 (27 MHz clock)

10 (27 MHz clock)

8 (54 MHz clock)

10 (54 MHz clock)

16

20

24

Y

CrCb

Y

CrCb

Y

Cb

Cr

Y9 to Y2 (MSB = Y9) 0x01

C9 to C2 (MSB = C9) 0x13

Y9 to Y0 (MSB = Y9) 0x01

C9 to C0 (MSB = C9) 0x13

Y9 to Y2 (MSB = Y9) 0x01

C9 to C2 (MSB = C9) 0x13

S9 to S2 (MSB = S9)

30

4:4:4

Y

Cb

Cr

Y9 to Y0 (MSB = Y9) 0x01

C9 to C0 (MSB = C9) 0x13

S9 to S0 (MSB = S9)

0x10

0x04

HDTV Only

16

20

24

4:2:2

4:4:4

Y

CrCb

Y

CrCb

Y

Cb

Cr

Y9 to Y2 (MSB = Y9) 0x01

C9 to C2 (MSB = C9) 0x13

Y9 to Y0 (MSB = Y9) 0x01

C9 to C0 (MSB = C9) 0x13

Y9 to Y2 (MSB = Y9) 0x01

C9 to C2 (MSB = C9) 0x13

S9 to S2 (MSB = S9)

0x20

0x40

0x20

0x44

0x20

0x00

30

24

30

4:4:4

Y

Cb

Cr

G

B

R

G

B

R

Y9 to Y0 (MSB = Y9) 0x01

C9 to C0 (MSB = C9) 0x13

S9 to S0 (MSB = S9)

0x20

0x04

HD RGB

Y9 to Y2 (MSB = Y9) 0x01

C9 to C2 (MSB = C9) 0x13

S9 to S2 (MSB = S9) 0x15

Y9 to Y0 (MSB = Y9) 0x01

C9 to C0 (MSB = C9) 0x13

S9 to S0 (MSB = S9) 0x15

S9 to S2 (MSB = S9) 0x01

Y9 to Y2 (MSB = Y9) 0x13

0x48

0x10 or 0x20

0x00

0x02

0x10 or 0x20

0x04

0x02

0x40

ITU-R BT.656 and PS

8 (SD)

8 (PS)

4:2:2

YCrCb

0x00

ITU-R BT.656 and PS

10 (SD)

10 (PS)

4:2:2

YCrCb

S9 to S0 (MSB = S9) 0x01

Y9 to Y0 (MSB = Y9) 0x13

0x48

0x40

0x44

0x10

ITU-R BT.656 and PS or HDTV

8

16

4:2:2

YCrCb

Y

CrCb

YCrCb

Y

S9 to S2 (MSB = S9) 0x01

Y9 to Y2 (MSB = Y9) 0x13

C9 to C2 (MSB = C9) 0x48

S9 to S0 (MSB = S9) 0x01

Y9 to Y0 (MSB = Y9) 0x13

C9 to C0 (MSB = C9) 0x48

0x30, 0x50, or 0x60

0x40

0x00

0x30, 0x50, or 0x60

0x44

0x10

10

20

4:2:2

CrCb

Rev. 0 | Page 40 of 92

ADV7324

FEATURES

OUTPUT CONFIGURATION

Table 23, Table 24, and Table 25 demonstrate what output signals are assigned to the DACs when the control bits are set accordingly.

Table 23. Output Configuration in SD Only Mode

RGB/YUV Output

0x02, Bit 5

SD DAC Output 1

0x42, Bit 2

SD DAC Output 2

0x42, Bit 1

DAC A

CVBS

G

DAC B

Luma

B

Luma

B

Luma

U

Luma

U

DAC C

DAC D

G

CVBS

G

DAC E

B

Luma

B

Luma

U

Luma

U

DAC F

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Chroma

R

Chroma

R

Chroma

V

Chroma

V

R

Chroma

R

Chroma

V

Chroma

V

Chroma

G

CVBS

Y

CVBS

Y

CVBS

Luma

Luma/Chroma Swap 0x44, Bit 7

0

1

Table as above

Table as above, but with all luma/chroma instances swapped

Table 24. Output Configuration in HD Only or PS Only Mode

Input

Format

RGB Input 0x15,

Bit 1

RGB/YPrPb Output

0x02, Bit 5

Color Swap 0x15,

Bit 3

DAC A DAC B DAC C DAC D DAC E

DAC F

YCrCb 4:2:2

YCrCb 4:4:4

RGB 4:4:4

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

N/A

G

Y

B

R

Pb

Pr

B

R

B

Pr

Pb

R

Y

G

Y

R

B

Pb

Pr

B

R

B

Pr

Pb

R

B

R

Y

G

RGB 4:4:4

R

B

Table 25. Output Configuration in Simultaneous SD/PS or SD/HD Mode

RGB/YPrPb Output

0x02, Bit 5

HD/PS Color Swap

0x15, Bit 3

Input Formats

DAC A

DAC B

DAC C

DAC D

DAC E

DAC F

ITU-R.BT656 and HD/PS

YCrCb in 4:2:2

ITU-R.BT656 and HD/PS

YCrCb in 4:2:2

ITU-R.BT656 and HD/PS

YCrCb in 4:2:2

ITU-R.BT656 and HD/PS

YCrCb in 4:2:2

0

1

0

1

0

1

CVBS

Luma

Chroma

G

B

R

CVBS

G

Y

R

B

Pb

Pr

Pb

Rev. 0 | Page 41 of 92

ADV7324

In async mode, the PLL must be turned off [Subaddress 0x00,

Bit 1 = 1]. Register 0x10 should be programmed to 0x01.

HD ASYNC TIMING MODE

[Subaddress 0x10, Bits 3 and 2]

Figure 57 and Figure 58 show examples of how to program the

ADV7324 to accept an HD standard other than SMPTE 293M,

SMPTE 274M, SMPTE 296M, or ITU-R BT.1358.

For any input data that does not conform to the standards

selectable in input mode (Subaddress 0x10), asynchronous

timing mode can be used to interface to the ADV7324. Timing

control signals for

programmed by the user. Macrovision and programmable

oversampling rates are not available in async timing mode.

,

, and

must be

HSYNC VSYNC

BLANK

Follow the specifications in Table 26 when programming the

control signals in async timing mode. For standards that do not

require a trisync level,

must be tied low at all times.

P_BLANK

Table 26. Async Timing Mode Truth Table

P_HSYNC P_VSYNC P_BLANK¹

Reference

Reference in Figure 57 and Figure 58

0

0 or 1

0

50% point of falling edge of trilevel horizontal sync signal

25% point of rising edge of trilevel horizontal sync signal

50% point of falling edge of trilevel horizontal sync signal

50% start of active video

a

b

c

1 → 0

0

0 → 1

0 or 1

0 → 1

1

d

e

0 → 1

1 → 0

50% end of active video

¹When async timing mode is enabled,

, Pin 25, becomes an active high input.

is set to active low using Address 0x10, Bit 6.

P_BLANK

CLK

P_HSYNC

PROGRAMMABLE

INPUT TIMING

P_VSYNC

P_BLANK

SET ADDRESS 0x14,

BIT 3 = 1

HORIZONTAL SYNC

ACTIVE VIDEO

ANALOG

OUTPUT

81

66

243

1920

a

b

c

d

e

Figure 57. Async Timing Mode—Programming Input Control Signals for SMPTE 295M Compatibility

CLK

P_HSYNC

0

P_VSYNC

1

P_BLANK

SET ADDRESS 0x14

BIT 3 = 1

HORIZONTAL SYNC

ACTIVE VIDEO

ANALOG OUTPUT

a

b

c

d

e

Figure 58. Async Timing Mode—Programming Input Control Signals for Bilevel Sync Signal

Rev. 0 | Page 42 of 92

ADV7324

b. In subcarrier phase reset, a low-to-high transition on

the RTC_SCR_TR pin (Pin 31) resets the subcarrier

phase to 0 on the field following the subcarrier phase

reset when the SD RTC/TR/SCR control bits at

Address 0x44 are set to 01.

HD TIMING RESET

A timing reset is achieved by toggling the HD timing reset control

bit [Subaddress 0x14, Bit 0] from 0 to 1. In this state, the horizontal

and vertical counters remain reset. When this bit is set back to 0,

the internal counters resume counting.

This reset signal must be held high for a minimum of

one clock cycle.

The minimum time the pin must be held high is one clock

cycle; otherwise, this reset signal might not be recognized. This

timing reset applies to the HD timing counters only.

Because the field counter is not reset, it is

recommended that the reset signal is applied in Field 7

(PAL) or Field 3 (NTSC). The reset of the phase will

then occur on the next field, i.e., Field 1, lined up

correctly with the internal counters. The field count

register at Address 0x7B can be used to identify the

number of active fields.

SD REAL-TIME CONTROL, SUBCARRIER RESET,

AND TIMING RESET

[Subaddress 0x44, Bit 2 and Bit 1]

Together with the RTC_SCR_TR pin and SD Mode Register 3

[Address 0x44, Bit 1 and Bit 2], the ADV7324 can be used in

(a) timing reset mode, (b) subcarrier phase reset mode, or

(c) RTC mode.

c. In RTC mode, the ADV7324 can be used to lock to an

external video source. The real-time control mode

allows the ADV7324 to automatically alter the

subcarrier frequency to compensate for line length

variations. When the part is connected to a device,

such as an ADV7402A video decoder (see Figure 61),

that outputs a digital data stream in RTC format, it

automatically changes to the compensated subcarrier

frequency on a line-by-line basis. This digital data

stream is 67 bits wide, and the subcarrier is contained

in Bit 0 to Bit 21. Each bit is two clock cycles long.

Write 0x00 into all four subcarrier frequency registers

when this mode is used.

a. A timing reset is achieved after a low-to-high

transition on the RTC_SCR_TR pin (Pin 31). In this

state, the horizontal and vertical counters remain

reset. Upon releasing this pin (set to low), the internal

counters resume counting, starting with Field 1, and

the subcarrier phase is reset.

The minimum time the pin must be held high is one

clock cycle; otherwise, this reset signal might not be

recognized. This timing reset applies to the SD timing

counters only.

DISPLAY

START OF FIELD 4 OR 8

F

PHASE = FIELD 4 OR 8

SC

307

310

313

320

NO TIMING RESET APPLIED

DISPLAY

START OF FIELD 1

F

PHASE = FIELD 1

SC

307

1

2

3

4

5

6

7

21

TIMING RESET PULSE

TIMING RESET APPLIED

Figure 59. Timing Reset Timing Diagram

Rev. 0 | Page 43 of 92

ADV7324

DISPLAY

310

START OF FIELD 4 OR 8

F

PHASE = FIELD 4 OR 8

SC

307

313

320

NO F RESET APPLIED

SC

DISPLAY

START OF FIELD 4 OR 8

F

PHASE = FIELD 1

SC

307

310

313

320

F

RESET PULSE

SC

F

RESET APPLIED

SC

Figure 60. Subcarrier Reset Timing Diagram

ADV7324

CLKIN_A

DAC A

DAC B

DAC C

DAC D

DAC E

DAC F

LCC1

RTC_SCR_TR

GLL

COMPOSITE

ADV7402A

VIDEO

1

VIDEO

P19–P10

5

Y9–Y0/S9–S0

DECODER

4 BITS

RESERVED

14 BITS

H/L TRANSITION

COUNT START

LOW

SEQUENCE RESET

SUBCARRIER

PHASE

3

4

BIT

RESERVED

2

PLL INCREMENT

128

F

SC

13

0

21

19

0

RTC

6768

TIME SLOT 01

14

VALID INVALID

SAMPLE SAMPLE

8/LINE

LOCKED

CLOCK

5 BITS

RESERVED

NOTES

1

FOR EXAMPLE, VCR OR CABLE.

2

F

PLL INCREMENT IS 22 BITS LONG. VALUE LOADED INTO ADV7324 F DDS REGISTER IS F PLL INCREMENTS BITS 21:0 PLUS BITS 0:9

SC

SC SC

OF SUBCARRIER FREQUENCY REGISTERS. ALL ZEROS SHOULD BE WRITTEN TO THE SUBCARRIER FREQUENCY REGISTERS

OF THE ADV7324.

3

4

5

SEQUENCE BIT PAL: 0 = LINE NORMAL, 1 = LINE INVERTED; NTSC: 0 = NO CHANGE.

RESET ADV7324 DDS.

SELECTED BY REGISTER ADDRESS 0x01, BIT 7.

Figure 61. RTC Timing and Connections

Rev. 0 | Page 44 of 92

ADV7324

In fast forward mode, the sync information at the start of a new

field in the incoming video usually occurs before the correct

number of lines/fields are reached; in rewind mode, this sync

signal usually occurs after the total number of lines/fields are

reached. Conventionally, this means that the output video will

have corrupted field signals, because one signal is generated by

the incoming video and another is generated when the internal

lines/field counters reach the end of a field.

RESET SEQUENCE

A reset is activated with a high-to-low transition on the

pin (Pin 33) according to the timing specifications, and the

ADV7324 reverts to the default output configuration. Figure 62

RESET

illustrates the

timing sequence.

RESET

SD VCR FF/RW SYNC

[Subaddress 0x42, Bit 5]

When the VCR FF/RW sync control is enabled, the line/field

In DVD record applications where the encoder is used with a

decoder, the VCR FF/RW sync control bit [Subaddress 0x42,

Bit 5] can be used for nonstandard input video, i.e., in fast

forward or rewind modes.

counters are updated according to the incoming

signal,

VSYNC

and the analog output matches the incoming

signal.

VSYNC

This control is available in all slave timing modes except Slave

Mode 0.

RESET

DACs

XXXXXX

A, B, C

OFF

VALID VIDEO

DIGITAL TIMING SIGNALS SUPPRESSED

TIMING ACTIVE

DIGITAL TIMING

XXXXXX

PIXEL DATA

VALID

RESET

Figure 62.

Timing Sequence

Rev. 0 | Page 45 of 92

ADV7324

VERTICAL BLANKING INTERVAL

SUBCARRIER FREQUENCY REGISTERS

The ADV7324 accepts input data that contains VBI data (such

as CGMS, WSS, VITS) in SD and HD modes.

[Subaddresses 0x4C to 0x4F]

Four 8-bit registers are used to set up the subcarrier frequency.

The value of these registers is calculated using the equation

For the SMPTE 293M (525p) standard, VBI data can be

inserted on Line 13 to Line 42 of each frame, or on Line 6 to

Line 43 for the ITU-R BT.1358 (625p) standard.

Subcarrier Frequency Register =

Number of subcarrier periods in one video line

× 2³²

This data can be present on Line 10 to Line 20 for SD NTSC

and on Line 7 to Line 22 for PAL.

Number of 27 MHz clock cycles in one video line

where the sum is rounded to the nearest integer.

For example, in NTSC mode

If VBI is disabled [Address 0x11, Bit 4 for HD; Address 0x43,

Bit 4 for SD], VBI data is not present at the output, and the

entire VBI is blanked. These control bits are valid in all master

and slave modes.

227.5

1716

⎛

⎜

⎝

⎞

⎠

Subcarrier Register Value =

×

³²= 569408543

⎟ 2

In Slave Mode 0, if VBI is enabled, the blanking bit in the

EAV/SAV code is overwritten. It is possible to use VBI in this

timing mode as well.

where:

Subcarrier Register Value = 0x21F07C1F

SD F_SCRegister 0: 0x1F

SD F_SCRegister 1: 0x7C

SD F_SCRegister 2: 0xF0

SD F_SCRegister 3: 0x21

In Slave Mode 1 or 2, the

control bit [Address 0x4A,

BLANK

Bit 3] must be enabled to allow VBI data to pass through the

ADV7324. Otherwise, the ADV7324 automatically blanks the

VBI to standard.

See the MPU Port Description section for more details on

accessing the subcarrier frequency registers.

If CGMS is enabled and VBI is disabled, the CGMS data will

nevertheless be available at the output.

Programming the F_SC

See Appendix 1—Copy Generation Management System.

The subcarrier register value is divided into four F_SCregisters, as

shown above. To load the value into the encoder, users must

write to the F_SCregisters in sequence, starting with F_SC0. The

value is not loaded until the F_SC4 write is complete.

Note that the ADV7324 power-up value for F_SC0 is 0x1E. For

precise NTSC F_SC, write 0x1F to this register.

Rev. 0 | Page 46 of 92

ADV7324

SQUARE PIXEL TIMING MODE

[Address 0x42, Bit 4]

In square pixel mode, the following timing diagrams apply.

ANALOG

VIDEO

EAV CODE

SAV CODE

C

r

C

b

8

0

F

A

B

A

B

A

B

8

0

C

b

C

r

F

0

X

Y

1

0

8

0

1

0

8

0

1

0

1

0

F

0

X

Y

C

b

C

r

Y

INPUT PIXELS

ANCILLARY DATA

(HANC)

4 CLOCK

NTSC/PAL M SYSTEM

(525 LINES/60Hz)

272 CLOCK

1280 CLOCK

1536 CLOCK

PAL SYSTEM

(625 LINES/50Hz)

344 CLOCK

START OF ACTIVE

VIDEO LINE

END OF ACTIVE

VIDEO LINE

Figure 63. EAV/SAV Embedded Timing

HSYNC

FIELD

PAL = 44 CLOCK CYCLES

NTSC = 44 CLOCK CYCLES

BLANK

PIXEL

DATA

Cr

Y

Cb

Y

PAL = 308 CLOCK CYCLES

NTSC = 236 CLOCK CYCLES

Figure 64. Active Pixel Timing

Rev. 0 | Page 47 of 92

ADV7324

EXTENDED UV FILTER MODE

FILTERS

0

–10

–20

–30

–40

–50

–60

Table 27 shows an overview of the programmable filters

available on the ADV7324.

Table 27. Selectable Filters

Filter

Subaddress

0x40

0x42

0x13

SD Luma LPF NTSC

SD Luma LPF PAL

SD Luma Notch NTSC

SD Luma Notch PAL

SD Luma SSAF

SD Luma CIF

SD Luma QCIF

0

1

2

3

4

5

6

FREQUENCY (MHz)

SD Chroma 0.65 MHz

SD Chroma 1.0 MHz

SD Chroma 1.3 MHz

SD Chroma 2.0 MHz

SD Chroma 3.0 MHz

SD Chroma CIF

SD Chroma QCIF

SD UV SSAF

HD Chroma Input

HD Sinc Filter

Figure 65. UV SSAF Filter

If this filter is disabled, one of the chroma filters shown in

Table 28 can be selected and used for the CVBS or luma/

chroma signal.

Table 28. Internal Filter Specifications

Pass-Band

3 dB Bandwidth²

(MHz)

Filter

Ripple¹(dB)

Luma LPF NTSC

Luma LPF PAL

Luma Notch NTSC

Luma Notch PAL

Luma SSAF

0.16

0.1

0.09

0.1

0.04

0.127

4.24

4.81

2.3/4.9/6.6

3.1/5.6/6.4

6.45

HD Chroma SSAF

SD Internal Filter Response

[Subaddress 0x40 [7:2]; Subaddress 0x42, Bit 0]

Luma CIF

3.02

The Y filter supports several frequency responses, including two

low-pass responses, two notch responses, an extended SSAF

response with or without gain boost attenuation, a CIF

response, and a QCIF response. The UV filter supports several

different frequency responses, including six low-pass responses,

a CIF response, and a QCIF response, as shown in Figure 35

and Figure 36.

Luma QCIF

Monotonic

0.09

1.5

0.65

1

1.395

2.2

3.2

0.65

0.5

Chroma 0.65 MHz

Chroma 1.0 MHz

Chroma 1.3 MHz

Chroma 2.0 MHz

Chroma 3.0 MHz

Chroma CIF

0.048

Monotonic

Chroma QCIF

If SD SSAF gain is enabled, there are 12 response options in the

range −4 dB to +4 dB [Subaddress 0x47, Bit 4]. Choose the

desired response by programming the correct value via the I²C

[Subaddress 0x62]. The variation of frequency responses are

shown in Figure 32 and Figure 33.

¹Pass-band ripple is the maximum fluctuation from the 0 dB response in the

pass band. The pass band is defined to have 0 Hz to fc (Hz) frequency limits

for a low-pass filter, and 0 Hz to f1 (Hz) and f2 (Hz) to infinity for a notch filter,

where fc, f1, and f2 are the −3 dB points.

²3 dB bandwidth refers to the −3 dB cutoff frequency.

In addition to the chroma filters listed in Table 27, the

ADV7324 contains an SSAF filter specifically designed for the

color difference component outputs, U and V. This filter has a

cutoff frequency of about 2.7 MHz and a gain of –40 dB at

3.8 MHz, as shown in Figure 65. This filter can be controlled

with Address 0x42, Bit 0.

Rev. 0 | Page 48 of 92

ADV7324

Table 29 shows sample color values that can be programmed

into the color registers when the output standard selection is

set to EIA 770.2.

PS/HD Sinc Filter

[Subaddress 0x13, Bit 3]

0.5

Table 29. Sample Color Values for EIA 770.2

Output Standard Selection

0.4

0.3

Sample Color

Y Value

235 (EB)

16 (10)

81 (51)

145 (91)

41 (29)

210 (D2)

170 (AA)

106 (6A)

Cr Value

128 (80)

240 (F0)

34 (22)

110 (6E)

146 (92)

16 (10)

Cb Value

128 (80)

90 (5A)

54 (36)

240 (F0)

16 (10)

0.2

White

Black

Red

Green

Blue

Yellow

Cyan

0.1

0

–0.1

–0.2

–0.3

–0.4

–0.5

166 (A6)

202 (CA)

Magenta

222 (DE)

0

5

10

15

20

25

30

RGB Matrix

FREQUENCY (MHz)

[Subaddresses 0x03 to 0x09]

Figure 66. HD Sinc Filter Enabled

The internal RGB matrix automatically performs all YCrCb to

RGB scaling according to the input standard programmed in

the device, as selected by input mode Register 0x01 [6:4]. Table 30

shows the options available in this matrix.

0.5

0.4

0.3

Note that it is not possible to do a color space conversion from

RGB-in to YPrPb-out. Also, it is not possible to input SD RGB.

0.2

0.1

Table 30. Matrix Conversion Options

0

HDTV/SD/PS

–0.1

–0.2

–0.3

–0.4

–0.5

Reg. 0x15, Bit 1

(RGB IN/YCrCb IN,

PS/HD Only)

Reg. 0x02,Bit 5

Input Output (YUV/RGB OUT)

YCrCb YPrPb

YCrCb RGB

1

0

1

0

5

10

15

20

25

30

RGB

FREQUENCY (MHz)

Figure 67. HD Sinc Filter Disabled

Manual RGB Matrix Adjust Feature

COLOR CONTROLS AND RGB MATRIX

Normally, there is no need to enable this feature in Register 0x02,

Bit 3, because the RGB matrix automatically performs color

space conversion depending on the input mode chosen (SD/PS,

HD) and the polarity of RGB/YPrPb output in Register 0x02,

Bit 5 (see Table 30). For this reason, the manual RGB matrix

adjust feature is disabled by default. However, For HDTV

YCrCb-to-RGB conversion, the RGB matrix must be enabled to

invoke the correct coefficients for this color space. The

coefficients do not need to be adjusted.

HD Y Level, HD Cr Level, HD Cb Level

[Subaddresses 0x16 to 0x18]

Three 8-bit registers at Address 0x16, Address 0x17, and

Address 0x18 are used to program the output color of the

internal HD test pattern generator, be it the lines of the cross

hatch pattern or the uniform field test pattern. They are not

functional as color controls for external pixel data input. For

this purpose, the RGB matrix is used.

The manual RGB matrix adjust feature provides custom

coefficient manipulation and is used in PS and HD modes only.

The values for Y and the color difference signals used to obtain

white, black, and saturated primary and complementary colors

conform to the ITU-R BT.601-4 standard.

Rev. 0 | Page 49 of 92

ADV7324

When the manual RGB matrix adjust feature is enabled, the

default values in Registers 0x05 to 0x09 are correct for HDTV

color space only. The color components are converted

according to the 1080i and 720p standards (SMPTE 274M,

SMPTE 296M):

If RGB output is selected, the RGB matrix scaler uses the

following equations:

G = GY × Y + GU × Pb + GV × Pr

B = GY × Y + BU × Pb

R = Y + 1.575Pr

R = GY × Y + RV × Pr

G = Y − 0.468Pr − 0.187Pb

B = Y + 1.855Pb

If YPrPb output is selected, the following equations are used:

Y = GY × Y

U = BU × Pb

V = RV × Pr

This is reflected in the preprogrammed values GY = 0x13B,

GU = 0x3B, GV = 0x93, BU = 0x248, and RV = 0x1F0.

If the RGB matrix is enabled and another input standard (such

as SD or PS) is used, the scale values for GY, GU, GV, BU, and

RV must be adjusted according to this input standard color

space. The user should consider that the color component

conversion might use different scale values. For example,

SMPTE 293M uses the following equations for conversion:

Upon power-up, the RGB matrix is programmed with the

default values listed in Table 31.

Table 31. RGB Matrix Default Values

Address

Default

0x03

0xF0

0x4E

0x0E

0x24

0x92

0x7C

0x03

0x04

0x05

0x06

0x07

0x08

0x09

R = Y + 1.402Pr

G = Y – 0.714Pr – 0.344Pb

B = Y + 1.773Pb

The manual RGB matrix adjust feature can be used to control

the HD output levels in cases where the video output does not

conform to the standard due to altering the DAC output stages

such as termination resistors. The programmable RGB matrix is

used for external HD/PS data and is not functional when internal

test patterns are enabled. To adjust Registers 0x05 to 0x09, the

manual RGB matrix adjust must be enabled [Register 0x02,

Bit 3 = 1].

When the manual RGB matrix adjust feature is not enabled, the

ADV7324 automatically scales YCrCb inputs to all standards

supported by this part, as selected by the input mode,

Register 0x01 [6:4].

SD Luma and Color Control

[Subaddresses 0x5C, 0x5D, 0x5E, 0x5F]

Programming the RGB Matrix

SD Y Scale, SD Cr Scale, and SD Cb Scale are three 10-bit-wide

control registers that scale the Y, Cb, and Cr output levels.

If custom manipulation of coefficients is required, enable the

RGB matrix in Address 0x02, Bit 3, set the output to RGB

[Address 0x02, Bit 5], and disable sync on PrPb (default)

[Address 0x15, Bit 2]. Enabling sync on RGB is optional

[Address 0x02, Bit 4].

Each of these registers represents the value required to scale the

Cb or Cr level from 0.0 to 2.0 and the Y level from 0.0 to 1.5 of

its initial level. The value of these 10 bits is calculated using the

following equation:

GY at Address 0x03 and Address 0x05 controls the green signal

output levels. BU at Address 0x04 and Address 0x08 controls

the blue signal output levels, and RV at Address 0x04 and

Address 0x09 controls the red signal output levels. To control

YPrPb output levels, enable the YUV output [Address 0x02, Bit 5].

In this case, GY [Address 0x05; Address 0x03, Bit 0 and Bit 1] is

used for the Y output, RV [Address 0x09; Address 0x04, Bit 0

and Bit 1] is used for the Pr output, and BU [Address 0x08;

Address 0x04, Bit 2 and Bit 3] is used for the Pb output.

Y, Cr, or Cb Scalar Value = Scale Factor × 512

For example,

Scale Factor = 1.18

Y, Cb, or Cr Scale Value = 1.18 × 512 = 665.6

Y, Cb, or Cr Scale Value = 665 (rounded to the nearest

integer)

Y, Cb, or Cr Scale Value = 1010 0110 01b

Rev. 0 | Page 50 of 92

ADV7324

Address 0x5C, SD LSB Register = 0x15

Address 0x5D, SD Y Scale Register = 0xA6

Address 0x5E, SD Cb Scale Register = 0xA6

Address 0x5F, SD Cr Scale Register = 0xA6

SD Brightness Control

[Subaddress 0x61]

The brightness is controlled by adding a programmable setup

level onto the scaled Y data. This brightness level may be added

onto the scaled Y data. For NTSC with pedestal, the setup can

vary from 0 IRE to 22.5 IRE. For NTSC without pedestal and

for PAL, the setup can vary from −7.5 IRE to +15 IRE.

Note that this feature affects all interlaced output signals, i.e.,

CVBS, Y-C, YPrPb, and RGB.

SD Hue Adjust Value

[Subaddress 0x60]

The brightness control register is an 8-bit register. Seven bits of

this 8-bit register are used to control the brightness level, which

can be a positive or negative value.

The hue adjust value is used to adjust the hue on the composite

and chroma outputs.

For example,

These eight bits represent the value required to vary the hue of

the video data, i.e., the variance in phase of the subcarrier

during active video with respect to the phase of the subcarrier

during the color burst. The ADV7324 provides a range of

22.5° increments of 0.17578125°. For normal operation (zero

adjustment), this register is set to 0x80. Values 0xFF and 0x00

represent the upper and lower limits, respectively, of attainable

adjustment.

1. To add +20 IRE brightness level to an NTSC signal with

pedestal, write 0x28 to Address 0x61, SD brightness.

0x[SD Brightness Value] =

0x[IRE Value × 2.015631] =

0x[20 × 2.015631] = 0x[40.31262] = 0x28

Hue Adjust (°) = 0.17578125° (HCR_d− 128) for positive hue

adjust value.

2. To add –7 IRE brightness level to a PAL signal, write 0x72 to

Address 0x61, SD brightness.

For example, to adjust the hue by +4°, write 0x97 to the hue

adjust value register:

[IRE Value| × 2.075631

[7 × 2.015631] = [14.109417] = 0001110b

4

⎛

⎜

⎝

⎞

⎟

⎠

+ 128 = 105d = 0x97

[0001110] into twos complement = [1110010]b = 0x72

Table 32. Brightness Control Values¹

0.17578125

where the sum is rounded to the nearest integer.

Setup Level in

NTSC with

Pedestal

Setup Level in

NTSC without

Pedestal

Setup

Level in

PAL

SD

Brightness

To adjust the hue by −4°, write 0x69 to the hue adjust value

register:

22.5 IRE

15 IRE

7.5 IRE

0 IRE

15 IRE

7.5 IRE

0 IRE

15 IRE

7.5 IRE

0 IRE

0x1E

0x0F

0x00

0x71

−4

⎛

⎜

⎝

⎞

⎟

⎠

+ 128 = 105d = 0x69

0.17578125

–7.5 IRE

where the sum is rounded to the nearest integer.

¹Values in the range of 0x3F to 0x44 might result in an invalid output

signal.

Rev. 0 | Page 51 of 92

ADV7324

Double buffering can be activated on the following HD

registers: HD Gamma Curve A, HD Gamma Curve B, and HD

CGMS registers.

SD Brightness Detect

[Subaddress 0x7A]

The ADV7324 allows monitoring the brightness level of the

incoming video data. Brightness detect is a read-only register.

Double buffering can be activated on the following SD registers:

SD Gamma Curve A, SD Gamma Curve B, SD Y scale, SD U

scale, SD V scale, SD brightness, SD closed captioning, and SD

Macrovision (Bits 5 to 0).

Double Buffering

[Subaddress 0x13, Bit 7; Subaddress 0x48, Bit 2]

Double-buffered registers are updated once per field upon the

falling edge of the Vsync signal. Double buffering improves the

overall performance, because modifications to register settings

will not be made during active video, but take effect upon the

start of the active video.

NTSC WITHOUT PEDESTAL

100 IRE

+7.5 IRE

–7.5 IRE

0 IRE

POSITIVE SETUP

VALUE ADDED

NEGATIVE SETUP

VALUE ADDED

NO SETUP

VALUE ADDED

Figure 68. Examples of Brightness Control Values

Rev. 0 | Page 52 of 92

ADV7324

Table 33. DAC Gain Control

PROGRAMMABLE DAC GAIN CONTROL

DAC

Current

(mA)

DAC A, DAC B, and DAC C are controlled by Register 0A.

Reg. 0x0A or

0x0B

% Gain

+7.5000%

+7.3820%

+7.3640%

...

Note

DAC D, DAC E, and DAC F are controlled by Register 0B.

0100 0000 (0x40)

0011 1111 (0x3F)

0011 1110 (0x3E)

...

4.658

4.653

4.648

...

The I²C control registers will adjust the output signal gain up or

down from its absolute level.

CASE A

...

GAIN PROGRAMMED IN DAC OUTPUT LEVEL

REGISTERS, SUBADDRESSES 0x0A, 0x0B

0000 0010 (0x02)

0000 0001 (0x01)

0000 0000 (0x00)

4.43

4.38

4.33

+0.0360%

+0.0180%

+0.0000%

700mV

(I²C Reset Value,

Nominal)

1111 1111 (0xFF)

1111 1110 (0xFE)

...

4.25

4.23

...

−0.0180%

−0.0360%

...

1100 0010 (0xC2) 4.018

1100 0001 (0xC1) 4.013

1100 0000 (0xC0) 4.008

−7.3640%

−7.3820%

−7.5000%

300mV

NEGATIVE GAIN PROGRAMMED IN

CASE B

DAC OUTPUT LEVEL REGISTERS,

SUBADDRESSES 0x0A, 0x0B

700mV

GAMMA CORRECTION

[Subaddresses 0x24 to 0x37 for HD,

Subaddresses 0x66 to 0x79 for SD]

Gamma correction is available for SD and HD video. For each

standard, there are twenty 8-bit-wide registers. They are used to

program Gamma Correction Curve A and Gamma Correction

Curve B. HD Gamma Curve A is programmed at Address 0x24

to Address 0x2D, and HD Gamma Curve B is programmed at

Address 0x2E to Address 0x37. SD Gamma Curve A is

300mV

Figure 69. Programmable DAC Gain—Positive and Negative Gain

programmed at Address 0x66 to Address 0x6F, and SD Gamma

Curve B is programmed at Address 0x70 to Address 0x79.

In Case A, the video output signal is gained. The absolute level

of the sync tip and blanking level both increase with respect to

the reference video output signal. The overall gain of the signal

is increased from the reference signal.

Generally gamma correction is applied to compensate for the

nonlinear relationship between signal input and brightness level

output (as perceived on the CRT). It can also be applied

wherever nonlinear processing is used.

In Case B, the video output signal is reduced. The absolute level

of the sync tip and blanking level both decrease with respect to

the reference video output signal. The overall gain of the signal

is reduced from the reference signal.

Gamma correction uses the function

γ

Signal_OUT

=

(

Signal_IN

)

The range of this feature is specified for 7.5% of the nominal

output from the DACs. For example, if the output current of the

DAC is 4.33 mA, the DAC tune feature can change this output

current from 4.008 mA (−7.5%) to 4.658 mA (+7.5%).

where γ = gamma power factor.

Gamma correction is performed on the luma data only. The

user may choose either of two curves: Curve A or Curve B. At

any one time, only one of these curves can be used.

The reset value of the vid_out_ctrl registers is 0x00; therefore,

nominal DAC current is output. Table 33 is an example of how

the output current of the DACs varies for a nominal 4.33 mA

output current.

The response of the curve is programmed at 10 predefined

locations. By changing the values at these locations, the gamma

curve can be modified. Between these points, linear interpolation

is used to generate intermediate values. If the curve has a total

length of 256 points, the 10 locations are at 24, 32, 48, 64, 80, 96,

128, 160, 192, and 224. Locations 0, 16, 240, and 255 are fixed

and cannot be changed.

Rev. 0 | Page 53 of 92

ADV7324

GAMMA CORRECTION BLOCK OUTPUT TO A RAMP INPUT

For lengths of 16 to 240 points, the gamma correction curve is

calculated as follows:

300

250

y = xγ

SIGNAL OUTPUT

0.5

where:

200

150

100

y = gamma corrected output.

x = linear input signal.

γ = gamma power factor.

To program the gamma correction registers, calculate the seven

values for y using the following formula:

SIGNAL INPUT

50

0

x_(n−16)

⎡

⎤

y_n=

γ ×(240 −16) + 16

⎢

⎥

(240 −16)

0

50

100

150

LOCATION

200

250

⎣

⎦

where:

_{(n − 16)}= value for x along x-axis at points n.

Figure 70. Signal Input (Ramp) and Signal Output for Gamma 0.5

x

n = 24, 32, 48, 64, 80, 96, 128, 160, 192, or 224.

y_n= value for y along the y-axis, which must be written into the

gamma correction register.

GAMMA CORRECTION BLOCK TO A RAMP INPUT FOR

VARIOUS GAMMA VALUES

300

250

For example,

0.3

y₂₄= [(8/224)0.5 × 224] + 16 = 58

y₃₂= [(16/224)0.5 × 224] + 16 = 76

y₄₈= [(32/224)0.5 × 224] + 16 = 101

y₆₄= [(48/224)0.5 × 224] + 16 = 120

y₈₀= [(64/224)0.5 × 224] + 16 = 136

y₉₆= [(80/224)0.5 × 224] + 16 = 150

200

0.5

150

1.5

100

1.8

50

0

50

100

150

LOCATION

200

250

y

₁₂₈= [(112/224)0.5 × 224] + 16 = 174

₁₆₀= [(144/224)0.5 × 224] + 16 = 195

₁₉₂= [(176/224)0.5 × 224] + 16 = 214

₂₂₄= [(208/224)0.5 × 224] + 16 = 232

Figure 71. Signal Input (Ramp) and Selectable Output Curves

where the sum of each equation is rounded to the nearest

integer.

The gamma curves in Figure 70 and Figure 71 are only examples;

any user-defined curve is acceptable in the range of 16 to 240.

Rev. 0 | Page 54 of 92

ADV7324

The derivative of the incoming signal is compared to the three

programmable threshold values: HD Adaptive Filter Threshold A,

HD Adaptive Filter Threshold B, and HD Adaptive Filter

Threshold C. The recommended threshold range is 16 to 235,

but any value between 0 and 255 can be used.

HD SHARPNESS FILTER AND ADAPTIVE FILTER

CONTROLS

[Subaddresses 0x20, 0x38 to 0x3D]

There are three filter modes available on the ADV7324: a

sharpness filter mode and two adaptive filter modes.

The edges can then be attenuated with the settings in HD

Adaptive Filter Gain 1, HD Adaptive Filter Gain 2, HD Adaptive

Filter Gain 3 registers, and HD sharpness filter gain register.

HD Sharpness Filter Mode

To enhance or attenuate the Y signal in the frequency ranges

shown in Figure 72, the HD sharpness filter must be enabled,

and the HD adaptive filter enable must be disabled.

According to the settings of the HD adaptive filter mode

control, there are two adaptive filter modes available:

To select one of the 256 individual responses, the corresponding

gain values, which range from –8 to +7, for each filter must be

programmed into the HD sharpness filter gain register at

Address 0x20.

•

Mode A is used when adaptive filter mode is set to 0. In

this case, Filter B (LPF) will be used in the adaptive filter

block. Also, only the programmed values for Gain B in the

HD sharpness filter gain and HD Adaptive Filter Gain 1,

HD Adaptive Filter Gain 2, and HD Adaptive Filter Gain 3

are applied when needed. The Gain A values are fixed and

cannot be changed.

HD Adaptive Filter Mode

The HD Adaptive Filter Threshold A, HD Adaptive Filter

Threshold B, and HD Adaptive Filter Threshold C registers; the

HD Adaptive Filter Gain 1, HD Adaptive Filter Gain 2, and HD

Adaptive Filter Gain 3 registers; and the HD sharpness gain

register are used in adaptive filter mode. To activate the

adaptive filter control, the HD sharpness filter and the HD

adaptive filter must be enabled.

•

Mode B is used when adaptive filter mode is set to 1. In

this mode, a cascade of Filter A and Filter B is used.

Settings for Gain A and Gain B in the HD sharpness filter

gain and HD Adaptive Filter Gain 1, HD Adaptive Filter

Gain 2, and HD Adaptive Filter Gain 3 become active

when needed.

SHARPNESS AND ADAPTIVE FILTERS CONTROL BLOCK

1.5

1.4

1.6

1.5

1.4

1.3

1.2

1.1

1.0

1.3

1.2

1.1

1.0

INPUT

SIGNAL:

STEP

ꢀ

1.3

1.2

1.1

1.0

0.9

0.8

0.7

0.6

0.5

0.9

0.8

0.7

0.6

0.5

0

2

4

6

8

10

FREQUENCY (MHz)

FREQUENCY RESPONSE IN SHARPNESS

FILTER MODE WITH K = 3 AND K = 7

12

FREQUENCY (MHz)

FILTER A RESPONSE (Gain K

FREQUENCY (MHz)

FILTER B RESPONSE (Gain K )

B

)

A

B

Figure 72. Sharpness and Adaptive Filters Control Block

Rev. 0 | Page 55 of 92

ADV7324

HD SHARPNESS FILTER AND ADAPTIVE FILTER

APPLICATION EXAMPLES

HD Sharpness Filter Application

The HD sharpness filter can be used to enhance or attenuate the

Y video output signal. The register settings listed in Table 34

were used to achieve the results shown in Figure 73. Input data

was generated by an external signal source.

Table 34. Sharpness Control

Address

0x00

0x01

0x02

0x10

0x11

0x20

Register Setting

Reference¹

0xFC

0x10

0x20

0x00

0x81

0x00

0x08

0x04

a

b

c

d

e

f

0x40

0x80

0x22

¹See Figure 73.

d

e

a

b

R2

R4

1

R1

c

f

1

R2

CH1 500mV

REF A

M 4.00

µ

s

CH1

ALL FIELDS

CH1 500mV

M 4.00

µ

s

CH1

ALL FIELDS

500mV 4.00

µ

s

1 9.99978ms

REF A

500mV 4.00

µ

s

1 9.99978ms

Figure 73. HD Sharpness Filter Control with Different Gain Settings for HD Sharpness Filter Gain Values

Rev. 0 | Page 56 of 92

ADV7324

When changing the adaptive filter mode to Mode B

Adaptive Filter Control Application

[Address 0x15, Bit 6], the output shown in Figure 76 can be

obtained from the input signal shown in Figure 74.

Figure 74 and Figure 75 show how a typical signal is processed

by the adaptive filter control block in Mode A.

Figure 76. Output Signal with Adaptive Filter Control (Mode B)

Figure 74. Input Signal to Adaptive Filter Control

SD DIGITAL NOISE REDUCTION

[Subaddresses 0x63, 0x64, 0x65]

DNR is applied to the Y data only. A filter block selects the high

frequency, low amplitude components of the incoming signal

(DNR input select). The absolute value of the filter output is

compared to a programmable threshold value (DNR threshold

control). There are two DNR modes available: DNR mode and

DNR sharpness mode.

In DNR mode, if the absolute value of the filter output is less

than the threshold, it is assumed to be noise. A programmable

amount (coring gain border, coring gain data) of this noise

signal will be subtracted from the original signal. Likewise, in

DNR sharpness mode, if the absolute value of the filter output is

less than the programmed threshold, it is assumed to be noise.

If the level exceeds the threshold and is identified as a valid

signal, a fraction of the signal (coring gain border, coring gain

data) will be added to the original signal to boost high

Figure 75. Output Signal with Adaptive Filter Control (Mode A)

The register settings in Table 35 were used to obtain the results

shown in Figure 75, i.e., to remove the ringing on the Y signal.

Input data was generated by an external signal source.

Table 35. Register Settings for Figure 75

frequency components and sharpen the video image.

Address

0x00

0x01

0x02

0x10

0x11

0x15

0x20

0x38

0x39

0x3A

0x3B

0x3C

0x3D

Register Setting

0xFC

0x38

0x20

0x00

0x81

0x80

0x00

0xAC

0x9A

0x88

0x28

0x3F

In MPEG systems, it is common to process the video

information in blocks of 8 pixels × 8 pixels for MPEG2 systems,

or 16 pixels × 16 pixels for MPEG1 systems (block size control).

DNR can be applied to the resulting block transition areas that

are known to contain noise. Generally, the block transition area

contains two pixels. It is possible to define this area to contain

four pixels (border area).

It is also possible to compensate for variable block positioning

or differences in YCrCb pixel timing with the use of the DNR

block offset.

The digital noise reduction registers are three 8-bit registers.

They are used to control the DNR processing.

0x64

Rev. 0 | Page 57 of 92

ADV7324

In DNR sharpness mode, the range of gain values is 0 to 0.5 in

increments of 1/16. This factor is applied to the DNR filter

output, which lies above the threshold range. The result is

added to the original signal.

DNR MODE

DNR CONTROL

BLOCK SIZE CONTROL

BORDER AREA

BLOCK OFFSET

GAIN

CORING GAIN DATA

CORING GAIN BORDER

APPLY DATA

APPLY BORDER

CORING GAIN CORING GAIN

NOISE

SIGNAL PATH

INPUT FILTER

BLOCK

O X X X X X X O O X X X X X X O

OFFSET CAUSED

BY VARIATIONS IN

INPUT TIMING

FILTER

SUBTRACT SIGNAL

IN THRESHOLD

RANGE FROM

OUTPUT

O X X X X X X O O X X X X X X O

Y DATA

INPUT

< THRESHOLD?

ORIGINAL SIGNAL

DNR27 – DNR24 = 0x01 O X X X X X X O O X X X X X X O

–

FILTER OUTPUT

> THRESHOLD

+

DNR OUT

MAIN SIGNAL PATH

Figure 78. DNR Offset Control

DNR THRESHOLD

DNR

SHARPNESS

MODE

DNR CONTROL

[Address 0x64, Bit 5 to Bit 0]

BLOCK SIZE CONTROL

BORDER AREA

BLOCK OFFSET

These six bits are used to define the threshold value in the range

of 0 to 63. The range is an absolute value.

GAIN

CORING GAIN DATA

CORING GAIN BORDER

NOISE

SIGNAL PATH

BORDER AREA

INPUT FILTER

BLOCK

[Address 0x64, Bit 6]

FILTER

ADD SIGNAL

ABOVE

THRESHOLD

RANGE FROM

ORIGINAL SIGNAL

OUTPUT

When this bit is set to Logic 1, the block transition area can be

defined to consist of four pixels. If this bit is set to Logic 0, the

border transition area consists of two pixels, where one pixel

refers to two clock cycles at 27 MHz.

Y DATA

INPUT

> THRESHOLD?

+

FILTER OUTPUT

< THRESHOLD

+

DNR OUT

MAIN SIGNAL PATH

720 × 485 PIXELS

2-PIXEL

BORDER

(NTSC)

Figure 77. DNR Block Diagram

DATA

CORING GAIN BORDER

[Address 0x63, Bit 3 to Bit 0]

These four bits are assigned to the gain factor applied to border

areas. In DNR mode, the range of gain values is 0 to 1 in

increments of 1/8. This factor is applied to the DNR filter

output, which lies below the set threshold range. The result is

then subtracted from the original signal.

8 × 8 PIXEL BLOCK

Figure 79. DNR Border Area

In DNR sharpness mode, the range of gain values is 0 to 0.5 in

increments of 1/16. This factor is applied to the DNR filter

output, which lies above the threshold range. The result is

added to the original signal.

BLOCK SIZE CONTROL

[Address 0x64, Bit 7]

This bit is used to select the size of the data blocks to be

processed. Setting the block size control function to Logic 1

defines a 16-pixel × 16-pixel data block, and Logic 0 defines an

8-pixel × 8-pixel data block, where one pixel refers to two clock

cycles at 27 MHz.

CORING GAIN DATA

[Address 0x63, Bit 7 to Bit 4]

These four bits are assigned to the gain factor applied to the luma

data inside the MPEG pixel block. In DNR mode, the range of

gain values is 0 to 1 in increments of 1/8. This factor is applied

to the DNR filter output, which lies below the set threshold

range. The result is then subtracted from the original signal.

DNR INPUT SELECT CONTROL

[Address 0x65, Bit 2 to Bit 0]

Three bits are assigned to select the filter, which is applied to the

incoming Y data. The signal that lies in the pass band of the

selected filter will be DNR processed. Figure 80 shows the filter

responses selectable with this control.

Rev. 0 | Page 58 of 92

ADV7324

not noise. The overall effect is that the signal will be boosted

(similar to using an extended SSAF filter).

1.0

0.8

0.6

0.4

0.2

0

FILTER D

FILTER C

BLOCK OFFSET CONTROL

[Address 0x65, Bit 7 to Bit 4]

Four bits are assigned to this control, which allows a maximum

shift of 15 pixels in a data block. Consider the fixed coring gain

positions. The block offset shifts the data in steps of one pixel

such that the border coring gain factors can be applied at the

same position regardless of variations in input timing of the data.

FILTER B

FILTER A

SD ACTIVE VIDEO EDGE

1

2

3

4

5

6

0

FREQUENCY (Hz)

[Subaddress 0x42, Bit 7]

Figure 80. DNR Input Select

When the active video edge feature is enabled, the first three

pixels and the last three pixels of the active video on the luma

channel are scaled so that maximum transitions on these pixels

are not possible. The scaling factors are ×1/8, ×1/2, and ×7/8.

All other active video passes through unprocessed.

DNR MODE CONTROL

[Address 0x65, Bit 4]

This bit is used to select the DNR mode. Logic 0 selects DNR

mode; Logic 1 selects DNR sharpness mode.

SAV/EAV STEP-EDGE CONTROL

DNR works on the principle of defining low amplitude, high

frequency signals as probable noise and subtracting this noise

from the original signal.

The ADV7324 has the capability of controlling fast rising and

falling signals at the start and end of active video to minimize

ringing.

In DNR mode, it is possible to subtract a fraction of the signal

that lies below the set threshold, assumed to be noise, from the

original signal. The threshold is set in DNR Register 1.

An algorithm monitors SAV and EAV and determines when the

edges are rising or falling too fast. The result is reduced ringing

at the start and end of active video for fast transitions.

Subaddress 0x42, Bit 7 = 1, enables this feature.

When DNR sharpness mode is enabled, it is possible to add a

fraction of the signal that lies above the set threshold to the

original signal, since this data is assumed to be valid data and

LUMA CHANNEL WITH

ACTIVE VIDEO EDGE

DISABLED

LUMA CHANNEL WITH

ACTIVE VIDEO EDGE

ENABLED

100 IRE

0 IRE

100 IRE

87.5 IRE

50 IRE

12.5 IRE

0 IRE

Figure 81. Example of Active Video Edge Functionality

Rev. 0 | Page 59 of 92

ADV7324

VOLTS

0.5

IRE:FLT

100

50

0

F2

L135

–50

2

0

4

6

8

10

12

Figure 82. Address 0x42, Bit 7 = 0

VOLTS

IRE:FLT

100

0.5

50

0

F2

L135

–50

0

–2

2

4

6

8

10

12

Figure 83. Address 0x42, Bit 7 = 1

Rev. 0 | Page 60 of 92

ADV7324

HSYNC/VSYNC OUTPUT CONTROL

The ADV7324 has the ability to accept either embedded time codes in the input data or external Hsync and Vsync signals on

/

, outputting the respective signals on the

and

pins.

P_HSYNC P_VSYNC

P_HSYNC

P_VSYNC

Table 36. Hsync Output Control¹

HD/ED

Sync Output

Enable

SD

HD/ED²

Slave Mode

(0x10, Bit 2)

Sync Output

Enable

(0x02, Bit 6)

I2C_Hsync_gen_sel

(0x14, Bit 1)

Signal on S_HSYNC Pin

(0x02, Bit 7)

Duration

x

0

1

x

Tristate

Pipelined SD Hsync

–

See Appendix 5—SD

Timing Modes

External Hsync &

Vsync /Field

Mode

1

x

0

External pipelined

HD/ED Hsync

As per Hsync timing

EAV/SAV Mode

1

x

0

1

Pipelined HD/ED Hsync based

on AV Code H bit

Pipelined HD/ED Hsync based

on horizontal counter

Same as line blanking

interval

Same as embedded

Hsync

x

______________________________

¹In all HD/ED standards where there is an Hsync o/p, the start of the Hsync pulse is aligned with the falling edge of the embedded Hsync in the output video.

²ED = enhanced definition.

Table 37. Vsync Output Control¹

HD/ED

Sync Output

SD

HD/ED²

Sync Output

Signal on

S_VSYNC Pin

Slave Mode

(0x10, Bit 2)

Enable

(0x02, Bit 7)

Enable

(0x02, Bit 6)

I2C_Vsync_gen_sel

(0x14, Bit 2)

Video Standard

Duration

x

0

1

x

Tristate

Pipelined SD

Vsync/ field

-

Interlaced

See Appendix 5—

SD Timing Modes

External Hysnc

& Vsync/Field

Mode

EAV/SAV Mode

x

1

x

0

1

x

External pipelined As per external

HD/ED Vsync or

field signal

Vsync or field signal

All HD interlace

standards

External pipelined Field

field signal based

on AV Code F bit

All HD/ED

progressive

standards

Pipelined Vsync

based on AV

Code V bit

Vertical blanking

interval

All HD/ED stan-

External pipelined Aligned with

dards except 525p HD/ED Vsync

based on vertical

serration lines

counter

x

1

x

1

525p

External pipelined Vertical blanking

HD/ED Vsync

based on vertical

counter

interval

¹In all HD/ED standards where there is an Hsync o/p, the start of the Hsync pulse is aligned with the falling edge of the embedded Hsync in the output video.

²ED = enhanced definition = progressive scan 525p or 625p.

Rev. 0 | Page 61 of 92

ADV7324

BOARD DESIGN AND LAYOUT

DAC TERMINATION AND LAYOUT

CONSIDERATIONS

CIRCUIT FREQUENCY RESPONSE

MAGNITUDE (dB)

0

–5

16n

14n

12n

10n

8n

–30

The ADV7324 contains an on-board voltage reference. The

ADV7324 can be used with an external V_REF(AD1580).

–60

–10

–15

–20

–25

–30

–35

–40

–90

PHASE (Degrees)

The R_SETresistors are connected between the R_SETpins and

AGND and are used to control the full-scale output current

and, therefore, the DAC voltage output levels. For full-scale

output, R_SETmust have a value of 3040 Ω. The R_SETvalues should

not be changed. R_LOADhas a value of 150 Ω for half-scale output.

–120

–150

–180

–210

–240

6n

GROUP DELAY (Seconds)

4n

VIDEO OUTPUT BUFFER AND OPTIONAL

OUTPUT FILTER

2n

0

1M

10M

100M

Output buffering on all six DACs is necessary to drive output

devices, such as SD or HD monitors. Analog Devices, Inc.,

produces a range of suitable op amps for this application, e.g.,

the AD8061. More information on line-driver buffering circuits

is given in the relevant op amps’ data sheets.

FREQUENCY (Hz)

Figure 85. Filter Plot for Output Filter for SD, 16× Oversampling

3.3µH

DAC OUTPUT

3

4

BNC OUTPUT

22pF

300Ω

1

An optional analog reconstruction low-pass filter (LPF) may be

required as an anti-imaging filter if the ADV7324 is connected

to a device that requires this filtering.

75Ω

300Ω

1.8kΩ

600Ω

The filter specifications vary with the application.

Figure 86. Example of Output Filter for PS, 8× Oversampling

Table 38. External Filter Requirements

Cutoff

Frequency

Application Oversampling (MHz)

Attenuation

–50 dB @

(MHz)

DAC OUTPUT

3

4

470nH 220nH

75Ω

1

3

300Ω

BNC OUTPUT

SD

PS

HDTV

2×

16×

1×

8×

1×

2×

>6.5

>12.5

>30

20.5

209.5

14.5

203.5

44.25

118.5

75Ω

1

33pF

82pF

4

500Ω

>30

Figure 87. Example of Output Filter for HDTV, 2× Oversampling

Table 39. Possible Output Rates

from the ADV7324

2.2µH

DAC OUTPUT

300Ω

3

4

BNC OUTPUT

75Ω

22pF

300Ω

1

Input Mode Address

0x01, Bit 6 to Bit 4

PLL Address

0x00, Bit 1

Output Rate

(MHz)

SD Only

Off

On

Off

On

Off

On

27 (2×)

216 (16×)

27 (1×)

216 (8×)

74.25 (1×)

148.5 (2×)

1.8kΩ

600Ω

PS Only

Figure 84. Example of Output Filter for SD, 16× Oversampling

HDTV Only

Rev. 0 | Page 62 of 92

ADV7324

CIRCUIT FREQUENCY RESPONSE

198

158

118

77.6

37.6

0

There should be separate analog and digital ground planes.

0

–6

20n

18n

16n

14n

12n

10n

Each power plane should encompass a digital power plane and

an analog power plane. The analog power plane should contain

the DACs and all associated circuitry, V_REFcircuitry. The digital

power plane should contain all logic circuitry.

–12

–18

–24

–30

–36

–42

–48

–54

–60

GROUP DELAY (Seconds)

MAGNITUDE (dB)

The analog and digital power planes should be individually

connected to the common power plane at a single point

through a suitable filtering device, such as a ferrite bead.

–42.4

8n

–82.4

6n

–122

–162

–202

4n

2n

0

DAC output traces on a PCB should be treated as transmission

lines. It is recommended that the DACs be placed as close as

possible to the output connector, with the analog output traces

being as short as possible (less than 3 inches). The DAC termi-

nation resistors should be placed as close as possible to the DAC

outputs and should overlay the PCB’s ground plane. As well as

minimizing reflections, short analog output traces reduce noise

pickup from neighboring digital circuitry.

PHASE (Degrees)

10M

1M

100M

FREQUENCY (Hz)

1G

Figure 88. Filter Plot for Output Filter for PS, 8× Oversampling

CIRCUIT FREQUENCY RESPONSE

480

360

240

120

0

–10

–20

–30

–40

–50

–60

18n

15n

12n

9n

To avoid crosstalk between the DAC outputs, it is recommended

that as much space as possible is left between the tracks of the

individual DAC output pins. The addition of ground tracks

between outputs is also recommended.

MAGNITUDE (dB)

GROUP DELAY (Seconds)

Supply Decoupling

Noise on the analog power plane can be further reduced by the

use of decoupling capacitors.

6n

Optimum performance is achieved by the use of 10 nF and

0.1 µF ceramic capacitors. Each group of V_AA, V_DD, or V_{DD_IO}

pins should be individually decoupled to ground. This should

be done by placing the capacitors as close as possible to the

device with the capacitor leads as short as possible, thus

minimizing lead inductance.

PHASE (Degrees)

–120

3n

–240

0

1M

10M

100M

1G

FREQUENCY (Hz)

Figure 89. Filter Plot for Output Filter for HDTV, 2× Oversampling

PCB BOARD LAYOUT

A 1 µF tantalum capacitor is recommended across the V_AA

supply in addition to 10 nF ceramic. See the circuit layout in

Figure 90.

The ADV7324 is optimally designed for lowest noise

performance of both radiated and conducted noise. To

complement the excellent noise performance of the ADV7324,

it is imperative that great care be given to the PC board layout.

Digital Signal Interconnect

The digital signal lines should be isolated as much as possible

from the analog outputs and other analog circuitry. Digital

signal lines should not overlay the analog power plane.

The layout should be optimized for lowest noise on the

ADV7324 power and ground lines. This can be achieved by

shielding the digital inputs and providing good decoupling. The

lead length between groups of V_AAand AGND, V_DDand DGND,

and V_{DD_IO}and GND_IO pins should be kept as short as

possible to minimized inductive ringing.

Due to the high clock rates, avoid long clock lines to the

ADV7324 to minimize noise pickup.

Any active pull-up termination resistors for the digital inputs

should be connected to the digital power plane, not the analog

power plane.

It is recommended that a 4-layer, printed circuit board is used,

with power and ground planes separating the layer of the signal

carrying traces of the components and solder side layer. Com-

ponent placement should be carefully considered to separate

noisy circuits, such as crystal clocks, high speed logic circuitry,

and analog circuitry.

Analog Signal Interconnect

Locate the ADV7324 as close as possible to the output

connectors to minimize noise pickup and reflections due to

impedance mismatch.

Rev. 0 | Page 63 of 92

ADV7324

For optimum performance, each analog output should be

source- and load-terminated, as shown in Figure 90. The

termination resistors should be as close as possible to the

ADV7324 to minimize reflections.

For optimum performance, it is recommended that all

decoupling and external components relating to the ADV7324

are located on the same side of the PCB and as close as possible

to the ADV7324. Unused inputs should be tied to ground.

POWER SUPPLY DECOUPLING

FOR EACH POWER SUPPLY GROUP

V

AA

+

V

10nF

1µF

AA AA

0.1

µF

0.1µF

DD

0.1

µ

F

V

DD_IO

10, 56

V

AA

DD_IO

5kΩ

45

36

41

1

10nF

1.1k

Ω

COMP1, 2

V

DD

AA

DD_IO

2

19

I C

46

44

V

REF

ADV7324

RECOMMENDED EXTERNAL

AD1580 FOR OPTIMUM

PERFORMANCE

100nF

S0–S9

DAC A

DAC B

DAC C

DAC D

DAC E

DAC F

150

Ω

50

49

S_HSYNC

S_VSYNC

43

42

39

38

37

48 S_BLANK

C0–C9

UNUSED

INPUTS

SHOULD BE

GROUNDED

Y0–Y9

63

23

CLKIN_B

P_HSYNC

V

24 P_VSYNC

25 P_BLANK

AA

+

4.7k

Ω

V

DD_IO

5k

DD_IO

33

32

RESET

Ω

5kΩ

100

Ω

2

I C BUS

22

21

SCLK

SDA

4.7µF

CLKIN_A

V

AA

820pF

34

EXT_LF

V

DD_IO

20

35

ALSB

5k

Ω

R

SET2

680Ω

3.9nF

SELECTION HERE

DETERMINES

DEVICE ADDRESS

3040Ω

47

R

SET1

GND_ IO

64

AGND DGND

40

3040Ω

11, 57

ALL COMPONENTS IN DASHED BOXES MUST BE LOCATED ON THE SAME SIDE

OF THE PCB AS THE ADV7324 AND AS CLOSE AS POSSIBLE TO THE ADV7324.

Figure 90. ADV7324 Circuit Layout

Rev. 0 | Page 64 of 92

ADV7324

APPENDIX 1—COPY GENERATION MANAGEMENT SYSTEM

PS CGMS

Data Registers 2 to 0

SD CGMS

Data Registers 2 to 0

[Subaddresses 0x21, 0x22, 0x23]

[Subaddresses 0x59, 0x5A, 0x5B]

The ADV7324 supports the copy generation management

system (CGMS), conforming to the EIAJ CPR-1204 and

ARIB TR-B15 standards. CGMS data is transmitted on Line 20

of the odd fields and Line 283 of the even fields. Bit C/W05 and

Bit C/W06 control whether CGMS data is output on odd or

even fields. CGMS data can only be transmitted when the

ADV7324 is configured in NTSC mode. The CGMS data is

20 bits long. The CGMS data is preceded by a reference pulse of

the same amplitude and duration as a CGMS bit; see Figure 93.

525p

Using the vertical blanking interval 525p system, 525p CGMS

conforms to the CGMS-A EIA-J CPR1204-1 (March 1998)

transfer method of video identification information and to the

IEC61880 (1998) 525p/60 video system’s analog interface for the

video and accompanying data.

When PS CGMS is enabled [Subaddress 0x12, Bit 6 = 1], CGMS

data is inserted on Line 41. The 525p CGMS data registers are at

Address 0x21, Address 0x22, and Address 0x23.

720p System

CGMS data is applied to Line 24 of the luminance vertical

blanking interval.

625p

The 625p CGMS conforms to the IEC62375 (2004) 625p/50

video system’s analog interface for the video and accompanying

data using the vertical blanking interval.

1080i System

CGMS data is applied to Line 19 and Line 582 of the luminance

vertical blanking interval.

When PS CGMS is enabled [Subaddress 0x12, Bit 6 = 1], CGMS

data is inserted on Line 43. The 625p CGMS data registers are at

Address 0x22 and Address 0x23.

CGMS FUNCTIONALITY

If SD CGMS CRC [Address 0x59, Bit 4] or PS/HD CGMS CRC

[Subaddress 0x12, Bit 7] is set to Logic 1, the last six bits, C19 to

C14, which compose the 6-bit CRC check sequence, are

automatically calculated on the ADV7324. This calculation is

based on the lower 14 bits (C0 to C13) of the data in the data

registers and output with the remaining 14 bits to form the

complete 20 bits of the CGMS data. The calculation of the CRC

sequence is based on the polynomial x⁶+ x + 1 with a preset

value of 111111. If SD CGMS CRC [Address 0x59, Bit 4] and

PS/HD CGMS CRC [Address 0x12, Bit 7] are set to Logic 0, all

20 bits (C0 to C19) are output directly from the CGMS registers

(CRC must be manually calculated by the user).

HD CGMS

[Address 0x12, Bit 6]

The ADV7324 supports the copy generation management

system (CGMS) in HDTV mode (720p and 1080i) in

accordance with EIAJ CPR-1204-2.

The HD CGMS data registers are found at Address 0x021,

Address 0x22, and Address 0x23.

Rev. 0 | Page 65 of 92

ADV7324

CRC SEQUENCE

+700mV

REF

70% ± 10%

C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19

0mV

–300mV

21.2µs ± 0.22µs

22T

5.8µs ± 0.15µs

6T

T = 1/(f_H× 33) = 963ns

f_H= HORIZONTAL SCAN FREQUENCY

T ± 30ns

Figure 91. PS 525p CGMS Waveform (Line 41)

PEAK WHITE

R = RUN-IN

S = START CODE

C0

LSB

C13

MSB

R

S

C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12

500mV ± 25mV

SYNC LEVEL

13.7µs

5.5µs ± 0.125µs

Figure 92. PS 625p CGMS-A Waveform (Line 43)

+100 IRE

CRC SEQUENCE

REF

+70 IRE

C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19

0 IRE

–40 IRE

49.1µs ± 0.5µs

11.2µs

2.235µs ± 20ns

Figure 93. SD CGMS Waveform

Rev. 0 | Page 66 of 92

ADV7324

CRC SEQUENCE

+700mV

REF

70% ± 10%

C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19

0mV

T ± 30ns

–300mV

17.2µs ± 160ns

4T

22T

3.128µs ± 90ns

T = 1/(f_H× 1650/58) = 781.93ns

f_H= HORIZONTAL SCAN FREQUENCY

1H

Figure 94. HDTV 720p CGMS Waveform

CRC SEQUENCE

+700mV

REF

70%

±

10%

C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19

0mV

T

± 30ns

–300mV

22.84

µ

s

±

210ns

4T

22T

4.15µs ± 60ns

T = 1/(f

×

2200/77) = 1.038

µs

H

f

= HORIZONTAL SCAN FREQUENCY

H

1H

Figure 95. HDTV 1080i CGMS Waveform

Rev. 0 | Page 67 of 92

ADV7324

APPENDIX 2—SD WIDE-SCREEN SIGNALING

WSS data is preceded by a run-in sequence and a start code (see

Figure 96). If SD WSS [Address 0x59, Bit 7] is set to Logic 1, it

enables the WSS data to be transmitted on Line 23. The latter

[Subaddresses 0x59, 0x5A, 0x5B]

The ADV7324 supports wide screen signaling (WSS)

conforming to the ETS 300 294 standard. WSS data is

transmitted on Line 23. WSS data can be transmitted only when

the device is configured in PAL mode. The WSS data is 14 bits

long, and the function of each bit is shown in Table 40. The

portion of Line 23 (42.5 s after the falling edge of

available for the insertion of video. It is possible to blank the

WSS portion of Line 23 with Subaddress 0x61, Bit 7.

) is

HSYNC

500mV

RUN-IN

START

ACTIVE

VIDEO

W0 W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13

SEQUENCE

CODE

11.0µs

38.4µs

42.5µs

Figure 96. WSS Waveform Diagram

Rev. 0 | Page 68 of 92

ADV7324

Table 40. Function of WSS Bits

Bit

Description

Bit 0 to Bit 2

Bit 3

Aspect ratio/format/position

Odd parity check of Bit 0 to Bit 2

B0

0

1

0

1

0

1

0

1

B1

0

1

0

1

B2

0

1

B3

1

0

1

0

1

0

Aspect Ratio

4:3

14:9

16:9

>16:9

14:9

Format

Position

N/A

Center

Top

Center

Top

Center

N/A

Full format

Letterbox

Full format

N/A

16:9

1

0

16:9

B4

0

1

Camera mode

Film mode

B5

0

Standard coding

1

Motion adaptive color plus

B6

0

No helper

1

Modulated helper

Reserved

B7

B8

0

No teletext subtitles

Teletext subtitles

1

B9

0

B10

0

No open subtitles

1

0

1

0

1

Subtitles in active image area

Subtitles out of active image area

Reserved

B11

0

1

No surround sound information

Surround sound mode

Reserved

B12

B13

Reserved

Rev. 0 | Page 69 of 92

ADV7324

APPENDIX 3—SD CLOSED CAPTIONING

[Subaddresses 0x51 to 0x54]

FCC Code of Federal Regulations (CFR) 47, section 15.119, and

EIA608 describe the closed captioning information for Line 21

and Line 284.

The ADV7324 supports closed captioning conforming to the

standard television synchronizing waveform for color

transmission. Closed captioning is transmitted during the

blanked active line time of Line 21 of the odd fields and

Line 284 of the even fields.

The ADV7324 uses a single-buffering method. This means that

the closed captioning buffer is only 1 byte deep; therefore, there

will be no frame delay in outputting the closed captioning data,

unlike other 2-byte-deep buffering systems. The data must be

loaded one line before it is output on Line 21 and Line 284. A

Closed captioning consists of a 7-cycle sinusoidal burst that is

frequency- and phase-locked to the caption data. After the

clock run-in signal, the blanking level is held for two data bits

and is followed by a Logic 1 start bit. Sixteen bits of data follow

the start bit. These consist of two 8-bit bytes, seven data bits,

and one odd parity bit. The data for these bytes is stored in the

SD closed captioning registers [Address 0x53 to Address 0x54].

typical implementation of this method is to use

to inter-

VSYNC

rupt a microprocessor, which in turn will load the new data

(2 bytes) in every field. If no new data is required for transmission,

0s must be inserted in both data registers; this is called nulling.

It is also important to load control codes, all of which are double

bytes, on Line 21, or a TV will not recognize them. If there is a

message such as “Hello World” that has an odd number of char-

acters, it is important to add a blank character at the end so that

the end-of-caption, 2-byte control code lands in the same field.

The ADV7324 also supports the extended closed captioning

operation, which is active during even fields and encoded on

Line 284. The data for this operation is stored in the SD closed

captioning registers [Address 0x51 to Address 0x52].

All clock run-in signals and timing to support closed captioning

on Line 21 and Line 284 are generated automatically by the

ADV7324. All pixels inputs are ignored during Line 21 and

Line 284 if closed captioning is enabled.

10.5 ± 0.25µs

12.91µs

7 CYCLES OF

0.5035MHz

CLOCK RUN-IN

TWO 7-BIT + PARITY

ASCII CHARACTERS

(DATA)

P

A

R

I

T

Y

P

A

R

I

T

Y

S

T

A

R

T

D0–D6

50 IRE

40 IRE

BYTE 0

BYTE 1

REFERENCE COLOR BURST

(9 CYCLES)

FREQUENCY = F = 3.579545MHz

SC

AMPLITUDE = 40 IRE

10.003µs

27.382µs

33.764µs

Figure 97. Closed Captioning Waveform (NTSC)

Rev. 0 | Page 70 of 92

ADV7324

APPENDIX 4—TEST PATTERNS

The ADV7324 can generate SD and HD test patterns.

T

2

CH2 200mV

M 10.0µs

A CH2 1.20V

CH2 100mV

M 10.0µs

CH2

EVEN

T

30.6000µs

T

1.82600ms

Figure 98. NTSC Color Bars

Figure 101. PAL Black Bar

(–21 mV, 0 mV, 3.5 mV, 7 mV, 10.5 mV, 14 mV, 18 mV, 23 mV)

T

2

CH2 200mV

M 10.0µs

A CH2 1.21V

CH2 200mV

M 4.0µs

CH2

EVEN

T

30.6000µs

T

1.82944ms

Figure 102. 525p Hatch Pattern

Figure 99. PAL Color Bars

T

2

CH2 100mV

M 10.0µs

CH2

EVEN

CH2 200mV

M 4.0µs

CH2

EVEN

T

1.82380ms

T

1.84208ms

Figure 100. NTSC Black Bar

(–21 mV, 0 mV, 3.5 mV, 7 mV, 10.5 mV, 14 mV,18 mV, 23 mV)

Figure 103. 625p Hatch Pattern

Rev. 0 | Page 71 of 92

ADV7324

T

2

CH2 200mV

M 4.0µs

CH2

EVEN

CH2 100mV

M 4.0µs

CH2

EVEN

T

1.82872ms

T

1.82936ms

Figure 106. 525p Black Bar

(−35 mV, 0 mV, 7 mV, 14 mV, 21 mV, 28 mV, 35 mV)

Figure 104. 525p Field Pattern

T

2

CH2 100mV

M 4.0µs

CH2

EVEN

CH2 200mV

M 4.0µs

CH2

EVEN

T

1.84176ms

T

1.84176ms

Figure 105. 625p Field Pattern

Figure 107. 625p Black Bar

(−35 mV, 0 mV, 7 mV, 14 mV, 21 mV, 28 mV, 5 mV)

Rev. 0 | Page 72 of 92

ADV7324

The register settings in Table 41 are used to generate an SD

NTSC CVBS output on DAC A, S-video on DACs B and C, and

YPrPb on DACs D, E, and F. Upon power-up, the subcarrier

registers are programmed with the appropriate values for

NTSC. All other registers are set as normal/default.

The register settings in Table 43 are used to generate a 525p

hatch pattern on DAC D, E, and F. All other registers are set as

normal/default.

Table 43. 525p Test Pattern Register Writes

Subaddress

Register Setting

Table 41. NTSC Test Pattern Register Writes

0x00

0xFC

Subaddress

Register Setting

0x01

0x10

0x00

0xFC

0x10

0x00

0x40

0x10

0x11

0x05

0x42

0x40

0x16

0xA0

0x44

0x4A

0x40 (internal test pattern on)

0x08

0x17

0x18

0x80

For PAL CVBS output on DAC A, the same settings are used,

except Subaddress 0x40 is programmed to 0x11 and the F_SC

registers are programmed as shown in Table 42.

For 625p hatch pattern on DAC D, the same register settings are

used, except Subaddress 0x10 = 0x18.

Table 42. PAL F_SCRegister Writes

Subaddress

Description

Register Setting

0x4C

0x4D

0x4E

0x4F

F_SC0

F_SC1

F_SC2

F_SC3

0xCB

0x8A

0x09

0x2A

Note that when programming the F_SCregisters, the user must

write the values in the sequence F_SC0, F_SC1, F_SC2, F_SC3. The full

F_SCvalue is only accepted after the F_SC3 write is complete.

Rev. 0 | Page 73 of 92

ADV7324

APPENDIX 5—SD TIMING MODES

[Subaddress 0x4A]

MODE 0 (CCIR-656)—SLAVE OPTION

(TIMING REGISTER 0 TR0 = X X X X X 0 0 0)

The ADV7324 is controlled by the SAV (start active video) and

EAV (end active video) time codes in the pixel data. All timing

information is transmitted using a 4-byte synchronization pattern.

A synchronization pattern is sent immediately before and after

each line during active picture and retrace. If Pin

,

S_VSYNC

, and Pin

S_BLANK

are not used, they should be

S_HSYNC

tied high during this mode. Blank output is available.

ANALOG

VIDEO

EAV CODE

SAV CODE

C

b

C

r

C

b

8

0

F

A

B

A

B

A

B

8

0

C

r

F

0

X

Y

1

0

8

0

1

0

8

0

1

0

1

0

F

0

X

Y

C

b

C

r

Y

INPUT PIXELS

ANCILLARY DATA

(HANC)

4 CLOCK

1440 CLOCK

268 CLOCK

NTSC/PAL M SYSTEM

(525 LINES/60Hz)

280 CLOCK

PAL SYSTEM

(625 LINES/50Hz)

START OF ACTIVE

VIDEO LINE

END OF ACTIVE

VIDEO LINE

Figure 108. SD Slave Mode 0

Rev. 0 | Page 74 of 92

ADV7324

MODE 0 (CCIR-656)—MASTER OPTION

(TIMING REGISTER 0 TR0 = X X X X X 0 0 1)

The ADV7324 generates H, V, and F signals required for the

SAV (start active video) and EAV (end active video) time codes

in the CCIR656 standard. The H, V, and F bits are output on

,

, and

, respectively.

S_HSYNC S_BLANK

S_VSYNC

DISPLAY

VERTICAL BLANK

4

522

523

524

525

1

2

3

5

6

7

8

10

11

20

21

22

9

H

V

ODD FIELD

EVEN FIELD

F

DISPLAY

VERTICAL BLANK

283

285

284

260

261

262

263

264

265

266

267

268

269

270

271

272

273

274

H

V

F

ODD FIELD

EVEN FIELD

Figure 109. SD Master Mode 0 (NTSC)

Rev. 0 | Page 75 of 92

ADV7324

DISPLAY

VERTICAL BLANK

622

623

624

625

4

22

23

1

2

3

5

6

7

21

H

V

ODD FIELD

EVEN FIELD

F

DISPLAY

VERTICAL BLANK

318

335

336

309

310

311

312

313

314

315

316

317

319

320

334

H

V

F

ODD FIELD

EVEN FIELD

Figure 110. SD Master Mode 0 (PAL)

ANALOG

VIDEO

H

F

V

Figure 111. SD Master Mode 0 (Data Transitions)

Rev. 0 | Page 76 of 92

ADV7324

MODE 1—SLAVE OPTION

(TIMING REGISTER 0 TR0 = X X X X X 0 1 0)

In this mode, the ADV7324 accepts horizontal sync and

odd/even field signals. When

is low, a transition of the

HSYNC

field input indicates a new frame, i.e., vertical retrace. The

signal is optional. When the input is disabled,

BLANK

ADV7324 automatically blanks all normally blank lines as per

CCIR-624. , and FIELD are input on

BLANK

,

HSYNC BLANK

,

, and

, respectively.

S_VSYNC

S_HSYNC S_BLANK

DISPLAY

VERTICAL BLANK

522

523

524

525

20

21

22

3

4

5

7

9

10

11

1

2

6

8

HSYNC

BLANK

FIELD

ODD FIELD

EVEN FIELD

DISPLAY

VERTICAL BLANK

283

285

284

260

261

262

263

264

265

266

267

268

269

270

271

272

273

274

HSYNC

BLANK

FIELD

ODD FIELD EVEN FIELD

Figure 112. SD Slave Mode 1 (NTSC)

Rev. 0 | Page 77 of 92

ADV7324

MODE 1—MASTER OPTION

(TIMING REGISTER 0 TR0 = X X X X X 0 1 1)

In this mode, the ADV7324 can generate horizontal sync and

odd/even field signals. When

is low, a transition of the

HSYNC

field input indicates a new frame, i.e., vertical retrace. The

signal is optional. When the input is disabled,

BLANK

ADV7324 automatically blanks all normally blank lines as per

CCIR-624. Pixel data is latched on the rising clock edge

following the timing signal transitions.

,

, and

HSYNC BLANK

FIELD are output on

respectively.

,

, and

,

S_VSYNC

S_HSYNC S_BLANK

DISPLAY

VERTICAL BLANK

3

4

5

7

622

623

624

625

1

2

6

21

22

23

HSYNC

BLANK

FIELD

ODD FIELD

EVEN FIELD

DISPLAY

VERTICAL BLANK

309

310

311

312

313

314

315

316

318

319

320

317

334

335

336

HSYNC

BLANK

FIELD

ODD FIELD

EVEN FIELD

Figure 113. SD Slave Mode 1 (PAL)

HSYNC

FIELD

PAL = 12 × CLOCK/2

NTSC = 16 × CLOCK/2

BLANK

PIXEL

DATA

Cr

Y

Cb

Y

PAL = 132 × CLOCK/2

NTSC = 122 × CLOCK/2

Figure 114. SD Timing Mode 1—Odd/Even Field Transitions Master/Slave

Rev. 0 | Page 78 of 92

ADV7324

MODE 2— SLAVE OPTION

(TIMING REGISTER 0 TR0 = X X X X X 1 0 0)

In this mode, the ADV7324 accepts horizontal and vertical sync

signals. A coincident low transition of both

and

HSYNC

VSYNC

inputs indicates the start of an odd field. A

low

VSYNC

transition when

is high indicates the start of an even

HSYNC

field. The

signal is optional. When the

input is

BLANK

disabled, ADV7324 automatically blanks all normally blank

lines as per CCIR-624.

,

, and

are input

VSYNC

HSYNC BLANK

S_HSYNC

on

,

, and

, respectively.

S_VSYNC

S_BLANK

DISPLAY

VERTICAL BLANK

522

523

524

525

1

3

2

4

5

6

7

8

20

21

22

10

11

9

HSYNC

BLANK

VSYNC

ODD FIELD

EVEN FIELD

DISPLAY

VERTICAL BLANK

283

285

284

260

261

262

263

264

265

266

267

268

269

270

271

272

273

274

HSYNC

BLANK

VSYNC

EVEN FIELD

ODD FIELD

Figure 115. SD Slave Mode 2 (NTSC)

DISPLAY

VERTICAL BLANK

4

622

623

624

625

1

2

3

5

6

7

21

22

23

HSYNC

BLANK

VSYNC

EVEN FIELD

ODD FIELD

DISPLAY

VERTICAL BLANK

309

310

311

312

313

314

315

316

318

319

320

317

334

335

336

HSYNC

BLANK

VSYNC

EVEN FIELD

ODD FIELD

Figure 116. SD Slave Mode 2 (PAL)

Rev. 0 | Page 79 of 92

ADV7324

MODE 2—MASTER OPTION

(TIMING REGISTER 0 TR0 = X X X X X 1 0 1)

In this mode, the ADV7324 can generate horizontal and vertical

sync signals. A coincident low transition of both

and

HSYNC

inputs indicates the start of an odd field.

VSYNC

A

low transition when

is high indicates the start

VSYNC

HSYNC

of an even field. The

signal is optional. When the

BLANK

input is disabled, the ADV7324 automatically blanks all normally

blank lines as per CCIR-624. , and are

BLANK

,

HSYNC BLANK

VSYNC

, respectively.

S_VSYNC

output on

,

, and

S_HSYNC S_BLANK

HSYNC

VSYNC

PAL = 12

×

CLOCK/2

NTSC = 16

×

BLANK

PIXEL

DATA

Cb

Cr

Y

PAL = 132

×

CLOCK/2

NTSC = 122

×

Figure 117. SD Timing Mode 2 Even-to-Odd Field Transition Master/Slave

HSYNC

VSYNC

PAL = 864 × CLOCK/2

NTSC = 858 × CLOCK/2

PAL = 12 × CLOCK/2

NTSC = 16 × CLOCK/2

BLANK

PIXEL

DATA

Cb

Cr

Y

Cb

Y

PAL = 132 × CLOCK/2

NTSC = 122 × CLOCK/2

Figure 118. SD Timing Mode 2 Odd-to-Even Field Transition

Rev. 0 | Page 80 of 92

ADV7324

MODE 3—MASTER/SLAVE OPTION

(TIMING REGISTER 0 TR0 = X X X X X 1 1 0 OR X X X X X 1 1 1)

In this mode, the ADV7324 accepts or generates horizontal

sync and odd/even field signals. When

is high, a

HSYNC

transition of the field input indicates a new frame, i.e., vertical

retrace. The signal is optional. When the input

BLANK

is disabled, ADV7324 automatically blanks all normally blank

lines as per CCIR-624.

,

, and

are

HSYNC BLANK

VSYNC

output in master mode and input in slave mode on

,

S_VSYNC

, and

, respectively.

S_BLANK

S_VSYNC

DISPLAY

VERTICAL BLANK

522

523

524

525

4

3

20

21

22

10

11

1

2

5

6

7

8

9

HSYNC

BLANK

FIELD

EVEN FIELD ODD FIELD

DISPLAY

VERTICAL BLANK

283

285

284

260

261

262

263

264

265

266

267

268

269

270

271

272

273

274

HSYNC

BLANK

FIELD

ODD FIELD EVEN FIELD

Figure 119. SD Timing Mode 3 (NTSC)

DISPLAY

VERTICAL BLANK

622

623

624

625

1

2

3

4

5

6

7

21

22

23

HSYNC

BLANK

FIELD

EVEN FIELD ODD FIELD

DISPLAY

VERTICAL BLANK

309

310

311

312

313

314

315

316

318

319

320

317

334

335

336

HSYNC

BLANK

FIELD

EVEN FIELD ODD FIELD

Figure 120. SD Timing Mode 3 (PAL)

Rev. 0 | Page 81 of 92

ADV7324

APPENDIX 6—HD TIMING

DISPLAY

FIELD 1

VERTICAL BLANKING INTERVAL

1124 1125

1

2

3

4

5

6

7

8

20

21

22

560

P_VSYNC

P_HSYNC

DISPLAY

VERTICAL BLANKING INTERVAL

FIELD 2

561

562

563

564

565

566

567

568

569

570

583

584

585

1123

P_VSYNC

P_HSYNC

HSYNC

VSYNC

Input Timing

Figure 121. 1080i

and

Rev. 0 | Page 82 of 92

ADV7324

APPENDIX 7—VIDEO OUTPUT LEVELS

HD YPrPb OUTPUT LEVELS

EIA-770.2 STANDARD FOR Y

EIA-770.3 STANDARD FOR Y

INPUT CODE

940

OUTPUT VOLTAGE

940

700mV

64

300mV

EIA-770.3 STANDARD FOR Pr/Pb

OUTPUT VOLTAGE

EIA-770.2 STANDARD FOR Pr/Pb

OUTPUT VOLTAGE

960

512

64

960

600mV

700mV

512

64

700mV

Figure 122. EIA 770.2 Standard Output Signals (525p/625p)

Figure 124. EIA 770.3 Standard Output Signals (1080i/720p)

EIA-770.1 STANDARD FOR Y

Y OUTPUT LEVELS FOR

FULL INPUT SELECTION

INPUT CODE

OUTPUT VOLTAGE

782mV

INPUT CODE

1023

OUTPUT VOLTAGE

940

700mV

714mV

64

300mV

286mV

Pr/Pb OUTPUT LEVELS FOR

FULL INPUT SELECTION

OUTPUT VOLTAGE

INPUT CODE

1023

EIA-770.1 STANDARD FOR Pr/Pb

OUTPUT VOLTAGE

960

700mV

512

64

300mV

Figure 123. EIA 770.1 Standard Output Signals (525p/625p)

Figure 125. Output Levels for Full Input Selection

Rev. 0 | Page 83 of 92

ADV7324

RGB OUTPUT LEVELS

Pattern: 100%/75% Color Bars

700mV

525mV

700mV

525mV

300mV

700mV

525mV

300mV

700mV

525mV

300mV

Figure 126. PS RGB Output Levels

Figure 128. SD RGB Output Levels—RGB Sync Disabled

700mV

525mV

700mV

525mV

300mV

0mV

300mV

0mV

525mV

300mV

0mV

300mV

0mV

525mV

300mV

0mV

300mV

0mV

Figure 129. SD RGB Output Levels—RGB Sync Enabled

Figure 127. PS RGB Output Levels—RGB Sync Enabled

Rev. 0 | Page 84 of 92

ADV7324

YPrPb LEVELS—SMPTE/EBU N10

Pattern: 100% Color Bars

700mV

Figure 130. Pb Levels (NTSC)

Figure 133. Pr Levels (PAL)

700mV

300mV

Figure 131. Pb Levels (PAL)

Figure 134. Y Levels (NTSC)

700mV

300mV

Figure 135. Y Levels (PAL)

Figure 132. Pr Levels (NTSC)

Rev. 0 | Page 85 of 92

ADV7324

VOLTS

0.6

VOLTS IRE:FLT

100

0.4

0.2

0

0.5

50

0

–0.2

0

F1

–50

L608

L76

0

10

20

30

40

50

60

10

20

MICROSECONDS

PRECISION MODE OFF

30

40

50

60

MICROSECONDS

NOISE REDUCTION: 0.00dB

APL = 39.1%

APL = 44.5%

525 LINE NTSC

PRECISION MODE OFF

SYNCHRONOUS SOUND-IN-SYNC OFF

FRAMES SELECTED 1, 2, 3, 4

SYNCHRONOUS SYNC = A

FRAMES SELECTED 1, 2

625 LINE NTSC NO FILTERING

SLOW CLAMP TO 0.00V AT 6.72µs

SLOW CLAMP TO 0.00 AT 6.72µs

Figure 136. NTSC Color Bars 75%

Figure 139. PAL Color Bars 75%

VOLTS

0.5

VOLTS IRE:FLT

0.4

50

0.2

0

–0.2

–0.4

–50

–0.5

F1

L76

L575

20

0

10

20

30

40

50

60

10

30

40

50

60

MICROSECONDS

NOISE REDUCTION: 15.05dB

APL NEEDS SYNC SOURCE

525 LINE NTSC NO FILTERING

SLOW CLAMP TO 0.00 AT 6.72µs

APL NEEDS SYNC SOURCE

625 LINE PAL NO FILTERING

SLOW CLAMP TO 0.00 AT 6.72µs

NO BUNCH SIGNAL

PRECISION MODE OFF

SYNCHRONOUS SYNC = B

FRAMES SELECTED 1, 2

SYNCHRONOUS SOUND-IN-SYNC OFF

FRAMES SELECTED 1

Figure 137. NTSC Chroma

Figure 140. PAL Chroma

VOLTS

0.5

VOLTS IRE:FLT

0.6

0.4

50

0

0.2

0

–0.2

F2

L238

L575

20

0

10

30

40

50

60

70

10

20

30

40

50

60

MICROSECONDS

NO BUNCH SIGNAL

APL NEEDS SYNC SOURCE

625 LINE PAL NO FILTERING

SLOW CLAMP TO 0.00 AT 6.72µs

NOISE REDUCTION: 15.05dB

APL = 44.3%

525 LINE NTSC NO FILTERING

SLOW CLAMP TO 0.00 AT 6.72µs

PRECISION MODE OFF

SYNCHRONOUS SYNC = SOURCE

FRAMES SELECTED 1, 2

SYNCHRONOUS SOUND-IN-SYNC OFF

FRAMES SELECTED 1

Figure 141. PAL Luma

Figure 138. NTSC Luma

Rev. 0 | Page 86 of 92

ADV7324

APPENDIX 8—VIDEO STANDARDS

0

DATUM

H

SMPTE 274M

ANALOG WAVEFORM

DIGITAL HORIZONTAL BLANKING

272T

*1

4T

1920T

DIGITAL

ACTIVE LINE

ANCILLARY DATA

(OPTIONAL) OR BLANKING CODE

EAV CODE

SAV CODE

F

0

F

0

C

r

C

INPUT PIXELS

Y

V

Y

b

r

H*

4 CLOCK

192

0

2199

SAMPLE NUMBER

2112

2116 2156

44

188

2111

FVH* = FVH AND PARITY BITS

SAV/EAV: LINE 1–562: F = 0

SAV/EAV: LINE 563–1125: F = 1

SAV/EAV: LINE 1–20; 561–583; 1124–1125: V = 1

SAV/EAV: LINE 21–560; 584–1123: V = 0

FOR A FRAME RATE OF 30Hz: 40 SAMPLES

FOR A FRAME RATE OF 25Hz: 480 SAMPLES

Figure 142. EAV/SAV Input Data Timing Diagram (SMPTE 274M)

SMPTE 293M

ANALOG WAVEFORM

ANCILLARY DATA

(OPTIONAL)

DIGITAL

SAV CODE

F

EAV CODE

F

ACTIVE LINE

F

0

F

0

C

b

C

r

C

INPUT PIXELS

V

Y

V

Y

r

Y

H*

4 CLOCK

853 857

SAMPLE NUMBER

719

723 736

DATUM

799

0

719

0

H

DIGITAL HORIZONTAL BLANKING

FVH* = FVH AND PARITY BITS

SAV: LINE 43–525 = 200H

SAV: LINE 1–42 = 2AC

EAV: LINE 43–525 = 274H

EAV: LINE 1–42 = 2D8

Figure 143. EAV/SAV Input Data Timing Diagram (SMPTE 293M)

Rev. 0 | Page 87 of 92

ADV7324

ACTIVE

VIDEO

ACTIVE

VIDEO

VERTICAL BLANK

522 523 524 525

1

2

5

6

7

8

9

12

13

14

15

16

42

43

44

Figure 144. SMPTE 293M (525p)

ACTIVE

VIDEO

ACTIVE

VIDEO

VERTICAL BLANK

12

13

1

2

5

6

7

8

9

43

44

45

622 623

624 625

4

10

11

Figure 145. ITU-R BT.1358 (625p)

DISPLAY

VERTICAL BLANKING INTERVAL

7

1

2

3

4

5

6

747

748

749

750

26

27

744

745

8

25

Figure 146. SMPTE 296M (720p)

DISPLAY

VERTICAL BLANKING INTERVAL

FIELD 1

560

1

2

5

6

7

8

21

22

1124

1125

3

4

20

DISPLAY

VERTICAL BLANKING INTERVAL

FIELD 2

561

562

563

564

565

566

567

568

569

570

583

584

585

1123

Figure 147. SMPTE 274M (1080i)

Rev. 0 | Page 88 of 92

ADV7324

OUTLINE DIMENSIONS

0.75

0.60

0.45

12.00 BSC

SQ

1.60

MAX

64

49

1

48

PIN 1

10.00

BSC SQ

TOP VIEW

(PINS DOWN)

1.45

1.40

1.35

0.20

0.09

7°

3.5°

0°

0.08 MAX

COPLANARITY

16

33

0.15

0.05

SEATING

PLANE

17

32

VIEW A

0.27

0.22

0.17

0.50

BSC

LEAD PITCH

VIEW A

ROTATED 90° CCW

COMPLIANT TO JEDEC STANDARDS MS-026BCD

Figure 148. 64-Lead Low Profile Quad Flat Package [LQFP]

(ST-64-2)

Dimensions shown in millimeters

ORDERING GUIDE

Model

Temperature Range

Package Description

Package Option

ADV7324KSTZ¹

0°C to 70°C

64-Lead Low Profile Quad Flat Package [LQFP]

Evaluation Board

ST-64-2

EVAL-ADV7324EB

¹Z = Pb-free part.

Rev. 0 | Page 89 of 92

ADV7324

NOTES

Rev. 0 | Page 90 of 92

ADV7324

NOTES

Rev. 0 | Page 91 of 92

ADV7324

NOTES

registered trademarks are the property of their respective owners.

D05220–0–11/04(0)

Rev. 0 | Page 92 of 92


型号：	ADV7324KSTZ
厂家：	ADI
描述：	Multiformat 216 MHz Video Encoder with Six NSV 14-Bit DACs 多格式216 MHz的视频编码器与六NSV 14位DAC 编码器
文件：	总92页 (文件大小：1008K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADV7324KSTZ [ADI]

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