CN-0109 [ADI]
Low Jitter Sampling Clock Generator for High Performance ADCs; 低抖动采样时钟发生器用于高性能ADC
| 型号： | CN-0109 |
| 厂家： | 
ADI |
| 描述： | Low Jitter Sampling Clock Generator for High Performance ADCs |
| 文件： | 总3页 (文件大小：121K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Circuit Note
CN-0109
Devices Connected/Referenced
500 MSPS/1 GSPS Direct Digital
Synthesizer (DDS)
AD9958/
AD9858
Circuit Designs Using Analog Devices Products
Apply these product pairings quickly and with confidence.
For more information and/or support call 1-800-AnalogD
(1-800-262-5643) or visit www.analog.com/circuit.
Clock Distribution IC and Pin Programmable
Mini-Divider
AD9515
AD6645 14-Bit, 80 MSPS/105 MSPS ADC
Low Jitter Sampling Clock Generator for High Performance ADCs Using the
AD9958/AD9858 500 MSPS/1GSPS DDS and AD9515 Clock Distribution IC
Wenzel crystal oscillator (www.wenzel.com). Data was taken on
two different DDSes: the AD9958 (500 MSPS) and the
AD9858 (1 GSPS).
CIRCUIT FUNCTION AND BENEFITS
This circuit uses a direct digital synthesizer (DDS) with sub-
Hertz tuning resolution as a low jitter sampling clock source for
high performance ADCs. The AD9515 clock distribution IC
provides PECL logic levels to the ADC. However, the AD9515
internal divider feature also allows the DDS to run at a higher
frequency into the AD9515 front end, effectively increasing
input slew rate. A higher slew rate into the AD9515 input
squaring circuit can help reduce broadband jitter in the
clock path.
FFT
ANALYSIS
BPF
AD6645
WENZEL
ULN-SERIES
CRYSTAL
AIN = 170.3MHz
OSCILLATOR
RECONSTRUCTION
FILTER
AD9958, AD9858
DDS
LPF/BPF
AD9515
Jitter on the ADC sampling clock produces degradation in the
overall signal-to-noise ratio (SNR). The relationship is given by
Equation 1.
DIFFERENTIAL PECL
SAMPLING CLOCK
ROHDE AND SCHWARZ SMA GENERATOR
500MHz AND 1GHz @ +6dBm
Figure 1. DDS-Based ADC Sampling Clock Generator
(Simplified Diagram)
1
(1)
SNR = 20 log10
2πft j
By evaluating the contribution of the ADC’s differential non-
linearity and thermal noise and then applying the DDS-based
clock and measuring the ADC SNR, the added jitter attributable
to the DDS-based clock can be derived. For more details on the
measurement setup and the jitter calculations, refer to
Application Note AN-823. Also, Application Note AN-837 is
instructive for designing DAC reconstruction filters with
optimal stop-band performance.
where f is the full-scale analog input frequency, and tj is the rms
jitter. "SNR" in Equation 1 is the SNR due solely to clock jitter
and does not depend on the resolution of the ADC.
The following data supports low jitter attainable from a DDS in
clocking applications. Further details on Equation 1 and its use
for evaluating the jitter on ADC sampling clocks can be found
in Application Note AN-501.
Table 1 shows data for the AD9958 test results. The data
confirms that better jitter performance is achieved as the
frequency, or slew rate, of the DDS output frequency is
increased and as the DDS output filter pass band is decreased.
Table 2 shows the AD9858 with a 5% band-pass filter, a
225 MHz low-pass filter, and various levels of DDS output
power. As expected, lower jitter is achieved as power is
increased and bandwidth reduced. With a 5% band-pass filter,
the majority of the spurs from the DAC are attenuated. The
jitter in this case is much more dependent on noise coupling
between the DAC output and the limiter input. This is proven
by the strong correlation between jitter reduction and increased
CIRCUIT DESCRIPTION
The circuit configuration in Figure 1 shows a DDS-based clock
generator, consisting of a DDS followed by a reconstruction
filter and an AD9515 clock distribution IC, used to provide the
sampling clock for an analog-to-digital converter (ADC). The
DDS sampling clock is derived from a Rohde and Schwarz
SMA signal generator. The jitter measurement was made by
using the clock derived from the DDS and the AD9515 as the
sampling clock for the high performance AD6645 14-bit,
80 MSPS/105 MSPS ADC. The analog input signal for the ADC
is a filtered 170.3 MHz sine wave derived from a low jitter
Rev. 0
“Circuits from the Lab” from Analog Devices have been designed and built by Analog Devices
engineers. Standard engineering practices have been employed in the design and construction of
each circuit, and their function and performance have been tested and verified in a lab environment
at room temperature. However, you are solely responsible for testing the circuit and determining its
suitability and applicability for your use and application. Accordingly, in no event shall Analog
Devices be liable for direct, indirect, special, incidental, consequential or punitive damages due to
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©2009 Analog Devices, Inc. All rights reserved.
CN-0109
Circuit Note
slew rate. Note that rms jitter values consistently less than 1 ps
can be achieved using the AD9858 circuit.
Data Converters and Solving the Mystery of AGND and DGND
and MT-101 Tutorial, Decoupling Techniques) in order to
achieve these performance levels. Consult the evaluation board
documentation for the AD9958, AD9858, AD9515, and
AD6645 for more guidance.
These circuits must be constructed on multilayer PC boards
with large area ground planes using proper grounding, layout,
and decoupling techniques (see MT-031 Tutorial, Grounding
Table 1. Jitter Response of AD9958 and AD9515 vs. fOUT, Power, Frequency, and Filter BW
DDS
Sample
Rate (MHz)
DDS Output
Frequency
(MHz)
DDS Output
Power
(dBm)
DDS
Reconstruction
Filter (MHz)
AD9515
Divider Output
Setting
AD9515 Output
Frequency
(MHz)
Jitter
(rms)
(ps)
Product
AD9958/AD9515 500
AD9958/AD9515 500
AD9958/AD9515 500
AD9958/AD9515 500
AD9958/AD9515 500
AD9958/AD9515 500
AD9958/AD9515 500
AD9958/AD9515 500
AD9958/AD9515 500
AD9958/AD9515 500
AD9958/AD9515 500
AD9958/AD9515 500
AD9958/AD9515 500
AD9958/AD9515 500
AD9958/AD9515 500
AD9958/AD9515 500
38.88
38.88
38.88
38.88
38.88
38.88
77.76
77.76
77.76
77.76
77.76
77.76
155.52
155.52
155.52
155.52
−3.6
−3.6
−4.7
−4.7
−3.3
−3.3
−3.8
−3.8
−4.9
−4.9
−3.8
−3.8
−5.5
−5.5
−5.6
−5.6
200 LPF
200 LPF
47 LPF
1
38.88
4.1
4.1
2.4
2.4
1.5
1.5
2.5
2.5
1.5
1.5
1.1
1.1
1.5
1.5
0.68
0.68
2
19.44
1
38.88
47 LPF
2
19.44
5% BPF
5% BPF
200 LPF
200 LPF
85 LPF
1
38.88
2
19.44
1
77.76
2, 4
1
38.88, 19.44
77.76
85 LPF
2, 4
1
38.88, 19.44
77.76
5% BPF
5% BPF
200 LPF
200 LPF
5% BPF
5% BPF
2, 4
2
38.88, 19.44
77.76
4, 8
2
38.88, 19.44
77.76
4, 8
38.88, 19.44
Table 2. Jitter Response of AD9858 and AD9515 vs. fOUT, Power, Frequency, and Filter BW
DDS
Sample
Rate (MHz)
DDS Output
Frequency
(MHz)
DDS
Reconstruction Divider Output
AD9515
Jitter
(rms)
DDS Output
Power (dBm)
AD9515 Output
Product
Filter (MHz)
225 LPF
225 LPF
5% BPF
5% BPF
225 LPF
225 LPF
5% BPF
5% BPF
225 LPF
225 LPF
5% BPF
5% BPF
Setting
Frequency (MHz) (ps)
AD9858/AD9515 1000
AD9858/AD9515 1000
AD9858/AD9515 1000
AD9858/AD9515 1000
AD9858/AD9515 1000
AD9858/AD9515 1000
AD9858/AD9515 1000
AD9858/AD9515 1000
AD9858/AD9515 1000
AD9858/AD9515 1000
AD9858/AD9515 1000
AD9858/AD9515 1000
155.52
155.52
155.52
155.52
155.52
155.52
155.52
155.52
155.52
155.52
155.52
155.52
+7.7
+7.7
+7.7
+7.7
+2.6
+2.6
+1.1
+1.1
−3.2
−3.2
−4.6
−4.6
2
77.76
0.56
0.56
0.33
0.33
0.63
0.63
0.42
0.42
0.73
0.73
0.64
0.64
4,8
2
38.88, 19.44
77.76
4, 8
2
38.88, 19.44
77.76
4, 8
2
38.88, 19.44
77.76
4, 8
2
38.88, 19.44
77.76
4, 8
2
38.88, 19.44
77.76
4, 8
38.88, 19.44
Rev. 0 | Page 2 of 3
Circuit Note
CN-0109
Data Sheets and Evaluation Boards
AD6645 Data Sheet.
COMMON VARIATIONS
Analog Devices offers a variety of direct digital synthesizer,
clock distribution chips, and clock buffers to build a DDS-based
clock generator. Refer to www.analog.com/dds and
www.analog.com/clock for more information.
AD9515 Data Sheet.
AD9858 Data Sheet.
AD9958 Data Sheet.
AD6645 Evaluation Board.
AD9515 Evaluation Board.
AD9858 Evaluation Board.
AD9958 Evaluation Board.
LEARN MORE
AN-501 Application Note, Aperture Uncertainty and ADC
System Performance. Analog Devices.
AN-823 Application Note, Direct Digital Synthesizers in
Clocking Applications. Analog Devices.
AN-837 Application Note, DDS-Based Clock Jitter Performance
vs. DAC Reconstruction Filter Performance. Analog Devices.
REVISION HISTORY
7/09—Revision 0: Initial Version
Kester, Walt. 2005. The Data Conversion Handbook. Analog
Devices. Chapters 6 and 7.
Kester, Walt. 2006. High Speed System Applications. Analog
Devices. Chapter 2, “Optimizing Data Converter Interfaces.”
Kester, Walt. 2006. High Speed System Applications. Analog
Devices. Chapter 3, “DACs, DDSs, PLLs, and Clock
Distribution.”
MT-031 Tutorial, Grounding Data Converters and Solving the
Mystery of AGND and DGND. Analog Devices.
MT-101 Tutorial, Decoupling Techniques. Analog Devices.
(Continued from first page) "Circuits from the Lab" are intended only for use with Analog Devices products and are the intellectual property of Analog Devices or its licensors. While you may
use the "Circuits from the Lab" in the design of your product, no other license is granted by implication or otherwise under any patents or other intellectual property by application or use of
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©2009 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
CN08396-0-7/09(0)
Rev. 0 | Page 3 of 3
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