CN-0147 [ADI]

Powering a Fractional-N Voltage Controlled Oscillator with Low Noise LDO Regulators for Reduced Phase Noise; 供电的小数N分频压控振荡器,低噪声LDO稳压器的精简相位噪声
CN-0147
型号: CN-0147
厂家: ADI    ADI
描述:

Powering a Fractional-N Voltage Controlled Oscillator with Low Noise LDO Regulators for Reduced Phase Noise
供电的小数N分频压控振荡器,低噪声LDO稳压器的精简相位噪声

振荡器 压控振荡器 稳压器
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Circuit Note  
CN-0147  
Devices Connected/Referenced  
Circuits from the Lab™ tested circuit designs address  
common design challenges and are engineered for  
quick and easy system integration. For more information  
and/or support, visit www.analog.com/CN0147.  
ADF4350  
ADP150  
Fractional-N PLL IC with Integrated VCO  
Low Noise 3.3 V LDO  
Powering a Fractional-N Voltage Controlled Oscillator (VCO) with Low Noise  
LDO Regulators for Reduced Phase Noise  
Wideband voltage controlled oscillators (VCOs) may have  
increased sensitivity to power supply noise, hence, ultralow  
noise regulators are recommended for best performance.  
EVALUATION AND DESIGN SUPPORT  
Circuit Evaluation Boards  
ADF4350 Evaluation Board (EVAL-ADF4350-EB1Z)  
Design and Integration Files  
The circuit shown in Figure 1 utilizes the ADF4350, a fully  
integrated fractional-N PLL and VCO that can generate  
frequencies from 137.5 MHz to 4400 MHz. The ADF4350 is  
powered from the ultralow noise 3.3 V ADP150 regulator for  
optimal LO phase noise performance.  
Schematics, Layout Files, Bill of Materials  
CIRCUIT FUNCTION AND BENEFITS  
This circuit uses low noise, low dropout (LDO) linear regulators  
to supply power to a wideband integrated PLL and VCO.  
LOCK  
DETECT  
VVCO  
VDD  
16  
17  
VVCO  
26  
30  
MUXOUT LD  
4
25  
28  
10  
6
32  
PDBRF  
SDVDD  
DVDD AVDD CE  
VP  
V
= 5.5V  
V
= 3.3V  
OUT  
IN  
OUT  
5
4
1
2
3
1nF 1nF  
VIN  
VOUT  
NC  
C
FREFIN  
REFIN  
IN  
RFOUTB+  
14  
15  
C
29  
51  
ADP150  
GND  
1µF  
1µF  
VVCO  
3.9nH  
RFOUTB–  
1
2
3
CLK  
DATA  
LE  
ON  
3.9nH  
EN  
1nF  
1nF  
OFF  
12  
13  
RFOUTA+  
RFOUTA–  
ADF4350  
NC = NO CONNECT  
22 RSET  
4.7kΩ  
V
= 5.5V  
V
= 3.3V  
OUT  
IN  
5
1
2
3
VIN  
VOUT  
VTUNE 20  
C
IN  
C
OUT  
ADP150  
GND  
680Ω  
1µF  
1µF  
CPOUT  
7
39nF  
ON  
4
NC  
EN  
2700pF  
1200pF  
SW  
VREF  
24  
5
OFF  
360Ω  
CPGND SDGND  
AGNDVCO DGND  
AGND  
9
TEMP VCOM  
19 23  
NC = NO CONNECT  
8
31  
11 18 21  
27  
10pF  
0.1µF 10pF  
10pF  
0.1µF  
0.1µF  
Figure 1. ADP150 Regulators Connected to ADF4350 (Simplified Schematic: All Connections and Decoupling Not Shown)  
Rev. C  
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CN-0147  
Circuit Note  
Table 1. ADF4350 VCO Pushing  
VCO Frequency (MHz) VTUNE (V)  
VCO Pushing (MHz/V)  
2200  
3300  
4400  
2.5  
2.5  
2.5  
0.73  
1.79  
5.99  
POWER SUPPLY  
SPECTRUM ANALYZER  
[R&S FSUP 26]  
5.5V  
RF OUT  
EVAL-ADF4350EB1Z  
REV B BOARD  
USB  
CABLE  
PC  
Figure 2. EVAL-ADF4350EB1Z Rev. B Evaluation Board  
Featuring ADP150 Low Noise Regulators  
Figure 3. ADF4350 Measurement Setup  
The lower integrated rms noise of the ADP150 LDO of only  
9 µV rms (10 Hz to 100 kHz) helps to minimize VCO phase  
noise and reduce the impact of VCO pushing (the VCO  
equivalent of power supply rejection).  
Experiments showed pushing to be at its maximum at  
4.4 GHz VCO output frequency, so the comparison of  
VCO performance with different regulators was made at this  
frequency. Rev. A evaluation boards of the ADF4350 used the  
ADP3334 LDO regulator. The integrated rms noise of this  
regulator is 27 µV (integrated from 10 Hz to 100 kHz). This  
compares to 9 µV for the ADP150, which is used on the  
EVAL-ADF4350EB1Z, Rev B. In order to measure the impact  
of the power supply noise, a narrow PLL loop bandwidth (10  
kHz) was used to facilitate greater examination of VCO phase  
noise. A diagram of this setup is shown in Figure 3. A more  
detailed examination of the output noise density with frequency  
is available from the data sheets of both the ADP3334 and  
ADP150.  
Figure 2 shows a photo of the evaluation board, which uses the  
ADP150 LDOs to power the ADF4350. The ADP150 represents  
the industrys lowest noise LDO in the smallest package at the  
lowest cost. It is available in a 4-ball, 0.8 mm × 0.8 mm, 0.4 mm  
pitch WLCSP or a convenient 5-lead TSOT package. Adding the  
ADP150s to the design, therefore, has minimal impact on  
system cost and board area while providing a significant  
improvement in phase noise.  
CIRCUIT DESCRIPTION  
The ADF4350 is a wideband PLL and VCO consisting of  
three separate multiband VCOs. Each VCO covers a range of  
approximately 700 MHz (with some overlap between VCOs).  
Lower frequencies are generated by output dividers.  
Figure 4 shows that the noise spectral density of the ADP3334  
regulator is 150 nV/√Hz at 100 kHz offset. The same plot for  
the ADP150 (Figure 5) shows 25 nV/√Hz.  
VCO pushing is measured by applying a steady dc tuning voltage  
to the ADF4350 VTUNE pin, varying the power supply voltage,  
and measuring the frequency change. The pushing figure (P)  
equals the frequency delta divided by the voltage delta, as shown  
in Table 1.  
The formula for calculating the degradation in phase noise due  
to the power supply noise is as follows:  
P × Sfm  
2 × fm  
L(LDO) = 20log  
In a PLL system, higher VCO pushing means that power supply  
noise will degrade the VCO phase noise. If VCO pushing is low,  
then power supply noise will not significantly degrade phase  
noise. However, for high VCO pushing, noisy power supplies  
will have a measurable impact on phase noise performance.  
Where L(LDO) is the noise contribution from the regulator to the  
VCO phase noise (in dBc/Hz), at an offset fm; P is the VCO  
pushing figure in Hz/V; Sfm is the noise spectral density at a  
given frequency offset in V/√Hz; and fm is the frequency offset  
at which the noise spectral density is measured in Hz.  
Rev. C | Page 2 of 4  
 
 
 
Circuit Note  
CN-0147  
100  
Table 2. Calculation and Measurement of VCO Noise  
ADP3334 ADP150  
V
= 2.2V  
OUT  
= 1mA  
I
L
10  
1
Noise contribution from regulator  
(nV/√Hz)  
Noise contribution from regulator  
(dBc/Hz)  
Total calculated noise at VCO output  
(dBc/Hz)  
Measured VCO noise at 100 kHz offset  
(dBc/Hz)  
C
C
= 10µF  
= 0  
L
150  
25  
C
C
= 10µF  
NR  
L
C
C
= 1µF  
L
= 10nF  
NR  
= 0  
NR  
−104  
−103  
−102.6  
−119.5  
−109.5  
−108.5  
0.1  
C
C
= 1µF  
L
= 10nF  
NR  
0.01  
0.001  
10  
100  
1k  
10k  
100k  
1M  
FREQUENCY (Hz)  
Figure 4. ADP3334 Output Noise Spectrum  
0.501  
0.451  
0.401  
0.351  
0.301  
0.251  
0.201  
0.151  
0.101  
0.051  
0.001  
V
V
V
= 1.8V  
OUT  
OUT  
OUT  
= 2.8V  
= 3.3V  
Figure 6. ADF4350 Phase Noise at 4.4 GHz with ADP3334 Regulators  
10  
100  
1k  
10k  
100k  
FREQUENCY (Hz)  
Figure 5. ADP150 output noise spectrum  
The noise contribution from the supply is then rss summed  
with the noise contribution of the VCO (itself measured with a  
very low noise supply) to give the total noise at the VCO output  
with a given regulator.  
These noise performances are rss summed together to give the  
expected VCO phase noise:  
2
L(TOTAL)  
=
L(VCO)2 + L(LDO)  
Or expressed in dB  
2
2
L(TOTAL) = 10log  
[
(
10LVCO / 20  
)
+
(
10LLDO / 20  
)
]
In this example, a 100 kHz noise spectral density offset is  
Figure 7. ADF4350 Phase Noise at 4.4 GHz with ADP150 Regulators  
chosen, a 6 MHz/V pushing figure is used, and −110 dBc/Hz is  
taken as the VCO noise with an ideal supply.  
The integrated phase noise improves from 1.95° to 1.4° rms  
also. The measured results correlate very closely with the  
calculations and clearly show the benefit of using the ADP150  
with the ADF4350.  
Using a dedicated signal source analyzer (like Rohde & Schwarz  
FSUP), the VCO phase noise is compared. At 100 kHz offset the  
ADP3334 delivers 102.6 dBc/Hz (Figure 6), and in the same  
configuration the ADP150 measures 108.5 dBc/Hz (Figure 7).  
A complete design support package for this circuit note can be  
found at http://www.analog.com/CN0147-DesignSupport.  
Rev. C | Page 3 of 4  
 
 
 
 
CN-0147  
Circuit Note  
COMMON VARIATIONS  
LEARN MORE  
Additional regulators can be added for greater isolation  
between power supplies, if desired. Also, one ADP150  
regulator can be used to power the entire ADF4350 part.  
However, care needs to be taken in this case to ensure the  
maximum rated current of the single ADP150 regulator is not  
exceeded. This is possible if the lowest output power setting  
on the ADF4350 is selected.  
CN0147 Design Support Package:  
http://www.analog.com/CN0147-DesignSupport  
ADIsimPLL Design Tool  
ADIsimPower Design Tool  
Basso, C., C. Fourtet, and P. Kadanka. “Get the Best from Your  
Low-Dropout Regulator.” EDN, 18 Feb. 1999.  
Data Sheets and Evaluation Boards  
ADF4350 Data Sheet  
CIRCUIT EVALUATION AND TEST  
This circuit note, CN-0147, uses the EVAL-ADF4350EB1Z  
board for evaluation of the described circuit, allowing for quick  
setup and evaluation. The EVAL-ADF4350EB1Z board uses the  
standard ADF4350 programming software, contained on the  
CD that accompanies the evaluation board.  
ADF4350 Evaluation Board  
ADP150 Data Sheet  
ADP3334 Data Sheet  
Equipment Needed  
REVISION HISTORY  
Windows® XP, Windows, Vista (32-bit), or Windows 7 (32-bit)  
PC with USB Port, the EVAL-ADF4350EB1Z, the ADF4350  
programming software, 5.5 V power supply, and a spectrum  
analyzer such as a Rhode and Schwartz FSUP26. See this circuit  
note CN-0147 and UG-109 user guide for evaluation board  
EVAL-ADF4350EB1Z and the ADF4350 data sheet.  
6/11—Rev. B to Rev. C  
Changes to Circuit Description.......................................................2  
11/10—Rev. A to Rev. B  
Added Evaluation and Design Support Section............................1  
Added Circuit Evaluation and Test Section...................................4  
Getting Started  
7/10—Rev. 0 to Rev. A  
This circuit note, CN-0147, contains a description of the circuit,  
the schematic, and a block diagram of the test setup. The ser  
guide, UG-109, details the installation and use of the EVAL-  
ADF4350 evaluation software. UG-109 also contains board  
setup instructions and the board schematic, layout, and bill of  
materials.  
Changes to Figure 1...........................................................................1  
Changes to Figure 3...........................................................................2  
4/10—Revision 0: Initial Version  
Functional Block Diagram  
This circuit note, CN-0147, contains the function block  
diagram of the described test setup in Figure 3.  
Setup and Test  
After setting up the equipment, standard RF test methods  
should be used to measure the spectral purity of the output  
signal.  
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the Circuits from the Lab circuits. Information furnished by Analog Devices is believed to be accurate and reliable. However, Circuits from the Lab circuits are supplied "as is" and without warranties  
of any kind, express, implied, or statutory including, but not limited to, any implied warranty of merchantability, noninfringement or fitness for a particular purpose and no responsibility is  
assumed by Analog Devices for their use, nor for any infringements of patents or other rights of third parties that may result from their use. Analog Devices reserves the right to change any  
Circuits from the Lab circuits at any time without notice but is under no obligation to do so.  
©2010–2011 Analog Devices, Inc. All rights reserved. Trademarks and  
registered trademarks are the property of their respective owners.  
CN08876-0-6/11(C)  
Rev. C | Page 4 of 4  

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