DAC08RC/883 [ADI]
8-Bit, High Speed, Multiplying D/A Converter (Universal Digital Logic Interface); 8位高速乘法D / A转换器（通用数字逻辑接口）
| 型号： | DAC08RC/883 |
| 厂家： | 
ADI |
| 描述： | 8-Bit, High Speed, Multiplying D/A Converter (Universal Digital Logic Interface) |
| 文件： | 总12页 (文件大小：262K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
a 8-Bit, High Speed, Multiplying D/A Converter
(Universal Digital Logic Interface)
DAC08
FEATURES
ence and full-scale currents eliminates the need for full-scale
trimming in most applications. Direct interface to all popular
logic families with full noise immunity is provided by the high
swing, adjustable threshold logic input.
Fast Settling Output Current: 85 ns
Full-Scale Current Prem atched to ؎1 LSB
Direct Interface to TTL, CMOS, ECL, HTL, PMOS
Nonlinearity to 0.1% Maxim um Over
Tem perature Range
High voltage compliance complementary current outputs are
provided, increasing versatility and enabling differential opera-
tion to effectively double the peak-to-peak output swing. In
many applications, the outputs can be directly converted to volt-
age without the need for an external op amp.
High Output Im pedance and Com pliance:
–10 V to +18 V
Com plem entary Current Outputs
Wide Range Multiplying Capability: 1 MHz Bandw idth
Low FS Current Drift: ؎10 ppm / ؇C
Wide Pow er Supply Range: ؎4.5 V to ؎18 V
Low Pow er Consum ption: 33 m W @ ؎5 V
Low Cost
All DAC08 series models guarantee full 8-bit monotonicity, and
nonlinearities as tight as ±0.1% over the entire operating tem-
perature range are available. Device performance is essentially
unchanged over the ±4.5 V to ±18 V power supply range, with
33 mW power consumption attainable at ±5 V supplies.
Available in Die Form
T he compact size and low power consumption make the
DAC08 attractive for portable and military/aerospace appli-
cations; devices processed to MIL-ST D-883, Level B are
available.
GENERAL D ESCRIP TIO N
T he DAC08 series of 8-bit monolithic digital-to-analog convert-
ers provide very high-speed performance coupled with low cost
and outstanding applications flexibility.
DAC08 applications include 8-bit, 1 µs A/D converters, servo
motor and pen drivers, waveform generators, audio encoders
and attenuators, analog meter drivers, programmable power
supplies, CRT display drivers, high-speed modems and other
applications where low cost, high speed and complete input/out-
put versatility are required.
Advanced circuit design achieves 85 ns settling times with very
low “glitch” energy and at low power consumption. Monotonic
multiplying performance is attained over a wide 20 to 1 refer-
ence current range. Matching to within 1 LSB between refer-
FUNCTIO NAL BLO CK D IAGRAM
REV. A
Inform ation furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assum ed by Analog Devices for its
use, nor for any infringem ents of patents or other rights of third parties
which m ay result from its use. No license is granted by im plication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norw ood, MA 02062-9106, U.S.A.
Tel: 617/ 329-4700
Fax: 617/ 326-8703
DAC08–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS(@ V = ؎15 V, IREF = 2.0 mA, –55؇C ≤ T ≤ +125؇C for DAC08/08A, 0؇C ≤ T ≤ +70؇C for
S
A
A
I
DAC08C, E & H unless otherwise noted. Output characteristics refer to both IOUT and OUT .)
D AC08A/H
Min Typ
D AC08E
Typ
D AC08C
Typ
P aram eter
Sym bol Conditions
Max
Min
Max
Min
Max
Units
Resolution
8
8
8
8
8
8
Bits
Bits
% FS
ns
Monotonicity
Nonlinearity
Settling T ime
NL
tS
±0.1
135
±0.19
150
±0.39
150
T o ±1/2 LSB,
85
85
85
All Bits Switched ON
or OFF, T A = 25°C1
Propagation Delay
Each Bit
tPLH
T A = 25°C1
35
60
35
60
35
60
ns
All Bits Switched
Full-Scale T empco1
tPHL
T CIFS
35
±10
60
±50
35
±10
60
±80
±50
35
±10
60
±80
ns
ppm/°C
DAC08E
Output Voltage
Compliance
(T rue Compliance)
VOC
Full-Scale Current
Change <1/2 LSB,
ROUT > 20 MΩ typ
VREF = 10.000 V
R14, R15 = 5.000 kΩ
T A = +25°C
–10
+18
–10
+18
–10
+18
V
Full Range Current
IFR4
1.984 1.992
2.000
1.94
1.99
2.04
1.94
1.99
2.04
mA
Full Range Symmetry
Zero-Scale Current
Output Current Range
IFRS
IZS
IOR1
IOR2
IFR4 – IFR2
±0.5
0.1
2.1
±4
1
±1
0.2
±8
2
±2
0.2
±16
4
µA
µA
mA
R14, R15 = 5.000 kΩ
VREF = +15.0 V,
V– = –10 V
VREF = +25.0 V,
V– = –12 V
2.1
4.2
2.1
4.2
4.2
mA
nA
Output Current Noise
Logic Input Levels
Logic “0”
Logic Input “1”
Logic Input Current
Logic “0”
Logic Input “1”
Logic Input Swing
Logic Threshold Range
Reference Bias Current
Reference Input
Slew Rate
IREF = 2 mA
25
25
25
VIL
VIL
VLC = 0 V
0.8
0.8
0.8
V
V
2
2
2
VLC = 0 V
IIL
IIH
VIS
VT HR
I15
VIN = –10 V to +0.8 V
VIN = 2.0 V to 18 V
V– = –15 V
VS = ±15 V1
–2
0.002
–10
–10
10
+18
+13.5
–3
–2
0.002
–10
10
+18
+13.5
–3
–2
0.002
–10
10
+18
+13.5
–3
µA
µA
V
V
µA
mA/µs
–10
–10
–10
–10
–10
–1
8
–1
8
–1
8
dI/dt
REQ = 200 Ω
RL = 100 Ω
CC = 0 pF
4
4
4
See Fast Pulsed Ref. Info Following.1
Power Supply Sensitivity PSSIFS+ V+ = 4.5 V to 18 V
PSSIFS– V– = –4.5 V to –18 V
IREF = 1.0 mA
±0.0003 ±0.01
±0.002 ±0.01
±0.0003 ±0.01
±0.002 ±0.01
±0.0003 ±0.01
±0.002 ±0.01
%∆IO/%∆V+
%∆IO/%∆V–
Power Supply Current
I+
I–
I+
I–
I+
I–
VS = ±5 V, IREF = 1.0 mA
2.3
–4.3
2.4
–6.4
2.5
–6.5
3.8
–5.8
3.8
–7.8
3.8
–7.8
2.3
–4.3
2.4
–6.4
2.5
–6.5
3.8
–5.8
3.8
–7.8
3.8
–7.8
2.3
–4.3
2.4
–6.4
2.5
–6.5
3.8
–5.8
3.8
–7.8
3.8
–7.8
mA
mA
mA
mA
mA
mA
VS = +5 V, –15 V,
IREF = 2.0 mA
VS = ±15 V, IREF
=
2.0 mA
Power Dissipation
Pd
±5 V, IREF = 1.0 mA
33
48
33
48
33
48
mW
+5 V, –15 V, IREF
2.0 mA
=
108
135
136
174
103
135
136
174
108
135
136
174
mW
mW
±15 V, IREF = 2.0 mA
NOT ES
1Guaranteed by design.
Specifications subject to change without notice.
–2–
REV. A
DAC08
(@ V = ؎15 V, and IREF = 2.0 mA, unless otherwise noted. Output
S
TYPICAL ELECTRICAL CHARACTERISTICS
I
characteristics apply to both IOUT and OUT .)
All Grades
Typical
P aram eter
Sym bol
dI/dt
Conditions
Units
Reference Input Slew Rate
Propagation Delay
Settling T ime
8
35
mA/µs
ns
t
PLH , tPHL
T A = 25°C, Any Bit
T o +1/2 LSB, All Bits
Switched ON or OFF,
T A = 25°C
tS
85
ns
NOT ES
For DAC08NT & GT 25°C characteristics, see DAC08N & G characteristics respectively.
Specifications subject to change without notice
ABSO LUTE MAXIMUM RATINGS1
P IN CO NNECTIO NS
Operating T emperature
16-P in D ual-In-Line P ackage
(Q Suffix)
DAC08AQ, Q . . . . . . . . . . . . . . . . . . . . . . –55°C to +125°C
DAC08HQ, EQ, CQ, HP, EP, CP, CS . . . . . 0°C to +70°C
Junction T emperature (TJ) . . . . . . . . . . . . . . –65°C to +150°C
Storage T emperature Q Package . . . . . . . . . . –65°C to +150°C
Storage T emperature P Package . . . . . . . . . . –65°C to +125°C
Lead T emperature (Soldering, 60 sec) . . . . . . . . . . . . . . 300°C
V+ Supply to V– Supply . . . . . . . . . . . . . . . . . . . . . . . . . . 36 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . V– to V– plus 36 V
VLC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V– to V+
Analog Current Outputs (at VS– = 15 V) . . . . . . . . . . 4.25 mA
Reference Input (V14 to V15) . . . . . . . . . . . . . . . . . . . V– to V+
Reference Input Differential Voltage
16-Lead SO
(S Suffix)
(V14 to V15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±18 V
Reference Input Current (I14
)
. . . . . . . . . . . . . . . . . . . 5.0 mA
2
P ackage Type
JA
JC
Units
16-Pin Hermetic DIP (Q)
16-Pin Plastic DIP (P)
20-Contact LCC (RC)
16-Pin SO (S)
100
82
76
16
39
36
35
°C/W
°C/W
°C/W
°C/W
111
NOT ES
1Absolute maximum ratings apply to both DICE and packaged parts, unless
otherwise noted.
2θJA is specified for worst case mounting conditions, i.e., θJA is specified for device
in socket for cerdip, P-DIP, and LCC packages; θJA is specified for device soldered
to printed circuit board for SO package.
D AC08RC/883 20-Lead LCC
(RC Suffix)
O RD ERING GUID E 1
16-P in D ual-In-Line P ackage
O perating
Tem perature
Range
NL
H erm etic
P lastic
LCC
0.1%
DAC08AQ2
DAC08HQ
MIL
COM
DAC08HP
0.19% DAC08Q2
DAC08EQ
DAC08RC/883
MIL
COM
DAC08EP
DAC08CP
DAC08CS3
0.39% DAC08CQ
COM
COM
NC = NO CONNECT
NOT ES
1Burn-in is available on commercial and industrial temperature range parts in
cerdip, plastic DIP, and T O-can packages.
2For devices processed in total compliance to MIL-ST D-883, add /883 after
part number. Consult factory for 883 data sheet.
3For availability and burn-in information on SO and PLCC packages, contact
your local sales office.
REV. A
–3–
DAC08
(@ V = ؎15 V, IREF = 2.0 mA, T = 125؇C for DAC08NT, DAC08GT devices; T = 25؇C for DAC08N,
S
A
A
WAFER TEST LIMITS
I
DAC08G and DAC08GR devices, unless otherwise noted. Output characteristics apply to both IOUT and OUT .)
D AC08NT
Lim it
D AC08N
Lim it
D AC08GT D AC08G D AC08GR
P aram eter
Sym bol
Conditions
Lim it
Lim it
Lim it
Units
Resolution
8
8
8
8
8
8
8
8
8
8
Bits min
Bits min
% FS max
V max
Monotonicity
Nonlinearity
Output Voltage
Compliance
NL
VOC
±0.1
+18
–10
2.04
1.94
±8
±0.1
+18
–10
2.04
1.94
±8
±0.19
+18
–10
2.04
1.94
±8
±0.19
+18
–10
2.04
1.94
±8
±0.39
+18
–10
2.04
1.94
±16
4
Full-Scale Current
Change < 1/2 LSB
VREF = 10.000 V
V min
Full-Scale Current
IFS4 or
IFS2
IFSS
mA max
mA min
µA max
µA max
R14, R15 = 5.000 kΩ
Full-Scale Symmetry
Zero-Scale Current
IZS
2
2
4
4
Output Current Range IFS1
V– = –10 V,
VREF = +15 V
V– = –12 V,
VREF = +25 V
R14, R15 = 5.000 kΩ
2.1
4.2
2.1
4.2
2.1
4.2
2.1
4.2
2.1
4.2
mA min
mA min
IFS2
Logic Input “0”
Logic Input “1”
Logic Input Current
Logic “0”
Logic “1”
Logic Input Swing
VIL
VIH
0.8
2
0.8
2
0.8
2
0.8
2
0.8
2
V max
V min
VLC = 0 V
IIL
IIH
VIS
VIN = –10 V to +0.8 V ±10
±10
±10
+18
–10
–3
±10
±10
+18
–10
–3
±10
±10
+18
–10
–3
±10
±10
+18
–10
–3
µA max
µA max
V max
V min
µA max
% FS/% V max
VIN = 2.0 V to 18 V
V– = –15 V
±10
+18
–10
–3
Reference Bias Current I15
Power Supply
Sensitivity
PSSIFS+
PSSIFS–
V+ = 4.5 V to 18 V
V– = –4.5 V to –18 V
IREF = 1.0 mA
VS = ±15 V
IREF ≤ 2.0 mA
VS = ±15 V
0.01
0.01
0.01
0.01
0.01
Power Supply Current I+
3.8
–7.8
174
3.8
–7.8
174
3.8
–7.8
174
3.8
–7.8
174
3.8
–7.8
174
mA max
µA max
mW max
Power Dissipation
Pd
IREF ≤ 2.0 mA
NOT E
Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed
for standard product dice. Consult factory to negotiate specifications based on dice lot qualification through sample lot assembly and testing.
D ICE CH ARACTERISTICS
(+125°C T ested D ice Available)
REV. A
–4–
DAC08
Figure 1. Pulsed Reference Operation
Figure 2. Burn-in Circuit
Figure 3. Fast Pulsed Reference
Operation
Figure 4. True and Com plim entary
Output Operation
Figure 5. LSB Switching
Figure 6. Full-Scale Settling Tim e
REV. A
–5–
–Typical Performance Characteristics
DAC08
Figure 8. LSB Propagation
Delay vs. IFS
Figure 9. Reference Input
Frequency Response
Figure 7. Full-Scale Current
vs. Reference Current
Figure 12. VTH–VLC vs. Tem perature
Figure 11. Logic Input Current vs.
Input Voltage
Figure 10. Reference Am p
Com m on-Mode Range
Figure 15. Bit Transfer Characteristics
Figure 14. Output Voltage
Com pliance vs. Tem perature
Figure 13. Output Current vs.
Output Voltage (Output
Voltage Com pliance)
REV. A
–6–
DAC08
Figure 16. Power Supply
Current vs. V+
Figure 17. Power Supply
Current vs. V–
Figure 18. Power Supply
Current vs. Tem perature
BASIC CO NNECTIO NS
Figure 19. Accom odating Bipolar References
Figure 20. Basic Positive Reference Operation
Figure 21. Basic Unipolar Negative Operation
REV. A
–7–
DAC08
Figure 22. Basic Bipolar Output Operation
Figure 24. Basic Negative Reference Operation
Figure 23. Recom m ended Full-Scale Adjustm ent Circuit
Figure 25. Offset Binary Operation
REV. A
–8–
DAC08
Figure 26. Positive Low Im pedance
Output Operation
Figure 27. Negative Low Im pedance
Output Operation
Figure 28. Interfacing With Various Logic Fam ilies
Bipolar references may be accommodated by offsetting VREF or
pin 15. T he negative common-mode range of the reference am-
plifier is given by: VCM– = V– plus (IREF × 1 kΩ) plus 2.5 V. T he
positive common-mode range is V+ less 1.5 V.
AP P LICATIO NS INFO RMATIO N
REFERENCE AMP LIFIER SET-UP
T he DAC08 is a multiplying D/A converter in which the output
current is the product of a digital number and the input refer-
ence current. T he reference current may be fixed or may vary
from nearly zero to +4.0 mA. T he full-scale output current is a
linear function of the reference current and is given by:
When a dc reference is used, a reference bypass capacitor is rec-
ommended. A 5.0 V T T L logic supply is not recommended as a
reference. If a regulated power supply is used as a reference, R14
should be split into two resistors with the junction bypassed to
ground with a 0.1 µF capacitor.
255
IFR
=
× IREF, where IREF = I14.
256
For most applications the tight relationship between IREF and
IFS will eliminate the need for trimming IREF. If required,
full-scale trimming may be accomplished by adjusting the value
of R14, or by using a potentiometer for R14. An improved
method of full-scale trimming which eliminates potentiometer
T .C. effects is shown in the recommended full-scale adjustment
circuit.
In positive reference applications, an external positive reference
voltage forces current through R14 into the VREF(+) terminal
(pin 14) of the reference amplifier. Alternatively, a negative ref-
erence may be applied to VREF(–) at pin 15; reference current
flows from ground through R14 into VREF(+) as in the positive
reference case. T his negative reference connection has the ad-
vantage of a very high impedance presented at pin 15. T he volt-
age at pin 14 is equal to and tracks the voltage at pin 15 due to
the high gain of the internal reference amplifier. R15 (nominally
equal to R14) is used to cancel bias current errors; R15 may be
eliminated with only a minor increase in error.
Using lower values of reference current reduces negative power
supply current and increases reference amplifier negative common-
mode range. T he recommended range for operation with a dc
reference current is +0.2 mA to +4.0 mA.
REV. A
–9–
DAC08
REFERENCE AMP LIFIER CO MP ENSATIO N FO R
MULTIP LYING AP P LICATIO NS
in a negative or inverted logic D/A converter. Both outputs may
be used simultaneously. If one of the outputs is not required it
must be connected to ground or to a point capable of sourcing
AC reference applications will require the reference amplifier to
be compensated using a capacitor from pin 16 to V–. T he value
of this capacitor depends on the impedance presented to pin 14:
for R14 values of 1.0, 2.5 and 5.0 kΩ, minimum values of CC
are 15, 37, and 75 pF. Larger values of R14 require proportion-
ately increased values of CC for proper phase margin, such that
the ratio of CC (pF) to R14 (kΩ) = 15.
I
FS; do not leave an unused output pin open.
Both outputs have an extremely wide voltage compliance en-
abling fast direct current-to-voltage conversion through a resis-
tor tied to ground or other voltage source. Positive compliance
is 36 V above V– and is independent of the positive supply.
Negative compliance is given by V– plus (IREF × 1 kΩ) plus 2.5 V.
For fastest response to a pulse, low values of R14 enabling small
CC values should be used. If pin 14 is driven by a high imped-
ance such as a transistor current source, none of the above val-
ues will suffice and the amplifier must be heavily compensated
which will decrease overall bandwidth and slew rate. For R14 =
1 kΩ and CC = 15 pF, the reference amplifier slews at 4 mA/µs
enabling a transition from IREF = 0 to IREF = 2 mA in 500 ns.
T he dual outputs enable double the usual peak-to-peak load
swing when driving loads in quasi-differential fashion. T his fea-
ture is especially useful in cable driving, CRT deflection and in
other balanced applications such as driving center-tapped coils
and transformers.
P O WER SUP P LIES
Operation with pulse inputs to the reference amplifier may be
accommodated by an alternate compensation scheme. T his
technique provides lowest full-scale transition times. An internal
clamp allows quick recovery of the reference amplifier from a
cutoff (IREF = 0) condition. Full-scale transition (0 mA to 2 mA)
occurs in 120 ns when the equivalent impedance at pin 14 is
200 Ω and CC = 0. T his yields a reference slew rate of 16 mA/µs
which is relatively independent of RIN and VIN values.
T he DAC08 operates over a wide range of power supply volt-
ages from a total supply of 9 V to 36 V. When operating at sup-
plies of ±5 V or less, IREF ≤ 1 mA is recommended. Low
reference current operation decreases power consumption and
increases negative compliance, reference amplifier negative
common-mode range, negative logic input range, and negative
logic threshold range; consult the various figures for guidance.
For example, operation at –4.5 V with IREF = 2 mA is not rec-
ommended because negative output compliance would be re-
duced to near zero. Operation from lower supplies is possible,
however at least 8 V total must be applied to insure turn-on of
the internal bias network.
LO GIC INP UTS
T he DAC08 design incorporates a unique logic input circuit
which enables direct interface to all popular logic families and
provides maximum noise immunity. T his feature is made pos-
sible by the large input swing capability, 2 µA logic input cur-
rent and completely adjustable logic threshold voltage. For V– =
–15 V, the logic inputs may swing between –10 V and +18 V.
T his enables direct interface with +15 V CMOS logic, even
when the DAC08 is powered from a +5 V supply. Minimum in-
put logic swing and minimum logic threshold voltage are given
by: V– plus ( IREF × 1 kΩ) plus 2.5 V. T he logic threshold may
be adjusted over a wide range by placing an appropriate voltage
at the logic threshold control pin (pin 1, VLC). T he appropriate
graph shows the relationship between VLC and VT H over the
temperature range, with VT H nominally 1.4 above VLC. For
T T L and DT L interface, simply ground pin 1. When interfacing
ECL, an IREF = 1 mA is recommended. For interfacing other
logic families, see preceding page. For general set-up of the logic
control circuit, it should be noted that pin 1 will source 100 µA
typical; external circuitry should be designed to accommodate
this current.
Symmetrical supplies are not required, as the DAC08 is quite
insensitive to variations in supply voltage. Battery operation is
feasible as no ground connection is required: however, an artifi-
cial ground may be used to insure logic swings, etc. remain be-
tween acceptable limits.
Power consumption may be calculated as follows:
Pd = (I+) (V+) + (I–) (V–). A useful feature of the DAC08 design
is that supply current is constant and independent of input logic
states; this is useful in cryptographic applications and further
serves to reduce the size of the power supply bypass capacitors.
TEMP ERATURE P ERFO RMANCE
T he nonlinearity and monotonicity specifications of the DAC08
are guaranteed to apply over the entire rated operating tempera-
ture range. Full-scale output current drift is low, typically
±10 ppm/°C, with zero-scale output current and drift essentially
negligible compared to 1/2 LSB.
Fastest settling times are obtained when pin 1 sees a low imped-
ance. If pin 1 is connected to a 1 kΩ divider, for example, it
should be bypassed to ground by a 0.01 µF capacitor.
T he temperature coefficient of the reference resistor R14 should
match and track that of the output resistor for minimum overall
full-scale drift. Settling times of the DAC08 decrease approxi-
mately 10% at –55°C; at +125°C an increase of about 15%
is typical.
ANALO G O UTP UT CURRENTS
Both true and complemented output sink currents are provided
T he reference amplifier must be compensated by using a capaci-
tor from pin 16 to V–. For fixed reference operation, a 0.01 µF
capacitor is recommended. For variable reference applications,
see previous section entitled “Reference Amplifier Compensa-
tion for Multiplying Applications”.
where IO
+
= IFS. Current appears at the “true” (IO) output
IO
when a “1” (logic high) is applied to each logic input. As the bi-
nary count increases, the sink current at pin 4 increases propor-
tionally, in the fashion of a “positive logic” D/A converter. When a
“0” is applied to any input bit, that current is turned off at pin 4
and turned on at pin 2. A decreasing logic count increases
as
IO
REV. A
–10–
DAC08
MULTIP LYING O P ERATIO N
Measurement of settling time requires the ability to accurately
resolve ±4 µA, therefore a 1 kΩ load is needed to provide ad-
equate drive for most oscilloscopes. T he settling time fixture
shown in schematic labelled “Settling T ime Measurement” uses
a cascode design to permit driving a 1 kΩ load with less than
5 pF of parasitic capacitance at the measurement node. At IREF
values of less than 1.0 mA, excessive RC damping of the output
is difficult to prevent while maintaining adequate sensitivity.
However, the major carry from 01111111 to 10000000 provides
an accurate indicator of settling time. T his code change does
not require the normal 6.2 time constants to settle to within
±0.2% of the final value, and thus settling times may be ob-
T he DAC08 provides excellent multiplying performance with an
extremely linear relationship between IFS and IREF over a range
of 4 mA to 4 mA. Monotonic operation is maintained over a
typical range of IREF from 100 µA to 4.0 mA.
SETTLING TIME
T he DAC08 is capable of extremely fast settling times, typically
85 ns at IREF = 2.0 mA. Judicious circuit design and careful
board layout must be employed to obtain full performance po-
tential during testing and application. T he logic switch design
enables propagation delays of only 35 ns for each of the 8 bits.
Settling time to within 1/2 LSB of the LSB is therefore 35 ns,
with each progressively larger bit taking successively longer. T he
MSB settles in 85 ns, thus determining the overall settling time
of 85 ns. Settling to 6-bit accuracy requires about 65 ns to 70 ns.
The output capacitance of the DAC08 including the package is
approximately 15 pF, therefore the output RC time constant
dominates settling time if RL > 500 Ω.
served at lower values of IREF
.
DAC08 switching transients or “glitches” are very low and may
be further reduced by small capacitive loads at the output at a
minor sacrifice in settling time.
Fastest operation can be obtained by using short leads, minimiz-
ing output capacitance and load resistor values, and by adequate
bypassing at the supply, reference and VLC terminals. Supplies
do not require large electrolytic bypass capacitors as the supply
current drain is independent of input logic states; 0.1 µF capaci-
tors at the supply pins provide full transient protection.
Settling time and propagation delay are relatively insensitive to
logic input amplitude and rise and fall times, due to the high
gain of the logic switches. Settling time also remains essentially
constant for IREF values. T he principal advantage of higher IREF
values lies in the ability to attain a given output level with lower
load resistors, thus reducing the output RC time constant.
Figure 30. Settling Tim e Measurem ent
REV. A
–11–
DAC08
O UTLINE D IMENSIO NS
D imensions shown in inches and (mm).
N-16
0.840 (21.33)
0.745 (18.93)
16
1
9
0.280 (7.11)
0.240 (6.10)
8
0.325 (8.25)
0.195 (4.95)
0.115 (2.93)
0.300 (7.62)
PIN 1
0.060 (1.52)
0.015 (0.38)
0.210 (5.33)
MAX
0.130
(3.30)
MIN
0.160 (4.06)
0.115 (2.93)
0.015 (0.381)
0.008 (0.204)
0.070 (1.77) SEATING
0.100
(2.54)
BSC
0.022 (0.558)
0.014 (0.356)
PLANE
0.045 (1.15)
Q -16
0.005 (0.13) MIN
16
0.080 (2.03) MAX
9
0.310 (7.87)
0.220 (5.59)
8
1
0.320 (8.13)
0.290 (7.37)
PIN 1
0.840 (21.34) MAX
0.060 (1.52)
0.015 (0.38)
0.200 (5.08)
MAX
0.150
(3.81)
MIN
0.200 (5.08)
0.125 (3.18)
0.015 (0.38)
0.008 (0.20)
SEATING
PLANE
0.023 (0.58)
0.014 (0.36)
0.100
(2.54)
BSC
0.070 (1.78)
15°
0°
0.030 (0.76)
SO -16
0.3937 (10.00)
0.3859 (9.80)
16
1
9
8
0.1574 (4.00)
0.1497 (5.80)
0.2550 (6.20)
0.2284 (5.80)
0.0688 (1.75)
0.0532 (1.35)
PIN 1
0.0196 (0.50)
x 45°
0.0098 (0.25)
0.0040 (0.10)
0.0099 (0.25)
8°
0°
0.0500
(1.27)
BSC
0.0192 (0.49)
0.0138 (0.35)
SEATING
PLANE
0.0500 (1.27)
0.0160 (0.41)
0.0099 (0.25)
0.0075 (0.19)
E-20
0.200 (5.08)
BSC
0.075
(1.91)
REF
0.100 (2.54)
0.064 (1.63)
0.358 (9.09)
0.100 (2.54) BSC
0.015 (0.38)
0.342 (8.69)
SQ
0.095 (2.41)
0.075 (1.90)
3
MIN
19
20
18
4
0.028 (0.71)
0.358
1
0.011 (0.28)
TOP
VIEW
0.022 (0.56)
(9.09)
MAX
SQ
BOTTOM
VIEW
0.007 (0.18)
R TYP
0.075 (1.91)
REF
0.050 (1.27)
BSC
14
13
8
9
45° TYP
0.055 (1.40)
0.045 (1.14)
0.088 (2.24)
0.054 (1.37)
0.150 (3.81)
BSC
REV. A
–12–
相关型号：
DAC08SAQ5/38510
IC PARALLEL, 8 BITS INPUT LOADING, 8-BIT DAC, CDIP16, 0.250 X 0.875 INCH, HERMETIC SEALED, CERAMIC, DIP-16, Digital to Analog Converter
ADI
DAC1000LCJ
PARALLEL, WORD INPUT LOADING, 0.5us SETTLING TIME, 10-BIT DAC, CDIP24, 0.600 INCH, CERAMIC, DIP-24
TI
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