DAC8043AFS [ADI]
12-Bit Serial Input Multiplying D/A Converter; 12位串行输入乘法D / A转换器
| 型号： | DAC8043AFS |
| 厂家： | 
ADI |
| 描述： | 12-Bit Serial Input Multiplying D/A Converter |
| 文件： | 总8页 (文件大小：139K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
12-Bit Serial Input
Multiplying D/A Converter
a
DAC8043A
FUNCTIONAL BLOCK DIAGRAM
FEATURES
Compact SO-8 and TSSOP Packages
True 12-Bit Accuracy
+5 V Operation @ <10 A
Fast 3-Wire Serial Input
Fast 1 s Settling Time
2.4 MHz 4-Quadrant Multiply BW
Pin-for-Pin Upgrade for DAC8043
Standard and Rotated Pinout
DAC8043A
V
R
I
DD
FB
V
DAC
REF
OUT
12
LD
DAC REG
12
APPLICATIONS
GND
CLK
SRI
12-BIT SHIFT
REGISTER
Ideal for PLC Applications in Industrial Control
Programmable Amplifiers and Attenuators
Digitally Controlled Calibration and Filters
Motion Control Systems
0.5
0.4
GENERAL DESCRIPTION
T
V
V
= +25؇C, +85؇C, –40؇C
A
The DAC8043A is an improved high accuracy 12-bit multiply-
ing digital-to-analog converter in space-saving 8-lead packages.
Featuring serial input, double buffering and excellent analog
performance, the DAC8043A is ideal for applications where PC
board space is at a premium. Improved linearity and gain error
performance permit reduced parts count through the elimina-
tion of trimming components. Separate input clock and load
DAC control lines allow full user control of data loading and
analog output.
= +5V
DD
= –10V
REF
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
The circuit consists of a 12-bit serial-in/parallel-out shift regis-
ter, a 12-bit DAC register, a 12-bit CMOS DAC and control
logic. Serial data is clocked into the input register on the rising
edge of the CLOCK pulse. When the new data word has been
clocked in, it is loaded into the DAC register with the LD input
pin. Data in the DAC register is converted to an output current
by the D/A converter.
0
512
1024
1536
2048
2560
3072
3584
4096
CODE
Figure 1. Integral Nonlinearity Error vs. Code
Consuming only 10 µA from a single +5 V power supply, the
DAC8043A is the ideal low power, small size, high performance
solution to many application problems.
The DAC8043A is specified over the extended industrial
(–40°C to +85°C) temperature range. DAC8043A is available
in plastic DIP, and the low profile 1.75 mm height SO-8 surface
mount packages. The DAC8043AFRU is available for ultra-
compact applications in a thin 1.1 mm TSSOP-8 package.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
World Wide Web Site: http://www.analog.com
© Analog Devices, Inc., 1999
DAC8043A–SPECIFICATIONS
(@ VDD = +5 V, VREF = +10 V, –40؇C < TA < +85؇C, unless otherwise noted.)
ELECTRICAL CHARACTERISTICS
Parameter
Symbol
Condition
E Grade F Grade Units
STATIC PERFORMANCE
Resolution
N
12
12
Bits
Relative Accuracy
Differential Nonlinearity
Gain Error1
INL
DNL
GFSE
±0.5
±0.5
±1.0
±2.0
±5
±1.0
±1.0
±2.0
±2.0
±5
LSB max
LSB max
LSB max
LSB max
ppm/°C max
nA max
All Grades Monotonic to 12 Bits
TA = +25°C, Data = FFFH
TA = –40°C, +85°C, Data = FFFH
IOUT Pin Measured
Gain Tempco2
Output Leakage Current
TCGFS
ILKG
Data = 000H, IOUT Pin Measured
±5
±5
TA = –40°C, +85°C, Data = 000H, IOUT Pin Measured ±25
±25
0.03
0.15
nA max
LSB max
LSB max
Zero-Scale Error3
IZSE
Data = 000H
0.03
0.15
TA = –40°C, +85°C, Data = 000H
REFERENCE INPUT
Input Resistance
RREF
CREF
Absolute Tempco < 50 ppm/°C
7/15
5
7/15
5
kΩ min/max
pF typ
Input Capacitance2
ANALOG OUTPUT
Output Capacitance2
COUT
Data = 000H
Data = FFFH
25
30
25
30
pF typ
pF typ
DIGITAL INPUTS
Digital Input Low
Digital Input High
Input Leakage Current
Input Capacitance2
VIL
VIH
IIL
0.8
2.4
0.8
2.4
V max
V min
VLOGIC = 0 V to +5 V
VLOGIC = 0 V
0.001/±1 0.001/±1 µA typ/max
10
CIL
10
pF max
INTERFACE TIMING2, 4
Data Setup
Data Hold
Clock Width High
Clock Width Low
Load Pulsewidth
LSB CLK to LD DAC
tDS
tDH
tCH
tCL
tLD
tASB
10
5
25
25
25
0
10
5
25
25
25
0
ns min
ns min
ns min
ns min
ns min
ns min
AC CHARACTERISTICS1, 2
Output Current Settling Time tS
To ±0.01% of Full Scale, Ext Op Amp OP42
Data = 000H to FFFH to 000H, VREF = 0 V
VREF = 20 V p-p, Data = 000H, f = 10 kHz
VREF = 6 V rms, Data = FFFH, f = 1 kHz
10 Hz to 100 kHz Between RFB and IOUT
1
20
1
–85
17
1
20
1
–85
17
2.4
µs max
nVs max
mV p-p
dB typ
nV/√Hz max
MHz typ
DAC Glitch
Q
Feedthrough (VOUT/VREF
)
FT
THD
en
Total Harmonic Distortion
Output Noise Density5
Multiplying Bandwidth
BW
–3 dB, VOUT/VREF, VREF = 100 mV rms, Data = FFFH 2.4
SUPPLY CHARACTERISTICS
Power Supply Range
Positive Supply Current
Power Dissipation
VDD RANGE
IDD
PDISS
4.5/5.5
10
50
4.5/5.5
10
50
V min/max
µA max
µW max
VLOGIC = 0 V or VDD
VLOGIC = 0 V or VDD
∆VDD = ±5%
Power Supply Sensitivity
PSS
0.002
0.002
%/% max
NOTES
1Using internal feedback resistor RFB, see Figure 19 test circuit with VREF = +10 V.
2These parameters are guaranteed by design and not subject to production testing.
3Calculated from worst case RREF: IZSE(LSB) = (RREF × ILKG × 4096)/VREF
.
4All input control signals are specified with tR = tF = 2 ns (10% to 90% of +5 V) and timed from a voltage level of 1.6 V.
5Calculation from en = √4KTRB where: K = Boltzmann Constant (J/°K), R = Resistance (Ω), T = Resistor Temperature (°K), B = 1 Hz Bandwidth.
Specifications subject to change without notice.
–2–
REV. 0
DAC8043A
PIN FUNCTION DESCRIPTIONS
ABSOLUTE MAXIMUM RATINGS*
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +8 V
#(*) Name Function
V
REF to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±18 V
RFB to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±18 V
Logic Inputs to GND . . . . . . . . . . . . . . –0.3 V, VDD + 0.3 V
VIOUT to GND . . . . . . . . . . . . . . . . . . . –0.3 V, VDD + 0.3 V
IOUT Short Circuit to GND . . . . . . . . . . . . . . . . . . . . . 50 mA
Package Power Dissipation . . . . . . . . . . . . . (TJ max – TA)/θJA
Thermal Resistance θJA
8-Lead Plastic DIP Package (N-8) . . . . . . . . . . . . 103°C/W
8-Lead SOIC Package (SO-8) . . . . . . . . . . . . . . . 158°C/W
TSSOP-8 Package (RU-8) . . . . . . . . . . . . . . . . . . 240°C/W
Maximum Junction Temperature (TJ max) . . . . . . . . +150°C
Operating Temperature Range . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . +300°C
1(7) VREF
DAC Reference Input Pin. Establishes DAC full-
scale voltage. Constant input resistance versus
code.
Internal Matching Feedback Resistor. Connect
to external op amp output.
2 (8) RFB
3 (1) IOUT
DAC Current Output, full-scale output 1 LSB
less than reference input voltage –VREF
.
4 (2) GND Analog and Digital Ground.
5 (3) LD
Load Strobe, Level-Sensitive Digital Input.
Transfers shift-register data to DAC register
while active low. See truth table for operation.
12-Bit Serial Register Input, data loads directly
into the shift register MSB first. Extra leading
bits are ignored.
6 (4) SRI
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
7 (5) CLK Clock Input, positive-edge clocks data into shift
register.
8 (6) VDD
Positive Power Supply Input. Specified range of
operation +5 V ± 10%.
*Note Pin numbers in parenthesis represent the rotated pinout of the
DAC8043A1ES and DAC8043A1FS models.
ORDERING GUIDE
INL
(LSB) Temp
Package
Description
Package
Option
DAC8043AE/F PIN CONFIGURATIONS
Model
DAC8043AEP
DAC8043AES
DAC8043A1ES ±0.5
DAC8043AFP
DAC8043AFS
DAC8043A1FS ±1.0
DAC8043AFRU ±1.0
±0.5
±0.5
–40/+85°C 8-Lead P-DIP N-8
1
8
7
6
5
V
V
DD
REF
–40/+85°C 8-Lead SOIC
–40/+85°C 8-Lead SOIC
SO-8
SO-8
2
3
4
CLK
SRI
LD
R
FB
TOP VIEW
(Not to Scale)
8
5
1
4
I
8
5
1
4
OUT
±1.0
±1.0
–40/+85°C 8-Lead P-DIP N-8
–40/+85°C 8-Lead SOIC SO-8
–40/+85°C 8-Lead SOIC* SO-8
–40/+85°C TSSOP-8 RU-8
GND
TSSOP-8
DAC8043A
FRU
PDIP-8
DAC8043A
EP/FP
SO-8
DAC8043A
ES/FS
NOTES
The DAC8043A contains 346 transistors. The die size measures 70.3 mil ×
57.1 mil, 4014 sq mil.
*The DAC8043A1ES and DAC8043A1FS have a rotated pinout.
TSSOP-8 Package Branding:
Line 1: yww (data code: year, work week).
Line 2: 8043A.
DAC8043A1E AND DAC8043A1F PIN CONFIGURATION
(Rotated Pinout)
1
2
3
4
8
7
6
5
I
R
V
OUT
FB
GND
LD
REF
DD
TOP VIEW
(Not to Scale)
V
SRI
CLK
SO-8
DAC8043A1ES
DAC8043A1FS
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the DAC8043A features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. 0
–3–
DAC8043A
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
SRI
CLK
tLD1
tASB
LD
DATA LOADED MSB(D11) FIRST
Dxx
DAC REGISTER LOAD
SRI
tDS
tDH
tCL
CLK
LD
tCH
tLD
tS
FS
؎1 LSB
ERROR BAND
V
OUT
ZS
Figure 2. Timing Diagram
Table I. Control-Logic Truth Table
CLK LD Serial Shift Register Function
DAC Register Function
u
L
L
H
L
u
Shift-Register-Data Advanced One Bit Latched
No Effect
No Effect
Updated with Current Shift Register Contents
Latched All Zeros
NOTES
u positive logic transition.
The DAC Register LD input is level-sensitive. Any time LD is logic-low data in the serial register will directly control the
switches in the R-2R DAC ladder.
Typical Performance Characteristics
35
30
25
20
15
10
5
50
SS = 200 UNITS
= –40؇C TO +85؇C
SS = 200 UNITS
= +25؇C
T
A
T
A
V
V
= +5V
DD
V
V
= +5V
DD
40
30
= +10V
REF
= +10V
REF
20
10
0
0
–1.0
0
1
2
–0.5
0.0
0.5
1.0
FULL SCALE TEMPCO – ppm/؇C
TOTAL UNADJUSTED ERROR – LSB
Figure 3. Total Unadjusted Error Histogram
Figure 4. Full-Scale Output Tempco Histogram
–4–
REV. 0
DAC8043A
0.5
0.4
0.3
0.2
0.1
0
100
80
⌬ V = +5V ؎10%
DD
T
V
= +25؇C
A
= +5V
DD
60
40
20
1k
10k
100k
1M
10M
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
LOGIC INPUT VOLTAGE – Volts
FREQUENCY – Hz
Figure 5. Supply Current vs. Logic Input Voltage
Figure 8. Power Supply Rejection vs. Frequency
10
0.5
0.4
0.3
V
V
= +5V
DD
V
V
= +5V
= 0V OR V
DD
LOGIC
= +10V
REF
DD
SUPERIMPOSED: T = –40؇C, +25؇C, +85؇C
A
1
0.2
0.1
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
0.01
0.001
–55
–35
–15
5
25
45
65
85
105
125
0
512
1024
1536
2048 2560
3072 3584
4096
TEMPERATURE – ؇C
CODE – Decimal
Figure 9. Linearity Error vs. Digital Code
Figure 6. Supply Current vs. Temperature
4
2
3500
3000
2500
2000
1500
1000
500
V
V
T
= +5V
DD
V
V
T
= +5V
DD
= +10V
= +25؇C
REF
= +10V
REF
A
= +25؇C
A
CODE = F55H
CODE = 800H
0
–2
–4
CODE = FFFH
0
1k
10k
100k
1M
10M
100M
–2000
–1000
0
1000
2000
FREQUENCY – Hz
OPAMP OFFSET V – V
OS
Figure 7. Supply Current vs. Clock Frequency
Figure 10. Linearity Error vs. External Op Amp VOS
REV. 0
–5–
DAC8043A
V
T
= +5V
= +25؇C
DD
0.5
A
V
V
f
= +5V
DD
= +10V
REF
= 2.5MHz
V
CLK
OUT
0.25
CODE: 7FF TO 800
(10mV/DIV)
H
H
0
LD
(5V/DIV)
–0.25
–0.5
20mV
0
5
10
TIME – 200ns/DIV
|
V
| – Volts
REF
Figure 11. Midscale Transition Performance
Figure 14. Linearity Error vs. Reference Voltage
1.2
SAMPLE SIZE = 50
5V
V
V
T
= +5V
1.0
DD
= +10V
REF
CLK
= +25؇C
A
(5V/DIV)
0.8
CODE = FFF
H
0.6
0.4
V
OUT
(5V/DIV)
CODE = 000
H
0.2
0
5V
0
100
200
300
400
500
600
TIME – 1s/DIV
HOURS OF OPERATION AT +150؇C
Figure 12. Large Signal Settling Time
Figure 15. Long-Term Drift Accelerated by Burn-In
0.032
0.018
0
–70
ALL BITS ON
(MSB) B
B
11
10
V
= 4V p-p
REF
12
24
36
48
60
72
84
96
108
OUTPUT OP AMP: OP42
B
9
8
7
6
5
4
–75
–80
B
B
B
B
0.010
B
B
B
B
3
2
1
0
0.0056
–85
–90
–95
(LSB) B
0.0032
0.0018
10
100
1k
FREQUENCY – Hz
10k
100k
100
1k
10k
100k
1M
10M
FREQUENCY – Hz
Figure 13. Reference Multiplying Bandwidth vs. Fre-
quency and Code
Figure 16. THD vs. Frequency
–6–
REV. 0
DAC8043A
PARAMETER DEFINITIONS
code. This constant current results in a constant input resis-
tance at VREF equal to R. The VREF input may be driven by any
reference voltage or current, ac or dc that is within the limits
stated in the Absolute Maximum Ratings.
INTEGRAL NONLINEARITY (INL)
This is the single most important DAC specification. ADI mea-
sures INL as the maximum deviation of the analog output (from
the ideal) from a straight line drawn between the end points. It
is expressed as a percent of full-scale range or in terms of LSBs.
Refer to Analog Devices Data Reference Manual for additional
digital-to-analog converter definitions.
10k⍀
20k⍀
S1
10k⍀
20k⍀
S2
10k⍀
20k⍀
S3
V
REF
20k⍀
20k⍀
S12
*
INTERFACE LOGIC INFORMATION
GND
The DAC8043A has been designed for ease of operation. The
timing diagram, Figure 2, illustrates the input register loading
sequence. Note that the most significant bit (MSB) is loaded
first. Once the 12-bit input register is full, the data is trans-
ferred to the DAC register by taking LD momentarily low.
I
OUT
10k⍀
R
FEEDBACK
*
BIT 1 (MSB)
BIT 2
DIGITAL INPUTS
BIT 3
BIT 12 (LSB)
(SWITCHES SHOWN FOR DIGITAL INPUTS "HIGH")
*THESE SWITCHES PERMANENTLY "ON"
DIGITAL SECTION
The DAC8043A’s digital inputs, SRI, LD, and CLK, are TTL
compatible. The input voltage levels affect the amount of cur-
rent drawn from the supply; peak supply current occurs as the
digital input (VIN) passes through the transition region. See the
Supply Current vs. Logic Input Voltage graph located in the
typical performance characteristics curves. Maintaining the
digital input voltage levels as close as possible to the supplies,
VDD and GND, minimizes supply current consumption. The
DAC8043A’s digital inputs have been designed with ESD resis-
tance incorporated through careful layout and the inclusion of
input protection circuitry. Figure 17 shows the input protection
diodes and series resistor; this input structure is duplicated on
each digital input. High voltage static charges applied to the
inputs are shunted to the supply and ground rails through for-
ward biased diodes. These protection diodes were designed to
clamp the inputs to well below dangerous levels during static
discharge conditions.
Figure 18. Simplified DAC Circuit
The twelve output current steering NMOS FET switches are in
series with each R-2R resistor.
To further ensure accuracy across the full temperature range,
permanently “ON” MOS switches were included in series with
the feedback resistor and the R-2R ladder’s terminating resistor.
Figure 18 shows the location of the series switches. During any
testing of the resistor ladder or RFEEDBACK (such as incoming
inspection), VDD must be present to turn “ON” these series
switches.
DYNAMIC PERFORMANCE
OUTPUT IMPEDANCE
The DAC8043A’s output resistance, as in the case of the output
capacitance, varies with the digital input code. This resistance,
looking back into the IOUT terminal, may be between 10 kΩ (the
feedback resistor alone when all digital inputs are LOW) and
7.5 kΩ (the feedback resistor in parallel with approximate 30 kΩ
of the R-2R ladder network resistance when any single bit logic
is HIGH). Static accuracy and dynamic performance will be
affected by these variations.
V
DD
5k⍀
LD, CLK, SRI
APPLICATIONS INFORMATION
GND
In most applications, linearity depends upon the potential of the
Figure 17. Digital Input Protection
GENERAL CIRCUIT INFORMATION
The DAC8043A is a 12-bit multiplying D/A converter with a
very low temperature coefficient. It contains an R-2R resistor
ladder network, data input and control logic, and two data
registers.
I
OUT and GND pins being at the same voltage potential. The
DAC is connected to an external precision op amp inverting
input. The external amplifiers noninverting input should be tied
directly to ground without the usual bias current compensating
resistor. (See Figures 19 and 20.) The selected amplifier should
have a low input bias current and low drift over temperature.
The amplifiers input offset voltage should be nulled to less than
200 microvolts (less than 10% of 1 LSB). All grounded pins
should tie to a single common ground point to avoid ground loops.
The VDD power supply should have a low noise level with ad-
equate bypassing. It is best to operate the DAC8043A from the
analog power supply and grounds.
The digital circuitry forms an interface in which serial data can
be loaded under microprocessor control into a 12-bit shift regis-
ter and then transferred, in parallel, to the 12-bit DAC register.
The analog portion of the DAC8043A contains an inverted
R-2R ladder network consisting of silicon-chrome, highly-stable
(+50 ppm/°C) thin-film resistors, and twelve pairs of NMOS
current-steering switches, see Figure 18. These switches steer
binarily weighted currents into either IOUT or GND; this yields a
constant current in each ladder leg, regardless of digital input
REV. 0
–7–
DAC8043A
UNIPOLAR 2-QUADRANT MULTIPLYING
The negative full-scale voltage will be VREF when the DAC is
loaded with all zeros. The positive full-scale output will be
–(VREF – 1 LSB) when the DAC is loaded with all ones. Thus
the digital coding is offset binary. The voltage output transfer
equation for various input data and reference (or signal) values
follows:
The most straightforward application of the DAC8043A is in
the 2-quadrant multiplying configuration shown in Figure 19. If
the reference input signal is replaced with a fixed dc voltage
reference, the DAC output will provide a proportional dc volt-
age output according to the transfer equation:
V
OUT = –D/4096 × VREF
where D is the decimal data loaded into the DAC register and
REF is the externally applied reference voltage source.
VOUT2 = (D/2048 – 1) × –VREF
where D is the decimal data loaded into the DAC register and
VREF is the externally applied reference voltage source.
V
Precision resistors will be necessary to avoid ratio errors. Other-
wise trimming will be required to achieve full accuracy specifica-
tions available from the DAC8043A device. See the various
Analog Devices Digital Potentiometer products for automated
trimming solutions (e.g., the AD5204 for low voltage applica-
tions or the AD7376 for high voltage applications).
V
DD
R
V
R
R
FB
REF
FB
10pF
2R
2R
V
؎10V
AC
P
I
OUT
GND
DIGITAL INPUTS OMITTED FOR CLARITY
OP77
V
OUT
V
20k⍀
20k⍀
DD
V
R
FB
R
REF
Figure 19. Unipolar (2-Quadrant) Operation
BIPOLAR 4-QUADRANT MULTIPLYING
R
2R
10pF
FB
2R
V
AC
10k⍀
؎10V
I
OUT
P
OP213
Figure 20 shows a suggested circuit to achieve 4-quadrant mul-
tiplying operation. The summing amplifier multiplies VOUT1 by
2, and offsets the output with the reference voltage so that a
midscale digital input code of 2048 places VOUT2 at zero volts.
V
OUT1
OP213
GND
DIGITAL INPUTS OMITTED FOR CLARITY
V
OUT2
(0V TO –V
)
REF
Figure 20. Bipolar (4-Quadrant) Operation
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
8-Lead Plastic DIP (N-8)
8-Lead SOIC (SO-8)
0.1968 (5.00)
0.1890 (4.80)
0.430 (10.92)
0.348 (8.84)
8
5
8
1
5
4
0.280 (7.11)
0.240 (6.10)
0.1574 (4.00)
0.1497 (3.80)
0.2440 (6.20)
0.2284 (5.80)
1
4
0.325 (8.25)
0.300 (7.62)
0.060 (1.52)
0.015 (0.38)
PIN 1
PIN 1
0.0688 (1.75)
0.0532 (1.35)
0.0196 (0.50)
0.0099 (0.25)
0.195 (4.95)
0.115 (2.93)
x 45°
0.210 (5.33)
MAX
0.0098 (0.25)
0.0040 (0.10)
0.130
(3.30)
MIN
0.160 (4.06)
0.115 (2.93)
0.015 (0.381)
0.008 (0.204)
8°
0°
SEATING
PLANE
0.100
(2.54)
BSC
0.0500
(1.27)
BSC
0.0192 (0.49)
0.0138 (0.35)
0.022 (0.558)
0.014 (0.356)
0.070 (1.77)
0.045 (1.15)
SEATING
PLANE
0.0098 (0.25)
0.0075 (0.19)
0.0500 (1.27)
0.0160 (0.41)
8-Lead TSSOP (RU-8)
0.122 (3.10)
0.114 (2.90)
8
5
4
1
PIN 1
0.0256 (0.65)
BSC
0.006 (0.15)
0.002 (0.05)
0.0433
(1.10)
MAX
0.028 (0.70)
0.020 (0.50)
8؇
0؇
0.0118 (0.30)
0.0075 (0.19)
SEATING
PLANE
0.0079 (0.20)
0.0035 (0.090)
–8–
REV. 0
相关型号：
DAC8043AFS-REEL7
SERIAL INPUT LOADING, 1 us SETTLING TIME, 12-BIT DAC, PDSO8, 1.75 MM HEIGHT, LOW PROFILE, SOIC-8
ROCHESTER
DAC8043AFSZ
SERIAL INPUT LOADING, 1 us SETTLING TIME, 12-BIT DAC, PDSO8, 1.75 MM HEIGHT, LOW PROFILE, SOIC-8
ROCHESTER
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