EV-ADF4360-9EB1Z [ADI]
Clock Generator PLL with Integrated VCO; 时钟发生器的PLL集成VCO
| 型号： | EV-ADF4360-9EB1Z |
| 厂家： | 
ADI |
| 描述： | Clock Generator PLL with Integrated VCO |
| 文件： | 总24页 (文件大小：1221K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Clock Generator PLL with Integrated VCO
Data Sheet
ADF4360-9
FEATURES
GENERAL DESCRIPTION
Primary output frequency range: 65 MHz to 400 MHz
Auxiliary divider from 2 to 31, output from 1.1 MHz to 200 MHz
3.0 V to 3.6 V power supply
1.8 V logic compatibility
Integer-N synthesizer
Programmable output power level
3-wire serial interface
Digital lock detect
The ADF4360-9 is an integrated integer-N synthesizer and
voltage-controlled oscillator (VCO). External inductors set the
ADF4360-9 center frequency. This allows a VCO frequency
range of between 65 MHz and 400 MHz.
An additional divider stage allows division of the VCO signal.
The CMOS level output is equivalent to the VCO signal divided
by the integer value between 2 and 31. This divided signal can
be further divided by 2, if desired.
Software power-down mode
Control of all the on-chip registers is through a simple 3-wire
interface. The device operates with a power supply ranging
from 3.0 V to 3.6 V and can be powered down when not in use.
APPLICATIONS
System clock generation
Test equipment
Wireless LANs
CATV equipment
FUNCTIONAL BLOCK DIAGRAM
AV
DV
R
SET
DD
DD
ADF4360-9
LD
CP
14-BIT R
COUNTER
REF
IN
LOCK
DETECT
MUTE
CLK
DATA
LE
24-BIT
FUNCTION
LATCH
24-BIT DATA
REGISTER
CHARGE
PUMP
PHASE
COMPARATOR
V
V
VCO
TUNE
L1
L2
C
C
C
N
RF
RF
A
B
OUT
OUT
VCO
CORE
OUTPUT
STAGE
13-BIT B
COUNTER
N = B
DIVIDE-BY-A
(2 TO 31)
DIVIDE-BY-2
CPGND
DIVOUT
MULTIPLEXER
AGND
DGND
Figure 1.
Rev. B
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ADF4360-9
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Input Shift Register .................................................................... 10
VCO ............................................................................................. 11
Output Stage................................................................................ 12
DIVOUT Stage............................................................................ 12
Latch Structure ........................................................................... 13
Power-Up..................................................................................... 17
Control Latch.............................................................................. 18
N Counter Latch......................................................................... 19
R Counter Latch ......................................................................... 19
Applications..................................................................................... 20
Choosing the Correct Inductance Value................................. 20
Encode Clock for ADC.............................................................. 20
GSM Test Clock.......................................................................... 21
Interfacing ................................................................................... 22
PCB Design Guidelines for Chip Scale Package .................... 22
Output Matching........................................................................ 23
Outline Dimensions....................................................................... 24
Ordering Guide .......................................................................... 24
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Characteristics ................................................................ 5
Absolute Maximum Ratings............................................................ 6
Transistor Count........................................................................... 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Descriptions............................. 7
Typical Performance Characteristics ............................................. 8
Circuit Description......................................................................... 10
Reference Input Section............................................................. 10
N Counter.................................................................................... 10
R Counter .................................................................................... 10
PFD and Charge Pump.............................................................. 10
Lock Detect ................................................................................. 10
REVISION HISTORY
2/12—Rev. A to Rev. B
Added EPAD Note............................................................................ 7
Updated Outline Dimensions....................................................... 24
Changes to Ordering Guide .......................................................... 24
3/08—Rev. 0 to Rev. A
Changes to Table 1 ........................................................................... 3
Changes to Figure 23...................................................................... 14
Changes to Output Matching Section.......................................... 23
1/08—Revision 0: Initial Version
Rev. B | Page 2 of 24
Data Sheet
ADF4360-9
SPECIFICATIONS
AVDD = DVDD = VVCO = 3.3 V 10%; AGND = DGND = 0 V; TA = TMIN to TMAX, unless otherwise noted.1
Table 1.
Parameter
B Version
Unit
Conditions/Comments
REFIN CHARACTERISTICS
REFIN Input Frequency
10/250
MHz min/MHz max
For f < 10 MHz, use a dc-coupled, CMOS-compatible
square wave, slew rate > 21 V/μs
REFIN Input Sensitivity
0.7/AVDD
0 to AVDD
5.0
V p-p min/V p-p max
V max
pF max
AC-coupled
CMOS-compatible
REFIN Input Capacitance
REFIN Input Current
PHASE DETECTOR
Phase Detector Frequency2
CHARGE PUMP
±±0
μA max
8
MHz max
ICP Sink/Source3
With RSET = 4.7 kΩ
High Value
Low Value
RSET Range
ICP Three-State Leakage Current
Sink and Source Current Matching
ICP vs. VCP
2.5
mA typ
mA typ
kΩ min/kΩ max
nA typ
% typ
% typ
0.312
2.7/10
0.2
2
1.5
1.25 V ≤ VCP ≤ 2.5 V
1.25 V ≤ VCP ≤ 2.5 V
VCP = 2.0 V
ICP vs. Temperature
LOGIC INPUTS
2
% typ
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINH/IINL
Input Capacitance, CIN
LOGIC OUTPUTS
Output High Voltage, VOH
Output High Current, IOH
Output Low Voltage, VOL
POWER SUPPLIES
AVDD
1.5
0.±
±1
3.0
V min
V max
μA max
pF max
DVDD − 0.4 V min
500
0.4
CMOS output chosen
IOL = 500 μA
μA max
V max
3.0/3.±
AVDD
AVDD
5
2.5
12.0
V min/V max
DVDD
VVCO
AIDD
4
mA typ
mA typ
mA typ
4
DIDD
4, 5
IVCO
ICORE = 5 mA
RF output stage is programmable
4
IRFOUT
3.5 to 11.0 mA typ
7
Low Power Sleep Mode4
RF OUTPUT CHARACTERISTICS5
μA typ
MHz
Maximum VCO Output Frequency
400
ICORE = 5 mA; depending on L1 and L2; see the
Choosing the Correct Inductance Value section
Minimum VCO Output Frequency
VCO Output Frequency
±5
90/108
MHz
MHz min/MHz max
L1, L2 = 270 nH; see the Choosing the Correct
Inductance Value section for other frequency values
VCO Frequency Range
VCO Sensitivity
1.2
2
Ratio
MHz/V typ
fMAX/fMIN
L1, L2 = 270 nH; see the Choosing the Correct
Inductance Value section for other sensitivity values
To within 10 Hz of final frequency
Lock Time±
400
μs typ
Rev. B | Page 3 of 24
ADF4360-9
Data Sheet
Parameter
B Version
0.24
10
−1±
−21
Unit
Conditions/Comments
Frequency Pushing (Open Loop)
Frequency Pulling (Open Loop)
Harmonic Content (Second)
Harmonic Content (Third)
Output Power5, 7
MHz/V typ
Hz typ
dBc typ
dBc typ
dBm typ
Into 2.00 VSWR load
−9/0
Using tuned load, programmable in 3 dB steps;
see Figure 35
Using 50 Ω resistors to VVCO, programmable in
3 dB steps; see Figure 33
Output Power5, 8
−14/−9
dBm typ
Output Power Variation
VCO Tuning Range
±3
1.25/2.5
dB typ
V min/V max
VCO NOISE CHARACTERISTICS
VCO Phase Noise Performance9,10
−91
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
@ 10 kHz offset from carrier
@ 100 kHz offset from carrier
@ 1 MHz offset from carrier
@ 3 MHz offset from carrier
@ 10 MHz offset from carrier
−117
−139
−140
−147
Normalized In-Band Phase Noise 10, 11
In-Band Phase Noise10, 11
RMS Integrated Jitter12
−218
−110
1.4
dBc/Hz typ
dBc/Hz typ
ps typ
@ 1 kHz offset from carrier
Measured at RFOUTA
Spurious Signals Due to PFD Frequency13
DIVOUT CHARACTERISTICS12
−75
dBc typ
Integrated Jitter Performance
(Integrated from 100 Hz to 1 GHz)
VCO frequency = 320 MHz to 380 MHz
DIVOUT = 180 MHz
DIVOUT = 95 MHz
DIVOUT = 80 MHz
DIVOUT = 52 MHz
1.4
1.4
1.4
1.4
ps rms
ps rms
ps rms
ps rms
A = 2, A output selected
A = 2, A/2 output selected
A = 2, A/2 output selected
A = 3, A/2 output selected (VCO = 312 MHz,
PFD = 1.± MHz)
DIVOUT = 45 MHz
DIVOUT = 10 MHz
1.4
1.±
ps rms
ps rms
A = 4, A/2 output selected
A = 18, A/2 output selected (VCO = 3±0 MHz,
PFD = 1.± MHz)
DIVOUT Duty Cycle
A Output
A/2 Output
1/A × 100
50
% typ
% typ
Divide-by-A selected
Divide-by-A/2 selected
1 Operating temperature range is −40°C to +85°C.
2 Guaranteed by design. Sample tested to ensure compliance.
3 ICP is internally modified to maintain constant loop gain over the frequency range.
4 TA = 25°C; AVDD = DVDD = VVCO = 3.3 V.
5 Unless otherwise stated, these characteristics are guaranteed for VCO core power = 5 mA. L1, L2 = 270 nH, 470 Ω resistors to GND in parallel with L1, L2.
± Jumping from 90 MHz to 108 MHz. PFD frequency = 200 kHz; loop bandwidth = 10 kHz.
7 For more detail on using tuned loads, see the Output Matching section.
8 Using 50 Ω resistors to VVCO into a 50 Ω load.
9 The noise of the VCO is measured in open-loop conditions. L1, L2 = 5± nH.
10 The phase noise is measured with the EV-ADF43±0-9EB1Z evaluation board and the Agilent E5052A signal source analyzer.
11
f
= 10 MHz; fPFD = 1 MHz; N = 3±0; loop B/W = 40 kHz. The normalized phase noise floor is estimated by measuring the in-band phase noise at the output of the
REFIN
VCO and subtracting 20logN (where N is the N divider value) and 10logfPFD. PNSYNTH = PNTOT − 10logfPFD − 20logN.
12 The jitter is measured with the EV-ADF43±0-9EB1Z evaluation board and the Agilent E5052A signal source analyzer. A low noise TCXO provides the REFIN for the
synthesizer, and the jitter is measured over the instrument’s jitter measurement bandwidth. fREFIN = 10 MHz; fPFD = 1 MHz; N = 3±0; loop BW = 40 kHz, unless otherwise
noted.
13 The spurious signals are measured with the EV-ADF43±0-9EB1Z evaluation board and the Agilent E5052A signal source analyzer. The spectrum analyzer provides
the REFIN for the synthesizer; fREFIN = 10 MHz @ 0 dBm. fREFIN = 10 MHz; fPFD = 1 MHz; N = 3±0; loop BW = 40 kHz.
Rev. B | Page 4 of 24
Data Sheet
ADF4360-9
TIMING CHARACTERISTICS1
AVDD = DVDD = VVCO = 3.3 V 10%; AGND = DGND = 0 V; 1.8 V and 3 V logic levels used; TA = TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter
Limit at TMIN to TMAX (B Version)
Unit
Test Conditions/Comments
LE setup time
DATA to CLK setup time
DATA to CLK hold time
CLK high duration
CLK low duration
t1
t2
t3
t4
t5
t±
t7
20
10
10
25
25
10
20
ns min
ns min
ns min
ns min
ns min
ns min
ns min
CLK to LE setup time
LE pulse width
1 Refer to the Power-Up section for the recommended power-up procedure for this device.
t4
t5
CLK
t2
t3
DB1
(CONTROL BIT C2)
DB0 (LSB)
(CONTROL BIT C1)
DB23 (MSB)
DB22
DB2
DATA
LE
t7
t1
t6
LE
Figure 2. Timing Diagram
Rev. B | Page 5 of 24
ADF4360-9
Data Sheet
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Table 3.
Parameter
AVDD to GND1
Rating
−0.3 V to +3.9 V
−0.3 V to +0.3 V
−0.3 V to +3.9 V
−0.3 V to +0.3 V
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
−40°C to + 85°C
−±5°C to +150°C
150°C
AVDD to DVDD
VVCO to GND
VVCO to AVDD
This device is a high performance RF integrated circuit with an
ESD rating of <1 kV, and it is ESD sensitive. Proper precautions
should be taken for handling and assembly.
Digital Input/Output Voltage to GND
Analog Input/Output Voltage to GND
REFIN to GND
Operating Temperature Range
Storage Temperature Range
Maximum Junction Temperature
LFCSP θJA Thermal Impedance
Paddle Soldered
Paddle Not Soldered
Lead Temperature, Soldering
Vapor Phase (±0 sec)
Infrared (15 sec)
TRANSISTOR COUNT
The transistor count is 12,543 (CMOS) and 700 (bipolar).
50°C/W
88°C/W
ESD CAUTION
215°C
220°C
1 GND = CPGND = AGND = DGND = 0 V.
Rev. B | Page ± of 24
Data Sheet
ADF4360-9
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PIN 1
INDICATOR
CPGND
AV
AGND
1
2
3
4
5
6
18 DATA
17 CLK
16 REF
DD
ADF4360-9
TOP VIEW
(Not to Scale)
IN
15 DGND
RF
A
B
OUT
RF
14 C
13 R
OUT
N
V
VCO
SET
NOTE
THE EXPOSED PADDLE MUST BE CONNECTED TO AGND.
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
Mnemonic Description
1
2
CPGND
AVDD
Charge Pump Ground. This is the ground return path for the charge pump.
Analog Power Supply. This ranges from 3.0 V to 3.± V. Decoupling capacitors to the analog ground plane
should be placed as close as possible to this pin. AVDD must have the same value as DVDD.
3, 8, 11, 22
4
AGND
Analog Ground. This is the ground return path of the prescaler and VCO.
VCO Output. The output level is programmable from 0 dBm to −9 dBm. See the Output Matching section for a
description of the various output stages.
VCO Complementary Output. The output level is programmable from 0 dBm to −9 dBm. See the Output
Matching section for a description of the various output stages.
Power Supply for the VCO. This ranges from 3.0 V to 3.± V. Decoupling capacitors to the analog ground plane
should be placed as close as possible to this pin. VVCO must have the same value as AVDD.
Control Input to the VCO. This voltage determines the output frequency and is derived from filtering the CP
output voltage.
An external inductor to AGND should be connected to this pin to set the ADF43±0-9 output frequency. L1 and
L2 need to be the same value. A 470 Ω resistor should be added in parallel to AGND.
RFOUT
RFOUT
VVCO
VTUNE
L1
A
5
B
±
7
9
10
L2
An external inductor to AGND should be connected to this pin to set the ADF43±0-9 output frequency. L1 and
L2 need to be the same value. A 470 Ω resistor should be added in parallel to AGND.
12
13
CC
RSET
Internal Compensation Node. This pin must be decoupled to ground with a 10 nF capacitor.
Connecting a resistor between this pin and CPGND sets the maximum charge pump output current for the
synthesizer. The nominal voltage potential at the RSET pin is 0.± V. The relationship between ICP and RSET is
ICPmax = 11.75/RSET
For example, RSET = 4.7 kΩ and ICPmax = 2.5 mA.
14
15
1±
CN
DGND
REFIN
Internal Compensation Node. This pin must be decoupled to VVCO with a 10 μF capacitor.
Digital Ground.
Reference Input. This is a CMOS input with a nominal threshold of VDD/2 and a dc equivalent input resistance of
100 kΩ (see Figure 1±). This input can be driven from a TTL or CMOS crystal oscillator, or it can be ac-coupled.
17
18
19
20
21
CLK
Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into the
24-bit shift register on the CLK rising edge. This input is a high impedance CMOS input.
Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits. This input is a
high impedance CMOS input.
Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of the
four latches, and the relevant latch is selected using the control bits.
This output allows the user to select VCO frequency divided by A or VCO frequency divided by 2A.
Alternatively, the scaled RF, or the scaled reference frequency, can be accessed externally through this output.
Digital Power Supply. This ranges from 3.0 V to 3.± V. Decoupling capacitors to the digital ground plane should
be placed as close as possible to this pin. DVDD must have the same value as AVDD.
DATA
LE
DIVOUT
DVDD
23
24
LD
CP
Lock Detect. The output on this pin is logic high to indicate that the part is in lock. Logic low indicates loss of lock.
Charge Pump Output. When enabled, this provides ±ICP to the external loop filter, which in turn drives the
internal VCO.
EP
Exposed Pad. The exposed pad must be connected to AGND.
Rev. B | Page 7 of 24
ADF4360-9
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
–20
–60
–70
–40
–80
–60
–90
–100
–110
–120
–130
–140
–150
–160
–80
–100
–120
–140
–160
1k
10k
100k
1M
10M
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 4. Open-Loop VCO Phase Noise at 218 MHz, L1, L2 = 56 nH
Figure 7. DIVOUT Phase Noise, 95 MHz, VCO = 380 MHz,
PFD Frequency = 1 MHz, Loop Bandwidth = 40 kHz, Jitter = 1.3 ps,
Divide-by-A/2 Selected, A = 2
–60
–70
–60
–70
–80
–80
–90
–90
–100
–110
–120
–130
–140
–150
–160
–100
–110
–120
–130
–140
–150
–160
100
1k
10k
100k
1k
10M
100
1k
10k
100k
1M
10M
FREQUENCY OFFSET (Hz)
FREQUENCY OFFSET (Hz)
Figure 5. VCO Phase Noise, 360 MHz, 1 MHz PFD, 40 kHz Loop Bandwidth,
RMS Jitter = 1.4 ps
Figure 8. DIVOUT Phase Noise, 80 MHz, VCO = 320 MHz,
PFD Frequency = 1 MHz, Loop Bandwidth = 40 kHz, Jitter = 1.3 ps,
Divide-by-A/2 Selected, A = 2
–60
–70
–60
–70
–80
–80
–90
–90
–100
–110
–120
–130
–140
–150
–160
–100
–110
–120
–130
–140
–150
–160
100
1k
10k
100k
1M
10M
100
1k
10k
100k
1M
FREQUENCY OFFSET (Hz)
FREQUENCY OFFSET (Hz)
Figure 6. DIVOUT Phase Noise, 180 MHz, VCO = 360 MHz,
Figure 9. DIVOUT Phase Noise, 52 MHz, VCO = 312 MHz,
PFD Frequency = 1 MHz, Loop Bandwidth = 40 kHz, Jitter = 1.3 ps,
Divide-by-A Selected, A = 2
PFD Frequency = 1.6 MHz, Loop Bandwidth = 40 kHz, Jitter = 1.4 ps,
Divide-by-A/2 Selected, A = 3
Rev. B | Page 8 of 24
Data Sheet
ADF4360-9
–60
–70
–80
–90
–100
–110
–120
–130
–140
–150
1
C1 FREQUENCY: 90MHz
C1 + DUTY: 28.98%
C1 PEAK TO PEAK: 1.55V
–160
100
CH1 500mV
M 2.00ns
A
CH1
20mV
1k
10k
100k
1M
10M
FREQUENCY OFFSET (Hz)
Figure 13. DIVOUT 90 MHz Waveform, VCO = 360 MHz, Divide-by-A Selected,
A = 4, Duty Cycle = ~25%
Figure 10. DIVOUT Phase Noise, 45 MHz, VCO = 360 MHz,
PFD Frequency = 1.6 MHz, Loop Bandwidth = 60 kHz, Jitter = 1.4 ps,
Divide-by-A/2 Selected, A = 2
–100
+25°C
–40°C
+85°C
–110
–120
1
–130
–140
–150
–160
C1 FREQUENCY: 36.01MHz
C1 + DUTY: 13.13%
C1 PEAK TO PEAK 1.28V
CH1 500mV
M 5.00ns
A
CH1
920mV
1k
10k
100k
1M
10M
FREQUENCY OFFSET (Hz)
Figure 11. DIVOUT Phase Noise over Temperature, 52 MHz, VCO = 312 MHz,
PFD Frequency = 1 MHz, Loop Bandwidth = 60 kHz,
Divide-by-A/2 Selected, A = 3
Figure 14. DIVOUT 36 MHz Waveform, VCO = 360 MHz, Divide-by-A Selected,
A = 10, Duty Cycle = ~10%
C1 FREQUENCY: 180MHz
C1 + DUTY: 45.32%
1
1
C1 FREQUENCY: 36MHz
C1 + DUTY: 49.41%
CH1 500mV
M 2.00ns
A
CH1
20mV
CH1 500mV
M 12.5ns
A
CH1
920mV
Figure 12. DIVOUT 180 MHz Waveform, VCO = 360 MHz,
Divide-by-A Selected, A = 2, Duty Cycle = ~50%
Figure 15. DIVOUT 36 MHz Waveform, VCO = 360 MHz,
Divide-by-A/2 Selected, A = 5, Duty Cycle = ~50%
Rev. B | Page 9 of 24
ADF4360-9
Data Sheet
CIRCUIT DESCRIPTION
V
P
CHARGE
PUMP
REFERENCE INPUT SECTION
The reference input stage is shown in Figure 16. SW1 and SW2
are normally closed switches, and SW3 is normally open. When
power-down is initiated, SW3 is closed, and SW1 and SW2 are
opened. This ensures that there is no loading of the REFIN pin at
power-down.
UP
HI
D1
Q1
U1
R DIVIDER
CLR1
POWER-DOWN
CONTROL
PROGRAMMABLE
DELAY
CP
U3
100kΩ
SW2
NC
ABP1
ABP2
TO R COUNTER
REF
IN
NC
SW1
BUFFER
CLR2
U2
DOWN
SW3
HI
D2
Q2
NO
Figure 16. Reference Input Stage
N DIVIDER
CPGND
N COUNTER
The CMOS N counter allows a wide division ratio in the PLL
feedback counter. The counters are specified to work when the
VCO output is 400 MHz or less. To avoid confusion, this is
referred to as the B counter. It makes it possible to generate
output frequencies that are spaced only by the reference
frequency divided by R. The VCO frequency equation is
R DIVIDER
N DIVIDER
CP OUTPUT
f
VCO = B × fREFIN/R
where:
VCO is the output frequency of the VCO.
B is the preset divide ratio of the binary 13-bit counter (3 to 8191).
REFIN is the external reference frequency oscillator.
Figure 17. PFD Simplified Schematic and Timing (In Lock)
LOCK DETECT
f
The LD pin outputs a lock detect signal. Digital lock detect is
active high. When lock detect precision (LDP) in the R counter
latch is set to 0, digital lock detect is set high when the phase error
on three consecutive phase detector cycles is <15 ns.
f
R COUNTER
The 14-bit R counter allows the input reference frequency
to be divided down to produce the reference clock to the phase
frequency detector (PFD). Division ratios from 1 to 16,383 are
allowed.
When LDP is set to 1, five consecutive cycles of <15 ns phase
error are required to set the lock detect. It stays set high until a
phase error of >25 ns is detected on any subsequent PD cycle.
INPUT SHIFT REGISTER
PFD AND CHARGE PUMP
The digital section of the ADF4360 family includes a 24-bit
input shift register, a 14-bit R counter, and an 18-bit N counter,
comprising a 5-bit A counter and a 13-bit B counter. Data is
clocked into the 24-bit shift register on each rising edge of CLK.
The data is clocked in MSB first. Data is transferred from the
shift register to one of four latches on the rising edge of LE. The
destination latch is determined by the state of the two control
bits (C2, C1) in the shift register. The two LSBs, DB1 and DB0,
are shown in Figure 2.
The PFD takes inputs from the R counter and N counter (N = B)
and produces an output proportional to the phase and frequency
difference between them. Figure 17 is a simplified schematic.
The PFD includes a programmable delay element that controls
the width of the antibacklash pulse. This pulse ensures that
there is no dead zone in the PFD transfer function and
minimizes phase noise and reference spurs. Two bits in the R
counter latch, ABP2 and ABP1, control the width of the pulse
(see Figure 25).
Rev. B | Page 10 of 24
Data Sheet
ADF4360-9
3.5
3.0
2.5
2.0
The truth table for these bits is shown in Table 5. Figure 22
shows a summary of how the latches are programmed. Note
that the test modes latch is used for factory testing and should
not be programmed by the user.
Table 5. C2 and C1 Truth Table
Control Bits
1.5
1.0
0.5
0
Data Latch
Control
R Counter
N Counter (B)
Test Modes
C2
0
0
1
1
C1
0
1
0
1
80
85
90
95
100
105
110
115
FREQUENCY (MHz)
VCO
Figure 18. VTUNE, ADF4360-9, L1 and L2 = 270 nH vs. Frequency
The VCO core in the ADF4360 family uses eight overlapping
bands, as shown in Figure 18, to allow a wide frequency range
to be covered without a large VCO sensitivity (KV) and resultant
poor phase noise and spurious performance.
The R counter output is used as the clock for the band select
logic and should not exceed 1 MHz. A programmable divider is
provided at the R counter input to allow division by 1, 2, 4, or 8
and is controlled by the BSC1 bit and the BSC2 bit in the R counter
latch. Where the required PFD frequency exceeds 1 MHz, the
divide ratio should be set to allow enough time for correct band
selection. For many applications, it is usually best to set this to 8.
The correct band is chosen automatically by the band select
logic at power-up or whenever the N counter latch is updated.
It is important that the correct write sequence be followed at
power-up. The correct write sequence is as follows:
After band selection, normal PLL action resumes. The value of
KV is determined by the value of the inductors used (see the
Choosing the Correct Inductance Value section). The ADF4360
family contains linearization circuitry to minimize any variation
of the product of ICP and KV.
1. R Counter Latch
2. Control Latch
3. N Counter Latch
During band selection, which takes five PFD cycles, the VCO
The operating current in the VCO core is programmable in four
steps: 2.5 mA, 5 mA, 7.5 mA, and 10 mA. This is controlled by
the PC1 bit and the PC2 bit in the control latch.
VTUNE is disconnected from the output of the loop filter and
connected to an internal reference voltage.
It is strongly recommended that only the 5 mA setting be used.
However, in applications requiring a low VCO frequency, the
high temperature coefficient of some inductors may lead to the
VCO tuning voltage varying as temperature changes. The 7.5 mA
VCO core power setting shows less tuning voltage variation over
temperature in these applications and can be used, provided that
240 Ω resistors are used in parallel with Pin 9 and Pin 10, instead of
the default 470 Ω.
Rev. B | Page 11 of 24
ADF4360-9
Data Sheet
DV
DD
OUTPUT STAGE
The RFOUTA and RFOUTB pins of the ADF4360 family are
connected to the collectors of an NPN differential pair driven
by buffered outputs of the VCO, as shown in Figure 19. To
allow the user to optimize the power dissipation vs. the output
power requirements, the tail current of the differential pair is
programmable via Bit PL1 and Bit PL2 in the control latch.
Four current levels can be set: 3.5 mA, 5 mA, 7.5 mA, and 11 mA.
These levels give output power levels of −9 dBm, −6 dBm,
−3 dBm, and 0 dBm, respectively, using the correct shunt inductor
to VDD and ac coupling into a 50 Ω load. Alternatively, both
outputs can be combined in a 1 + 1:1 transformer or a 180°
microstrip coupler (see the Output Matching section).
A COUNTER/2 OUTPUT
A COUNTER OUTPUT
R COUNTER OUTPUT
N COUNTER OUTPUT
DIVOUT
MUX
CONTROL
DGND
Figure 20. DIVOUT Circuit
The primary use of this pin is to derive the lower frequencies
from the VCO by programming various divider values to the
auxiliary A divider. Values ranging from 2 to 31 are possible.
The duty cycle of this output is 1/A times 100%, with the logic
high pulse width equal to the inverse of the VCO frequency.
That is,
Another feature of the ADF4360 family is that the supply
current to the RF output stage is shut down until the part
achieves lock, as measured by the digital lock detect circuitry.
This is enabled by the mute-till-lock detect (MTLD) bit in the
control latch.
Pulse Width [seconds] = 1/fVCO (Frequency [Hz])
RF
A
RF
B
OUT
OUT
See Figure 21 for a graphical description. By selecting the
divide-by-2 function, this divided down frequency can in turn
be divided by 2 again. This provides a 50% duty cycle in contrast to
the A counter output, which may be more suitable for some
applications (see Figure 21).
VCO
BUFFER
fVCO
fVCO/A (A = 4)
Figure 19. RF Output Stage
DIVOUT STAGE
The output multiplexer on the ADF4360 family allows the user
to access various internal points on the chip. The state of DIVOUT
is controlled by D3, D2, and D1 in the control latch. The full
truth table is shown in Figure 23. Figure 20 shows the DIVOUT
section in block diagram form.
fVCO/2A (A = 4)
Figure 21. DIVOUT Waveforms
Rev. B | Page 12 of 24
Data Sheet
ADF4360-9
LATCH STRUCTURE
Figure 22 shows the three on-chip latches for the ADF4360-9. The two LSBs decide which latch is programmed.
CONTROL LATCH
OUTPUT
POWER
LEVEL
CORE
POWER
LEVEL
CURRENT
SETTING 2
CURRENT
SETTING 1
DIVOUT
CONTROL
CONTROL
BITS
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8
RSV RSV PD2 PD1 CPI6 CPI5 CPI4 CPI3 CPI2 CPI1 PL2 PL1 MTLD CPG CP PDP
DB7
D3
DB6
D2
DB5
D1
DB4
CR
DB3
PC2
DB2
DB1
DB0
PC1 C2 (0) C1 (0)
N COUNTER LATCH
CONTROL
BITS
13-BIT B COUNTER
5-BIT DIVOUT
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8
RSV RSV CPG B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1
DB7
RSV
DB6
A5
DB5
DB4
A3
DB3
DB2
A1
DB1
DB0
A4
A2
C2 (1) C1 (0)
R COUNTER LATCH
BAND
SELECT
CLOCK
ANTI-
BACKLASH
PULSE WIDTH
CONTROL
BITS
14-BIT REFERENCE COUNTER
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8
RSV RSV BSC2 BSC1 TMB LDP ABP2 ABP1 R14 R13 R12 R11 R10 R9 R8 R7
DB7
R6
DB6
R5
DB5
R4
DB4
R3
DB3
R2
DB2
R1
DB1
DB0
C2 (0) C1 (1)
Figure 22. Latch Structure
Rev. B | Page 13 of 24
ADF4360-9
Data Sheet
OUTPUT
POWER
LEVEL
CORE
POWER
LEVEL
CURRENT
SETTING 2
CURRENT
SETTING 1
DIVOUT
CONTROL
CONTROL
BITS
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
RSV RSV PD2 PD1 CPI6 CPI5 CPI4 CPI3 CPI2 CPI1 PL2 PL1 MTLD CPG CP PDP D3 D2 D1 CR PC2 PC1 C2 (0) C1 (0)
PC2
CORE POWER LEVEL
2.5mA
5mA (RECOMMENDED)
7.5mA
10mA
PC1
0
0
1
1
0
1
0
1
I
(mA)
PHASE DETECTOR
POLARITY
NEGATIVE
POSITIVE
CPI6
CPI3
CPI5
CPI2
CPI4
CPI1
CP
PDP
0
1
4.7kΩ
0.31
0.62
0.93
1.25
1.56
1.87
2.18
2.50
COUNTER
CR OPERATION
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
NORMAL
R, A, B COUNTERS
HELD IN RESET
CHARGE PUMP
OUTPUT
NORMAL
THREE-STATE
CP
0
1
CP GAIN
CPG
0
1
CURRENT SETTING 1
CURRENT SETTING 2
MUTE-TIL-LOCK DETECT
DISABLED
MTLD
0
1
ENABLED
D3
0
0
D2
0
0
D1
0
1
PL2
PL1
OUTPUT POWER LEVEL
CURRENT USING TUNED LOAD USING 50Ω TO V
MUXOUT
DV
DD
VCO
DIGITAL LOCK DETECT
(ACTIVE HIGH)
N DIVIDER OUTPUT
0
0
1
1
0
1
0
1
3.5mA
5.0mA
7.5mA
11.0mA
–9dBm
–6dBm
–3dBm
0dBm
–19dBm
–15dBm
–12dBm
–9dBm
0
0
1
1
0
1
DV
DD
R DIVIDER OUTPUT
A CNTR/2 OUT
A CNTR OUT
DGND
1
1
1
1
0
0
1
1
0
1
0
1
CE PIN
PD2
PD1 MODE
0
1
1
1
X
X
0
1
X
0
1
1
ASYNCHRONOUS POWER-DOWN
NORMAL OPERATION
ASYNCHRONOUS POWER-DOWN
SYNCHRONOUS POWER-DOWN
THESE BITS ARE
NOT USED BY THE
DEVICE AND ARE
DON'T CARE BITS.
Figure 23. Control Latch
Rev. B | Page 14 of 24
Data Sheet
ADF4360-9
CONTROL
BITS
RESERVED
13-BIT B COUNTER
5-BIT DIVOUT
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
RSV RSV CPG B13 B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
RSV
A5
A4
A3
A2
A1 C2 (1) C1 (0)
THIS BIT IS NOT
USED BY THE
DEVICE AND IS A
DON'T CARE BIT.
A5
0
0
0
0
.
.
.
1
1
1
1
A4
A2
0
0
1
1
.
.
.
0
0
1
1
A1
OUTPUT DIVIDE RATIO
NOT ALLOWED
NOT ALLOWED
2
3
.
.
.
28
29
30
31
0
0
0
0
.
.
.
1
1
1
1
............
............
............
............
............
............
............
............
............
............
............
0
1
0
1
.
.
.
0
1
0
1
B13 B12 B11
B3
B2
0
0
1
1
.
.
.
0
0
1
1
B1
0
1
0
1
.
.
.
0
1
0
1
B COUNTER DIVIDE RATIO
NOT ALLOWED
NOT ALLOWED
NOT ALLOWED
3
.
.
.
8188
8189
8190
8191
0
0
0
0
.
0
0
0
0
.
0
0
0
0
.
............
............
............
............
............
............
............
............
............
............
............
0
0
0
1
.
.
.
1
1
1
1
.
.
.
.
.
.
1
1
1
1
1
1
1
1
1
1
1
1
CP GAIN OPERATION
0
1
CHARGE PUMP CURRENT SETTING 1
IS PERMANENTLY USED
CHARGE PUMP CURRENT SETTING 2
IS PERMANENTLY USED
THESE BITS ARE
NOT USED BY THE
DEVICE AND ARE
DON'T CARE BITS.
Figure 24. N Counter Latch
Rev. B | Page 15 of 24
ADF4360-9
Data Sheet
ANTI-
BACKLASH
PULSE
BAND
SELECT
CLOCK
CONTROL
BITS
14-BIT REFERENCE COUNTER
WIDTH
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
RSV RSV BSC2 BSC1 TMB LDP ABP2 ABP1 R14
R13
R12
R11
R10
R9
R8
R7
R6
R5
R4
R3
R2
R1 C2 (0) C1 (1)
R14
R13
R12
R3
0
0
0
1
.
.
.
1
1
1
1
R2
R1
1
0
1
0
.
.
.
0
1
0
1
DIVIDE RATIO
1
2
3
4
.
.
.
16380
16381
16382
16383
0
0
0
0
.
.
.
1
1
1
1
0
0
0
0
.
.
.
1
1
1
1
0
0
0
0
.
.
.
1
1
1
1
..........
..........
..........
..........
..........
..........
..........
..........
..........
..........
..........
0
1
1
0
.
.
.
0
0
1
1
TEST MODE
BIT SHOULD
BE SET TO 0
FOR NORMAL
OPERATION.
THESE BITS ARE
NOT USED BY
THE DEVICE
AND ARE DON'T
CARE BITS.
ABP2
ABP1
ANTIBACKLASH PULSE WIDTH
0
0
1
1
0
1
0
1
3.0ns
1.3ns
6.0ns
3.0ns
LDP
0
LOCK DETECT PRECISION
THREE CONSECUTIVE CYCLES OF PHASE DELAY LESS THAN
15ns MUST OCCUR BEFORE LOCK DETECT IS SET.
1
FIVE CONSECUTIVE CYCLES OF PHASE DELAY LESS THAN
15ns MUST OCCUR BEFORE LOCK DETECT IS SET.
BSC2
BSC1
BAND SELECT CLOCK DIVIDER
0
0
1
1
0
1
0
1
1
2
4
8
Figure 25. R Counter Latch
Rev. B | Page 1± of 24
Data Sheet
ADF4360-9
During initial power-up, a write to the control latch powers up
the part, and the bias currents of the VCO begin to settle. If
these currents have not settled to within 10% of their steady-
state value, and if the N counter latch is then programmed, the
VCO may not oscillate at the desired frequency, which does not
allow the band select logic to choose the correct frequency
band, and the ADF4360-9 may not achieve lock. If the
recommended interval is inserted, and the N counter latch is
programmed, the band select logic can choose the correct
frequency band, and the part locks to the correct frequency.
POWER-UP
Power-Up Sequence
The correct programming sequence for the ADF4360-9 after
power-up is as follows:
1. R Counter Latch
2. Control Latch
3. N Counter Latch
Initial Power-Up
Initial power-up refers to programming the part after the
application of voltage to the AVDD, DVDD, and VVCO pins. On
initial power-up, an interval is required between programming
the control latch and programming the N counter latch. This
interval is necessary to allow the transient behavior of the
ADF4360-9 during initial power-up to settle.
The duration of this interval is affected by the value of the
capacitor on the CN pin (Pin 14). This capacitor is used to
reduce the close-in noise of the ADF4360-9 VCO. The
recommended value of this capacitor is 10 μF. Using this
value requires an interval of ≥15 ms between the latching in
of the control latch bits and latching in of the N counter latch
bits. If a shorter delay is required, the capacitor can be reduced.
A slight phase noise penalty is incurred by this change, which is
further explained in Table 6.
Table 6. CN Capacitance vs. Interval and Phase Noise
Open-Loop Phase Noise @ 10 kHz Offset
Recommended Interval Between
CN Value
10 μF
440 nF
Control Latch and N Counter Latch
L1 and L2 = 18.0 nH
−100 dBc/Hz
−99 dBc/Hz
L1 and L2 = 110.0 nH
−97 dBc/Hz
−9± dBc/Hz
L1 and L2 = 560.0 nH
−99 dBc/Hz
−98 dBc/Hz
≥15 ms
≥±00 μs
POWER-UP
CLK
R COUNTER
DATA
CONTROL
LATCH DATA
N COUNTER
LATCH DATA
LATCH DATA
LE
REQUIRED INTERVAL
CONTROL LATCH WRITE TO
N COUNTER LATCH WRITE
Figure 26. Power-Up Timing
Rev. B | Page 17 of 24
ADF4360-9
Data Sheet
Software Power-Up/Power-Down
Charge Pump Currents
If the part is powered down via the software (using the control
latch) and powered up again without any change to the N counter
latch during power-down, the part locks at the correct frequency
because the part is already in the correct frequency band. The
lock time depends on the value of capacitance on the CN pin,
which is <15 ms for 10 μF capacitance. The smaller capacitance
of 440 nF on this pin enables lock times of <600 μs.
CPI3, CPI2, and CPI1 in the ADF4360 family determine
Current Setting 1. CPI6, CPI5, and CPI4 determine Current
Setting 2 (see the truth table in Figure 23).
Output Power Level
Bit PL1 and Bit PL2 set the output power level of the VCO (see
the truth table in Figure 23).
Mute-Till-Lock Detect
The N counter value cannot be changed while the part is in
power-down because the part may not lock to the correct
frequency on power-up. If it is updated, the correct program-
ming sequence for the part after power-up is to the R counter
latch, followed by the control latch, and finally the N counter
latch, with the required interval between the control latch and
N counter latch, as described in the Initial Power-Up section.
DB11 of the control latch in the ADF4360 family is the mute-
till-lock detect bit. This function, when enabled, ensures that
the RF outputs are not switched on until the PLL is locked.
CP Gain
DB10 of the control latch in the ADF4360 family is the charge
pump gain bit. When it is programmed to 1, Current Setting 2
is used. When programmed to 0, Current Setting 1 is used.
CONTROL LATCH
With (C2, C1) = (0, 0), the control latch is programmed. Figure 23
shows the input data format for programming the control latch.
Charge Pump Three-State
This bit (DB9) puts the charge pump into three-state mode
when programmed to a 1. For normal operation, it should be
set to 0.
Power-Down
DB21 (PD2) and DB20 (PD1) provide programmable power-
down modes.
Phase Detector Polarity
In the programmed asynchronous power-down, the device
powers down immediately after latching a 1 into Bit PD1, with
the condition that PD2 is loaded with a 0. In the programmed
synchronous power-down, the device power-down is gated by
the charge pump to prevent unwanted frequency jumps. Once
the power-down is enabled by writing a 1 into Bit PD1 (on the
condition that a 1 is also loaded in PD2), the device goes into
power-down on the second rising edge of the R counter output,
after LE goes high. When a power-down is activated (either
synchronous or asynchronous mode), the following events occur:
The PDP bit in the ADF4360 family sets the phase detector
polarity. The positive setting enabled by programming a 1 is
used when using the on-chip VCO with a passive loop filter or
with an active noninverting filter. It can also be set to 0, which
is required if an active inverting loop filter is used.
DIVOUT Control
The on-chip multiplexer is controlled by D3, D2, and D1 (see
the truth table in Figure 23).
Counter Reset
DB4 is the counter reset bit for the ADF4360 family. When this
is 1, the R counter and the A, B counters are reset. For normal
operation, this bit should be 0.
•
•
All active dc current paths are removed.
The R, N, and timeout counters are forced to their load
state conditions.
Core Power Level
•
•
•
•
•
The charge pump is forced into three-state mode.
The digital lock detect circuitry is reset.
PC1 and PC2 set the power level in the VCO core. The
recommended setting is 5 mA. The 7.5 mA setting is
permissible in some applications (see the truth table in Figure 23).
The RF outputs are debiased to a high impedance state.
The reference input buffer circuitry is disabled.
The input register remains active and capable of loading
and latching data.
Rev. B | Page 18 of 24
Data Sheet
ADF4360-9
N COUNTER LATCH
R COUNTER LATCH
Figure 24 shows the input data format for programming the
N counter latch.
With (C2, C1) = (0, 1), the R counter latch is programmed.
Figure 25 shows the input data format for programming the
R counter latch.
5-Bit Divider
R Counter
A5 to A1 program the output divider. The divide range is 2 (00010)
to 31 (11111). If unused, this divider should be set to 0. The output
or the output divided by 2 is available at the DIVOUT pin.
R1 to R14 set the counter divide ratio. The divide range is
1 (00 … 001) to 16,383 (111 … 111).
Reserved Bits
Antibacklash Pulse Width
DB23, DB22, and DB7 are spare bits and are designated as
reserved. They should be programmed to 0.
DB16 and DB17 set the antibacklash pulse width.
Lock Detect Precision
B Counter Latch
DB18 is the lock detect precision bit. This bit sets the number of
reference cycles with <15 ns phase error for entering the locked
state. With LDP at 1, five cycles are taken; with LDP at 0, three
cycles are taken.
B13 to B1 program the B counter. The divide range is 3
(00 … 0011) to 8191 (11 … 111).
Overall Divide Range
Test Mode Bit
The overall VCO feedback divide range is defined by B.
DB19 is the test mode bit (TMB) and should be set to 0. With
TMB = 0, the contents of the test mode latch are ignored and
normal operation occurs, as determined by the contents of the
control latch, R counter latch, and N counter latch. Note that
test modes are for factory testing only and should not be
programmed by the user.
CP Gain
DB21 of the N counter latch in the ADF4360 family is the
charge pump gain bit. When it is programmed to 1, Current
Setting 2 is used. When programmed to 0, Current Setting 1 is
used. This bit can also be programmed through DB10 of the
control latch. The bit always reflects the latest value written to it,
whether this is through the control latch or the N counter latch.
Band Select Clock
These bits (DB20 and DB21) set a divider for the band select
logic clock input. The output of the R counter is, by default, the
value used to clock the band select logic; if this value is too high
(>1 MHz), a divider can be switched on to divide the R counter
output to a smaller value (see Figure 25). A value of 8 is
recommended.
Reserved Bits
DB23 to DB22 are spare bits that are designated as reserved.
They should be programmed to 0.
Rev. B | Page 19 of 24
ADF4360-9
Data Sheet
APPLICATIONS
12
10
8
CHOOSING THE CORRECT INDUCTANCE VALUE
The ADF4360-9 can be used at many different frequencies
simply by choosing the external inductors to give the correct
output frequency. Figure 27 shows a graph of both minimum
and maximum frequency vs. the external inductor value. The
correct inductor should cover the maximum and minimum
frequencies desired. The inductors used are 0603 CS or 0805 CS
type from Coilcraft. To reduce mutual coupling, the inductors
should be placed at right angles to one another.
6
4
2
0
The lowest center frequency of oscillation possible is approximately
65 MHz, which is achieved using 560 nH inductors. This
relationship can be expressed by
0
100
200
300
400
500
600
INDUCTANCE (nH)
1
fO
=
Figure 28. Tuning Sensitivity vs. Inductance
2π 9.3 pF
(
0.9 nH + LEXT
)
ENCODE CLOCK FOR ADC
where:
fO is the center frequency.
Analog-to-digital converters (ADCs) require a sampling clock
for their operation. Generally, this is provided by TCXO or VCXOs,
which can be large and expensive. The frequency range is usually
quite limited. An alternative solution is the ADF4360-9, which can
be used to generate a CMOS clock signal suitable for use in all
but the most demanding converter applications.
LEXT is the external inductance.
450
400
350
300
250
Figure 29 shows an ADF4360-9 with a VCO frequency of
320 MHz and a DIVOUT frequency of 80 MHz. Because a 50%
duty cycle is preferred by most sampling clock circuitry, the A/2
mode is selected. Therefore, A is programmed to 2, giving an
overall divide value of 4. The AD9215-80 is a 10-bit, 80 MSPS
ADC that requires an encode clock jitter of 6 ps or less. The
ADF4360-9 takes a 10 MHz TCXO frequency and divides this to
1 MHz; therefore, R = 10 is programmed and N = 320 is
programmed
200
150
100
50
0
0
100
200
300
400
500
600
to achieve a VCO frequency of 320 MHz. The resultant 80 MHz
CMOS signal has a jitter of <1.5 ps, which is more than adequate
for the application.
INDUCTANCE (nH)
Figure 27. Output Center Frequency vs. External Inductor Value
The approximate value of capacitance at the midpoint of the
center band of the VCO is 9.3 pF, and the approximate value of
internal inductance due to the bond wires is 0.9 nH. The VCO
sensitivity is a measure of the frequency change vs. the tuning
voltage. It is a very important parameter for the low-pass filter.
Figure 28 shows a graph of the tuning sensitivity (in MHz/V)
vs. the inductance (nH). It can be seen that as the inductance
increases, the sensitivity decreases. This relationship can be
derived from the previous equation; that is, because the
inductance increased, the change in capacitance from the
varactor has less of an effect on the frequency.
SPI
TCXO
10MHz
ADF4360-9
80MHz
PC
21nH
470Ω
21nH
USB
470Ω
SIGNAL
GENERATOR
ENCODE
CLOCK
AD9215-80
HC-ADC-
EVALA-SC
A
IN
LPF
Figure 29. The ADF4360-9 Used as an Encode Clock for an ADC
Rev. B | Page 20 of 24
Data Sheet
ADF4360-9
Two 21 nH inductors are required for the specified frequency
range. The reference frequency is from a 20 MHz TCXO from
Fox; therefore, an R value of 20 is programmed. Taking into
account the high PFD frequency and its effect on the band
select logic, the band select clock divider is enabled. In this case,
a value of 8 is chosen. A very simple shunt resistor and dc-blocking
capacitor complete the RF output stage. Because these outputs
are not used, they are terminated in 50 Ω resistors. This is
recommended for circuit stability. Leaving the RF outputs
open is not recommended.
GSM TEST CLOCK
Figure 30 shows the ADF4360-9 used to generate three different
frequencies at DIVOUT. The frequencies required are 45 MHz,
80 MHz, and 95 MHz. This is achieved by generating 360 MHz,
320 MHz, and 380 MHz and programming the correct A divider
ratio. Because a 50% duty cycle is required, the A/2 DIVOUT
mode is selected. This means that A values of 4, 2, and 2 are
selected, respectively, for each of the output frequencies
previously mentioned.
The low-pass filter was designed using ADIsimPLL™ for a
channel spacing of 1 MHz and an open-loop bandwidth of
40 kHz. Larger PFD frequencies can be used to reduce in-band
noise and, therefore, rms jitter. However, for the purposes of
this example, 1 MHz is used. The measured rms jitter from this
circuit at each frequency is less than 1.5 ps.
The CMOS level output frequency is available at DIVOUT. If
the frequency has to drive a low impedance load, a buffer is
recommended.
LOCK
V
V
VDD
DETECT
VCO
6
2
21
DV
23
10µF
V
7
AV
LD
V
TUNE
CP
DD
DD
VCO
12kΩ
24
14
16
C
2.2nF
N
1nF 1nF
FOX
801BE-160
20MHz
150pF
56pF
REF
IN
5.6kΩ
51Ω
17 CLK
ADF4360-9
20
DIVOUT
18
DATA
LE
V
19
12
VCO
C
C
51Ω
51Ω
100pF
13
R
SET
1nF
51Ω
51Ω
RF
RF
A
4
5
OUT
4.7kΩ
CPGND
1
AGND DGND L1 L2
B
OUT
9
3
8
11 22 15
10
100pF
21nH
470Ω
21nH
470Ω
Figure 30.GSM Test Clock
Rev. B | Page 21 of 24
ADF4360-9
Data Sheet
ADSP-21xx Interface
INTERFACING
Figure 32 shows the interface between the ADF4360 family and
the ADSP-21xx digital signal processor. The ADF4360 family
needs a 24-bit serial word for each latch write. The easiest way
to accomplish this using the ADSP-21xx family is to use the
autobuffered transmit mode of operation with alternate framing.
This provides a means for transmitting an entire block of serial
data before an interrupt is generated.
The ADF4360 family has a simple SPI-compatible serial interface
for writing to the device. CLK, DATA, and LE control the data
transfer. When LE goes high, the 24 bits that are clocked into
the appropriate register on each rising edge of CLK are transferred
to the appropriate latch. See Figure 2 for the timing diagram
and Table 5 for the latch truth table.
The maximum allowable serial clock rate is 20 MHz. This
means that the maximum update rate possible is 833 kHz, or
one update every 1.2 μs. This is more than adequate for systems
that have typical lock times in hundreds of microseconds.
SCLOCK
SCLK
MOSI
TFS
SDATA
LE
ADF4360-x
ADuC812 Interface
ADSP-21xx
I/O PORTS
CE
Figure 31 shows the interface between the ADF4360 family and
the ADuC812 MicroConverter®. Because the ADuC812 is based
on an 8051 core, this interface can be used with any 8051-based
microcontrollers. The MicroConverter is set up for SPI master
mode with CPHA = 0. To initiate the operation, the I/O port
driving LE is brought low. Each latch of the ADF4360 family
needs a 24-bit word, which is accomplished by writing three
8-bit bytes from the MicroConverter to the device. After the
third byte is written, the LE input should be brought high to
complete the transfer.
MUXOUT
(LOCK DETECT)
Figure 32. ADSP-21xx to ADF4360-x Interface
Set up the word length for 8 bits and use three memory
locations for each 24-bit word. To program each 24-bit latch,
store the 8-bit bytes, enable the autobuffered mode, and write to
the transmit register of the DSP. This last operation initiates the
autobuffer transfer.
PCB DESIGN GUIDELINES FOR CHIP SCALE
PACKAGE
SCLOCK
MOSI
SCLK
SDATA
The leads on the chip scale package (CP-24-2) are rectangular.
The PCB pad for these should be 0.1 mm longer than the
package lead length and 0.05 mm wider than the package lead
width. The lead should be centered on the pad to ensure that
the solder joint size is maximized.
ADuC812
I/O PORTS
LE
ADF4360-x
CE
MUXOUT
(LOCK DETECT)
The bottom of the chip scale package has a central thermal pad.
The thermal pad on the PCB should be at least as large as this
exposed pad. On the PCB, there should be a clearance of at least
0.25 mm between the thermal pad and the inner edges of the
pad pattern to ensure that shorting is avoided.
Figure 31. ADuC812 to ADF4360-x Interface
I/O port lines on the ADuC812 are used to detect lock (MUXOUT
configured as lock detect and polled by the port input). When
operating in the described mode, the maximum SCLOCK rate
of the ADuC812 is 4 MHz. This means that the maximum rate
at which the output frequency can be changed is 166 kHz.
Thermal vias can be used on the PCB thermal pad to improve
thermal performance of the package. If vias are used, they should
be incorporated into the thermal pad at 1.2 mm pitch grid. The
via diameter should be between 0.3 mm and 0.33 mm, and the
via barrel should be plated with 1 ounce of copper to plug the via.
The user should connect the printed circuit thermal pad to AGND.
This is internally connected to AGND.
Rev. B | Page 22 of 24
Data Sheet
ADF4360-9
The recommended value of this inductor changes with the VCO
center frequency. Figure 35 shows a graph of the optimum
inductor value vs. center frequency.
OUTPUT MATCHING
There are a number of ways to match the VCO output of the
ADF4360-9 for optimum operation; the most basic is to use a
51 Ω resistor to VVCO. A dc bypass capacitor of 100 pF is connected
in series, as shown in Figure 33. Because the resistor is not
frequency dependent, this provides a good broadband match.
The output power in the circuit in Figure 33 typically gives
−9 dBm output power into a 50 Ω load.
300
250
200
150
V
VCO
51Ω
100
50
0
100pF
RF
OUT
50Ω
Figure 33. Simple Output Stage
0
100
200
300
400
500
A better solution is to use a shunt inductor (acting as an RF
choke) to VVCO. This gives a better match and, therefore, more
output power.
CENTER FREQUENCY (MHz)
Figure 35. Optimum Shunt Inductor vs. Center Frequency
Both complementary architectures can be examined using the
EV-ADF4360-9EB1Z evaluation board. If the user does not
need the differential outputs available on the ADF4360-9, the
user should either terminate the unused output with the same
circuitry as much as possible or combine both outputs using a
balun. Alternatively, instead of the LC balun, both outputs can
be combined using a 180° rat-race coupler.
Experiments have shown that the circuit shown in Figure 34
provides an excellent match to 50 Ω over the operating range of
the ADF4360-9. This gives approximately 0 dBm output power
across the specific frequency range of the ADF4360-9 using the
recommended shunt inductor, followed by a 100 pF dc-blocking
capacitor.
V
VCO
If the user is only using DIVOUT and does not use the RF
outputs, it is still necessary to terminate both RF output pins
with a shunt inductor/resistor to VVCO and also a dc bypass
capacitor and a 50 Ω load. The circuit in Figure 33 is probably
the simplest and most cost-effective solution. It is important
that the load on each pin be balanced because an unbalanced
load is likely to cause stability problems. Terminations should
be identical as much as possible.
L
100pF
RF
OUT
50Ω
Figure 34. Optimum Output Stage
Rev. B | Page 23 of 24
ADF4360-9
Data Sheet
OUTLINE DIMENSIONS
4.10
4.00 SQ
3.90
0.60 MAX
0.60 MAX
PIN 1
INDICATOR
1
18
19
24
0.50
BSC
PIN 1
INDICATOR
2.45
2.30 SQ
2.15
3.75 BSC
SQ
EXPOSED
PAD
(BOTTOM VIEW)
13
12
6
7
0.50
0.40
0.30
0.20 MIN
TOP VIEW
2.50 BCS
0.70 MAX
0.65 TYP
12° MAX
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
1.00
0.85
0.80
0.05 MAX
0.02 NOM
SECTION OF THIS DATA SHEET.
COPLANARITY
0.08
0.30
0.23
0.18
SEATING
PLANE
0.20 REF
COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-2
Figure 36. 24-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
4 mm × 4 mm Body, Very Thin Quad
(CP-24-2)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
ADF43±0-9BCPZ
ADF43±0-9BCPZRL
ADF43±0-9BCPZRL7
EV-ADF43±0-9EB1Z
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
24-Lead LFCSP_VQ
24-Lead LFCSP_VQ
24-Lead LFCSP_VQ
Evaluation Board
Frequency Range
Package Option
CP-24-2
CP-24-2
±5 MHz to 400 MHz
±5 MHz to 400 MHz
±5 MHz to 400 MHz
CP-24-2
1 Z = RoHS Compliant Part.
©2008–2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07139-0-2/12(B)
Rev. B | Page 24 of 24
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