EVAL-AD1955EB [ADI]
High Performance Multibit with SACD Playback; 高性能多位与SACD播放
| 型号： | EVAL-AD1955EB |
| 厂家： | 
ADI |
| 描述： | High Performance Multibit with SACD Playback |
| 文件： | 总24页 (文件大小：903K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
High Performance Multibit ꢀ-ꢁ DAC
a
with SACD Playback
AD1955
FEATURES
FUNCTIONAL BLOCK DIAGRAM
5 V Power Supply Stereo Audio DAC System
Accepts 16-/18-/20-/24-Bit Data
Supports 24-Bit, 192 kHz Sample Rate PCM Audio Data
Supports SACD Bit Stream and External Digital Filter
Interface
DSD
BITSTREAM
INPUT
MASTER
CLOCK INPUT
CONTROL
DATA INPUT
3
4
DIGITAL
SUPPLY
Accepts a Wide Range of PCM Sample Rates Including:
32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz, and
192 kHz
Multibit Sigma-Delta Modulator with "Perfect Differen-
tial Linearity Restoration" for Reduced Idle Tones and
Noise Floor
AUTO-CLOCK
DIVIDER
SPI CONTROL
16-/20-/24-BIT
AUDIO DATA/
EXTERNAL
DIGITAL
3/4
MUX
DSD FILTER
FILTER INPUT
Data Directed Scrambling DAC––Low Sensitivity to Jitter
Supports SACD Playback with "Bit Expansion" Filter
Differential Current Output for Optimum Performance
8.64 mA p-p Differential Output
120 dB SNR/DNR (not muted) at 48 kHz Sample Rate
(A-Weighted Stereo)
SERIAL DATA
INTERFACE
EXTERNAL
FILTER I/F
RESET
MUTE
DIGITAL
FILTER ENGINE
S/H
ANALOG
SUPPLY
123 dB SNR/DNR (Mono)
–110 dB THD + N
110 dB Stop-Band Attenuation with ꢂ0.0002 dB
Pass-Band Ripple
ZERO
FLAGS
NOISE-SHAPED
SCRAMBLING
MULTIBIT ꢀ-ꢁ
MODULATOR
8ꢃ Oversampling Digital Filter
On-Chip Clickless Volume Control
VOLTAGE
REFERENCE
I-DAC
I-DAC
Supports SACD-Mute Pattern Detection
Supports 64 fS/128 fS DSD SACD with Phase Mode
Internal Digital Filter Pass-Through for External Filter
Master Clock: 256 fS, 512 fS, 768 fS
Hardware and Software Controllable Clickless Mute
Serial (SPI) Control for Serial Mode, Number of Bits,
Sample Rate, Volume, Mute, De-Emphasis, Mono Mode
Digital De-Emphasis for 32 kHz, 44.1 kHz, and 48 kHz
Sample Rates
L-CH
DIFFERENTIAL
CURRENT OUTPUT
R-CH
PRODUCT OVERVIEW
The AD1955 is a complete, high performance, single-chip, stereo
digital audio playback system. It is comprised of a multibit sigma-
delta modulator, high performance digital interpolation filters,
and continuous-time differential current output DACs. Other
features include an on-chip clickless stereo attenuator and mute
capability, programmed through an SPI compatible serial control
port. The AD1955 is fully compatible with all known DVD audio
formats including 192 kHz as well as 96 kHz sample frequencies
and 24 bits. It is also backward compatible by supporting 50 µs/
15 µs digital de-emphasis intended for “redbook” compact discs,
as well as de-emphasis at 32 kHz and 48 kHz sample rates.
Flexible Serial Data Port with Right-Justified, Left-
Justified, I2S, and DSP Modes
28-Lead SSOP Plastic Package
APPLICATIONS
High End DVD Audio
SACD
CD
Home Theater Systems
Automotive Audio Systems
Sampling Musical Keyboards
Digital Mixing Consoles
Digital Audio Effects Processors
The AD1955 has a very flexible serial data input port that
allows for glueless interconnection to a variety of ADCs, DSPs,
SACD decoders, external digital filters, AES/EBU receivers, and
(continued on page 12)
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
www.analog.com
© Analog Devices, Inc., 2002
AD1955–SPECIFICATIONS
TEST CONDITIONS
(Unless otherwise noted.)
Analog Supply Voltages (AVDD
Digital Supply Voltages (DVDD
)
)
. . . . . . . . . . . . . . . . . . . . 5 V
. . . . . . . . . . . . . . . . . . . . 5 V
Reference Current (IREF) . . . . . . . . . . . . . . . . . . . . . 0.960 mA
Ambient Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . 25°C
Input Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.288 MHz
Input Signal . . . . . . . . . . . . . . . . . 984.375 Hz, 0 dB Full Scale
Input Sample Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 kHz
Measurement Bandwidth . . . . . . . . . . . . . . . . 20 Hz to 20 kHz
Word Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Bits
Load Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 pF
Load Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 kΩ
Input Voltage HI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4 V
Input Voltage LO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.8 V
ANALOG PERFORMANCE (See figures. IREF = 0.960 mA, VBIAS = 2.80 V.)
Parameter
Min
Typ
Max
Unit
Resolution
24
Bits
SIGNAL-TO-NOISE RATIO (20 Hz to 20 kHz)*
Differential Output (A-Weighted, RMS) (Stereo)
Differential Output (A-Weighted, RMS) (Mono)
Single-Ended (A-Weighted, RMS) (Stereo)
120
123
119
114
dB
dB
dB
DYNAMIC RANGE (20 Hz to 20 kHz, –60 dB Input)*
Differential Output (A-Weighted, RMS) (Stereo)
Differential Output (A-Weighted, RMS) (Mono)
Single-Ended (A-Weighted, RMS) (Stereo)
120
123
119
114
dB
dB
dB
Total Harmonic Distortion + Noise (Stereo) at 0 dBFS
–110
–102.5
100
dB
ANALOG OUTPUTS
Differential Output Range (Full Scale)
Output Capacitance at Each Output Pin
Output Bias Current, Each Output
8.64
mA p-p
pF
mA
–3.24
Out-of-Band Energy (0.5 ꢀ fS to 100 kHz)
Reference Voltage
–90
2.505
dB
V
2.245
2.39
DC ACCURACY
Gain Error
6
%
Interchannel Gain Mismatch
Gain Drift
0.01
25
0.26
dB
ppm/°C
Interchannel Crosstalk (EIAJ Method)
Interchannel Phase Deviation
Mute Attenuation
–125
0.1
–100
dB
Degrees
dB
De-Emphasis Gain Error
0.1
dB
*Measured with Audio Precision System Two Cascade in RMS Mode. Averaging Mode will show approximately 2 dB better performance.
Performance of right and left channels are identical (exclusive of the Interchannel Gain Mismatch and Interchannel Phase Deviation specifications).
Specifications subject to change without notice.
–2–
REV. 0
AD1955
DIGITAL I/O (–40ꢄC to +85ꢄC, unless otherwise noted.)
Parameter
Min
Typ
Max
Unit
Input Voltage HI (VIH)
Input Voltage LO (VIL)
2.2
V
V
µA
µA
V
0.8
+3
+3
Input Leakage (IIH @ VIH = 2.4 V)
Input Leakage (IIL @ VIL = 0.8 V)
High Level Output Voltage (VOH) IOH = 1 mA
Low Level Output Voltage (VOL) IOL = 1 mA
Input Capacitance
–3
–3
2.4
0.4
20
V
pF
Specifications subject to change without notice.
TEMPERATURE
Parameter
Min
Typ
Max
Unit
Specifications Guaranteed
Functionality Guaranteed
Storage
25
°C
°C
°C
–40
–55
+85
+125
Specifications subject to change without notice.
POWER
Parameter
Min
Typ
Max
Unit
SUPPLIES
Voltage, Digital
Voltage, Analog
Analog Current
Analog Current—Reset
Digital Current
4.50
4.50
5
5
20
20
22
2
5.50
5.50
V
V
mA
mA
mA
mA
Digital Current—Reset
DISSIPATION
Operation—Both Supplies
Operation—Analog Supply
Operation—Digital Supply
210
100
110
mW
mW
mW
POWER SUPPLY REJECTION RATIO
1 kHz 300 mV p-p Signal at Analog Supply Pins
20 kHz 300 mV p-p Signal at Analog Supply Pins
–77
–72
dB
dB
Specifications subject to change without notice.
DIGITAL FILTER CHARACTERISTICS
Stop-Band
Sample Rate (kHz)
Pass Band (kHz)
Stop Band (kHz)
Attenuation (dB)
Pass-Band Ripple (dB)
44.1
48
96
DC–20
24.1–328.7
26.23–358.28
56.9–327.65
117–327.65
110
110
115
95
0.0002
0.0002
0.0005
0/–0.04 (DC – 21.8 kHz)
0/–0.5 (DC – 65.4 kHz)
0/–1.5 (DC – 87.2 kHz)
DC–21.8
DC–39.95
DC–87.2
192
Specifications subject to change without notice.
REV. 0
–3–
AD1955
SPECIFICATIONS (continued)
GROUP DELAY
Chip Mode
Group Delay Calculation
fS (kHz)
Group Delay
Unit
INT8ꢀ Mode
INT4ꢀ Mode
INT2ꢀ Mode
5553/(128 ꢀ fS)
5601/(64 ꢀ fS)
5659/(32 ꢀ fS)
48
96
192
903.8
911.6
921
µs
µs
µs
Specifications subject to change without notice.
DIGITAL TIMING (Guaranteed over –40ꢄC to +85ꢄC, AVDD = DVDD = 5.0 V ꢂ 10%.)
Parameter
Description
Min
Unit
tDMP
tDML
tDMH
tDBH
tDBL
MCLK Period (FMCLK = 256 ꢀ FLRCLK
MCLK LO Pulsewidth (All Modes)
MCLK HI Pulsewidth (All Modes)
BCLK/EF_BCLK High
BCLK/EF_BCLK Low
BCLK/EF_BCLK Period
LRCLK/EF_WCLK Setup
LRCLK Hold (DSP Serial Port Mode Only)
EF_WCLK High
)
50
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
0.4 ꢀ tDMP
0.4 ꢀ tDMP
20
20
60
0
15
20
20
0
tDBP
tDLS
tDLH
tDWH
tDWL
tDDS
tDDH
tDPHS
tDSDS
tDSDH
tDSKP
tDSKH
tDSKL
tDMP
tDML
tDMH
tCLS
EF_WCLK Low
SDATA/EF_LDATA/EF_RDATA Setup
SDATA/EF_LDATA/EF_RDATA Hold
DSD_PHASE Setup
DSD_DATA Setup
DSD_DATA Hold
DSD_SCLK Period
DSD_SCLK High
DSD_SCLK Low
CCLK Period
CCLK LO Pulsewidth
CCLK HI Pulsewidth
CLATCH Setup
20
20
5
5
60
20
20
50
15
10
0
15
0
5
tCLH
tCDS
tCDH
tRSTL
CLATCH Hold
CDATA Setup
CDATA Hold
RST LO Pulsewidth
10
Specifications subject to change without notice.
–4–
REV. 0
AD1955
*
ABSOLUTE MAXIMUM RATINGS
PACKAGE CHARACTERISTICS
Parameter
Min
Max
Unit
Package
Typ
Unit
DVDD to DGND
AVDD to AGND
Digital Inputs
–0.3
–0.3
DGND – 0.3
AGND – 0.3
6
6
V
V
V
V
V
ꢁJA (Thermal Resistance
[Junction-to-Ambient])
ꢁJC (Thermal Resistance
[Junction-to-Case])
109.0
°C/W
DVDD + 0.3
AVDD + 0.3
+0.3
(AVDD + 0.3)/2
300
39.0
°C/W
Analog Outputs
AGND to DGND –0.3
Reference Voltage
Soldering
°C
sec
10
*Stresses greater than those listed under Absolute Maximum Ratings may cause
permanent damage to the device. This is a stress rating only; functional operation
of the device at these or any other conditions above those indicated in the
operational section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
ORDERING GUIDE
*
Model
Temperature
Package Description
Package Option
AD1955ARS
AD1955ARSRL
EVAL-AD1955EB
–40°C to +85°C
–40°C to +85°C
28-Lead SSOP
28-Lead SSOP
Evaluation Board
RS-28
RS-28 on 13" Reels
*RS = Shrink Small Outline Package
PIN CONFIGURATION
DVDD
DGND
MCLK
CCLK
1
2
28
27
26
25
24
23
22
21
20
19
18
17
16
15
LRCLK/EF_WCLK
BCLK/EF_BCLK
SDATA/EF_LDATA
EF_RDATA
DSD_SCLK
DSD_LDATA
DSD_RDATA
DSD_PHASE
AGND
3
4
CLATCH
CDATA
5
6
PD/RST
AD1955
TOP VIEW
(Not to Scale)
MUTE
7
ZEROL
ZEROR
AGND
IOUTL+
IOUTL–
FILTB
8
9
10
11
12
13
14
IOUTR+
IOUTR–
FILTR
IREF
AVDD
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD1955 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. 0
–5–
AD1955
PIN FUNCTION DESCRIPTIONS
Pin No.
I/O
Mnemonic
Description
1
2
DVDD
Digital Power Supply Connected to Digital 5 V Supply
Input
Input
Input
LRCLK/EF_WCLK
Left/Right Clock Input for Input Data in PCM Mode
Word Clock in External Filter Mode
3
4
BCLK/EF_BCLK
Bit Clock Input for Input Data in PCM Mode
Bit Clock Input in External Filter Mode
SDATA/EF_LDATA
MSB First, Twos Complement Serial Audio Data
Two Channel (left and right), 16-Bit to 24-Bit Data in PCM Mode
Left Channel Data in External Filter Mode
5
6
Input
I/O
EF_RDATA
DSD_SCLK
Not used in PCM Mode
Right channel data in External Filter Mode
Serial Clock Input for DSD Data. This clock should be 64 ꢀ 44.1 kHz,
2.8224 MHz or 128 ꢀ 44.1 kHz, 5.6448 MHz in Normal Mode, 128 ꢀ
44.1 kHz, 5.6448 MHz or 256 ꢀ 44.1 kHz, 11.2896 MHz in Phase Mode.
7
8
9
Input
Input
I/O
DSD_LDATA
DSD_RDATA
DSD_PHASE
DSD Left Channel Data Input
DSD Right Channel Data Input
DSD Phase Reference Signal. This clock should be 64 ꢀ 44.1 kHz,
2.8224 MHz. If not used, this pin should be connected low.
10
11
12
13
AGND
Analog Ground
Output
Output
Output
IOUTR+
IOUTR–
FILTR
Right Channel Positive Analog Output
Right Channel Negative Analog Output
Voltage Reference Filter Capacitor Connection. Bypass and decouple the
voltage reference with parallel 10 µF and 0.1 µF capacitors to AGND.
14
15
16
17
18
19
20
IREF
Connection Point for External Bias Resistor
Analog Power Supply Connected to Analog 5 V Supply
Filter Capacitor Connection with Parallel 10 µF and 0.1 µF Capacitors to AGND
Left Channel Negative Analog Output
AVDD
FILTB
IOUTL–
IOUTL+
AGND
ZEROR
Output
Output
Output
Left Channel Positive Analog Output
Analog Ground
Output
Output
Input
Right Channel Zero Flag Output. This pin goes high when the right channel
has no signal input or the DSD mute pattern is detected.
21
22
23
ZEROL
MUTE
PD/RST
Left Channel Zero Flag Output. This pin goes high when the left channel has
no signal input or the DSD mute pattern is detected.
Mute. Assert high to mute both stereo analog outputs. Deassert low for nor-
mal operation.
Input
Power Down/Reset. The AD1955 is placed in a reset state and the digital
circuitry is powered down when this pin is held low. The AD1955 is reset on
the rising edge of this signal. The serial control port registers are reset to the
default values. Connect high for normal operation.
24
Input
CDATA
Serial Control Input, MSB First, Containing 16 Bits of Unsigned Data. Used
for specifying control information and channel-specific attenuation.
25
26
Input
Input
CLATCH
Latch Input for Control Data
CCLK
Clock Input for Control Data. Control input data must be valid on the rising
edge of CCLK. CCLK may be continuous or gated.
27
28
Input
MCLK
DGND
Master Clock Input. Connect to an external clock source.
Digital Ground
–6–
REV. 0
Typical Performance Characteristics–AD1955
TPC 1. Pass-Band Response, 8ꢀ Mode, 48 kHz Sample Rate
TPC 4. Complete Response, 4ꢀ Mode, 96 kHz Sample Rate
TPC 5. Pass-Band Response, 2ꢀ Mode, 192 kHz
TPC 2. Complete Response, 8ꢀ Mode, 48 kHz Sample Rate
Sample Rate
TPC 6. Complete Response, 2ꢀ Mode, 192 kHz
Sample Rate
TPC 3. 44 kHz Pass-Band Response 4
Sample Rate
ꢀ Mode, 96 kHz
REV. 0
–7–
AD1955
TPC 10. FFT Plot, DNR = 121 dBFS (A-Weight), PCM
SR = 48 kHz, –60 dBFS @ 1 kHz
TPC 7. DSD Digital Filter Pass Band
TPC 11. FFT Plot, SNR = 121 dBFS (A-Weight), PCM
SR = 48 kHz with Zero Input
TPC 8. DSD Digital Filter Response, Input Sample
Rate = 2.8224 MHz
TPC 12. Linearity, PCM SR = 48 kHz, 0 dBFS to
–140 dBFS Input @ 200 Hz
TPC 9. FFT Plot, THD + N = –110 dBFS, PCM SR = 48
kHz, 0 dBFS @ 1 kHz
–8–
REV. 0
AD1955
TPC 16. Wideband FFT Plot, PCM SR = 48 kHz, 0
dBFS @ 20 kHz
TPC 13. THD + N vs. Amplitude Plot, PCM SR = 48
kHz, 0 dBFS to –120 dBFS Input @ 1 kHz
TPC 17. De-emphasis Frequency Response, PCM SR =
32 kHz, 0 dBFS Input
TPC 14. THD + N vs. Frequency Plot, PCM SR = 48
kHz, 0 dBFS Input
TPC 18. De-emphasis Frequency Response, PCM
SR = 44.1 kHz, 0 dBFS Input
TPC 15. FFT Plot, PCM SR = 48 kHz, 0 dBFS @ 20
kHz, BW = 22 kHz
REV. 0
–9–
AD1955
TPC 19. De-emphasis Frequency Response, PCM
SR = 48 kHz, 0 dBFS Input
TPC 22. FFT Plot, PCM SR = 96 kHz, Zero Input,
BW = 22 kHz
TPC 20. FFT Plot, PCM SR = 96 kHz, 0 dBFS @ 1 kHz,
BW = 22 kHz
TPC 23. Wideband FFT Plot, PCM SR = 96 kHz,
0 dBFS Input @ 37 kHz
TPC 21. FFT Plot, PCM SR = 96 kHz, –60 dBFS @
1 kHz, BW = 22 kHz
TPC 24. FFT Plot, PCM SR = 192 kHz, 0 dBFS Input
@ 1 kHz
–10–
REV. 0
AD1955
TPC 25. FFT Plot, PCM SR = 192 kHz, –60 dBFS Input
@ 1 kHz
TPC 28. FFT Plot, 64 ꢀ fS DSD, SR = 44.1 kHz,
0 dBFS @ 1 kHz
TPC 26. FFT Plot, PCM SR = 192 kHz, Zero Input
TPC 29. FFT Plot, 64 ꢀ fS DSD, SR = 44.1 kHz,
–60 dBFS @ 1 kHz
TPC 27. Wideband FFT Plot, PCM SR = 192 kHz,
0 dBFS @ 60 kHz
TPC 30. FFT Plot, 64 ꢀ fS DSD, SR = 44.1 kHz, Zero Input
REV. 0
–11–
AD1955
TPC 31. FFT Plot, 64 ꢀ fS DSD, SR = 44.1 kHz,
TPC 32. Wideband FFT Plot, 64 ꢀ fS DSD,
0 dBFS @ 10 kHz
SR = 44.1 kHz, 0 dBFS @ 10 kHz
(continued from page 1)
Serial Data Format in PCM Mode
The supported formats are shown in Figure 1. For detailed
timing, see Figure 2.
sample rate converters. The AD1955 can be configured in left-
justified, I2S, right-justified, or DSP serial port compatible
modes. It can support MSB first, twos complement format, 16,
18, 20, and 24 bits in all standard PCM modes. The AD1955
also has an interface for SACD playback and an external digital
filter interface for use with an external digital interpolation filter
or HDCD decoder. The AD1955 uses a 5 V power supply. It is
fabricated on a single monolithic integrated circuit and is housed
in a 28-lead SSOP package for operation over the temperature
range –40°C to +85°C.
In Left-Justified Mode, LRCLK is high for the left channel and
low for the right channel. Data should be valid on the rising
edge of BCLK. The MSB is left-justified to an LRCLK transi-
tion, with no MSB delay.
In I2S Mode, LRCLK is low for the left channel and high for
the right channel. Data should be valid on the rising edge of
BCLK. The MSB is left-justified to an LRCLK transition but
with a single BCLK period delay.
OPERATING FEATURES
Serial Data Input Port
In DSP serial port mode, LRCLK must pulse high for at least
one bit clock period before the MSB of the left channel is valid,
and LRCLK must pulse high again for at least one bit clock
period before the MSB of the right channel is valid. Data should
be valid on the falling edge of BCLK. The DSP serial port mode
can be used with any word length up to 24 bits.
The AD1955’s flexible serial data input port accepts standard
PCM audio data and external digital filter output data in twos
complement, MSB-first format in PCM/External Digital Filter
Mode, and a dedicated SACD serial port accepts DSD bit stream
data in SACD Mode. If the PCM Mode is selected by Control
Register 0 Bits 12 and 13, the left channel data field always pre-
cedes the right channel data field. The serial data format and
word length in PCM Mode are set by the mode select bits (Bits 4
and 5 and Bits 2 and 3, respectively) in the SPI control register.
In this mode, it is the responsibility of the DSP to ensure that the
left data is transmitted with the first LRCLK pulse after RESET,
and that synchronism is maintained from that point forward.
In Right-Justified Mode (16 bits shown), LRCLK is high for the
left channel and low for the right channel. Data should be valid
on the rising edge of BCLK.
In all data formats except for the Right-Justified Mode, the
serial port will accept an arbitrary number of bits up to a limit of
24 (extra bits will not cause an error, but they will be truncated
internally). In Right-Justified Mode, Control Register 0, Bits 2
and 3 are used to set the word length to 16, 18, 20, or 24 bits.
The default on power up is 24-bit, I2S.
In normal operation, there are 64 bit clocks per frame (or 32 per
half-frame). When the SPI word length control bits (Bits 2 and
3 in Control Register 0) are set to 24 bits (0:0), the serial port
will begin to accept data starting at the eighth bit clock pulse
after the LRCLK transition. When the word length control bits
are set to 20-bit mode, data is accepted starting at the 12th bit
clock position. In 18-bit mode, data is accepted starting at the
14th bit clock position. In 16-bit mode, data is accepted starting
at the 16th bit clock position.
In the External Digital Filter Mode, selected by Control Regis-
ter 0 Bits 12 and 13, Bits 2 and 3 are used to set the word length
to 16, 18, 20, or 24 bits and the format is set with Bits 4 and 5.
For a burst-mode clock, the format should be set to left-justified.
DSP Mode is not used. The LRCLK is always falling-edge active.
The default on power-up is 24-bit mode in PCM and External
Digital Filter Mode.
Note that the AD1955 is capable of a 32 ꢀ fS BCLK frequency
“packed mode” where the MSB is left-justified to an LRCLK
transition, and the LSB is right-justified to the next LRCLK
transition. LRCLK is high for the left channel, and low for the
right channel. Data is valid on the rising edge of BCLK. Packed
mode can be used when the AD1955 is programmed in Left-
Justified Mode.
In SACD Mode, selected by Control Register 0 Bits 12 and 13,
the SACD port will accept a DSD bit stream.
When the SPI Control Port is not being used, the SPI pins (24,
25, and 26) should be tied to DGND or DVDD.
–12–
REV. 0
AD1955
Serial Data Format in External Digital Filter Mode
In the SACD Mode, the AD1955 accepts a 256fS, 512fS, or
768fS Master Clock, where fS is nominally 44.1 kHz. In Slave
Mode, by default, the rising edge of DSD_SCLK should coincide
with the rising edge of MCLK. Control Register 1, Bit 2 should
be set to 1 if the rising edge of DSD_SCLK coincides with the
falling edge of MCLK. In Master Mode this bit can be used to
select the MCLK edge used to generate the DSD clock outputs.
In the External Digital Filter Mode, the AD1955 will accept
up to 24-bit serial, twos complement, MSB-first data from an
external digital filter, an HDCD decoder, or a general-purpose
DSP. If the External Digital Filter Mode is selected by Control
Register 0, Bits 12 and 13, Pin 2 to Pin 5 are assigned as the word
clock input (EF_WCLK, Pin 2), bit clock input (EF_BCLK,
Pin 3), left channel data input (EF_LDATA, Pin 4), and right
channel data input (EF_RDATA, Pin 5), respectively, to accept
8fS (48 kHz), 4fS (96 kHz), or 2fS (196 kHz) oversampled data.
Zero Detection
When the AD1955 detects that the audio input data is continu-
ously zero during 1024 LRCLK periods in PCM Mode or 8192
LRCLK periods in 8fS External Digital Filter Mode, ZEROL
(Pin 21) or ZEROR (Pin 20) is set to active.
Left and right channel data should be valid on the rising edge
of EF_BCLK. The mode can be set to Left- or Right-Justified.
A burst mode BCLK can be used in Left-Justified Mode.
When the AD1955 is in SACD Mode, it will detect an SACD
mute pattern. If the input bit stream shows a mute pattern for
about 22 ms, the AD1955 will set ZEROL (Pin 21) or ZEROR
(Pin 20) to active. The outputs can be set to active high or low
using Control Register 1, Bit 8.
Serial Data Format in SACD Mode
In the SACD Mode, the AD1955 supports both normal mode
or phase modulation mode, which are selected by Control
Register 1, Bit 6. If normal mode is selected, DSD_SCLK,
DSD_LDATA, and DSD_RDATA are used to interface with
DSD decoder chip. In this mode, the DSD data is clocked in
the AD1955 using the rising edge of DSD_SCLK with a 64fS
rate, 2.8224 MHz. DSD_PHASE pin should be connected LOW.
Reset/Power-Down
The AD1955 will be reset when the PD/RST pin is set low. The
part may be powered down using Bit 15, Control Register 0.
Audio Outputs
If Phase Modulation Mode is selected, the DSD_PHASE pin is
also used to interface with the DSD decoder. In this mode, a
64fS DSD_PHASE signal is used as a reference signal to receive
the data from the decoder. The DSD data is clocked into the
AD1955 with a 128fS DSD_SCLK.
Active I/V converters should be used, which will hold the DAC
outputs at a constant voltage level. Passive I/V conversion should
not be used, since the DAC performance will be seriously degraded.
For best THD + N performance over temperature, a reference
voltage of 2.80 V should be used with the I/V converters. For a
lower parts count, the voltage at FILTR can be used. In this
instance, THD + N performance at high temperature can be
improved by reducing IREF, with an attendant reduction in gain
(linear dependence) and DNR/SNR (square-root dependence).
The AD1955 can operate as a master or slave device. In Master
Mode, the AD1955 will output DSD_SCLK and DSD_PHASE
(if in Phase Modulation Mode) to a DSD decoder and will
support Normal Mode and Phase Modulation Mode 0. In Slave
Mode, the AD1955 will accept DSD_SCLK and DSD_PHASE
(if in Phase Modulation Mode) from a DSD decoder and sup-
ports all of the normal and phase modulation modes.
The AD1955 audio outputs sink a current proportional to the
input signal, superimposed on a steady bias current. The cur-
rent-to-voltage (I/V) converters used need to be able to supply
this bias current, as well as the signal current, or a resistor or
current source can be used to a positive voltage to null this
current in order to center the range of the I/V converters.
When the SACD Port is not being used, the SACD pins (Pins
6, 7, 8, and 9) should be tied to a valid logic level. Please note
that there are weak pull-ups (0.6 mA typical) on DSD_SCLK
and DSD_PHASE.
If pull-up resistors are used to bring the output of the I/V convert-
ers to 0 V for maximum headroom and THD balance, as shown
in the applications circuits, the following equation can be used:
Master Clock
The AD1955 must be set to the proper sample rate and master
clock rate using Control Registers 0 and 1. The allowable master
clock frequencies for each interpolation mode are shown below.
RPULLUP = V
–VBIAS
I
+ (VBIAS RI/V
BIAS
)
]
[
] [
SUPPLY
In the External Filter Mode, the AD1955 accepts master clock
frequencies depending on the input sample rate as shown below.
PCM Mode
Allowable Master Clock Frequencies (
؋
fS) Nominal Input
Sample Rate (kHz)
Interpolation Mode
48 kHz (INT 8×) Mode
96 kHz (INT 4×) Mode
192 kHz (INT 2×) Mode
64
96
128
192
256
384
512
768
•
•
•
32, 44.1, 48
88.2, 96
•
•
•
•
•
•
176.4, 192
External Filter Mode
Allowable Master Clock Frequencies (
؋
fS) Nominal Input Sample Rate
(to External Filter) (kHz)
Input Sample Rate
64
96
128
192
256
384
512
768
8 × fS
4 × fS
2 × fS
•
•
•
•
32, 44.1, 48
88.2, 96
•
•
•
•
•
176.4, 192
REV. 0
–13–
AD1955
For example, with the stereo circuits given in Figures 7 through
10, this gives:
Serial Control Port
The AD1955 has an SPI compatible control port to permit pro-
gramming the internal control registers. The SPI control port is
a 3-wire serial port. Its format is similar to the Motorola SPI
format except that the input data-word is 16 bits wide. The serial
bit clock may be completely asynchronous to the sample rate of the
DAC. The following figure shows the format of the SPI signal
Note that the CCLK may be continuous or a 16-clock burst.
12.0V – 2.80V 3.24 mA + 2.80V 2.00 K = 1.98 kΩ
(
)
[
]
[
]
A 2.00 kΩ resistor is used.
The supply used should be as quiet as possible.
SPI REGISTER DEFINITIONS
Table I. DAC Control Register 0
Table II. DAC Control Register 1
Bit
Description
Value
Definition
Bit
Description
Value
Definition
15
Power-Down
0
1
Operation
Powered Down
10:9
MCLK Mode
00
01
10
11
256 ꢀ fS
512 ꢀ fS
768 ꢀ fS
Reserved
14
Mute
0
1
Not Muted
Muted
8
Zero Flag Polarity
SACD Bit Rate
SACD Mode
0
1
Active High
Active Low
13:12
Data Format
00
01
10
11
PCM
External DF
SACD Slave
SACD Master
7
0
1
64 ꢀ fS
128 ꢀ fS
11:10
9:8
Output Format
00
01
10
11
Stereo
6
0
1
Normal
Phase Mode
Not Allowed
Mono Left
Mono Right
5:4
SACD Phase Select
00
01
10
11
Phase 0
Phase 1
Phase 2
Phase 3
PCM Sample Rate
00
01
10
11
48 kHz
96 kHz
192 kHz
Reserved
3
2
SACD Bit Inversion
0
1
Normal
Inverted
7:6
De-Emphasis Curve
Select
00
01
10
11
None
SACD MCLK to
BCLK Phase
0
1
Rising Edge
Falling Edge
44.1 kHz
32 kHz
48 kHz
1:0
SPI Register Address
01
Default = 0
5:4
PCM/EF Serial Data
Format
00
01
10
11
I2S
Right-Justified
DSP
Left-Justified
Table III. DAC Volume Registers
Bit
Description
Value
Definition
3:2
PCM/EF Serial Data
Width
00
01
10
11
24 bits
20 bits
18 bits
16 bits
14-Bit
Unsigned
15:2
1:0
Volume
SPI Register Address
10
11
Left Volume
Right Volume
1:0
SPI Register Address
00
Default = Full Volume
Default = 0
–14–
REV. 0
AD1955
LEFT CHANNEL
LEFT CHANNEL
LRCLK
BCLK
RIGHT CHANNEL
RIGHT CHANNEL
MSB
LSB
LSB
MSB
SDATA
2
I S MODE –16 TO 24 BITS PER CHANNEL
LRCLK
BCLK
MSB
LSB
MSB
LSB
SDATA
RIGHT-JUSTIFIED MODE – SELECT NUMBER OF BITS PER CHANNEL
LRCLK
BCLK
MSB
MSB
LSB
SDATA
DSP MODE – 16 TO 24 BITS PER CHANNEL
RIGHT CHANNEL
LRCLK
BCLK
LEFT CHANNEL
MSB
MSB
LSB
LSB
SDATA
LEFT-JUSTIFIED MODE – 16 TO 24 BITS PER CHANNEL
1/fS
NOTES
1. DSP MODE DOES NOT IDENTIFY CHANNEL.
2. LRCLK NORMALLY OPERATES AT fS EXCEPT FOR DSP MODE, WHICH IS 2 ꢃ fS.
3. BCLK FREQUENCY IS NORMALLY 64 ꢃ LRCLK BUT MAY BE OPERATED IN BURST MODE.
Figure 1. Supported Serial Data Formats
tDBH
tDBP
BCLK
tDBL
tDLS
L/RCLK
tDDS
SDATA
LEFT-JUSTIFIED
MODE
MSB
tDDH
MSB-1
tDDS
SDATA
2
I S-JUSTIFIED
MSB
tDDH
MODE
tDDS
LSB
tDDS
MSB
tDDH
SDATA
RIGHT-JUSTIFIED
MODE
tDDH
8-BIT CLOCKS
(24-BIT DATA)
12-BIT CLOCKS
(20-BIT DATA)
16-BIT CLOCKS
(16-BIT DATA)
Figure 2. Serial Data Port Timing
REV. 0
–15–
AD1955
D0
D1
DSD_DATA
DSD_BCLK
NORMAL
MODE
D0
DSD_DATA
DSD_BCLK
D0
DSD_PHASE_0
DSD_PHASE_1
PHASE
MOD
MODE
DSD_PHASE_2
DSD_PHASE_3
Figure 3. DSD Modes
DSD_PHASE
DSD_SCLK
tDSKP
tDSKH
tDPHS
tDSKL
tDSDS
DSD_LDATA, DSD_RDATA
tDSDH
Figure 4. DSD Serial Port Timing
tCLATCHH
tCLKL
tCLKH
CLATCH
CCLK
D15
D14
D0
CDATA
tCDH
tCDS
Figure 5. Serial Control Port Timing
–16–
REV. 0
AD1955
DVDD
AVDD
CONNECT VBIAS TO VREFA FOR BEST PERFORMANCE
OR VREF FOR LOWER PARTS COUNT
L2
600Z
L3
600Z
VREF
VBIAS
AVDD
C2
0.1F
C1
0.1F
OR
VREFA
R56
2.21k⍀
VREFA
2.80V
DVDD
AVDD
MCLK
MCLK
U1
IOUTL+
IOUTL+
IOUTL–
RDATA
SDATA
BCLK
EF_RDATA
+
C43
47F
C44
0.1F
R57
2.80k⍀
SDATA/EF_LDATA
BCLK/EF_BCLK
LRCLK/EF_WCLK
IOUTL–
LRCLK
DSD_PHASE
DSD_RDATA
DSD_LDATA
DSD_SCLK
DSD_PHASE
DSD_RDATA
DSD_LDATA
DSD_SCLK
IOUTR+
IOUTR–
IOUTR+
IOUTR–
AD1955
CDATA
CDATA
CLATCH
CCLK
CLATCH
VREF
2.39V
FILTR
FILTB
CCLK
MUTE
ZEROR
ZEROL
MUTE
C5
0.1F
ZEROR
ZEROL
IREF
+
+
C4
10F
C6
47F
PD/RST
PD/RST
AGND1 AGND2
DGND
R1
2.49k⍀
C3
0.1F
600Z
L1
Figure 6. DAC Power Supply and Bypass
REV. 0
–17–
AD1955
R5
2.00kꢆ
12V
C10
100pF
R6
100ꢆ
R3
2.00kꢆ
R2
2.00kꢆ
U2-A
COMP
IOUTL+
AD797
–3dB at 100 kHz
J1
+
R11
R9
C7
OUT
1.00kꢆ
1.00kꢆ
OPEN
NL–
C9
LEFT
NL+
C12
390pF
100pF
DIRECT
OUT
–
C8
OPEN
U3-A
6VRMS
G
R10
1.00kꢆ
C13
470pF
C14
470pF
R12
1.00kꢆ
COMP
OUT
IOUTL–
VBIAS
AD797
R4
402ꢆ
+12V
NL–
NL+
R7
100ꢆ
C11
100pF
+
4.7ꢅF
4.7ꢅF
0.1ꢅF
0.1ꢅF
R8
2.00kꢆ
AD797
+
OP AMP BYPASS
DUPLICATE FOR EACH PART
–12V
Figure 7. Left Channel Differential Output
R16
2.00kꢆ
12V
C18
100pF
R17
100ꢆ
R14
2.00kꢆ
R13
2.00kꢆ
U4-A
COMP
IOUTR+
AD797
–3dB at 100 kHz
J2
+
R22
R20
C15
OUT
1.00kꢆ
1.00kꢆ
OPEN
NL–
C17
RIGHT
DIRECT
OUT
NL+
C20
390pF
100pF
–
C16
OPEN
U5-A
6VRMS
G
R21
1.00kꢆ
C21
C22
470pF
R23
1.00kꢆ
COMP
OUT
470pF
IOUTR–
VBIAS
AD797
R15
402ꢆ
+12V
NL–
NL+
R18
100ꢆ
C19
100pF
+
4.7ꢅF
4.7ꢅF
0.1ꢅF
0.1ꢅF
R19
2.00kꢆ
AD797
+
OP AMP BYPASS
DUPLICATE FOR EACH PART
–12V
Figure 8. Right Channel Differential Output
–18–
REV. 0
AD1955
R27
2.00kꢆ
12V
C26
100pF
R28
100ꢆ
R24
2.00kꢆ
R25
2.00kꢆ
C30
R37
U6-A
COMP
2.7nF
R33
100ꢆ
226ꢆ
R31
681ꢆ
R34
324ꢆ
IOUTL+
AD797
U8-A
–3dB at 75 kHz
C23
OUT
COMP
C28
5.6nF
OPEN
R38
332ꢆ
NL–
J3
C25
100pF
NL+
AD797
OUT
C24
U7-A
LEFT
OPEN
C29
FILTER
OUT
C32
3.9nF
R39
OPEN
NL–
COMP
OUT
5.6nF
R32
681ꢆ
NL+
IOUTL–
VBIAS
2VRMS
AD797
R35
324ꢆ
R26
402ꢆ
NL–
R36
226ꢆ
C31
2.7nF
NL+
R29
100ꢆ
C27
100pF
R30
2.00kꢆ
+12V
+
4.7ꢅF
4.7ꢅF
0.1ꢅF
AD797
+
0.1ꢅF
OP AMP BYPASS
DUPLICATE FOR EACH PART
–12V
Figure 9. Left Channel Single-Ended Output
R43
2.00kꢆ
12V
C36
100pF
R44
100ꢆ
R40
R41
2.00kꢆ
C40
R53
100ꢆ
U9-A
COMP
2.00kꢆ
2.7nF
R49
226ꢆ
R47
681ꢆ
R50
324ꢆ
IOUTR+
AD797
–3dB at 75 kHz
U11-A
COMP
C33
OPEN
OUT
C38
5.6nF
R54
332ꢆ
NL–
J4
C35
100pF
NL+
AD797
OUT
C34
OPEN
RIGHT
FILTER
OUT
U10-A
C39
C42
3.9nF
R55
OPEN
NL–
COMP
5.6nF
R48
681ꢆ
NL+
IOUTR–
VBIAS
2VRMS
AD797
R51
OUT
324ꢆ
R42
402ꢆ
NL–
R52
226ꢆ
C41
2.7nF
NL+
R45
100ꢆ
C37
100pF
R46
2.00kꢆ
+12V
+
4.7ꢅF
4.7ꢅF
0.1ꢅF
AD797
+
0.1ꢅF
OP AMP BYPASS
DUPLICATE FOR EACH PART
–12V
Figure 10. Right Channel Single-Ended Output
–19–
REV. 0
AD1955
R5
1.00kꢆ
12V
C10
100pF
R6
100ꢆ
R3
1.00kꢆ
R2
1.00kꢆ
U2-A
IOUTL+
IOUTR–
COMP
AD797
–3dB at 100 kHz
J1
+
R11
R9
C7
OUT
1.00kꢆ
1.00kꢆ
OPEN
NL–
C9
MONO
DIRECT
OUT
NL+
C12
390pF
100pF
–
C8
OPEN
U3-A
6VRMS
G
R10
1.00kꢆ
C13
470pF
C14
470pF
R12
1.00kꢆ
COMP
OUT
IOUTL–
IOUTR+
AD797
R4
402ꢆ
+12V
NL–
VBIAS
NL+
SET CONTROL REGISTER 0, BITS 11:10
TO SELECT LEFT OR RIGHT CHANNEL
NOTE REVERSE POLARITY
OF RIGHT CHANNEL OUTPUTS
R7
100ꢆ
C11
100pF
+
4.7ꢅF
4.7ꢅF
0.1ꢅF
0.1ꢅF
R8
1.00kꢆ
AD797
+
OP AMP BYPASS
DUPLICATE FOR EACH PART
–12V
Figure 11. Mono Differential Output
R27
1.00kꢆ
12V
C26
100pF
R28
100ꢆ
R24
R25
1.00kꢆ
C30
2.7nF
R37
U6-A
COMP
1.00kꢆ
R33
100ꢆ
IOUTL+
IOUTR–
226ꢆ
R31
681ꢆ
R34
324ꢆ
AD797
–3dB at 75 kHz
U8-A
C23
OUT
COMP
C28
5.6nF
OPEN
R38
332ꢆ
NL–
J3
C25
100pF
NL+
AD797
OUT
C24
U7-A
MONO
OPEN
C29
FILTER
OUT
C32
3.9nF
R39
OPEN
NL–
COMP
OUT
5.6nF
R32
681ꢆ
NL+
IOUTL–
2VRMS
AD797
R35
IOUTR+
VBIAS
324ꢆ
NL–
R36
226ꢆ
C31
2.7nF
NL+
R26
402ꢆ
SET CONTROL REGISTER 0, BITS 11:10
TO SELECT LEFT OR RIGHT CHANNEL
R29
100ꢆ
C27
100pF
NOTE REVERSE
POLARITY OF RIGHT
CHANNEL OUTPUTS
R30
1.00kꢆ
+12V
+
+
4.7ꢅF
4.7ꢅF
0.1ꢅF
0.1ꢅF
AD797
OP AMP BYPASS
DUPLICATE FOR EACH PART
–12V
Figure 12. Mono Single-Ended Output
–20–
REV. 0
AD1955
OUTLINE DIMENSIONS
Dimensions shown in millimeters
28-Lead Shrink Small Outline Package (SSOP)
(RS-28)
10.50
10.20
9.90
28
15
5.60 8.20
5.30 7.80
5.00 7.40
14
1
1.85
1.75
1.65
0.10
COPLANARITY
2.00 MAX
0.25
0.09
8ꢄ
4ꢄ
0ꢄ
0.95
0.75
0.55
0.38
0.22
0.65
BSC
0.05
MIN
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-150AH
REV. 0
–21–
–22–
–23–
–24–
相关型号：
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