EVAL-AD5666EB [ADI]
Quad, 16-Bit DAC with 5 ppm/C On-Chip Reference in 14-Lead TSSOP; 四， 16位DAC，为5ppm / C片内基准14引脚TSSOP
| 型号： | EVAL-AD5666EB |
| 厂家： | 
ADI |
| 描述： | Quad, 16-Bit DAC with 5 ppm/C On-Chip Reference in 14-Lead TSSOP |
| 文件： | 总28页 (文件大小：820K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Quad, 16-Bit DAC with 5 ppm/°C
On-Chip Reference in 14-Lead TSSOP
AD5666
FUNCTIONAL BLOCK DIAGRAM
FEATURES
Low power quad 16-bit DAC
14-lead TSSOP
On-chip 1.25 V/2.5 V, 5 ppm/°C reference
Power down to 400 nA @ 5 V, 200 nA @ 3 V
2.7 V to 5.5 V power supply
Guaranteed monotonic by design
Power-on reset to zero scale or midscale
3 power-down functions
V
/V
V
REFIN REFOUT
DD
AD5666
1.25V/2.5V
REF
LDAC
BUFFER
BUFFER
BUFFER
BUFFER
INPUT
REGISTER
DAC
STRING
DAC A
V
V
V
V
A
B
C
D
OUT
OUT
OUT
OUT
REGISTER
SCLK
INPUT
REGISTER
DAC
REGISTER
STRING
DAC B
INTERFACE
LOGIC
SYNC
DIN
DAC
REGISTER
STRING
DAC C
INPUT
REGISTER
DAC
REGISTER
STRING
DAC D
INPUT
REGISTER
SDO
POWER-DOWN
LOGIC
POWER-ON
RESET
Hardware LDAC with LDAC override function
CLR function to programmable code
SDO daisy-chaining option
POR
GND
LDAC CLR
Figure 1.
Rail-to-rail operation
APPLICATIONS
Process control
Data acquisition systems
Portable battery-powered instruments
Digital gain and offset adjustment
Programmable voltage and current sources
Programmable attenuators
GENERAL DESCRIPTION
The AD5666 is a low power, quad, 16-bit, buffered voltage-
output DAC. The part operates from a single 2.7 V to 5.5 V
supply and is guaranteed monotonic by design.
The outputs of all DACs can be updated simultaneously using
the function, with the added functionality of user-select-
LDAC
able DAC channels to simultaneously update. There is also an
asynchronous that clears all DACs to a software-selectable
CLR
The AD5666 has an on-chip reference with an internal gain of 2.
The AD5666-1 has a 1.25 V 5 ppm/°C reference, giving a full-scale
output of 2.5 V; the AD5666-2 has a 2.5 V 5 ppm/°C reference,
giving a full-scale output of 5 V. The on-board reference is off at
power-up, allowing the use of an external reference. The internal
reference is turned on by writing to the DAC.
code—0 V, midscale, or full scale.
The AD5666 utilizes a versatile 3-wire serial interface that operates
at clock rates of up to 50 MHz and is compatible with standard
SPI®, QSPI™, MICROWIRE™, and DSP interface standards. The
on-chip precision output amplifier enables rail-to-rail output
swing.
The part incorporates a power-on reset circuit that ensures that
the DAC output powers up to 0 V (POR pin low) or to midscale
(POR pin high) and remains powered up at this level until a valid
write takes place. The part contains a power-down feature that
reduces the current consumption of the device to 400 nA at 5 V
and provides software-selectable output loads while in power-down
mode for any or all DAC channels.
PRODUCT HIGHLIGHTS
1. Quad, 16-bit DAC.
2. On-chip 1.25 V/2.5 V, 5 ppm/°C reference.
3. Available in 14-lead TSSOP.
4. Selectable power-on reset to 0 V or midscale.
5. Power-down capability. When powered down, the DAC
typically consumes 200 nA at 3 V and 400 nA at 5 V.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
© 2005 Analog Devices, Inc. All rights reserved.
AD5666
TABLE OF CONTENTS
Features .............................................................................................. 1
Resistor String............................................................................. 20
Internal Reference ...................................................................... 20
Output Amplifier........................................................................ 21
Serial Interface............................................................................ 21
Input Shift Register .................................................................... 22
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
AC Characteristics........................................................................ 7
Timing Characteristics ................................................................ 8
Absolute Maximum Ratings.......................................................... 10
ESD Caution................................................................................ 10
Pin Configuration and Function Descriptions........................... 11
Typical Performance Characteristics ........................................... 12
Terminology .................................................................................... 18
Theory of Operation ...................................................................... 20
D/A Section................................................................................. 20
Interrupt .......................................................................... 22
SYNC
Daisy-Chaining........................................................................... 23
Internal Reference Register....................................................... 23
Power-On Reset.......................................................................... 23
Power-Down Modes .................................................................. 23
Clear Code Register ................................................................... 25
Function .......................................................................... 25
LDAC
Power Supply Bypassing and Grounding................................ 25
Outline Dimensions....................................................................... 27
Ordering Guide .......................................................................... 27
REVISION HISTORY
11/05—Rev. 0 to Rev. A
Change to General Description...................................................... 1
Change to Specifications.................................................................. 3
10/05—Revision 0: Initial Version
Rev. A | Page 2 of 28
AD5666
SPECIFICATIONS
VDD = 4.5 V to 5.5 V, RL = 2 kΩ to GND, CL = 200 pF to GND, VREFIN = VDD. All specifications TMIN to TMAX, unless otherwise noted.
Table 1.
A Grade1
Typ
B Grade1
Typ
Parameter
STATIC PERFORMANCE2
Min
Max
Min
Max
Unit
Conditions/Comments
Resolution
Relative Accuracy
Differential Nonlinearity
16
16
Bits
LSB
LSB
32
1
16
1
See Figure 6
Guaranteed monotonic by design
(see Figure 7)
Zero-Code Error
Zero-Code Error Drift
Full-Scale Error
Gain Error
Gain Temperature Coefficient
Offset Error
1
9
1
9
mV
All 0s loaded to DAC register (see Figure 13)
All 1s loaded to DAC register (see Figure 12)
Of FSR/°C
2
2
μV/°C
% FSR
% FSR
ppm
mV
−0.2
−1
1
−0.2
−1
1
2.ꢀ
1
2.ꢀ
1
9
9
DC Power Supply Rejection
Ratio
–80
–80
dB
VDD 10%
DC Crosstalk
(External Reference)
10
10
μV
Due to full-scale output change,
RL = 2 kΩ to GND or VDD
ꢀ
10
2ꢀ
ꢀ
10
2ꢀ
μV/mA
μV
μV
Due to load current change
Due to powering down (per channel)
Due to full-scale output change,
RL = 2 kΩ to GND or VDD
DC Crosstalk
(Internal Reference)
10
10
μV/mA
Due to load current change
OUTPUT CHARACTERISTICS3
Output Voltage Range
0
VDD
0
VDD
V
Capacitive Load Stability
2
2
nF
nF
Ω
mA
μs
RL = ∞
RL = 2 kΩ
10
0.ꢀ
30
4
10
0.ꢀ
30
4
DC Output Impedance
Short-Circuit Current
Power-Up Time
VDD = ꢀ V
Coming out of power-down mode VDD = ꢀ V
REFERENCE INPUTS
Reference Input Voltage
Reference Current
Reference Input Range
Reference Input Impedance
REFERENCE OUTPUT
Output Voltage
Reference TC3
Reference Output
Impedance
VDD
20
VDD
20
V
μA
V
30
VDD
30
VDD
VREF = VDD = ꢀ.ꢀ V
Per DAC channel
At ambient
0
0
14.6
14.6
kΩ
2.49ꢀ
2.ꢀ0ꢀ 2.49ꢀ
10
2.ꢀ0ꢀ
10
V
ꢀ
7.ꢀ
ꢀ
7.ꢀ
ppm/°C
kΩ
LOGIC INPUTS3
Input Current
3
0.8
2
3
0.8
μA
V
V
All digital inputs
VDD = ꢀ V
VDD = ꢀ V
Input Low Voltage, VINL
Input High Voltage, VINH
Pin Capacitance
2
3
3
pF
Rev. A | Page 3 of 28
AD5666
A Grade1
Typ
B Grade1
Typ
Parameter
Min
Max
Min
Max
Unit
Conditions/Comments
LOGIC OUTPUTS (SDO)3
Output Low Voltage, VOL
Output High Voltage, VOH
0.4
0.4
V
ISINK = 2 mA
ISOURCE = 2 mA
VDD
1
−
VDD
1
−
High Impedance Leakage
Current
0.2ꢀ
0.2ꢀ ꢁA
High Impedance Output
Capacitance
2
2
pF
POWER REQUIREMENTS
VDD
4.ꢀ
ꢀ.ꢀ
4.ꢀ
ꢀ.ꢀ
V
All digital inputs at 0 or VDD,
DAC active, excludes load current
VIH = VDD and VIL = GND
Internal reference off
IDD (Normal Mode)4
VDD = 4.ꢀ V to ꢀ.ꢀ V
VDD = 4.ꢀ V to ꢀ.ꢀ V
IDD (All Power-Down Modes)ꢀ
0.7
1.3
0.9
1.6
0.7
1.3
0.9
1.6
mA
mA
Internal reference on
VDD = 4.ꢀ V to ꢀ.ꢀ V
0.4
1
0.4
1
μA
VIH = VDD and VIL = GND
1 Temperature range is −40°C to +10ꢀ°C, typical at 2ꢀ°C.
2 Linearity calculated using a reduced code range of ꢀ12 to 6ꢀ,024. Output unloaded.
3 Guaranteed by design and characterization; not production tested.
4 Interface inactive. All DACs active. DAC outputs unloaded.
ꢀ All four DACs powered down.
Rev. A | Page 4 of 28
AD5666
VDD = 2.7 V to 3.6 V, RL = 2 kΩ to GND, CL = 200 pF to GND, VREFIN = VDD. All specifications TMIN to TMAX, unless otherwise noted.
Table 2.
A Grade1
Typ Max
B Grade1
Typ Max
Parameter
STATIC PERFORMANCE2
Min
Min
Unit
Conditions/Comments
Resolution
16
16
Bits
Relative Accuracy
Differential Nonlinearity
Zero-Code Error
Zero-Code Error Drift
Full-Scale Error
Gain Error
Gain Temperature
Coefficient
32
1
16
1
LSB
LSB
mV
μV/°C
% FSR
% FSR
ppm
See Figure ꢀ
Guaranteed monotonic by design (see Figure 6)
All 0s loaded to DAC register (see Figure 13)
1
9
1
9
2
2
−0.2 −1
−0.2 −1
All 1s loaded to DAC register (see Figure 12)
Of FSR/°C
1
1
2.ꢀ
2.ꢀ
Offset Error
DC Power Supply Rejection
Ratio
1
–80
9
1
–80
9
mV
dB
VDD 10%
DC Crosstalk
(External Reference)
10
10
μV
Due to full-scale output change,
RL = 2 kΩ to GND or VDD
ꢀ
10
2ꢀ
ꢀ
10
2ꢀ
μV/mA
μV
μV
Due to load current change
Due to powering down (per channel)
Due to full-scale output change,
RL = 2 kΩ to GND or VDD
DC Crosstalk
(Internal Reference)
10
10
μV/mA
Due to load current change
OUTPUT CHARACTERISTICS3
Output Voltage Range
0
VDD
0
VDD
V
Capacitive Load Stability
2
2
nF
nF
Ω
mA
ꢁs
RL = ∞
RL = 2 kΩ
10
0.ꢀ
30
4
10
0.ꢀ
30
4
DC Output Impedance
Short-Circuit Current
Power-Up Time
VDD = 3 V coming out of power-down mode
Coming out of power-down VDD = 3 V
REFERENCE INPUTS
Reference Input Voltage
Reference Current
Reference Input Range
Reference Input Impedance
REFERENCE OUTPUT
Output Voltage
Reference TC3
Reference Output
Impedance
VDD
40
VDD
40
V
μA
ꢀ0
VDD
ꢀ0
VDD
VREF = VDD = 3.6 V
Per DAC channel
At ambient
0
0
14.6
14.6
kΩ
1.247
1.2ꢀ3 1.247
1ꢀ
1.2ꢀ3
1ꢀ
V
ꢀ
7.ꢀ
ꢀ
7.ꢀ
ppm/°C
kΩ
LOGIC INPUTS3
Input Current
3
0.8
2
3
0.8
μA
V
V
Input Low Voltage, VINL
Input High Voltage, VINH
Pin Capacitance
LOGIC OUTPUTS (SDO)3
Output Low Voltage, VOL
Output High Voltage, VOH
VDD = 3 V
VDD = 3 V
2
3
2
3
pF
0.4
0.4
V
ISINK = 2 mA
ISOURCE = 2 mA
VDD
0.ꢀ
−
VDD
0.ꢀ
−
High Impedance Leakage
Current
High Impedance Leakage
Current
0.2ꢀ
0.2ꢀ ꢁA
pF
2
Rev. A | Page ꢀ of 28
AD5666
A Grade1
Typ Max
B Grade1
Typ Max
Parameter
Min
Min
Unit
Conditions/Comments
POWER REQUIREMENTS
VDD
2.7
3.6
2.7
3.6
V
All digital inputs at 0 or VDD,
DAC active, excludes load current
VIH = VDD and VIL = GND
Internal reference off
IDD (Normal Mode)4
VDD = 2.7 V to 3.6 V
VDD = 2.7 V to 3.6 V
IDD (All Power-Down Modes)ꢀ
0.6ꢀ 0.8ꢀ
0.6ꢀ 0.8ꢀ
mA
mA
1.3
1.ꢀ
1.3
1.ꢀ
Internal reference on
VDD = 2.7 V to 3.6 V
0.2
1
0.2
1
μA
VIH = VDD and VIL = GND
1 Temperature range is −40°C to +10ꢀ°C, typical at 2ꢀ°C.
2 Linearity calculated using a reduced code range of ꢀ12 to 6ꢀ,024. Output unloaded.
3 Guaranteed by design and characterization; not production tested.
4 Interface inactive. All DACs active. DAC outputs unloaded.
ꢀ All four DACs powered down.
Rev. A | Page 6 of 28
AD5666
AC CHARACTERISTICS
VDD =2.7V to 5.5 V, RL = 2 kΩ to GND, CL = 200 pF to GND, VREFIN = VDD. All specifications TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter1, 2
Min Typ
Max
Unit
μs
V/μs
nV-s
dB
nV-s
nV-s
nV-s
nV-s
nV-s
kHz
Conditions/Comments3
Output Voltage Settling Time
Slew Rate
Digital-to-Analog Glitch Impulse
Reference Feedthrough
SDO Feedthrough
Digital Feedthrough
Digital Crosstalk
Analog Crosstalk
DAC-to-DAC Crosstalk
Multiplying Bandwidth
Total Harmonic Distortion
Output Noise Spectral Density
6
1.ꢀ
4
−90
3
0.1
0.ꢀ
2.ꢀ
3
340
−80
120
100
1ꢀ
10
¼ to ¾ scale settling to 2 LSB
1 LSB change around major carry (see Figure 29)
VREF = 2 V 0.1 V p-p, frequency = 10 Hz to 20 MHz
Daisy-chain mode; SDO load is 10 pF
VREF = 2 V 0.2 V p-p
dB
VREF = 2 V 0.1 V p-p, frequency = 10 kHz
DAC code = 0x8400, 1 kHz
DAC code = 0x8400, 10 kHz
0.1 Hz to 10 Hz
nV/√Hz
nV/√Hz
ꢁV p-p
Output Noise
1 Guaranteed by design and characterization; not production tested.
2 See the Terminology section.
3 Temperature range is −40°C to + 10ꢀ°C, typical at 2ꢀ°C.
Rev. A | Page 7 of 28
AD5666
TIMING CHARACTERISTICS
All input signals are specified with tr = tf = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See Figure 3 and
Figure 5. VDD = 2.7 V to 5.5 V. All specifications TMIN to TMAX, unless otherwise noted.
Table 4.
Limit at TMIN, TMAX
Parameter
VDD = 2.7 V to 5.5 V
Unit
Conditions/Comments
1
t1
t2
t3
t4
20
8
8
13
4
4
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns typ
ns max
ns min
ns min
ns min
SCLK cycle time
SCLK high time
SCLK low time
SYNC to SCLK falling edge set-up time
Data set-up time
tꢀ
t6
t7
Data hold time
0
SCLK falling edge to SYNC rising edge
Minimum SYNC high time
SYNC rising edge to SCLK fall ignore
SCLK falling edge to SYNC fall ignore
LDAC pulse width low
t8
1ꢀ
13
0
t9
t10
t11
t12
t13
t14
t1ꢀ
10
1ꢀ
ꢀ
SCLK falling edge to LDAC rising edge
CLR pulse width low
0
SCLK falling edge to LDAC falling edge
CLR pulse activation time
300
22
ꢀ
2, 3
t16
t17
SCLK rising edge to SDO valid
SCLK falling edge to SYNC rising edge
SYNC rising edge to SCLK rising edge
SYNC rising edge to LDAC falling edge
3
3
t18
8
3
t19
0
1 Maximum SCLK frequency is ꢀ0 MHz at VDD = 2.7 V to ꢀ.ꢀ V. Guaranteed by design and characterization; not production tested.
2 Measured with the load circuit of Figure 16. t16 determines the maximum SCLK frequency in daisy-chain mode.
3 Daisy-chain mode only.
2mA
I
OL
TO OUTPUT
PIN
V
(MIN)
OH
C
L
50pF
2mA
I
OH
Figure 2. Load Circuit for Digital Output (SDO) Timing Specifications
Rev. A | Page 8 of 28
AD5666
t10
t1
t9
SCLK
SYNC
DIN
t2
t8
t7
t3
t4
t6
t5
DB31
DB0
t14
t11
1
LDAC
t12
2
LDAC
t13
CLR
1
2
ASYNCHRONOUS LDAC UPDATE MODE
SYNCHRONOUS LDAC UPDATE MODE
Figure 3. Serial Write Operation
t1
SCLK
32
64
t18
t3
t2
t7
t4
t17
SYNC
DIN
t8
t9
DB0
DB31
DB0
DB31
INPUT WORD FOR DAC N
INPUT WORD FOR DAC N + 1
INPUT WORD FOR DAC N
t16
DB31
DB0
SDO
UNDEFINED
t19
t11
LDAC
Figure 4. Daisy-Chain Timing Diagram
Rev. A | Page 9 of 28
AD5666
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 5.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Parameter
Rating
VDD to GND
−0.3 V to +7 V
Digital Input Voltage to GND
VOUT to GND
VREFIN/VREFOUT to GND
Operating Temperature Range
Industrial
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
−40°C to +10ꢀ°C
−6ꢀ°C to +1ꢀ0°C
+1ꢀ0°C
Storage Temperature Range
Junction Temperature (TJ MAX
)
TSSOP Package
Power Dissipation
θJA Thermal Impedance
(TJ MAX − TA)/θJA
1ꢀ0.4°C/W
Reflow Soldering Peak Temperature
SnPb
Pb Free
240°C
260°C
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. A | Page 10 of 28
AD5666
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
LDAC
14
13
12
11
10
9
SCLK
DIN
SYNC
V
GND
DD
AD5666
TOP VIEW
(Not to Scale)
V
V
A
C
V
V
B
D
OUT
OUT
OUT
OUT
POR
CLR
SDO
8
V
/V
REFIN REFOUT
Figure 5. 14-Lead TSSOP (RU-14)
Table 6. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
LDAC
Pulsing this pin low allows any or all DAC registers to be updated if the input registers have new data.
This allows all DAC outputs to simultaneously update. Alternatively, this pin can be tied permanently low.
2
SYNC
Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes
low, it powers on the SCLK and DIN buffers and enables the input shift register. Data is transferred in
on the falling edges of the next 32 clocks. If SYNC is taken high before the 32nd falling edge, the rising
edge of SYNC acts as an interrupt and the write sequence is ignored by the device.
3
VDD
Power Supply Input. These parts can be operated from 2.7 V to ꢀ.ꢀ V, and the supply should be decoupled
with a 10 μF capacitor in parallel with a 0.1 μF capacitor to GND.
4
ꢀ
6
VOUT
VOUT
POR
A
C
Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation.
Power-on Reset Pin. Tying this pin to GND powers up the part to 0 V. Tying this pin to VDD powers up
the part to midscale.
7
8
9
VREFIN/VREFOUT
The ADꢀ666 has a common pin for reference input and reference output. When using the internal
reference, this is the reference output pin. When using an external reference, this is the reference input
pin. The default for this pin is as a reference input.
Serial Data Output. Can be used for daisy-chaining a number of these devices together or for reading
back the data in the shift register for diagnostic purposes. The serial data is transferred on the rising edge
of SCLK and is valid on the falling edge of the clock.
Asynchronous Clear Input. The CLR input is falling edge sensitive. When CLR is low, all LDAC pulses are
ignored. When CLR is activated, the input register and the DAC register are updated with the data
contained in the CLR code register—zero, midscale, or full scale. Default setting clears the output to 0 V.
SDO
CLR
10
11
12
13
VOUT
VOUT
GND
DIN
D
B
Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.
Ground Reference Point for All Circuitry on the Part.
Serial Data Input. This device has a 32-bit shift register. Data is clocked into the register on the falling
edge of the serial clock input.
14
SCLK
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input.
Data can be transferred at rates of up to ꢀ0 MHz.
Rev. A | Page 11 of 28
AD5666
TYPICAL PERFORMANCE CHARACTERISTICS
1.0
0.8
0.6
0.4
0.2
V
V
= 5V
DD
10
= 2.5V
REFOUT
V
= V
= 5V
DD
REF
TA = 25°C
8
T
= 25°C
A
6
4
2
0
0
–2
–4
–0.2
–0.4
–0.6
–6
–8
–0.8
–1.0
–10
0
5k 10k 15k 20k 25k 30k 35k 40k 45k 50k 55k 60k 65k
CODE
CODE
Figure 9. DNL—AD5666-2
Figure 6. INL
10
V
V
= 3V
DD
REFOUT
1.0
8
6
= 1.25V
V
= V
= 25°C
= 5V
DD
REF
T
= 25°C
A
0.8
0.6
0.4
0.2
T
A
4
2
0
0
–2
–4
–6
–0.2
–0.4
–0.6
–8
–0.8
–1.0
–10
0
10k
20k
30k
CODE
40k
50k
60k
CODE
Figure 7. DNL
Figure 10. INL—AD5666-1
1.0
10
8
V
V
T
= 3V
V
V
= 5V
DD
DD
0.8
0.6
= 1.25V
= 2.5V
REFOUT
= 25°C
REFOUT
TA = 25°C
A
6
0.4
4
0.2
2
0
0
–0.2
–0.4
–0.6
–2
–4
–6
–0.8
–1.0
–8
–10
CODE
CODE
Figure 8. INL—AD5666-2
Figure 11. DNL—AD5666-1
Rev. A | Page 12 of 28
AD5666
1.0
0
–0.02
–0.04
–0.06
–0.08
V
= 5V
T
= 25°C
DD
A
0.5
0
ZERO-SCALE ERROR
GAIN ERROR
–0.5
–1.0
–1.5
–0.10
–0.12
–0.14
–0.16
FULL-SCALE ERROR
–2.0
–2.5
OFFSET ERROR
–0.18
–0.20
2.7
3.2
3.7
4.2
(V)
4.7
5.2
–40
–20
0
20
40
60
80
100
V
TEMPERATURE (°C)
DD
Figure 12. Gain Error and Full-Scale Error vs. Temperature
Figure 15. Zero-Scale Error and Offset Error vs. Supply Voltage
3.5
1.5
V
V
= 3.6V
= 5.5V
DD
DD
1.0
3.0
2.5
2.0
1.5
1.0
0.5
0
ZERO-SCALE ERROR
0.5
0
–0.5
–1.0
–1.5
–2.0
–2.5
OFFSET ERROR
0.62 0.63 0.64 0.65 0.66 0.67 0.68 0.69 0.7 0.71 0.72
(mA)
–40
–20
0
20
40
60
80
100
I
TEMPERATURE (°C)
DD
Figure 13. Zero-Scale Error and Offset Error vs. Temperature
Figure 16. IDD Histogram with External Reference
2.5
2.0
1.5
1.0
0.5
0
1.0
0.5
V
V
= 3.6V
= 5.5V
DD
DD
GAIN ERROR
0
FULL-SCALE ERROR
–0.5
–1.0
–1.5
–2.0
1.26
1.28
1.30
1.32
1.34
1.36
1.38
2.7
3.2
3.7
4.2
(V)
4.7
5.2
I
(mA)
V
DD
DD
Figure 17. IDD Histogram with Internal Reference
Figure 14. Gain Error and Full-Scale Error vs. Supply Voltage
Rev. A | Page 13 of 28
AD5666
0.50
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
T
= 25°C
V
= V
= 5V
A
DAC LOADED WITH
FULL-SCALE
SOURCING CURRENT
DAC LOADED WITH
ZERO-SCALE
SINKING CURRENT
DD
REF
0.40
0.30
0.20
0.10
0
V
V
= 3V
DD
V
= V
= 3V
= 1.25V
DD
REF
REFOUT
–0.10
–0.20
–0.30
–0.40
V
V
= 5V
DD
= 2.5V
–2
REFOUT
–0.50
–10
–8
–6
–4
0
2
4
6
8
10
512
10512
20512
30512
CODE
40512
50512
60512
CURRENT (mA)
Figure 18. Headroom at Rails vs. Source and Sink
Figure 21. Supply Current vs. Code
6.00
5.00
4.00
3.00
2.00
1.00
0
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
V
V
= 5V
DD
FULL SCALE
= 2.5V
REFOUT
= 25°C
V
= V
= 5.5V
DD
REFIN
T
A
3/4 SCALE
V
= V
= 3.6V
MIDSCALE
1/4 SCALE
DD
REFIN
ZERO SCALE
–1.00
–30
–20
–10
0
10
20
30
–40
–20
0
20
40
60
80
100
CURRENT (mA)
TEMPERATURE (°C)
Figure 19. Source and Sink Current Capability with VDD = 3 V
Figure 22. Supply Current vs. Temperature
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
4.00
T
= 25°C
A
V
V
= 3V
DD
= 1.25V
REFOUT
= 25°C
T
A
3.00
2.00
1.00
FULL SCALE
3/4 SCALE
MIDSCALE
1/4 SCALE
0
ZERO SCALE
–1.00
2.7
3.2
3.7
4.2
(V)
4.7
5.2
–30
–20
–10
0
10
20
30
V
CURRENT (mA)
DD
Figure 20. Source and Sink Current Capability with VDD = 5 V
Figure 23. Supply Current vs. Supply Voltage
Rev. A | Page 14 of 28
AD5666
4.0
3.5
T
= 25°C
A
V
= V = 5V
REF
DD
= 25°C
T
A
3.0
2.5
2.0
V
DD
1
2
V
= 5V
DD
1.5
1.0
0.5
0
V
OUT
V
= 3V
DD
0
1
2
3
4
5
6
CH1 2.0V
CH2 1.0V
M100μs 125MS/s
A CH1 1.28V
8.0ns/pt
V
(V)
LOGIC
Figure 27. Power-On Reset to Midscale
Figure 24. Supply Current vs. Logic Input Voltage
SYNC
SLCK
1
3
V
= V = 5V
REF
DD
= 25°C
T
A
FULL-SCALE CODE CHANGE
0x0000 TO 0xFFFF
OUTPUT LOADED WITH 2kΩ
AND 200pF TO GND
V
OUT
V
= 909mV/DIV
OUT
V
= 5V
DD
2
1
CH1 5.0V
CH3 5.0V
CH2 500mV
M400ns
A CH1
1.4V
TIME BASE = 4μs/DIV
Figure 28. Exiting Power-Down to Midscale
Figure 25. Full-Scale Settling Time
2.505
2.504
2.503
2.502
2.501
2.500
2.499
2.498
2.497
2.496
2.495
2.494
2.493
2.492
2.491
2.490
2.489
2.488
2.487
2.486
2.485
V
V
= 5V
DD
REFOUT
= 25°C
V
= V = 5V
REF
DD
= 25°C
= 2.5V
T
A
T
A
4ns/SAMPLE NUMBER
GLITCH IMPULSE = 3.55nV-s
1 LSB CHANGE AROUND
MIDSCALE (0x8000 TO 0x7FFF)
V
DD
1
2
MAX(C2)*
420.0mV
V
OUT
0
64
128
192
256
SAMPLE
320
384
448
512
CH1 2.0V
CH2 500mV
M100μs 125MS/s
A CH1 1.28V
8.0ns/pt
Figure 29. Digital-to-Analog Glitch Impulse
Figure 26. Power-On Reset to 0 V
Rev. A | Page 1ꢀ of 28
AD5666
2.5000
2.4995
2.4990
2.4985
2.4980
2.4975
2.4970
2.4965
2.4960
2.4955
V
V
= 5V
DD
REFOUT
= 25°C
= 2.5V
T
A
DAC LOADED WITH MIDSCALE
1
V
V
= 5V
DD
REFOUT
= 25°C
= 2.5V
T
A
4ns/SAMPLE NUMBER
2.4950
0
64
128
192
256
320 384 448 512
5s/DIV
SAMPLE
Figure 33. 0.1 Hz to 10 Hz Output Noise Plot, Internal Reference
Figure 30. Analog Crosstalk
2.4900
2.4895
2.4890
2.4885
2.4880
2.4875
2.4870
2.4865
2.4860
V
V
= 3V
DD
REFOUT
= 25°C
= 1.25V
T
A
DAC LOADED WITH MIDSCALE
1
V
V
= 5V
DD
REFOUT
= 25°C
= 2.5V
T
A
4ns/SAMPLE NUMBER
2.4855
0
64
128
192
256
320 384 448 512
SAMPLE
4s/DIV
Figure 34. 0.1 Hz to 10 Hz Output Noise Plot, Internal Reference
Figure 31. DAC-to-DAC Crosstalk
800
T
= 25°C
A
MIDSCALE LOADED
700
600
500
400
300
200
V
= V
REF
= 5V
DD
= 25°C
T
A
DAC LOADED WITH MIDSCALE
1
V
V
= 5V
DD
REFOUT
= 2.5V
100
0
V
V
= 3V
DD
REFOUT
= 1.25V
1000
Y AXIS = 2μV/DIV
X AXIS = 4s/DIV
100
10000
FREQUENCY (Hz)
100000
1000000
Figure 35. Noise Spectral Density, Internal Reference
Figure 32. 0.1 Hz to 10 Hz Output Noise Plot, External Reference
Rev. A | Page 16 of 28
AD5666
–20
–30
–40
V
= 5V
= 25°C
DD
T
A
DAC LOADED WITH FULL SCALE
V
CLR
3
= 2V ± 0.3Vp-p
REF
V
F
–50
–60
–70
OUT
–80
V
B
OUT
4
2
–90
–100
2k
4k
6k
8k
10k
CH2 1.0V
CH4 1.0V
M200ns A CH3
1.10V
CH3 5.0V
FREQUENCY (Hz)
CLR
Figure 36. Total Harmonic Distortion
Figure 38. Hardware
5
0
16
14
12
10
8
V
A
= 5V
DD
V
T
= V
DD
= 25°C
REF
T
= 25°C
A
–5
V
= 3V
DD
–10
–15
–20
–25
–30
–35
–40
V
=
5V
DD
6
4
0
1
2
3
4
5
6
7
8
9
10
10k
100k
1M
10M
CAPACITANCE (nF)
FREQUENCY (Hz)
Figure 37. Settling Time vs. Capacitive Load
Figure 39. Multiplying Bandwidth
Rev. A | Page 17 of 28
AD5666
TERMINOLOGY
Relative Accuracy
Full-Scale Error
For the DAC, relative accuracy, or integral nonlinearity (INL), is
a measure of the maximum deviation in LSBs from a straight
line passing through the endpoints of the DAC transfer
function. Figure 6 shows a plot of typical INL vs. code.
Full-scale error is a measure of the output error when full-scale
code (0xFFFF) is loaded into the DAC register. Ideally, the
output should be VDD − 1 LSB. Full-scale error is expressed as a
percentage of the full-scale range. Figure 13 shows a plot of
typical full-scale error vs. temperature.
Differential Nonlinearity
Differential nonlinearity (DNL) is the difference between the
measured change and the ideal 1 LSB change between any two
adjacent codes. A specified differential nonlinearity of 1 LSB
maximum ensures monotonicity. This DAC is guaranteed mono-
tonic by design. Figure 7 shows a plot of typical DNL vs. code.
Digital-to-Analog Glitch Impulse
Digital-to-analog glitch impulse is the impulse injected into the
analog output when the input code in the DAC register changes
state. It is normally specified as the area of the glitch in nV-s
and is measured when the digital input code is changed by
1 LSB at the major carry transition (0x7FFF to 0x8000). See
Figure 29.
Offset Error
Offset error is a measure of the difference between the actual
VOUT and the ideal VOUT, expressed in millivolts in the linear
region of the transfer function. Offset error is measured on the
AD5666 with Code 512 loaded into the DAC register. It can be
negative or positive and is expressed in millivolts.
DC Power Supply Rejection Ratio (PSRR)
PSRR indicates how the output of the DAC is affected by changes
in the supply voltage. PSRR is the ratio of the change in VOUT to
a change in VDD for full-scale output of the DAC. It is measured
in decibels. VREF is held at 2 V, and VDD is varied 10%.
Zero-Code Error
Zero-code error is a measure of the output error when zero
code (0x0000) is loaded into the DAC register. Ideally, the
output should be 0 V. The zero-code error is always positive in
the AD5666, because the output of the DAC cannot go below 0 V.
It is due to a combination of the offset errors in the DAC and
output amplifier. Zero-code error is expressed in millivolts.
Figure 13 shows a plot of typical zero-code error vs.
temperature.
DC Crosstalk
DC crosstalk is the dc change in the output level of one DAC in
response to a change in the output of another DAC. It is measured
with a full-scale output change on one DAC (or soft power-down
and power-up) while monitoring another DAC kept at midscale.
It is expressed in microvolts.
DC crosstalk due to load current change is a measure of the
impact that a change in load current on one DAC has to another
DAC kept at midscale. It is expressed in microvolts per milliamp.
Gain Error
Gain error is a measure of the span error of the DAC. It is the
deviation in slope of the DAC transfer characteristic from the
ideal, expressed as a percentage of the full-scale range.
Reference Feedthrough
Reference feedthrough is the ratio of the amplitude of the signal
at the DAC output to the reference input when the DAC output
is not being updated (that is,
decibels.
is high). It is expressed in
LDAC
Zero-Code Error Drift
Zero-code error drift is a measure of the change in zero-code
error with a change in temperature. It is expressed in μV/°C.
Digital Feedthrough
Digital feedthrough is a measure of the impulse injected into
the analog output of a DAC from the digital input pins of the
device, but is measured when the DAC is not being written to
Gain Error Drift
Gain error drift is a measure of the change in gain error with
changes in temperature. It is expressed in (ppm of full-scale
range)/°C.
(
held high). It is specified in nV-s and measured with a
SYNC
full-scale change on the digital input pins, that is, from all 0s to
all 1s or vice versa.
Rev. A | Page 18 of 28
AD5666
Digital Crosstalk
Multiplying Bandwidth
Digital crosstalk is the glitch impulse transferred to the output
of one DAC at midscale in response to a full-scale code change
(all 0s to all 1s or vice versa) in the input register of another
DAC. It is measured in standalone mode and is expressed in
nV-s.
The amplifiers within the DAC have a finite bandwidth. The
multiplying bandwidth is a measure of this. A sine wave on the
reference (with full-scale code loaded to the DAC) appears on
the output. The multiplying bandwidth is the frequency at
which the output amplitude falls to 3 dB below the input.
Analog Crosstalk
Total Harmonic Distortion (THD)
Analog crosstalk is the glitch impulse transferred to the output
of one DAC due to a change in the output of another DAC. It is
measured by loading one of the input registers with a full-scale
Total harmonic distortion is the difference between an ideal
sine wave and its attenuated version using the DAC. The sine
wave is used as the reference for the DAC, and the THD is a
measure of the harmonics present on the DAC output. It is
measured in decibels.
code change (all 0s to all 1s or vice versa) while keeping
LDAC
high, and then pulsing
low and monitoring the output of
LDAC
the DAC whose digital code has not changed. The area of the
glitch is expressed in nV-s.
DAC-to-DAC Crosstalk
DAC-to-DAC crosstalk is the glitch impulse transferred to the
output of one DAC due to a digital code change and subsequent
output change of another DAC. This includes both digital and
analog crosstalk. It is measured by loading one of the DACs
with a full-scale code change (all 0s to all 1s or vice versa) with
low and monitoring the output of another DAC. The
LDAC
energy of the glitch is expressed in nV-s.
Rev. A | Page 19 of 28
AD5666
THEORY OF OPERATION
D/A SECTION
R
R
R
The AD5666 DAC is fabricated on a CMOS process. The archi-
tecture consists of a string of DACs followed by an output buffer
amplifier. The parts include an internal 1.25 V/2.5 V, 5 ppm/°C
reference with an internal gain of 2. Figure 40 shows a block
diagram of the DAC architecture.
TO OUTPUT
AMPLIFIER
V
DD
REF (+)
RESISTOR
STRING
V
DAC REGISTER
OUT
OUTPUT
AMPLIFIER
(GAIN = +2)
REF (–)
R
R
GND
Figure 40. DAC Architecture
Because the input coding to the DAC is straight binary, the ideal
output voltage when using an external reference is given by
Figure 41. Resistor String
INTERNAL REFERENCE
D
⎛
⎜
⎝
⎞
⎟
⎠
VOUT =VREFIN
×
2N
The AD5666 has an on-chip reference with an internal gain of 2.
The AD5666-1 has a 1.25 V 5 ppm/°C reference, giving a full-scale
output of 2.5 V. The AD5666-2 has a 2.5 V 5 ppm/°C reference,
giving a full-scale output of 5 V. The on-board reference is off at
power-up, allowing the use of an external reference. The internal
reference is enabled via a write to a control register.
The ideal output voltage when using and internal reference is
given by
D
⎛
⎜
⎝
⎞
⎟
⎠
VOUT = 2×VREFOUT
×
2N
The internal reference associated with each part is available at
the VREFOUT pin. A buffer is required if the reference output is
used to drive external loads. When using the internal reference,
it is recommended that a 100 nF capacitor be placed between
the reference output and GND for reference stability.
where:
D = decimal equivalent of the binary code that is loaded to the
DAC register.
0 to 65,535 for AD5666 (16 bits).
N = the DAC resolution.
Individual channel power-down is not supported while using
the internal reference.
RESISTOR STRING
The resistor string section is shown in Figure 41. It is simply a
string of resistors, each of value R. The code loaded into the
DAC register determines at which node on the string the
voltage is tapped off to be fed into the output amplifier. The
voltage is tapped off by closing one of the switches connecting
the string to the amplifier. Because it is a string of resistors, it is
guaranteed monotonic.
Rev. A | Page 20 of 28
AD5666
Table 7. Command Definitions
Command
OUTPUT AMPLIFIER
The output buffer amplifier can generate rail-to-rail voltages on
its output, which gives an output range of 0 V to VDD. The
amplifier is capable of driving a load of 2 kΩ in parallel with
1000 pF to GND. The source and sink capabilities of the output
amplifier can be seen in Figure 19 and Figure 20. The slew rate
is 1.5 V/ꢀs with a ¼ to ¾ scale settling time of 10 ꢀs.
C3 C2 C1 C0 Description
0
0
0
0
0
0
0
0
1
0
1
0
Write to Input Register n
Update DAC Register n
Write to Input Register n, update all
(software LDAC)
0
0
0
0
0
1
1
–
1
0
1
1
1
1
0
0
–
1
1
0
0
1
1
0
0
–
1
1
0
1
0
1
0
1
–
1
Write to and update DAC Channel n
Power down/power up DAC
Load clear code register
Load LDAC register
Reset (power-on reset)
Set up DCEN/REF register
Reserved
SERIAL INTERFACE
The AD5666 has a 3-wire serial interface (
, SCLK, and
SYNC
DIN) that is compatible with SPI, QSPI, and MICROWIRE
interface standards as well as most DSPs. See Figure 3 for a
timing diagram of a typical write sequence.
Reserved
Reserved
The write sequence begins by bringing the
line low. Data
SYNC
from the DIN line is clocked into the 32-bit shift register on the
falling edge of SCLK. The serial clock frequency can be as high
as 50 MHz, making the AD5666 compatible with high speed
DSPs. On the 32nd falling clock edge, the last data bit is clocked
in and the programmed function is executed, that is, a change
in DAC register contents and/or a change in the mode of
operation. At this stage, the
brought high. In either case, it must be brought high for a
minimum of 15 ns before the next write sequence so that a
Table 8. Address Commands
Address (n)
Selected DAC
Channel
A3
0
A2
0
A1
0
A0
0
1
0
1
line can be kept low or be
SYNC
DAC A
DAC B
DAC C
DAC D
All DACs
0
0
0
0
0
1
falling edge of
can initiate the next write sequence.
SYNC
0
0
1
Because the
buffer draws more current when VIN = 2 V
SYNC
1
1
1
1
than it does when VIN = 0.8 V,
should be idled low
SYNC
between write sequences for even lower power operation of the
part. As is mentioned previously, however, must be
SYNC
brought high again just before the next write sequence.
Rev. A | Page 21 of 28
AD5666
INTERRUPT
SYNC
INPUT SHIFT REGISTER
In a normal write sequence, the
line is kept low for at
SYNC
least 32 falling edges of SCLK, and the DAC is updated on the
32nd falling edge. However, if
is brought high before the
The input shift register is 32 bits wide (see Figure 42). The first
four bits are don’t cares. The next four bits are the command
bits, C3 to C0 (see Table 8), followed by the 4-bit DAC address
bits, A3 to A0 (see Table 9) and finally the 16-bit data-word.
The data-word comprises the 16-bit input code followed by four
don’t care bits for the AD5666 (see Figure 42). These data bits
are transferred to the DAC register on the 32nd falling edge of
SCLK.
SYNC
32nd falling edge, this acts as an interrupt to the write sequence.
The shift register is reset, and the write sequence is seen as
invalid. Neither an update of the DAC register contents nor a
change in the operating mode occurs (see Figure 43).
DB31 (MSB)
DB0 (LSB)
X
X
X
X
C3 C2 C1 C0 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
X
X
X
X
DATA BITS
COMMAND BITS
ADDRESS BITS
Figure 42. AD5666 Input Register Content
SCLK
SYNC
DIN
DB31
DB0
DB31
DB0
INVALID WRITE SEQUENCE:
SYNC HIGH BEFORE 32ND FALLING EDGE
VALID WRITE SEQUENCE, OUTPUT UPDATES
ON THE 32ND FALLING EDGE
SYNC
Figure 43.
Interrupt Facility
Rev. A | Page 22 of 28
AD5666
DAISY-CHAINING
POWER-ON RESET
For systems that contain several DACs, or where the user
wishes to read back the DAC contents for diagnostic purposes,
the SDO pin can be used to daisy-chain several devices together
and provide serial readback.
The AD5666 contains a power-on reset circuit that controls the
output voltage during power-up. By connecting the POR pin
low, the AD5666 output powers up to 0 V; by connecting the
POR pin high, the AD5666 output powers up to midscale. The
output remains powered up at this level until a valid write
sequence is made to the DAC. This is useful in applications
where it is important to know the state of the output of the DAC
while it is in the process of powering up. There is also a software
executable reset function that resets the DAC to the power-on
reset code. Command 0111 is reserved for this reset function
The daisy-chain mode is enabled through a software executable
DCEN command. Command 1000 is reserved for this DCEN
function (see Table 7). The daisy-chain mode is enabled by
setting a bit (DB1) in the DCEN register. The default setting is
standalone mode, where Bit DCEN = 0. Table 9 shows how the
state of the bits corresponds to the mode of operation of the
device.
(see Table 7). Any events on
or during power-on
LDAC CLR
reset are ignored.
The SCLK is continuously applied to the input shift register
POWER-DOWN MODES
when
is low. If more than 32 clock pulses are applied, the
SYNC
The AD5666 contains four separate modes of operation.
Command 0100 is reserved for the power-down function (see
Table 7). These modes are software-programmable by setting
two bits, Bit DB19 and Bit DB18, in the control register. Table 11
shows how the state of the bits corresponds to the mode of
operation of the device. Any or all DACs (DAC D to DAC A)
can be powered down to the selected mode by setting the cor-
responding four bits (DB7, DB6, DB1, DB0) to 1. See Table 12
for the contents of the input shift register during power-down/
power-up operation. When using the internal reference, only
all channel power-down to the selected modes is supported.
data ripples out of the shift register and appears on the SDO
line. This data is clocked out on the rising edge of SCLK and is
valid on the falling edge. By connecting this line to the DIN
input on the next DAC in the chain, a multi-DAC interface is
constructed. Each DAC in the system requires 32 clock pulses;
therefore, the total number of clock cycles must equal 32N,
where N is the total number of devices in the chain.
When the serial transfer to all devices is complete,
is
SYNC
taken high. This prevents any further data from being clocked
into the input shift register.
When both bits are set to 0, the part works normally with its
normal power consumption of 700 ꢀA at 5 V. However, for the
three power-down modes, the supply current falls to 400 nA at
5 V (200 nA at 3 V). Not only does the supply current fall, but
the output stage is also internally switched from the output of
the amplifier to a resistor network of known values. This has the
advantage that the output impedance of the part is known while
the part is in power-down mode. There are three different
options. The output is connected internally to GND through
either a 1 kΩ or a 100 kΩ resistor, or it is left open-circuited
(three-state). The output stage is illustrated in Figure 44.
If
is taken high before 32 clocks are clocked into the part,
SYNC
it is considered an invalid frame and the data is discarded.
The serial clock can be continuous or a gated clock. A con-
tinuous SCLK source can be used only if the
low for the correct number of clock cycles. In gated clock mode,
a burst clock containing the exact number of clock cycles must
be used, and
can be held
SYNC
must be taken high after the final clock to
SYNC
latch the data.
INTERNAL REFERENCE REGISTER
The on-board reference is off at power-up by default. This
allows the use of an external reference if the application requires
it. The on-board reference can be turned on/off by a user-
programmable REF register by setting Bit DB0 high or low (see
Table 9). Command 1000 is reserved for this internal REF set-
up command (see Table 7). Table 11 shows how the state of the
bits in the input shift register corresponds to the mode of
operation of the device.
The bias generator, output amplifier, resistor string, and other
associated linear circuitry are shut down when the power-down
mode is activated. The internal reference is powered down only
when all channels are powered down. However, the contents of
the DAC register are unaffected when in power-down. The time
to exit power-down is typically 4 ꢀs for VDD = 5 V and for
VDD = 3 V (see Figure 28).
Any combination of DACs can be powered up by setting PD1
and PD0 to 0 (normal operation). The output powers up to the
value in the input register (
Low) or to the value in the
LDAC
DAC register before powering down (
high).
LDAC
Rev. A | Page 23 of 28
AD5666
Table 9. Daisy-Chain Enable/Internal Reference Register
DCEN (DB1)
REF (DB0)
Action
0
0
1
1
0
1
0
1
Standalone mode, reference off (default)
Standalone mode, reference on
DCEN mode, reference off
DCEN mode, reference on
Table 10. 32-Bit Input Shift Register Contents for Daisy-Chain Enable and Reference Set-Up Function
MSB
LSB
DB0
1/0
DB31 to DB28
X
DB27
DB26
DB25
DB24
DB23
DB22
DB21
DB20
DB19 to DB2
X
DB1
1
0
0
0
X
X
X
X
1/0
Don’t cares
Command bits (C3 to C0)
Address bits (A3 to A0)
Don’t cares
DCEN/REF
register
Table 11. Modes of Operation
DB9
DB8
Operating Mode
Normal operation
Power-down modes
1 kΩ to GND
100 kΩ to GND
Three-state
0
0
0
1
1
1
0
1
Table 12. 32-Bit Input Shift Register Contents for Power-Up/Power-Down Function
MSB
LSB
DB31 to
DB28
DB19 to
DB10
DB7 to
DB4
DB27
DB26
DB25
DB24
DB23
DB22
DB21
DB20
DB9
DB8
DB3
DB2
DAC C
DB1
DB0
X
0
1
0
0
X
X
X
X
X
PD1
PD0
X
DAC D
DAC B
DAC A
Don’t
cares
Command bits (C2 to C0)
Address bits (A3 to A0)—
don’t cares
Don’t
cares
Power-down
mode
Don’t
cares
Power-down/power-up channel selection—
set bit to 1 to select
RESISTOR
STRING DAC
AMPLIFIER
V
OUT
POWER-DOWN
CIRCUITRY
RESISTOR
NETWORK
Figure 44. Output Stage During Power-Down
Rev. A | Page 24 of 28
AD5666
updates synchronously; that is, the DAC register is updated
after new data is read, regardless of the state of the pin.
CLEAR CODE REGISTER
LDAC
pin as being tied low. (See Table 15
The AD5666 has a hardware
pin that is an asynchronous
CLR
It effectively sees the
LDAC
clear input. The
input is falling edge sensitive. Bringing the
CLR
for the
register mode of operation.) This flexibility is
LDAC
line low clears the contents of the input register and the
CLR
DAC registers to the data contained in the user-configurable
register and sets the analog outputs accordingly. This
useful in applications where the user wants to simultaneously
update select channels while the rest of the channels are
synchronously updating.
CLR
function can be used in system calibration to load zero scale,
midscale, or full scale to all channels together. These clear code
values are user-programmable by setting two bits, Bit DB1 and
Bit DB0, in the control register (see Table 13). The default
setting clears the outputs to 0 V. Command 0101 is reserved for
loading the clear code register (see Table 7).
Writing to the DAC using command 0110 loads the 4-bit
LDAC
register (DB3 to DB0). The default for each channel is 0; that is,
the pin works normally. Setting the bits to 1 means the
LDAC
DAC channel is updated regardless of the state of the
LDAC
pin. See Table 16 for the contents of the input shift register
during the load register mode of operation.
LDAC
The part exits clear code mode on the 32nd falling edge of the
next write to the part. If
sequence, the write is aborted.
is activated during a write
CLR
POWER SUPPLY BYPASSING AND GROUNDING
When accuracy is important in a circuit, it is helpful to carefully
consider the power supply and ground return layout on the
board. The printed circuit board containing the AD5666 should
have separate analog and digital sections. If the AD5666 is in a
system where other devices require an AGND-to-DGND
connection, the connection should be made at one point only.
This ground point should be as close as possible to the AD5666.
The pulse activation time—the falling edge of
to when
CLR
CLR
the output starts to change—is typically 280 ns. However, if outside
the DAC linear region, it typically takes 520 ns after executing
for the output to start changing (see Figure 38).
CLR
See Table 14 for contents of the input shift register during the
loading clear code register operation
The power supply to the AD5666 should be bypassed with 10 ꢀF
and 0.1 ꢀF capacitors. The capacitors should physically be as
close as possible to the device, with the 0.1 ꢀF capacitor ideally
right up against the device. The 10 ꢀF capacitors are the
tantalum bead type. It is important that the 0.1 ꢀF capacitor has
low effective series resistance (ESR) and low effective series
inductance (ESI), such as is typical of common ceramic types of
capacitors. This 0.1 ꢀF capacitor provides a low impedance path
to ground for high frequencies caused by transient currents due
to internal logic switching.
FUNCTION
LDAC
The outputs of all DACs can be updated simultaneously using
the hardware
pin.
LDAC
Synchronous
: After new data is read, the DAC registers
LDAC
are updated on the falling edge of the 32nd SCLK pulse.
can be permanently low or pulsed as in Figure 3.
LDAC
Asynchronous
: The outputs are not updated at the same
LDAC
time that the input registers are written to. When
low, the DAC registers are updated with the contents of the
input register.
goes
LDAC
The power supply line should have as large a trace as possible to
provide a low impedance path and reduce glitch effects on the
supply line. Clocks and other fast switching digital signals
should be shielded from other parts of the board by digital
ground. Avoid crossover of digital and analog signals if possible.
When traces cross on opposite sides of the board, ensure that
they run at right angles to each other to reduce feedthrough
effects through the board. The best board layout technique is
the microstrip technique, where the component side of the
board is dedicated to the ground plane only and the signal
traces are placed on the solder side. However, this is not always
possible with a 2-layer board.
Alternatively, the outputs of all DACs can be updated
simultaneously using the software
function by writing to
LDAC
Input Register n and updating all DAC registers. Command
0011 is reserved for this software function.
LDAC
register gives the user extra flexibility and control
An
LDAC
over the hardware
pin. This register allows the user to
LDAC
select which combination of channels to simultaneously update
when the hardware pin is executed. Setting the bit
LDAC
register to 0 for a DAC channel means that this channel’s update
is controlled by the pin. If this bit is set to 1, this channel
LDAC
LDAC
Rev. A | Page 2ꢀ of 28
AD5666
Table 13. Clear Code Register
Clear Code Register
DB1
CR1
0
DB0
CR0
0
Clears to Code
0x0000
0
1
0x8000
1
0
0xFFFF
1
1
No operation
Table 14. 32-Bit Input Shift Register Contents for Clear Code Function
MSB
LSB
DB0
1/0
DB31 to DB28
X
DB27
DB26
DB25
DB24
DB23
DB22
DB21
DB20
DB19 to DB2
X
DB1
0
1
0
1
X
X
X
X
1/0
Don’t cares
Command bits (C3 to C0)
Address bits (A3 to A0)
Don’t cares
Clear code register
(CR1 to CR0)
Table 15.
Overwrite Definition
LDAC
Load DAC Register
LDAC Bits (DB3 to DB0)
LDAC Pin
1/0
LDAC Operation
0
1
Determined by LDAC pin
DAC channels update, overrides the LDAC pin. DAC channels see LDAC as 0.
X—don’t care
Table 16. 32-Bit Input Shift Register Contents for
Overwrite Function
LDAC
MSB
LSB
DB31
to
DB19
to
DB28
DB27
DB26
DB25
DB24
DB23
DB22
DB21
DB20
DB4
DB3
DB2
DB1
DAC B
DB0
X
0
1
1
0
X
X
X
X
X
DAC D
DAC C
DAC A
Don’t
cares
Command bits (C3 to C0)
Address bits (A3 to A0)—
don’t cares
Don’t
cares
LDAC
LDAC
bit to 1 override pin
Setting
Rev. A | Page 26 of 28
AD5666
OUTLINE DIMENSIONS
5.10
5.00
4.90
14
8
7
4.50
4.40
4.30
6.40
BSC
1
PIN 1
0.65
BSC
1.05
1.00
0.80
0.20
0.09
1.20
MAX
0.75
0.60
0.45
8°
0°
0.15
0.05
0.30
0.19
SEATING
PLANE
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-153-AB-1
Figure 45. 14-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-14)
Dimensions shown in millimeters
ORDERING GUIDE
Package
Option
Power-On
Reset to Code
Internal
Reference
Model
Temperature Range
−40°C to +10ꢀ°C
−40°C to +10ꢀ°C
−40°C to +10ꢀ°C
−40°C to +10ꢀ°C
−40°C to +10ꢀ°C
−40°C to +10ꢀ°C
Package Description
14-Lead TSSOP
14-Lead TSSOP
14-Lead TSSOP
14-Lead TSSOP
14-Lead TSSOP
14-Lead TSSOP
Evaluation Board
Accuracy
16 LSB INL
16 LSB INL
16 LSB INL
16 LSB INL
32 LSB INL
32 LSB INL
ADꢀ666BRUZ-11
ADꢀ666BRUZ-1REEL71
ADꢀ666BRUZ-21
ADꢀ666BRUZ-2REEL71
ADꢀ666ARUZ-21
ADꢀ666ARUZ-2REEL71
EVAL-ADꢀ666EB
RU-14
RU-14
RU-14
RU-14
RU-14
RU-14
Zero
Zero
Zero
Zero
Zero
Zero
1.2ꢀ V
1.2ꢀ V
2.ꢀ V
2.ꢀ V
2.ꢀ V
2.ꢀ V
1 Z = Pb-free part.
Rev. A | Page 27 of 28
AD5666
NOTES
©
2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05298–0–11/05(A)
Rev. A | Page 28 of 28
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