EVAL-AD7147EBZ [ADI]
CapTouch⑩ Programmable Controller for Single-Electrode Capacitance Sensors; CapTouch⑩可编程控制器,用于单电极电容式传感器型号: | EVAL-AD7147EBZ |
厂家: | ADI |
描述: | CapTouch⑩ Programmable Controller for Single-Electrode Capacitance Sensors |
文件: | 总68页 (文件大小:1407K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
CapTouch™ Programmable Controller for
Single-Electrode Capacitance Sensors
AD7147
FUNCTIONAL BLOCK DIAGRAM
FEATURES
AC
V
GND
10
BIAS
9
SHIELD
CC
Programmable capacitance-to-digital converter (CDC)
Femtofarad resolution
8
11
POWER-ON
RESET LOGIC
13 capacitance sensor inputs
19
20
21
22
23
24
1
CIN0
CIN1
CIN2
CIN3
CIN4
CIN5
CIN6
CIN7
CIN8
CIN9
CIN10
CIN11
CIN12
9 ms update rate, all 13 sensor inputs
No external RC components required
Automatic conversion sequencer
On-chip automatic calibration logic
Automatic compensation for environmental changes
Automatic adaptive threshold and sensitivity levels
Register map is compatible with the AD7142
On-chip RAM to store calibration data
SPI-compatible (serial-peripheral-interface-compatible)
serial interface (AD7147)
I2C-compatible serial interface (AD7147-1)
Separate VDRIVE level for serial interface
Interrupt output and general-purpose input/output (GPIO)
24-lead, 4 mm × 4 mm LFCSP
EXCITATION
SOURCE
CALIBRATION
AD7147
RAM
2
3
16-BIT
Σ-Δ
CDC
CALIBRATION
ENGINE
4
5
6
CONTROL
AND DATA
REGISTERS
7
2.6 V to 3.3 V supply voltage
INTERRUPT
AND GPIO
LOGIC
Low operating current
Full power mode: 1 mA
SERIAL INTERFACE
AND CONTROL LOGIC
12
18
GPIO
V
DRIVE
Low power mode: 21.5 μA
13
14
15
16
17
SDO/ SDI/ SCLK CS/
SDA ADD0 ADD1
INT
APPLICATIONS
Cell phones
Figure 1. AD7147 Block Diagram
Personal music and multimedia players
Smart handheld devices
Television, A/V, and remote controls
Gaming consoles
The AD7147 is designed for single-electrode capacitance
sensors (grounded sensors). There is an active shield output to
minimize noise pickup in the sensor.
Digital still cameras
The AD7147 has on-chip calibration logic to compensate for
changes in the ambient environment. The calibration sequence
is performed automatically and at continuous intervals as long
as the sensors are not touched. This ensures that there are no
false or nonregistering touches on the external sensors due to
a changing environment.
GENERAL DESCRIPTION
The AD7147 is designed for use with capacitance sensors
implementing functions such as buttons, scroll bars, and
wheels. The sensors need only one PCB layer, enabling ultra
thin applications.
The AD7147 is an integrated CDC with on-chip environmental
calibration. The CDC has 13 inputs channeled through a switch
matrix to a 16-bit, 250 kHz sigma-delta (∑-Δ) converter. The CDC
is capable of sensing changes in the capacitance of the external
sensors and uses this information to register a sensor activation.
By programming the registers, the user has full control over the
CDC setup.
The AD7147 has an SPI-compatible serial interface, and the
AD7147-1 has an I2C®-compatible serial interface. Both parts have
an interrupt output, as well as a GPIO. There is a VDRIVE pin to set
the voltage level for the serial interface independent of VCC
.
The AD7147 is available in a 24-lead, 4 mm × 4 mm LFCSP and
operates from a 2.6 V to 3.6 V supply. The operating current con-
sumption in low power mode is typically 26 μA for 13 sensors.
High resolution sensors require minor software to run on the
host processor.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2007 Analog Devices, Inc. All rights reserved.
AD7147
TABLE OF CONTENTS
Features .............................................................................................. 1
Capacitance Sensor Behavior Without Calibration............... 23
Capacitance Sensor Behavior with Calibration...................... 24
Slow FIFO.................................................................................... 24
SLOW_FILTER_UPDATE_LVL.............................................. 24
Adaptive Threshold and Sensitivity ............................................. 25
Interrupt Output............................................................................. 27
CDC Conversion-Complete Interrupt .................................... 27
Sensor-Touch Interrupt ............................................................. 27
Applications....................................................................................... 1
General description.......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
SPI Timing Specifications (AD7147)......................................... 5
I2C Timing Specifications (AD7147-1) ..................................... 6
Absolute Maximum Ratings............................................................ 7
ESD Caution.................................................................................. 7
Pin Configurations and Function Descriptions ........................... 8
Typical Performance Characteristics ............................................. 9
Theory of Operation ...................................................................... 11
Capacitance-Sensing Theory .................................................... 11
BIAS Pin....................................................................................... 12
Operating Modes........................................................................ 12
Capacitiance-to-Digital Converter............................................... 14
Oversampling the CDC Output ............................................... 14
Capacitance Sensor Offset Control.......................................... 14
Conversion Sequencer ............................................................... 14
CDC Conversion Sequence Time ............................................ 16
CDC Conversion Results........................................................... 16
Capacitance Sensor Input Configuration.................................... 17
CINx Input Multiplexer Setup.................................................. 17
Single-Ended Connections to the CDC .................................. 17
Noncontact Proximity Detection ................................................. 18
Recalibration ............................................................................... 18
Proximity Sensitivity.................................................................. 18
FF_SKIP_CNT............................................................................ 21
Environmental Calibration ........................................................... 23
INT
GPIO
Output Control ....................................................... 29
Outputs ............................................................................................ 31
ACSHIELD Output .......................................................................... 31
GPIO ............................................................................................ 31
Using the GPIO to Turn On/Off an LED................................ 31
Serial Interface ................................................................................ 32
SPI Interface................................................................................ 32
I2C-Compatible Interface .......................................................... 34
VDRIVE Input ................................................................................. 36
PCB Design Guidelines ................................................................. 37
Capacitive Sensor Board Mechanical Specifications............. 37
Chip Scale Packages ................................................................... 37
Power-Up Sequence ....................................................................... 38
Typical Application Circuits ......................................................... 39
Register Map ................................................................................... 40
Detailed Register Descriptions ..................................................... 41
Bank 1 Registers ......................................................................... 41
Bank 2 Registers ......................................................................... 51
Bank 3 Registers ......................................................................... 56
Outline Dimensions....................................................................... 68
Ordering Guide .......................................................................... 68
REVISION HISTORY
09/07—Revision 0: Initial Version
Rev. 0 | Page 2 of 68
AD7147
SPECIFICATIONS
VCC = 2.6 V to 3.6 V, TA = −40oC to +85°C, unless otherwise noted.
Table 1.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
CAPACITANCE-TO-DIGITAL CONVERTER
Update Rate
8.73
17.46
34.9
9
9.27
18.54
37.1
ms
ms
ms
Bits
pF
12 conversion stages, decimation = 64
12 conversion stages, decimation = 128
12 conversion stages, decimation = 256
18
36
16
8
Resolution
CINx Input Range
No Missing Codes
16
Bits
Guaranteed by design, but not production
tested
CINx Input Leakage
25
nA
Maximum Output Load
Total Unadjusted Error
Output Noise (Peak-to-Peak)
20
20
pF
%
Capacitance load on CINx to ground
12
7
3
1.1
0.8
0.5
20
0.32
Codes
Codes
Codes
Codes
Codes
Codes
pF
Decimation rate = 64
Decimation rate = 128
Decimation rate = 256
Decimation rate = 64
Decimation rate = 128
Decimation rate = 256
Output Noise (RMS)
CSTRAY Offset Range
CSTRAY Offset Resolution
Low Power Mode Delay Accuracy
pF
%
4
Percentage of 200 ms, 400 ms, 600 ms,
or 800 ms
ACSHIELD
Frequency
Output Voltage
250
kHz
V
0
VCC
Oscillating
Short-Circuit Source Current
Short-Circuit Sink Current
Maximum Output Load
LOGIC INPUTS (SDI, SCLK, CS, SDA, GPI)
VIH Input High Voltage
VIL Input Low Voltage
IIH Input High Current
IIL Input Low Current
10
10
mA
mA
pF
150
Capacitance load on ACSHIELD to ground
0.7 × VDRIVE
−1
V
V
μA
μA
mV
0.4
1
VIN = VDRIVE
VIN = GND
Hysteresis
150
0.1
OPEN-DRAIN OUTPUTS (SCLK, SDA, INT)
VOL Output Low Voltage
IOH Output High Leakage Current
LOGIC OUTPUTS (SDO, GPO)
VOL Output Low Voltage
VOH Output High Voltage
0.4
1
V
μA
ISINK = −1 mA
VOUT = VDRIVE
0.4
1
V
V
μA
ISINK = 1 mA, VDRIVE = 1.65 V to 3.6 V
ISOURCE = 1 mA, VDRIVE = 1.65 V to 3.6 V
Pin three-state, leakage measured to
GND and VCC
VDRIVE − 0.6
GPO, SDO Floating State Leakage
Current
POWER
VCC
VDRIVE
ICC
2.6
1.65
3.3
3.6
3.6
1
V
V
mA
μA
Serial interface operating voltage
In full power mode, VCC + VDRIVE
0.9
15.5
21.5
Low power mode, converter idle, VCC + VDRIVE
,
decimation = 256
2.3
7.5
μA
Full shutdown, VCC + VDRIVE
Rev. 0 | Page 3 of 68
AD7147
Table 2. Typical Average Current in Low Power Mode1
Current Values of Conversion Stages (ꢀA)
Low Power
Mode Delay
Decimation
Rate
1
2
3
4
5
6
7
8
9
10
11
12
200 ms
400 ms
600 ms
800 ms
64
20.83 24.18 27.52 30.82 34.11 37.37 40.6
25.3 31.92 38.45 44.87 51.21 57.45 63.6
34.11 46.99 59.51 71.66 83.47 94.94 106.1
18.17 19.86 21.55 23.23 24.9 26.57 28.23
20.43 23.79 27.12 30.43 33.72 36.98 40.22
24.9 31.53 38.06 44.5 50.83 57.08 63.23
43.81
69.66
46.99
75.63
50.16
81.52
53.3
87.33
56.41
93.05
128
256
64
128
256
64
128
256
64
128
256
116.96 127.52 137.81 147.82 157.58
29.88
43.43
69.3
31.53
46.62
75.28
26.25
36.49
56.27
23.59
31.34
46.43
33.17
49.78
81.17
27.36
38.65
60.39
24.43
32.98
49.6
34.81
52.93
86.98
28.47
40.81
64.47
25.26
34.62
52.74
36.44
56.05
92.71
29.57
42.95
68.51
26.09
36.25
55.86
17.28 18.41 19.54 20.67 21.79 22.91 24.03
18.79 21.04 23.28 25.51 27.73 29.94 32.13
21.79 26.25 30.67 35.04 39.37 43.66 47.9
16.84 17.69 18.53 19.38 20.23 21.07 21.91
25.14
34.32
52.11
22.75
29.69
43.24
17.97 19.66 21.35 23.03 24.7
26.37 28.03
20.23 23.59 26.93 30.24 33.53 36.79 40.03
1 VCC = 3.3 V, T = 25°C, load = 5 pF.
Table 3. Maximum Average Current in Low Power Mode1
Current Values of Conversion Stages (ꢀA)
Low Power
Mode
Delay
Decimation
Rate
1
2
3
4
5
6
7
8
9
10
11
12
200 ms
400 ms
600 ms
800 ms
64
27.71 31.65 35.56 39.44 43.28
32.96 40.72 48.37 55.89 63.3
43.28 58.37 72.99 87.17 100.92 114.26 127.22 139.8
47.1
70.59
50.89
77.77
54.64
84.84
58.37
91.8
62.07
98.66
65.74
105.41 112.07
69.38
128
256
64
128
256
64
128
256
64
128
256
152.03 163.92 175.48 186.73
24.61 26.6
27.26 31.21 35.12 39
28.58 30.55 32.51
42.85
34.47
46.67
70.18
30.18
38.43
54.5
36.42
50.46
77.36
31.5
38.36
54.22
84.44
32.8
43.56
64.38
30
40.29
57.95
91.41
34.11
46.11
69.24
30.98
40.07
57.74
42.21
61.65
98.27
35.41
48.64
74.05
31.97
42
44.13
65.33
105.03 111.69
46.04
68.97
32.51 40.29 47.94 55.47 62.88
23.58 24.91 26.23 27.55 28.87
25.35 27.99 30.62 33.24 35.84
28.87 34.11 39.29 44.41 49.48
23.06 24.06 25.05 26.05 27.04
24.39 26.38 28.36 30.33 32.29
36.7
38
41
51.16
78.81
32.95
43.91
65.12
53.66
83.53
33.92
45.82
68.77
59.46
29.02
36.2
28.03
34.25
46.46
38.14
54.01
27.04 30.98 34.9
38.78 42.64
50.25
61.45
1 VCC = 3.6 V, TA = −40oC to +85°C, load = 5 pF.
Rev. 0 | Page 4 of 68
AD7147
SPI TIMING SPECIFICATIONS (AD7147)
TA = −40°C to +85°C, VDRIVE = 1.65 V to 3.6 V, and VCC = 2.6 V to 3.6 V, unless otherwise noted. Sample tested at 25°C to ensure
compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of VCC) and timed from a voltage level of 1.6 V.
Table 4. SPI Timing Specifications
Parameter
Limit
Unit
Description
fSCLK
t1
5
5
MHz max
ns min
ns min
ns min
ns min
ns min
ns max
ns max
ns min
SCLK frequency
CS falling edge to first SCLK falling edge
SCLK high pulse width
SCLK low pulse width
SDI setup time
SDI hold time
SDO access time after SCLK falling edge
CS rising edge to SDO high impedance
SCLK rising edge to CS high
t2
t3
t4
t5
t6
t7
20
20
15
15
20
16
15
t8
CS
t1
t2
1
t8
t3
15
15
2
3
16
1
2
16
SCLK
t4
t5
MSB
LSB
SDI
t6
t7
SDO
MSB
LSB
Figure 2. SPI Detailed Timing Diagram
Rev. 0 | Page 5 of 68
AD7147
I2C TIMING SPECIFICATIONS (AD7147-1)
TA = −40°C to +85°C, VDRIVE = 1.65 V to 3.6 V, and VCC = 2.6 V to 3.6 V, unless otherwise noted. Sample tested at 25°C to ensure
compliance. All input signals timed from a voltage level of 1.6 V.
Table 5. I2C Timing Specifications1
Parameter
Limit
400
0.6
1.3
0.6
100
300
0.6
0.6
1.3
Unit
Description
fSCLK
t1
t2
t3
t4
t5
t6
t7
t8
kHz max
μs min
μs min
μs min
ns min
ns min
μs min
μs min
μs min
ns max
ns max
Start condition hold time, tHD; STA
Clock low period, tLOW
Clock high period, tHIGH
Data setup time, tSU; DAT
Data hold time, tHD; DAT
Stop condition setup time, tSU; STO
Start condition setup time, tSU; STA
Bus-free time between stop and start conditions, tBUF
Clock/data rise time
tR
tF
300
300
Clock/data fall time
1 Guaranteed by design, not production tested.
tR
tF
t1
t2
SCLK
t3
t7
t1
t6
t5
t4
SDA
t8
STOP START
START
STOP
Figure 3. I2C Detailed Timing Diagram
Rev. 0 | Page 6 of 68
AD7147
ABSOLUTE MAXIMUM RATINGS
Table 6.
Parameter
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rating
VCC to GND
−0.3 V to +3.6 V
−0.3 V to VCC + 0.3 V
−0.3 V to VDRIVE + 0.3 V
−0.3V to VDRIVE + 0.3 V
10 mA
Analog Input Voltage to GND
Digital Input Voltage to GND
Digital Output Voltage to GND
Input Current to Any Pin Except Supplies1
ESD Rating (Human Body Model)
Operating Temperature Range
Storage Temperature Range
Junction Temperature
2.5 kV
−40°C to +105°C
−65°C to +150°C
150°C
200µA
I
OL
TO OUTPUT
PIN
1.6V
LFCSP
Power Dissipation
C
L
450 mW
50pF
θJA Thermal Impedance
IR Reflow Peak Temperature
Lead Temperature (Soldering 10 sec)
135.7°C/W
260°C ( 0.5°C)
300°C
200µA
I
OH
Figure 4. Load Circuit for Digital Output Timing Specifications
1 Transient currents of up to 100 mA do not cause SCR latch-up.
ESD CAUTION
Rev. 0 | Page 7 of 68
AD7147
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
PIN 1
PIN 1
INDICATOR
INDICATOR
CIN6
CIN7
CIN8
CIN9
CIN10
CIN11
1
2
3
4
5
6
18 GPIO
17 INT
16 CS
15 SCLK
14 SDI
13 SDO
CIN6
CIN7
CIN8
CIN9
CIN10
CIN11
1
2
3
4
5
6
18 GPIO
17 INT
16 ADD1
15 SCLK
14 ADD0
13 SDA
AD7147
AD7147-1
TOP VIEW
TOP VIEW
(Not to Scale)
(Not to Scale)
Figure 5. AD7147 Pin Configuration
Figure 6. AD7147-1 Pin Configuration
Table 7. Pin Function Descriptions
Pin No.
AD7147-1
AD7147
1
Mnemonic
CIN6
CIN7
CIN8
CIN9
CIN10
CIN11
CIN12
ACSHIELD
BIAS
Description
1
Capacitance Sensor Input.
Capacitance Sensor Input.
Capacitance Sensor Input.
Capacitance Sensor Input.
Capacitance Sensor Input.
Capacitance Sensor Input.
Capacitance Sensor Input.
CDC Active Shield Output. Connect to external shield or plane.
Bias Node for Internal Circuitry. Requires 10 nF capacitor to ground.
Ground Reference Point for All Circuitry.
Supply Voltage.
Serial Interface Operating Voltage Supply.
SPI Serial Data Output.
I2C Serial Data Input/Output. SDA requires pull-up resistor.
SPI Serial Data Input.
I2C Address Bit 0.
Clock Input for Serial Interface.
SPI Chip Select Signal.
I2C Address Bit 1.
General-Purpose Open-Drain Interrupt Output. Programmable polarity; requires pull-up resistor.
Programmable GPIO.
Capacitance Sensor Input.
Capacitance Sensor Input.
Capacitance Sensor Input.
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
11
12
13
N/A
14
N/A
15
16
N/A
17
18
19
20
21
22
23
24
10
11
12
N/A
13
N/A
14
15
N/A
16
17
18
19
20
21
22
23
24
GND
VCC
VDRIVE
SDO
SDA
SDI
ADD0
SCLK
CS
ADD1
INT
GPIO
CIN0
CIN1
CIN2
CIN3
CIN4
CIN5
Capacitance Sensor Input.
Capacitance Sensor Input.
Capacitance Sensor Input.
Rev. 0 | Page 8 of 68
AD7147
TYPICAL PERFORMANCE CHARACTERISTICS
70
60
50
40
30
20
10
0
935
200ms
400ms
915
895
DECIMATION = 64
875
DECIMATION = 128
600ms
DECIMATION = 256
855
800ms
835
815
795
2.5
2.7
2.9
3.1
(V)
3.3
3.5
3.7
2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7
V
CC
V
(V)
CC
Figure 10. Low Power Supply Current vs. Supply Voltage,
Decimation Rate = 64
Figure 7. Supply Current vs. Supply Voltage
180
160
140
120
100
80
2.5
200ms
2.0
1.5
1.0
0.5
0
400ms
600ms
60
800ms
40
20
0
2.5
2.7
2.9
3.1
(V)
3.3
3.5
3.7
2.7
2.8
2.9
3.0
3.1
3.2
(V)
3.3
3.4
3.5
3.6
V
V
CC
CC
Figure 8. Low Power Supply Current vs. Supply Voltage,
Decimation Rate = 256
Figure 11. Shutdown Supply Current vs. Supply Voltage
1150
0.12
0.10
0.08
0.06
0.04
0.02
0
1100
1050
1000
950
200ms
400ms
600ms
800ms
900
0
100
AC
200
300
400
500
2.5
2.7
2.9
3.1
(V)
3.3
3.5
3.7
CAPACITIVE LOAD (pF)
V
SHIELD
CC
Figure 12. Supply Current vs. Capacitive Load on ACSHIELD
Figure 9. Low Power Supply Current vs. Supply Voltage,
Decimation Rate = 128
Rev. 0 | Page 9 of 68
AD7147
58000
56000
54000
52000
50000
48000
46000
44000
42000
40000
160
140
120
100
80
25mV
50mV
75mV
100mV
125mV
150mV
175mV
200mV
60
40
20
0
0
100
AC
200
300
400
500
CAPACITIVE LOAD (pF)
SHIELD
SINE WAVE FREQUENCY (Hz)
Figure 13. Output Code vs. Capacitive Load on ACSHIELD
Figure 16. Power Supply Sine Wave Rejection, VCC = 3.6 V
960
120
100
80
60
40
20
0
25mV
50mV
75mV
100mV
125mV
150mV
175mV
200mV
940
920
900
880
860
840
820
800
780
3.6V
3.3V
2.6V
–60
–40
–20
0
20
40
60
80
100
120
TEMPERATURE (°C)
SQUARE WAVE FREQUENCY (Hz)
Figure 14. Supply Current vs. Temperature
Figure 17. Power Supply Square Wave Rejection, VCC = 3.6 V
12
10
8
35
30
25
20
15
10
5
6
3.6V
4
3.3V
2.6V
115
2
0
–45
0
–25
–5
15
35
55
75
95
135
0
10000
20000
30000
40000
50000
60000
TEMPERATURE (°C)
CDC OUTPUT CODE
Figure 15. Shutdown Supply Current vs. Temperature
Figure 18. CDC Linearity, VCC = 3.3 V
Rev. 0 | Page 10 of 68
AD7147
THEORY OF OPERATION
The AD7147 and AD7147-1 are CDCs with on-chip
environmental compensation. They are intended for use in
portable systems requiring high resolution user input. The
internal circuitry consists of a 16-bit, ∑-Δ converter that can
change a capacitive input signal into a digital value. There are
13 input pins, CIN0 to CIN12, on the AD7147 or AD7147-1. A
switch matrix routes the input signals to the CDC. The result of
each capacitance-to-digital conversion is stored in on-chip
registers. The host subsequently reads the results over the serial
interface. The AD7147 has an SPI interface, and the AD7147-1
has an I2C interface, ensuring that the parts are compatible with
a wide range of host processors. AD7147 refers to both the
AD7147 and AD7147-1, unless otherwise noted, from this
point forward in this data sheet.
require low power operation to provide the user with significant
power savings and full functionality.
INT
The AD7147 has an interrupt output,
, to indicate when
INT
new data has been placed into the registers.
is used to
interrupt the host on sensor activation. The AD7147 operates
from a 2.6 V to 3.6 V supply and is available in a 24-lead, 4 mm ×
4 mm LFCSP.
CAPACITANCE-SENSING THEORY
The AD7147 measures capacitance changes from single-electrode
sensors. The sensor electrode on the PCB comprises one plate
of a virtual capacitor. The other plate of the capacitor is the user’s
finger, which is grounded with respect to the sensor input.
The AD7147 first outputs an excitation signal to charge the
plate of the capacitor. When the user comes close to the sensor,
the virtual capacitor is formed, with the user acting as the second
capacitor plate.
The AD7147 interfaces with up to 13 external capacitance
sensors. These sensors can be arranged as buttons, scroll bars,
or wheels, or as a combination of sensor types. The external
sensors consist of an electrode on a single- or multiple-layer
PCB that interfaces directly to the AD7147.
The AD7147 can be set up to implement any set of input
sensors by programming the on-chip registers. The registers can
also be programmed to control features such as averaging,
offsets, and gains for each of the external sensors. There is an
on-chip sequencer that controls how each of the capacitance
inputs is polled.
PLASTIC COVER
SENSOR PCB
The AD7147 has on-chip digital logic and 528 words of RAM
that are used for environmental compensation. The effects of
humidity, temperature, and other environmental factors can
affect the operation of capacitance sensors. Transparent to the
user, the AD7147 performs continuous calibration to compen-
sate for these effects, allowing the AD7147 to consistently
provide error-free results.
Σ-Δ
ADC
16-BIT
DATA
EXCITATION
SIGNAL
250kHz
AD7147
The AD7147 requires a companion algorithm that runs on the
host or another microcontroller to implement high resolution
sensor functions, such as scroll bars or wheels. However, no
companion algorithm is required to implement buttons. Button
sensors are implemented on chip, entirely in digital logic.
Figure 19. Capacitance-Sensing Method
A square wave excitation signal is applied to CINx during
the conversion, and the modulator continuously samples the
charge going through CINx. The output of the modulator is
processed via a digital filter, and the resulting digital data is
stored in the CDC_RESULT_Sx registers for each conversion
stage, at Address 0x00B to Address 0x016.
The AD7147 can be programmed to operate in either full power
mode or low power automatic wake-up mode. The automatic
wake-up mode is particularly suited for portable devices that
Rev. 0 | Page 11 of 68
AD7147
Registering a Sensor Activation
Complete Solution for Capacitance Sensing
When a user approaches a sensor, the total capacitance associated
with that sensor changes and is measured by the AD7147. If
the change causes a set threshold to be exceeded, the AD7147
interprets this as a sensor activation.
Analog Devices, Inc., provides a complete solution for
capacitance sensing. The two main elements to the solution are
the sensor PCB and the AD7147.
If the application requires high resolution sensors such as scroll
bars or wheels, software is required that runs on the host
processor. The memory requirements for the host depend on
the sensor and are typically 10 kB of code and 600 bytes of data
memory, depending on the sensor type.
On-chip threshold limits are used to determine when a sensor
activation occurs. Figure 20 shows the change in CDC_RESULT_Sx
when a user activates a sensor. The sensor is deemed to be active
only when the value of CDC_RESULT_Sx is either greater than the
value of STAGEx_HIGH_THRESHOLD or less than the value
of STAGEx_LOW_THRESHOLD.
SENSOR PCB
SENSOR ACTIVE (A)
HOST PROCESSOR
1 MIPS
2
SPI OR I C
AD7147
10kB ROM
STAGEx_HIGH_THRESHOLD
CDC_RESULT_Sx
600 BYTES RAM
AMBIENT OR
NO-TOUCH VALUE
Figure 21. Three-Part Capacitance-Sensing Solution
Analog Devices supplies the sensor PCB footprint design
libraries to the customer and supplies any necessary software on
an open-source basis.
STAGEx_LOW_THRESHOLD
SENSOR ACTIVE (B)
BIAS PIN
Figure 20. Sensor Activation Thresholds
This pin is connected internally to a bias node of the AD7147.
To ensure correct operation of the AD7147 connect a 10 nF
capacitor between the BIAS pin and ground. The voltage seen at
the BIAS pin is VCC/2.
In Figure 20, two sensor activations are shown. Sensor Active A
occurs when a sensor is connected to the positive input of the
converter. In this case, when a user activates the sensor, there is an
increase in CDC code, and the value of CDC_RESULT_Sx exceeds
that of STAGEx_HIGH_THRESHOLD. Sensor Active B occurs
when the sensor is connected to the negative input of the converter.
In this case, when a user activates the sensor, there is a decrease
in CDC code, and the value of CDC_RESULT_Sx becomes less
than the value of STAGEx_LOW_THRESHOLD.
OPERATING MODES
The AD7147 has three operating modes. Full power mode, where
the device is always fully powered, is suited for applications where
power is not a concern (for example, game consoles that have an
ac power supply). Low power mode, where the part automatically
powers down when no senosr is active, is tailored to provide
significant power savings compared with full power mode and
is suited for mobile applications, where power must be
For each conversion stage, the STAGEx_HIGH_THRESHOLD
and STAGEx_LOW_THRESHOLD registers are in Register Bank
3. The values in these registers are updated automatically by the
AD7147 due to its environmental calibration and adaptive
threshold logic.
conserved. In shutdown mode, the part shuts down completely.
The POWER_MODE bits (Bit 0 and Bit 1) of the control
register set the operating mode on the AD7147. The control
register is at Address 0x000. Table 8 shows the POWER_MODE
settings for each operating mode. To put the AD7147 into
shutdown mode, set the POWER_MODE bits to either 01 or 11.
At power-up, the values in the STAGEx_HIGH_THRESHOLD
and STAGEx_LOW_THRESHOLD registers are the same as those
in the STAGEx_OFFSET_HIGH and STAGEx_OFFSET_LOW
registers in Bank 2. The user must program the STAGEx_OFFSET
_HIGH and STAGEx_OFFSET_LOW registers on device power-
up. See the Environmental Calibration section of the data sheet
for more information.
Table 8. POWER_MODE Settings
POWER_MODE Bits
Operating Mode
Full power mode
Shutdown mode
Low power mode
Shutdown mode
00
01
10
11
The power-on default setting of the POWER_MODE bits is 00,
full power mode.
Rev. 0 | Page 12 of 68
AD7147
Full Power Mode
When an external sensor is touched, the AD7147 begins a con-
version sequence every 36 ms to read back data from the sensors.
In full power mode, all sections of the AD7147 remain fully
powered and converting at all times. While a sensor is being
touched, the AD7147 processes the sensor data. If no sensor is
touched, the AD7147 measures the ambient capacitance level
and uses this data for the on-chip compensation routines. In full
power mode, the AD7147 converts at a constant rate. See the
CDC Conversion Sequence Time section for more information.
In low power mode, the total current consumption of the AD7147
is an average of the current used during a conversion and the
current used while the AD7147 is waiting for the next conversion
to begin. For example, when LP_CONV_DELAY l is 400 ms, the
AD7147 typically uses 0.85 mA of current for 36 ms and 14 μA
of current for 400 ms during the conversion interval. (Note that
these conversion timings can be altered through the register
settings. See the CDC Conversion Sequence Time section for
more information.)
Low Power Mode
When AD7147 is in low power mode, the POWER_MODE bits
are set to 10 upon device initialization. If the external sensors
are not touched, the AD7147 reduces its conversion frequency,
thereby greatly reducing its power consumption. The part remains
in a reduced power state while the sensors are not touched. The
AD7147 performs a conversion after a delay defined by the
LP_CONV_DELAY bits, and it uses this data to update the
compensation logic and check if the sensors are active. The
LP_CONV_DELAY bits set the delay between conversions to
200 ms, 400 ms, 600 ms, or 800 ms.
The time for the AD7147 to transition from a full power state to
a reduced power state after the user stops touching the external
sensors is configurable. The PWR_DOWN_TIMEOUT bits (in
the Ambient Compensation Control 0 (AMB_COMP_CTRL0)
Register at Address 0x002) control the time delay before the
AD7147 transitions to the reduced power state after the user
stops touching the sensors.
AD7147 SETUP
AND INITIALIZATION
POWER_MODE = 10
ANY
NO
YES
SENSOR
TOUCHED?
CONVERSION SEQUENCE
EVERY LP_CONV_DELAY
UPDATE COMPENSATION
LOGIC DATA PATH
CONVERSION SEQUENCE
EVERY 36ms FOR
SENSOR READBACK
YES
ANY SENSOR
TOUCHED?
NO
TIMEOUT
PROXIMITY TIMER
COUNTDOWN
Figure 22. Low Power Mode Operation
Rev. 0 | Page 13 of 68
AD7147
CAPACITIANCE-TO-DIGITAL CONVERTER
The capacitance-to-digital converter on the AD7147 has a Σ-ꢀ
architecture with 16-bit resolution. There are 13 possible inputs to
the CDC that are connected to the input of the converter through a
switch matrix. The sampling frequency of the CDC is 250 kHz.
The goal is to ensure that the CDC_RESULT_Sx is as close
to midscale as possible. This process is only required once
during the initial capacitance sensor characterization.
6
+DAC
POS_AFE_OFFSET
(20pF RANGE)
OVERSAMPLING THE CDC OUTPUT
The decimation rate, or oversampling ratio, is determined by
Bits [9:8] of the power control (PWR_CONTROL) register
(Address 0x000), as listed in Table 9.
POS_AFE_OFFSET_SWAP BIT
+
CINx
16
16-BIT
CDC
Table 9. CDC Decimation Rate
_
CDC Output Rate
Decimation Rate Per Stage (ms)
DECIMATION Bits
NEG_AFE_OFFSET_SWAP BIT
00
01
10
11
256
128
64
3.072
1.536
0.768
0.768
6
–DAC
(20pF RANGE)
NEG_AFE_OFFSET
64
The decimation process on the AD7147 is an averaging process,
where a number of samples are taken and the averaged result is
output. Due to the architecture of the digital filter employed, the
number of samples taken (per stage) is equal to 3× the decimation
rate. So 3 × 256 or 3 × 128 samples are averaged to obtain each
stage result.
CINx_CONNECTION_SETUP
Figure 23. Analog Front-End Offset Control
CONVERSION SEQUENCER
The AD7147 has an on-chip sequencer to implement conversion
control for the input channels. Up to 12 conversion stages can be
performed in one sequence. Each of the 12 conversions stages can
measure the input from a different sensor. By using the Bank 2
registers, each stage can be uniquely configured to support multiple
capacitance sensor interface requirements. For example, a slider
sensor can be assigned to STAGE1 through STAGE8, with a
button sensor assigned to STAGE0. For each conversion stage,
the input mux that connects the CINx inputs to the converter
can have a unique setting.
The decimation process reduces the amount of noise present in
the final CDC result. However, the higher the decimation rate,
the lower the output rate per stage; therefore, there is a trade-off
possible between the amount of noise in the signal and the
speed of sampling.
CAPACITANCE SENSOR OFFSET CONTROL
There are two programmable DACs on board the AD7147 to null
the effect of any stray capacitances on the CDC measurement.
These offsets are due to stray capacitance to ground.
The AD7147 on-chip sequence controller provides conversion
control, beginning with STAGE0. Figure 24 shows a block diagram
of the CDC conversion stages and CINx inputs. A conversion
sequence is defined as a sequence of CDC conversions starting
at STAGE0 and ending at the stage determined by the value
programmed in the SEQUENCE_STAGE_NUM bits. Depending
on the number and type of capacitance sensors that are used, not all
conversion stages are required. Use the SEQUENCE_STAGE_NUM
bits to set the number of conversions in one sequence. This number
will depend on the sensor interface requirements. For example, the
register should be set to 5 if the CINx inputs are mapped to only six
conversion stages. In addition, the STAGE_CAL_EN register
should be set according to the number of stages that are used.
A simplified block diagram in Figure 23 shows how to apply the
STAGEx_AFE_OFFSET registers to null the offsets. The 6-bit
POS_AFE_OFFSET and NEG_AFE_OFFSET bits program the
offset DAC to provide 0.32 pF resolution offset adjustment over
a range of 20 pF.
The best practice is to ensure that the CDC output for any stage
is approximately equal to midscale (~32,700) when all sensors
are inactive. To correctly offset the stray capacitance to ground for
each stage use the following procedure:
1. Read back the CDC value from the CDC_RESULT_Sx register.
2. If this value is not close to midscale, increase the value of
POS_AFE_OFFSET or NEG_AFE_OFFSET (depending
on if the CINx input is connected to the positive or negative
input of the converter) by 1. The CINx connections are
determined by the STAGEx_CONNECTION registers.
The number of required conversion stages depends solely on
the number of sensors attached to the AD7147. Figure 25 shows
how many conversion stages are required for each sensor and
how many inputs to the AD7147 each sensor requires.
3. If the CDC value in CDC_RESULT_Sx is now closer
to midscale, repeat Step 2. If the CDC value is further
from midscale, decrease the POS_AFE_OFFSET or
NEG_AFE_OFFSET value by 1.
Rev. 0 | Page 14 of 68
AD7147
A button sensor generally requires one sequencer stage; this is
shown in Figure 25 as B1. However, it is possible to configure
two button sensors to operate differentially for one conversion
stage. Only one button can be activated at a time; pressing both
buttons simultaneously results in neither button being activated.
The configuration with two button sensors operating differentially
requires one conversion stage and is shown in Figure 25, with
B2 and B3 representing the differentially configured button sensors.
A wheel sensor requires eight stages, whereas a slider requires two
stages. The result from each stage is used by the host software to
determine the user’s position on the slider or wheel. The algorithms
that perform this process are available from Analog Devices and are
free of charge, but require signing a software license.
STAGE11
STAGE10
STAGE9
STAGE8
STAGE7
STAGE6
STAGE5
STAGE4
STAGE3
STAGE2
STAGE1
STAGE0
CIN0
CIN1
CIN2
CIN3
CIN4
CIN5
CIN6
CIN7
CIN8
CIN9
CIN10
CIN11
CIN12
Σ-Δ
16-BIT
ADC
Figure 24. CDC Conversion Stages
AD7147
AD7147
SEQUENCER
SEQUENCER
BUTTONS
STAGE0
STAGE8
B1
+
+
CDC
–
CDC
–
STAGE1
STAGE9
+
B2
B3
+
CDC
–
CDC
–
STAGE2
+
CDC
–
STAGE3
+
CDC
–
SCROLL
WHEEL
STAGE4
+
AD7147
CDC
–
SEQUENCER
STAGE10
STAGE5
+
+
CDC
–
CDC
–
SLIDER
STAGE6
STAGE11
+
+
CDC
–
CDC
–
STAGE7
+
CDC
–
Figure 25. Sequencer Setup for Sensors
Rev. 0 | Page 15 of 68
AD7147
CDC CONVERSION SEQUENCE TIME
Table 10. CDC Conversion Times for Full Power Mode
Conversion Time (ms)
Decimation = 128
SEQUENCE_STAGE_NUM
Decimation = 64
0.768
Decimation = 256
3.072
0
1.536
3.072
4.608
6.144
7.68
1
2
3
1.536
2.304
3.072
6.144
9.216
12.288
15.36
4
3.84
5
6
4.608
5.376
9.216
10.752
12.288
13.824
15.36
16.896
18.432
18.432
21.504
24.576
27.648
30.72
7
8
6.144
6.912
9
10
11
7.68
8.448
9.216
33.792
36.864
The time required for the CDC to complete the measurement of
all 12 stages is defined as the CDC conversion sequence time. The
SEQUENCE_STAGE_NUM and DECIMATION bits determine
the conversion time, as listed in Table 10.
AD7147 automatically wakes up, performing a conversion every
800 ms.
Table 11. LP_CONV_DELAY Settings
LP_CONV_DELAY Bits
Delay Between Conversions (ms)
For example, if the device is operated with a decimation rate
of 128 and the SEQUENCE_STAGE_NUM bit is set to 5 for the
conversion of six stages in a sequence, the conversion sequence
time is 9.216 ms.
00
01
10
11
200
400
600
800
Full Power Mode CDC Conversion Sequence Time
The full power mode CDC conversion sequence time for all
12 stages is set by configuring the SEQUENCE_STAGE_NUM
and DECIMATION bits as outlined in Table 10.
Figure 27 shows a simplified timing example of the low power
mode CDC conversion time. As shown, the low power mode CDC
conversion time is set by tCONV_FP and the LP_CONV_DELAY bits.
tCONV_LP
Figure 26 shows a simplified timing diagram of the full power
mode CDC conversion time. The full power mode CDC con-
version time (tCONV_FP) is set using the values shown in Table 10.
tCONV_FP
CDC CONVERSION
CONVERSION
CONVERSION
SEQUENCE N + 1
LP_CONV_DELAY
SEQUENCE N
tCONV_FP
Figure 27. Low Power Mode CDC Conversion Sequence Time
CDC
CONVERSION
CONVERSION
CONVERSION
CONVERSION
SEQUENCE N SEQUENCE N + 1 SEQUENCE N + 2
CDC CONVERSION RESULTS
Figure 26. Full Power Mode CDC Conversion Sequence Time
Certain high resolution sensors require the host to read back the
CDC conversion results for processing. The registers required
for host processing are located in the Bank 3 registers. The host
processes the data read back from these registers using a software
algorithm in order to determine position information.
Low Power Mode CDC Conversion Sequence Time
with Delay
The frequency of each CDC conversion while operating in the
low power automatic wake-up mode is controlled by using the
LP_CONV_DELAY bits located at Address 0x000 [3:2] in
addition to the registers listed in Table 10. This feature provides
some flexibility for optimizing the tradeoff between the conversion
time needed to meet system requirements and the power
consumption of the AD7147.
In addition to the results registers in the Bank 3 registers, the
AD7147 provides the 16-bit CDC output data directly, starting
at Address 0x00B of Bank 1. Reading back the CDC 16-bit
conversion data register allows for customer-specific application
data processing.
For example, maximum power savings is achieved when the
LP_CONV_DELAY bits are set to 11. With a setting of 11, the
Rev. 0 | Page 16 of 68
AD7147
CAPACITANCE SENSOR INPUT CONFIGURATION
Each input connection from the external capacitance sensors to
the AD7147’s converter can be uniquely configured by using the
registers in Bank 2 (see Table 38). These registers are used to
configure the input pin connection setups, sensor offsets, sensor
sensitivities, and sensor limits for each stage. Each sensor can be
individually optimized. For example, a button sensor connected
to STAGE0 can have different sensitivity and offset values than a
button with another function that is connected to a different stage.
SINGLE-ENDED CONNECTIONS TO THE CDC
A single-ended connection to the CDC is defined as one CINx
input connected to either the positive or negative CDC input
for one conversion stage. A differential connection to the CDC is
defined as one CINx input connected to the positive CDC input
and a second CINx input connected to the negative input of the
CDC for one conversion stage.
For any stage, if a single-ended connection to the CDC is made
in that stage, the SE_CONNECTION_SETUP bits (Bits [13:12] in
the STAGEx_CONNECTION [12:7] register) should be applied as
follows:
CINx INPUT MULTIPLEXER SETUP
Table 34 and Table 35 list the available options for the
CINx_CONNECTION_SETUP bits when the sensor input
pins are connected to the CDC.
•
•
SE_CONNECTION_SETUP = 00: do not use.
SE_CONNECTION_SETUP = 01: single-ended connection.
For this stage, there is one CINx connected to the negative
CDC input.
The AD7147 has an on-chip multiplexer that routes the input
signals from each CINx pin to the input of the converter. Each
input pin can be tied to either the negative or positive input of
the CDC, or it can be left floating. Each input can also be
internally connected to the BIAS signal to help prevent cross
coupling. If an input is not used, always connect it to the BIAS.
•
•
SE_CONNECTION_SETUP = 10: single-ended connection.
For this stage, there is one CINx connected to the positive
CDC input.
SE_CONNECTION_SETUP = 11: differential connection.
For this stage, there is one CINx connected to the nega
tive CDC input and one CINx connected to the positive
CDC input.
Connecting a CINx input pin to the positive CDC input results
in an increase in CDC output code when the corresponding
sensor is activated. Connecting a CINx input pin to the negative
CDC input results in a decrease in CDC output code when the
corresponding sensor is activated.
These bits ensure that during a single-ended connection to the
CDC, the input paths to both CDC terminals are matched,
which in turn improves the power-supply rejection of the
converter measurement.
The AD7147 performs a sequence of 12 conversions. The multi-
plexer can have different settings for each of the 12 conversions.
For example, CIN0 is connected to the negative CDC input for
conversion STAGE1, left floating for conversion STAGE1, and
so on, for all 12 conversion stages.
These bits should be applied in addition to setting the other bits
in the STAGEx_CONNECTION registers, as outlined in the
CINX Input Multiplexer Setup section.
For each CINx input for each conversion stage, two bits control
how the input is connected to the converter, as shown in Figure 28.
If more than one CINx input is connected to either the positive
or negative input of the converter for the same conversion, set
SE_CONNECTION_SETUP to 11. For example, if CIN0 and
CIN3 are connected to the positive input of the CDC, set
SE_CONNECTION_SETUP to 11.
Examples
To connect CIN3 to the positive CDC input on Stage 0 use the
following setting:
STAGE0_CONNECTION [6:0] = 0xFFBF
STAGE0_CONNECTION [12:7] = 0x2FFF
To connect CIN0 to the positive CDC input and CIN12 to the
negative CIN input on Stage 5 use the following settings:
STAGE5_CONNECTION [6:0] = 0xFFFE
STAGE5_CONNECTION [12:7] = 0x37FF
CIN CONNECTION SETUP BITS
CIN SETTING
CIN0
CIN1
CIN2
CIN3
CIN4
CIN5
CIN6
CIN7
CIN8
CIN9
CIN10
CIN11
CIN12
00
01
10
11
CINx FLOATING
CINx CONNECTED TO
NEGATIVE CDC INPUT
+
–
CDC
CINx CONNECTED TO
POSITIVE CDC INPUT
CINx CONNECTED TO
BIAS
Figure 28. Input Mux Configuration Options
Rev. 0 | Page 17 of 68
AD7147
NONCONTACT PROXIMITY DETECTION
The AD7147 internal signal processing continuously monitors
all capacitance sensors for noncontact proximity detection. This
feature provides the ability to detect when a user is approaching
a sensor, at which time all internal calibration is immediately
disabled while the AD7147 is automatically configured to detect
a valid contact.
by the PROXIMITY_RECAL_LVL bits for a set period of time
known as the recalibration timeout. In full power mode, the
recalibration timeout is controlled by FP_PROXIMITY_RECAL;
in low power mode, by LP_PROXMTY_RECAL.
The recalibration timeout in full power mode is the value of the
FP_PROXIMITY_RECAL multiplied by the time for one con-
version sequence in full power mode. The recalibration timeout in
low power mode is the value of the LP_PROXIMITY_RECAL
multiplied by the time for one conversion sequence in low
power mode.
The proximity control register bits are described in Table 12. The
FP_PROXIMITY_CNT and LP_PROXIMITY_CNT register bits
control the length of the calibration disable period after the user
stops touching the sensor and is not in close proximity to the
sensor during full or low power mode. The calibration is disabled
during this period and then enabled again. Figure 29 and Figure
30 show examples of how these registers are used to set the
calibration disable periods for the full and low power modes.
Figure 31 and Figure 32 show examples of how the
FP_PROXIMITY_RECAL and LP_PROXIMITY_RECAL
register bits control the timeout period before a recalibration
while operating in the full and low power modes. In these
examples, a user approaches a sensor and then leaves, but the
proximity detection remains active. The measured CDC value
exceeds the stored ambient value by the amount set in the
PROXIMITY_RECAL_LVL bits for the entire timeout period.
The sensor is automatically recalibrated at the end of the
timeout period.
The calibration disable period in full power mode is the value
of the FP_PROXIMITY_CNT multiplied by 16 multiplied by
the time for one conversion sequence in full power mode. The
calibration disable period in low power mode is the value of the
LP_PROXIMITY_CNT multiplied by 4 multiplied by the time
for one conversion sequence in low power mode.
RECALIBRATION
PROXIMITY SENSITIVITY
In certain situations, for example, when a user hovers over a
sensor for a long time, the proximity flag can be set for a long
period. The environmental calibration on the AD7147 is
suspended while proximity is detected, but changes may occur
to the ambient capacitance level during the proximity event.
This means that the ambient value stored on the AD7147 no
longer represents the actual ambient value. In this case, even
when the user is not in close proximity to the sensor, the
proximity flag may still be set. This situation can occur if the
user interaction creates some moisture on the sensor, causing
the new sensor ambient value to be different from the expected
value. In this situation, the AD7147 automatically forces a
recalibration internally. This ensures that the ambient values are
recalibrated, regardless of how long the user hovers over the
sensor. A recalibration ensures maximum AD7147 sensor
performance.
The fast filter in Figure 33 is used to detect when someone is
close to the sensor (proximity). Two conditions, detected by
Comparator 1 and Comparator 2, set the internal proximity
detection signal: Comparator 1 detects when a user is
approaching or leaving a sensor, and Comparator 2 detects
when a user hovers over a sensor or approaches a sensor very
slowly.
The sensitivity of Comparator 1 is controlled by the
PROXIMITY_DETECTION_RATE bits. For example, if
PROXIMITY_DETECTION_RATE is set to 4, the Proximity 1
signal is set when the absolute difference between WORD1 and
WORD3 exceeds (4 × 16) LSB codes.
The sensitivity of Comparator 2 is controlled by the
PROXIMITY_RECAL_LVL bits (Address 0x003). For example,
if PROXIMITY_RECAL_LVL is set to 75, the Proximity 2 signal is
set when the absolute difference between the fast filter average
value and the ambient value exceeds (75 × 16) LSB codes.
The AD7147 recalibrates automatically when the measured CDC
value exceeds the stored ambient value by an amount determined
Rev. 0 | Page 18 of 68
AD7147
Table 12. Proximity Control Registers (See Figure 33)
Length
(Bits)
Bit Name
Register Address
0x002 [7:4]
0x002 [11:8]
0x004 [9:0]
0x004 [15:10]
0x003 [7:0]
Description
FP_PROXIMITY_CNT
LP_PROXIMITY_CNT
FP_PROXIMITY_RECAL
LP_PROXIMITY_RECAL
PROXIMITY_RECAL_LVL
4
4
8
6
8
Calibration disable time in full power mode.
Calibration disable time in low power mode.
Full power mode proximity recalibration time.
Low power mode proximity recalibration time.
Proximity recalibration level. This value multiplied by 16 controls the
sensitivity of Comparator 2 (see Figure 33).
PROXIMITY_DETECTION_RATE
6
0x003 [13:8]
Proximity detection rate. This value multiplied by 16 controls the
sensitivity of Comparator 1 (see Figure 33).
USER APPROACHES
SENSOR
USER LEAVES
SENSOR AREA
tCONV_FP
CDC CONVERSION
SEQUENCE
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
tCALDIS
(INTERNAL)
PROXIMITY
DETECTION
(INTERNAL)
CALIBRATION
(INTERNAL)
CALIBRATION DISABLED
CALIBRATION ENABLED
Figure 29. Example of Full Power Mode Proximity Detection (FP_PROXIMITY_CNT = 1)
USER APPROACHES
SENSOR
USER LEAVES
SENSOR AREA
tCONV_LP
1
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
CDC CONVERSION
SEQUENCE
(INTERNAL)
tCALDIS
PROXIMITY
DETECTION
(INTERNAL)
CALIBRATION
(INTERNAL)
CALIBRATION DISABLED
CALIBRATION ENABLED
NOTES
1. SEQUENCE CONVERSION TIME tCONV_LP
=
tCONV_FP + LP_CONV_DELAY.
2. PROXIMITY IS SET WHEN USER APPROACHES THE SENSOR, AT WHICH TIME THE INTERNAL CALIBRATION IS DISABLED.
3. tCALDIS = (tCONV_LP × LP_PROXIMITY_CNT × 4).
Figure 30. Example of Low Power Mode Proximity Detection (LP_PROXIMITY_CNT = 4)
Rev. 0 | Page 19 of 68
AD7147
USER APPROACHES
SENSOR
tRECAL
MEASURED CDC VALUE > STORED AMBIENT
BY PROXIMITY_RECAL _LVL
USER LEAVES
SENSOR AREA
tCONV_FP
16
30
70
CDC CONVERSION
SEQUENCE
(INTERNAL)
tCALDIS
PROXIMITY
DETECTION
(INTERNAL)
CALIBRATION
(INTERNAL)
CALIBRATION DISABLED
RECALIBRATION TIMEOUT
tRECAL_TIMEOUT
CALIBRATION ENABLED
RECALIBRATION
COUNTER
(INTERNAL)
NOTES
1. SEQUENCE CONVERSION TIME tCONV_FP (SEE TABLE 10).
2. tCALDIS tCONV_FP × FP_PROXIMITY_CNT × 16.
3. tRECAL_TIMEOUT tCONV_FP × FP_PROXIMITY_RECAL.
4. tRECAL = 2 × tCONV_FP
=
=
.
Figure 31. Example of Full Power Mode Proximity Detection with Forced Recalibration (FP_PROXIMITY_CNT = 1 and FP_PROXIMITY_RECAL = 40)
USER APPROACHES
SENSOR
tRECAL
MEASURED CDC VALUE > STORED AMBIENT
USER LEAVES
SENSOR AREA
BY PROXIMITY_RECAL _LVL
tCONV_LP
16
30
70
CDC CONVERSION
SEQUENCE
(INTERNAL)
PROXIMITY
DETECTION
(INTERNAL)
tCALDIS
CALIBRATION
(INTERNAL)
CALIBRATION DISABLED
RECALIBRATION TIMEOUT
tRECAL_TIMEOUT
CALIBRATION ENABLED
RECALIBRATION
(INTERNAL)
NOTES
1. SEQUENCE CONVERSION TIME tCONV_LP
2. tCALDIS tCONV_LP × LP_PROXIMITY_CNT × 4.
3. tRECAL_TIMEOUT tCONV_LP × LP_PROXIMITY_RECAL.
4. tRECAL = 2 × tCONV_LP
=
tCONV_FP + LP_CONV_DELAY.
=
=
.
Figure 32. Example of Low Power Mode Proximity Detection with Forced Recalibration (LP_PROXIMITY_CNT = 4 and LP_PROXIMITY_RECAL = 40)
Rev. 0 | Page 20 of 68
AD7147
Determining the FF_SKIP_CNT value is required only once
FF_SKIP_CNT
during the initial setup of the capacitance sensor interface.
Table 13 shows how FF_SKIP_CNT controls the update rate of
the fast FIFO. The recommended value for the setting when
using all 12 conversion stages on the AD7147 is 0000, or no
samples skipped.
The proximity detection fast FIFO is used by the on-chip logic
to determine if proximity is detected. The fast FIFO expects to
receive samples from the converter at a set rate. FF_SKIP_CNT
is used to normalize the frequency of the samples going into the
FIFO, regardless of how many conversion stages are in a sequence.
In Register 0x002, Bits [3:0] are the fast filter skip control,
FF_SKIP_CNT. This value determines which CDC samples
are not used (skipped) by the proximity detection fast FIFO.
Table 13. FF_SKIP_CNT Settings
FAST FIFO Update Rate
Decimation = 128
FF_SKIP
_CNT
Decimation = 64
Decimation = 256
0
1
2
3
4
5
0.768 × (SEQUENCE_STAGE_NUM + 1) ms 1.536 × (SEQUENCE_STAGE_NUM + 1) ms
1.536 × (SEQUENCE_STAGE_NUM + 1) ms 3.072 × (SEQUENCE_STAGE_NUM + 1) ms
3.072 × (SEQUENCE_STAGE_NUM + 1) ms
6.144 × (SEQUENCE_STAGE_NUM + 1) ms
9.216 × (SEQUENCE_STAGE_NUM + 1) ms
12.288 × (SEQUENCE_STAGE_NUM + 1) ms
15.36 × (SEQUENCE_STAGE_NUM + 1) ms
18.432 × (SEQUENCE_STAGE_NUM + 1) ms
2.3 × (SEQUENCE_STAGE_NUM + 1) ms
4.608 × (SEQUENCE_STAGE_NUM + 1) ms
3.072 × (SEQUENCE_STAGE_NUM + 1) ms 6.144 × (SEQUENCE_STAGE_NUM + 1) ms
3.84 × (SEQUENCE_STAGE_NUM + 1) ms
4.6 × (SEQUENCE_STAGE_NUM + 1) ms
7.68 × (SEQUENCE_STAGE_NUM + 1) ms
9.216 × (SEQUENCE_STAGE_NUM + 1) ms
6
7
8
5.376 × (SEQUENCE_STAGE_NUM + 1) ms 10.752 × (SEQUENCE_STAGE_NUM + 1) ms 21.504 × (SEQUENCE_STAGE_NUM + 1) ms
6.144 × (SEQUENCE_STAGE_NUM + 1) ms 12.288 × (SEQUENCE_STAGE_NUM + 1) ms 24.576 × (SEQUENCE_STAGE_NUM + 1) ms
6.912 × (SEQUENCE_STAGE_NUM + 1) ms 13.824 × (SEQUENCE_STAGE_NUM + 1) ms 27.648 × (SEQUENCE_STAGE_NUM + 1) ms
9
7.68 × (SEQUENCE_STAGE_NUM + 1) ms
15.36 × (SEQUENCE_STAGE_NUM + 1) ms
30.72 × (SEQUENCE_STAGE_NUM + 1) ms
10
11
12
13
14
15
8.448 × (SEQUENCE_STAGE_NUM + 1) ms 16.896 × (SEQUENCE_STAGE_NUM + 1) ms 33.792 × (SEQUENCE_STAGE_NUM + 1) ms
9.216 × (SEQUENCE_STAGE_NUM + 1) ms 18.432 × (SEQUENCE_STAGE_NUM + 1) ms 36.864 × (SEQUENCE_STAGE_NUM + 1) ms
9.984 × (SEQUENCE_STAGE_NUM + 1) ms 19.968 × (SEQUENCE_STAGE_NUM + 1) ms 39.936 × (SEQUENCE_STAGE_NUM + 1) ms
10.752 × (SEQUENCE_STAGE_NUM + 1) ms 21.504 × (SEQUENCE_STAGE_NUM + 1) ms 43.008 × (SEQUENCE_STAGE_NUM + 1) ms
11.52 × (SEQUENCE_STAGE_NUM + 1) ms 23.04 × (SEQUENCE_STAGE_NUM + 1) ms
46.08 × (SEQUENCE_STAGE_NUM + 1) ms
12.288 × (SEQUENCE_STAGE_NUM + 1) ms 24.576 × (SEQUENCE_STAGE_NUM + 1) ms 49.152 × (SEQUENCE_STAGE_NUM + 1) ms
Rev. 0 | Page 21 of 68
AD7147
FP_PROXIMITY_CNT
REGISTER 0x002
LP_PROXIMITY_CNT
REGISTER 0x002
16
CDC
STAGEx_FF_WORD0
STAGEx_FF_WORD1
STAGEx_FF_WORD2
STAGEx_FF_WORD3
STAGEx_FF_WORD4
STAGEx_FF_WORD5
STAGEx_FF_WORD6
STAGEx_FF_WORD7
PROXIMITY 1
PROXIMITY
COMPARATOR 1
PROXIMITY TIMING
CONTROL LOGIC
|WORD0 – WORD3|
PROXIMITY_DETECTION_RATE
REGISTER 0x003
FP_PROXIMITY_RECAL
REGISTER 0x004
LP_PROXIMITY_RECAL
REGISTER 0x004
BANK 3 REGISTERS
7
WORD(N)
STAGEx_FF_AVG
BANK 3 REGISTERS
Σ
N = 0
8
COMPARATOR 2
|AVERAGE – AMBIENT|
STAGEx_FF_WORDx
PROXIMITY
SW1
SLOW_FILTER_EN
PROXIMITY_RECAL_LVL
REGISTER 0x003
COMPARATOR 3
STAGEx_SF_WORD0
STAGEx_SF_WORD1
STAGEx_SF_WORD2
STAGEx_SF_WORD3
STAGEx_SF_WORD4
STAGEx_SF_WORD5
STAGEx_SF_WORD6
STAGEx_SF_WORD7
WORD0 – CDC VALUE
AMBIENT
VALUE
STAGEx_SF_AMBIENT
BANK 3 REGISTERS
STAGEx_SF_WORDx
SLOW_FILTER_UPDATE_LVL
REGISTER 0x003
SENSOR
CONTACT
t
BANK 3 REGISTERS
NOTES
|STAGEx_SF_
|
1. SLOW_FILTER_EN, WHICH IS THE NAME OF THE OUTPUT OF COMPARATOR 3, IS SET AND SW1 IS CLOSED WHEN
EXCEEDS THE VALUE PROGRAMMED IN THE SLOW_FILTER_UPDATE_LVL REGISTER PROVIDING PROXIMITY IS NOT SET.
|STAGEx_FF_
WORD0 – CDC VALUE
|
2. PROXIMITY 1 IS SET WHEN
WORD0 – STAGEx_FF_WORD3 EXCEEDS THE VALUE PROGRAMMED IN THE
PROXIMITY_DETECTION_RATE REGISTER.
|
|
3. PROXIMITY 2 IS SET WHEN AVERAGE – AMBIENT EXCEEDS THE VALUE PROGRAMMED IN THE PROXIMITY_RECAL_LVL REGISTER.
4. DESCRIPTION OF COMPARATOR FUNCTIONS:
COMPARATOR 1: USED TO DETECT WHEN A USER IS APPROACHING OR LEAVING A SENSOR.
COMPARATOR 2: USED TO DETECT WHEN A USER IS HOVERING OVER A SENSOR OR APPROACHING A SENSOR VERY SLOWLY.
ALSO USED TO DETECT IF THE SENSOR AMBIENT LEVEL HAS CHANGED AS A RESULT OF THE USER INTERACTION.
FOR EXAMPLE, HUMIDITY OR DIRT LEFT BEHIND ON SENSOR.
COMPARATOR 3: USED TO ENABLE THE SLOW FILTER UPDATE RATE. THE SLOW FILTER IS UPDATED WHEN SLOW_FILTER_EN IS SET AND
PROXIMITY IS NOT SET.
Figure 33. AD7147 Proximity-Detection Logic
Rev. 0 | Page 22 of 68
AD7147
ENVIRONMENTAL CALIBRATION
SENSOR 1 INT
ASSERTED
The AD7147 provides on-chip capacitance sensor calibration to
automatically adjust for environmental conditions that have an
effect on the ambient levels of the capacitance sensor. The output
levels of the capacitance sensor are sensitive to temperature,
humidity, and, in some cases, dirt.
STAGEx_HIGH_THRESHOLD
CDC AMBIENT VALUE
The AD7147 achieves optimal and reliable sensor
performance by continuously monitoring the CDC ambient
levels and compensating for any environmental changes by
adjusting the values of the STAGEx_HIGH_THRESHOLD
and STAGEx_LOW_THRESHOLD registers as described in
Equation 1 and Equation 2. The CDC ambient level is defined
as the output level of the capacitance sensor during periods
when the user is not approaching or in contact with the sensor.
STAGEx_LOW_THRESHOLD
SENSOR 2 INT
ASSERTED
t
CHANGING ENVIRONMENTAL CONDITIONS
Figure 34. Ideal Sensor Behavior with a Constant Ambient Level
CAPACITANCE SENSOR BEHAVIOR WITHOUT
CALIBRATION
After the AD7147 is configured, the compensation logic runs
automatically with each conversion when the AD7147 is not
being touched. This allows the AD7147 to compensate for
rapidly changing environmental conditions.
Figure 35 shows the typical behavior of a capacitance sensor
when calibration is not applied. This figure shows ambient
levels drifting over time as environmental conditions change. As
a result of the initial threshold levels remaining constant while
the ambient levels drift upward, Sensor 2 fails to detect a user
contact in this example.
The ambient compensation control registers provide the host
with access to general setup and controls for the compensation
algorithm. On-chip RAM stores the compensation data for each
conversion stage, as well as setup information specific for each stage.
The Capacitance Sensor Behavior with Calibration section
describes how the AD7147 adaptive calibration algorithm
prevents such errors from occurring.
Figure 34 shows an example of the ideal behavior of a
capacitance sensor, where the CDC ambient level remains
constant regardless of the environmental conditions. The CDC
output shown is for a pair of differential button sensors, where
one sensor caused an increase and the other caused a decrease
in measured capacitance when activated. The positive and
negative sensor threshold levels are calculated as a percentage of
the STAGEx_OFFSET_HIGH and STAGEx_OFFSET_LOW
values and are based on the threshold sensitivity settings and
the ambient value. These values are sufficient to detect a sensor
SENSOR 1 INT
ASSERTED
STAGEx_HIGH_THRESHOLD
CDC AMBIENT
VALUE DRIFTING
INT
contact and result in the AD7147 asserting the
when the threshold levels are exceeded.
output
STAGEx_LOW_THRESHOLD
SENSOR 2 INT
NOT ASSERTED
t
CHANGING ENVIRONMENTAL CONDITIONS
Figure 35. Typical Sensor Behavior Without Calibration
STAGEx _ OFFSET _ HIGH
⎛
⎞
⎛
⎝
⎞
⎠
STAGEx _ OFFSET _ HIGH −
⎜ ⎜
⎟ ⎟
STAGEx _ OFFSET _ HIGH
4
⎛
⎝
⎞
⎟
⎠
⎜
⎟
STAGEx _ HIGH _ THRESHOLD = STAGEx _ SF _ AMBIENT +
+
× POS _ THRESHOLD _ SENSITIVITY
⎜
⎜
⎜
⎝
⎟
⎟
⎠
4
16
Equation 1. On-Chip Logic Stage High Threshold Calculation
STAGEx _ OFFSET _ LOW
⎛
⎞
⎛
⎝
⎞
⎠
STAGEx _ OFFSET _ LOW −
⎜ ⎜
⎟ ⎟
STAGEx _ OFFSET _ LOW
4
⎛
⎜
⎝
⎞
⎟
⎠
⎜
⎟
STAGEx _ LOW _THRESHOLD = STAGEx _ SF _ AMBIENT +
+
× NEG _THRESHOLD _ SENSITIVITY
⎜
⎟
4
16
⎜
⎟
⎠
⎝
Equation 2. On-Chip Logic Stage Low Threshold Calculation
Rev. 0 | Page 23 of 68
AD7147
AVG_FP_SKIP and AVG_LP_SKIP
CAPACITANCE SENSOR BEHAVIOR WITH
CALIBRATION
In Register 0x001, Bits [13:12] are the slow FIFO skip control
for full power mode, AVG_FP_SKIP. Bits [15:14] in the same
register are the slow FIFO skip control for low power mode,
AVG_LP_SKIP, and determine which CDC samples are not
used (skipped) in the slow FIFO. Changing the values of the
AVG_FP_SKIP and AVG_LP_SKIP bits slows down or speeds
up the rate at which the ambient capacitance value tracks the
measured capacitance value read by the converter:
The AD7147 on-chip adaptive calibration algorithm prevents
sensor detection errors such as the one shown in Figure 35.
This is achieved by monitoring the CDC ambient levels
and readjusting the initial STAGEx_OFFSET_HIGH and
STAGEx_OFFSET_LOW values according to the amount of
ambient drift measured on each sensor. Based on the new
stage offset values, the internal STAGEx_HIGH_THRESHOLD
and STAGEx_LOW_THRESHOLD values described in
Equation 1 and Equation 2 are automatically updated.
•
Slow FIFO update rate in full power mode = AVG_FP_SKIP ×
[(3 × Decimation Rate) × (SEQUENCE_STAGE_NUM + 1) ×
(FF_SKIP_CNT + 1) × 4 × 10−7].
This closed-loop routine ensures the reliability and repeatable
operation of every sensor connected to the AD7147 when they
are subjected to dynamic environmental conditions. Figure 36
shows a simplified example of how the AD7147 applies the
adaptive calibration process, resulting in no interrupt errors
even with changing CDC ambient levels due to dynamic
environmental conditions.
•
Slow FIFO update rate in low power mode = (AVG_LP_SKIP
+ 1) × [(3 × Decimation Rate) × (SEQUENCE_STAGE_NUM
+ 1) × (FF_SKIP_CNT + 1) × 4 x 10−7]/[(FF_SKIP_CNT + 1)
+ LP_CONV_DELAY].
The slow FIFO is used by the on-chip logic to track the ambient
capacitance value. The slow FIFO expects to receive samples from
the converter at a rate between 33 ms and 40 ms. AVG_FP_SKIP
and AVG_LP_SKIP are used to normalize the frequency of the
samples going into the FIFO, regardless of how many conversion
stages are in a sequence.
SENSOR 1 INT
ASSERTED
3
STAGEx_HIGH_THRESHOLD
(POSTCALIBRATED
2
REGISTER VALUE)
1
CDC AMBIENT
Determining the AVG_FP_SKIP and AVG_LP_SKIP values is
required only once during the initial setup of the capacitance
sensor interface. The recommended values for these settings
when using all 12 conversion stages on the AD7147 are as follows:
VALUE DRIFTING
6
5
STAGEx_LOW_THRESHOLD
(POSTCALIBRATED
REGISTER VALUE)
4
•
•
AVG_FP_SKIP = 00 = skip three samples
AVG_LP_SKIP = 00 = skip zero samples
SENSOR 2 INT
ASSERTED
t
CHANGING ENVIRONMENTAL CONDITIONS
SLOW_FILTER_UPDATE_LVL
1
2
3
4
5
6
INITIAL STAGEx_OFFSET_HIGH REGISTER VALUE.
The SLOW_FILTER_UPDATE_LVL controls whether the most
recent CDC measurement goes into the slow FIFO (slow filter).
The slow filter is updated when the difference between the
current CDC value and the last value of the slow FIFO is greater
than the value of SLOW_FILTER_UPDATE_LVL. This variable
is in Ambient Control Register 1 (AMB_COMP_CTRL1)
(Address 0x003).
POSTCALIBRATED REGISTER STAGEx_HIGH_THRESHOLD.
POSTCALIBRATED REGISTER STAGEx_HIGH_THRESHOLD.
INITIAL STAGEx_LOW_THRESHOLD.
POSTCALIBRATED REGISTER STAGEx_LOW_THRESHOLD.
POSTCALIBRATED REGISTER STAGEx_LOW_THRESHOLD.
Figure 36. Typical Sensor Behavior with Calibration Applied on the Data Path
SLOW FIFO
As shown in Figure 33, there are a number of FIFOs
implemented on the AD7147. These FIFOs are located in
Bank 3 of the on-chip memory. The slow FIFOs are used by the
on-chip logic to monitor the ambient capacitance level from
each sensor.
Rev. 0 | Page 24 of 68
AD7147
ADAPTIVE THRESHOLD AND SENSITIVITY
The AD7147 provides an on-chip, self-adjusting adaptive
threshold and sensitivity algorithm. This algorithm continu-
ously monitors the output levels of each sensor and automatically
rescales the threshold levels in proportion to the sensor area
covered by the user. As a result, the AD7147 maintains optimal
threshold and sensitivity levels for all users regardless of their
finger sizes.
result in a large average maximum or minimum value, whereas
a small finger will result in smaller values. When the average
maximum or minimum value changes, the threshold levels are
rescaled to ensure that the threshold levels are appropriate for
the current user. Figure 38 shows how the minimum and
maximum sensor responses are tracked by the on-chip logic.
Reference A in Figure 37 shows a less sensitive threshold level
for a user with small fingers and demonstrates the disadvantages
of a fixed threshold level.
The threshold level is always referenced from the ambient level
and is defined as the CDC converter output level that must be
exceeded before a valid sensor contact can occur. The sensitivity
level is defined as how sensitive the sensor must be before a
valid contact can be registered.
By enabling the adaptive threshold and sensitivity algorithm,
the positive and negative threshold levels are determined by the
POS_THRESHOLD_SENSITIVITY and NEG_THRESHOLD_
SENSITIVITY bit values and by the most recent average
maximum sensor output value. These bits can be used to select
16 different positive and negative sensitivity levels ranging between
25% and 95.32% of the most recent average maximum output
level referenced from the ambient value. The smaller the
sensitivity percentage setting, the easier it is to trigger a sensor
activation. Reference B shows that the positive adaptive threshold
level is set at almost mid-sensitivity with a 62.51% threshold
level by setting POS_THRESHOLD_ SENSITIVITY = 1000.
Figure 37 also provides a similar example for the negative
threshold level, with NEG_THRESHOLD_SENSITIVITY =
0011.
Figure 37 provides an example of how the adaptive threshold
and sensitivity algorithm works. The positive and negative
sensor threshold levels are calculated as a percentage of the
STAGEx_OFFSET_HIGH and STAGEx_OFFSET_LOW
values and are based on the threshold sensitivity settings and
the ambient value. After the AD7147 is configured, initial
estimates are supplied for both STAGEx_OFFSET_HIGH
and STAGEx_OFFSET_LOW, and then the calibration engine
automatically adjusts the STAGEx_HIGH_THRESHOLD and
STAGEx_LOW_THRESHOLD values for sensor response.
The AD7147 tracks the average maximum and minimum values
measured from each sensor. These values provide an indication
of how the user is interacting with the sensor. A large finger will
AVERAGE MAXIMUM VALUE
95.32%
STAGEx_OFFSET_HIGH
IS UPDATED
AVERAGE MAXIMUM VALUE
62.51% =
A
POS_THRESHOLD
STAGEx_OFFSET_HIGH
_SENSITIVITY
95.32%
STAGEx_OFFSET_HIGH
IS UPDATED
62.51% =
POS_THRESHOLD
_SENSITIVITY
25%
B
25%
AMBIENT LEVEL
25%
NEG_THRESHOLD_SENSITIVITY = 39.08%
STAGEx_OFFSET_LOW
IS UPDATED
25%
STAGEx_OFFSET_LOW
NEG_THRESHOLD_SENSITIVITY = 39.08%
95.32%
STAGEx_OFFSET_LOW
IS UPDATED
95.32%
SENSOR CONTACTED
BY LARGE FINGER
SENSOR CONTACTED
BY SMALL FINGER
Figure 37. Example of Threshold Sensitivity (POS_THRESHOLD_SENSITIVITY = 1000, NEG_THRESHOLD_SENSITIVITY = 0011)
Rev. 0 | Page 25 of 68
AD7147
STAGEx_MAX_WORD0
STAGEx_MAX_WORD1
STAGEx_MAX_WORD2
STAGEx_MAX_WORD3
BANK 3 REGISTERS
MAXIMUM
LEVEL
DETECTION
LOGIC
STAGEx_MAX_AVG
BANK 3 REGISTERS
Σ-Δ
16-BIT
CDC
16
STAGEx_MAX_TEMP
BANK 3 REGISTERS
STAGEx_HIGH_THRESHOLD
BANK 3 REGISTERS
STAGEx_MIN_WORD0
STAGEx_MIN_WORD1
STAGEx_MIN_WORD2
STAGEx_MIN_WORD3
BANK 3 REGISTERS
MINIMUM
LEVEL
DETECTION
LOGIC
STAGEx_MIN_AVG
BANK 3 REGISTERS
STAGEx_MIN_TEMP
BANK 3 REGISTERS
STAGEx_LOW_THRESHOLD
BANK 3 REGISTERS
Figure 38. Tracking the Minimum and Maximum Average Sensor Values
Table 14. Additional Information About Environmental Calibration and Adaptive Threshold Registers
Register
Location Description
Register/Bit
NEG_THRESHOLD_SENSITIVITY
NEG_PEAK_DETECT
Bank 2
Bank 2
Used in Equation 2. This value is programmed once at startup.
Used by internal adaptive threshold logic only.
The NEG_PEAK_DETECT is set to a percentage of the difference between the ambient
CDC value and the minimum average CDC value. If the output of the CDC approaches the
NEG_PEAK_DETECT percentage of the minimum average, the minimum average value is updated.
POS_THRESHOLD_SENSITIVITY
POS_PEAK_DETECT
Bank 2
Bank 2
Used in Equation 1. This value is programmed once at startup.
Used by internal adaptive threshold logic only.
The POS_PEAK_DETECT is set to a percentage of the difference between the ambient
CDC value and the maximum average CDC value. If the output of the CDC approaches the
POS_PEAK_DETECT percentage of the maximum average, the maximum average value is updated.
STAGEx_OFFSET_LOW
Bank 2
Bank 2
Bank 2
Used in Equation 2. An initial value (based on sensor characterization) is programmed into
this register at startup. The AD7147 on-chip calibration algorithm automatically updates this
register based on the amount of sensor drift due to changing ambient conditions. Set this
register to 80% of the STAGEx_OFFSET_LOW_CLAMP value.
STAGEx_OFFSET_HIGH
Used in Equation 1. An initial value (based on sensor characterization) is programmed into
this register at startup. The AD7147 on-chip calibration algorithm automatically updates this
register based on the amount of sensor drift due to changing ambient conditions. Set this
register to 80% of the STAGEx_OFFSET_HIGH_CLAMP value.
STAGEx_OFFSET_HIGH_CLAMP
Used by internal environmental calibration and adaptive threshold algorithms only.
An initial value (based on sensor characterization) is programmed into this register at startup.
The value in this register prevents a user from causing a sensor’s output value to exceed the
expected nominal value.
Set this register to the maximum expected sensor response or the maximum change in CDC
output code.
STAGEx_OFFSET_LOW_CLAMP
STAGEx_SF_AMBIENT
Bank 2
Bank 3
Used by internal environmental calibration and adaptive threshold algorithms only.
An initial value (based on sensor characterization) is programmed into this register at startup.
The value in this register prevents a user from causing a sensor’s output value to exceed the
expected nominal value.
Set this register to the minimum expected sensor response or the minimum change in CDC
output code.
Used in Equation 1 and Equation 2. This is the ambient sensor output when the sensor is not
touched, as calculated using the slow FIFO.
STAGEx_HIGH_THRESHOLD
STAGEx_LOW_THRESHOLD
Bank 3
Bank 3
Equation 1 value.
Equation 2 value.
Rev. 0 | Page 26 of 68
AD7147
INTERRUPT OUTPUT
The AD7147 has an interrupt output that triggers an interrupt
INT
Configuring the AD7147 into this mode results in the interrupt
being asserted when the user makes contact with the sensor and
again when the user stops touching the sensor. The second
interrupt is required to alert the host processor that the user is
no longer contacting the sensor.
service routine on the host processor. The
signal is on
Pin 17 and is an open-drain output. There are three types of
interrupt events on the AD7147: a CDC conversion-complete
interrupt, a sensor touch interrupt, and a GPIO interrupt. Each
interrupt has enable and status registers. The conversion-
complete and sensor-touch (sensor-activation) interrupts can be
enabled on a per-conversion-stage basis. The status registers
The registers located at Address 0x005 and Address 0x006 are
used to enable the interrupt output for each stage. The registers
located at Address 0x008 and Address 0x009 are used to read
back the interrupt status for each stage.
INT
indicate what type of interrupt triggered the
pin. Status
INT
registers are cleared, and the
signal is reset high during a
Figure 39 shows the interrupt output timing during contact with
one of the sensors connected to STAGE0 while operating in the
sensor-touch interrupt mode. For a low limit configuration, the
interrupt output is asserted as soon as the sensor is contacted and
again after the user has stopped contacting the sensor. (Note that
the interrupt output remains low until the host processor reads
back the interrupt status registers located at Address 0x008 and
Address 0x009.)
read operation. The signal returns high as soon as the read
address has been set up.
CDC CONVERSION-COMPLETE INTERRUPT
The AD7147 interrupt signal asserts low to indicate the completion
of a conversion stage and that new conversion result data is
available in the registers.
The interrupt can be independently enabled for each conversion
stage. Each conversion-stage-complete interrupt can be enabled via
the STAGE_COMPLETE_INT_ENABLE register (Address 0x007).
This register has a bit that corresponds to each conversion stage.
Setting this bit to 1 enables the interrupt for that stage. Clearing this
bit to 0 disables the conversion-complete interrupt for that stage.
The interrupt output is asserted when there is a change in the
interrupt status bits. This can indicate that a user is touching the
sensor(s) for the first time, the number of sensors being
touched has changed, or the user is no longer touching the
sensor(s). Reading the status bits in the interrupt status register
shows the current sensor activations.
The AD7147 interrupt should be enabled only for the last stage
in a conversion sequence. For example, if there are five
conversion stages, only the conversion-complete interrupt for
FINGER ON SENSOR
1
3
FINGER OFF SENSOR
INT
STAGE4 is enabled. Therefore,
only asserts when all five
CONVERSION
STAGE
conversion stages are complete and the host can read new data
from all five result registers. The interrupt is cleared by reading
the STAGE_COMPLETE_INT_STATUS register located at
Address 0x00A.
STAGE0
STAGE1
2
4
SERIAL
READBACK
Register 0x00A is the conversion-complete interrupt status
register. Each bit in this register corresponds to a conversion
stage. If a bit is set, it means that the conversion-complete
interrupt for the corresponding stage was triggered. This
register is cleared upon a read if the underlying condition that
triggered the interrupt is not present.
INT OUTPUT
1
2
3
4
USER TOUCHING SENSOR.
ADDRESS 0x008 IS READ BACK TO CLEAR INTERRUPT.
USER STOPS TOUCHING SENSOR.
ADDRESS 0x008 IS READ BACK TO CLEAR INTERRUPT.
Figure 39. Example of Sensor-Touch Interrupt
SENSOR-TOUCH INTERRUPT
The sensor-touch interrupt mode is implemented when the host
processor requires an interrupt only when a sensor is contacted.
Rev. 0 | Page 27 of 68
AD7147
STAGE0
STAGE1
STAGE2
STAGE3
STAGE4
STAGE5
STAGE6
STAGE7
STAGE8
STAGE9
STAGE10
STAGE11
CONVERSIONS
INT
1
2
3
SERIAL
READS
NOTES
THIS IS AN EXAMPLE OF A CDC CONVERSION-COMPLETE INTERRUPT.
THIS TIMING EXAMPLE SHOWS THAT THE INTERRUPT OUTPUT HAS BEEN ENABLED TO BE ASSERTED AT THE END OF A CONVERSION CYCLE FOR
STAGE0, STAGE5, AND STAGE9. THE INTERRUPTS FOR ALL OTHER STAGES HAVE BEEN DISABLED.
STAGEx CONFIGURATION PROGRAMMING NOTES FOR STAGE0, STAGE5, AND STAGE9 (x = 0, 5, 9):
STAGEx_LOW_INT_ENABLE (ADDRESS 0x005) = 0
STAGEx_HIGH_INT_ENABLE (ADDRESS 0x006) = 0
STAGEx_COMPLETE_INT_ENABLE (ADDRESS 0x007) = 1
STAGEx CONFIGURATION PROGRAMMING NOTES FOR STAGE1 THROUGH STAGE8, STAGE10, AND STAGE11 (x = 1, 2, 3, 4, 5, 6, 7, 8, 10, 11):
STAGEx_LOW_INT_ENABLE (ADDRESS 0x005) = 0
STAGEx_HIGH_INT_ENABLE (ADDRESS 0x006) = 0
STAGEx_COMPLETE_INT_ENABLE (ADDRESS 0x007) = 0
SERIAL READBACK REQUIREMENTS FOR STAGE0, STAGE5, AND STAGE9 (THIS READBACK OPERATION IS REQUIRED TO CLEAR THE INTERRUPT OUTPUT.):
1
READ THE STAGE0_COMPLETE_INT_STATUS (ADDRESS 0x00A) BIT
READ THE STAGE5_COMPLETE_INT_STATUS (ADDRESS 0x00A) BIT
READ THE STAGE9_COMPLETE_INT_STATUS (ADDRESS 0x00A) BIT
2
3
Figure 40. Example of Configuring the Registers for Conversion-Complete Interrupt Setup
CONVERSIONS
STAGE0
STAGE1
STAGE2
STAGE3
STAGE4
STAGE5
STAGE6
STAGE7
STAGE8
STAGE9
STAGE10
STAGE11
INT
1
4
2
SERIAL
READS
NOTES
THIS IS AN EXAMPLE OF A SENSOR-TOUCH INTERRUPT FOR A CASE WHERE THE LOW THRESHOLD LEVELS WERE EXCEEDED.
FOR EXAMPLE, THE SENSOR CONNECTED TO STAGE0 AND STAGE9 WERE CONTACTED, AND THE LOW THRESHOLD LEVELS WERE EXCEEDED, RESULTING
IN THE INTERRUPT BEING ASSERTED. THE STAGE6 INTERRUPT WAS NOT ASSERTED BECAUSE THE USER DID NOT CONTACT THE SENSOR CONNECTED TO
STAGE6.
STAGEx CONFIGURATION PROGRAMMING NOTES FOR STAGE0, STAGE6, AND STAGE9 (x = 0, 6, 9):
STAGEx_LOW_INT_ENABLE (ADDRESS 0x005) = 1
STAGEx_HIGH_INT_ENABLE (ADDRESS 0x006) = 0
STAGEx_COMPLETE_INT_ENABLE (ADDRESS 0x007) = 0
STAGEx CONFIGURATION PROGRAMMING NOTES FOR STAGE1 THROUGH STAGE7, STAGE8, STAGE10, AND STAGE11 (x = 1, 2, 3, 4, 5, 6, 7, 8, 10, 11):
STAGEx_LOW_INT_ENABLE (ADDRESS 0x005) = 0
STAGEx_HIGH_INT_ENABLE (ADDRESS 0x006) = 0
STAGEx_COMPLETE_INT_ENABLE (ADDRESS 0x007) = 0
SERIAL READBACK REQUIREMENTS FOR STAGE0 AND STAGE9 (THIS READBACK OPERATION IS REQUIRED TO CLEAR THE INTERRUPT OUTPUT.):
1
READ THE STAGE0_LOW_INT_STATUS (ADDRESS 0x008) BIT
READ THE STAGE5_LOW_INT_STATUS (ADDRESS 0x008) BIT
2
Figure 41. Example of Configuring the Registers for Sensor-Touch Interrupt Setup
Rev. 0 | Page 28 of 68
AD7147
INT
interrupt. This bit is set to 1 when the GPIO has triggered
.
GPIO INT OUTPUT CONTROL
The bit is cleared upon reading the GPIO_INT_STATUS bit if the
condition that caused the interrupt is no longer present.
INT
The
output signal can be controlled by the GPIO pin when
the GPIO is configured as an input. The GPIO is configured as
an input by setting the GPIO_SETUP bits in the interrupt
configuration register to 01. See the GPIO section for more
information on how to configure the GPIO.
The GPIO interrupt can be set to trigger on a rising edge,
falling edge, high level, or low level at the GPIO input pin. Table 15
shows how the settings of the GPIO_INPUT_CONFIG bits in
the interrupt enable (STAGE_LOW_INT_ENABLE) register
Enable the GPIO interrupt by setting the GPIO_INT_ENABLE
bit in Register 0x007 to 1, or disable the GPIO interrupt by
clearing this bit to 0. The GPIO status bit in the conversion-
complete interrupt status register reflects the status of the GPIO
INT
affect the behavior of
.
Figure 42 to Figure 45 show how the interrupt output is cleared
upon a read from the GPIO_INT_STATUS bit.
1
1
SERIAL
READBACK
SERIAL
READBACK
GPIO INPUT HIGH WHEN REGISTER IS READ BACK
GPIO INPUT HIGH WHEN REGISTER IS READ BACK
GPIO
INPUT
GPIO
INPUT
INT
OUTPUT
INT
OUTPUT
GPIO INPUT LOW WHEN REGISTER IS READ BACK
GPIO INPUT LOW WHEN REGISTER IS READ BACK
GPIO
INPUT
GPIO
INPUT
INT
OUTPUT
INT
OUTPUT
1
1
READ GPIO_INT_STATUS BIT TO RESET INT OUTPUT.
READ GPIO_INT_STATUS BIT TO RESET INT OUTPUT.
INT
INT
Figure 43. Example of Output Controlled by the GPIO Input
(GPIO_SETUP = 01, GPIO_INPUT_CONFIG = 01)
Figure 42. Example of
Output Controlled by the GPIO Input
(GP IO_SETUP = 01, GPIO_INPUT_CONFIG = 00)
Rev. 0 | Page 29 of 68
AD7147
1
1
SERIAL
READBACK
SERIAL
READBACK
GPIO INPUT LOW WHEN REGISTER IS READ BACK
GPIO INPUT LOW WHEN REGISTER IS READ BACK
GPIO
INPUT
GPIO
INPUT
INT
OUTPUT
INT
OUTPUT
GPIO INPUT HIGH WHEN REGISTER IS READ BACK
GPIO INPUT HIGH WHEN REGISTER IS READ BACK
GPIO
INPUT
GPIO
INPUT
INT
OUTPUT
INT
OUTPUT
NOTES
1
1
READ GPIO_INT_STATUS BIT TO RESET INT OUTPUT.
READ GPIO_INT_STATUS BIT TO RESET INT OUTPUT.
INT
Output Controlled by the GPIO Input
INT
Figure 45. Example of
Figure 44. Example of
Output Controlled by the GPIO Input
(GPIO_SETUP = 01, GPIO_INPUT_CONFIG = 11)
(GPIO_SETUP = 01, GPIO_INPUT_CONFIG = 10)
Table 15. GPIO Interrupt Behavior
INT
INT Behavior
GPIO_INPUT_CONFIG
GPIO Pin
GPIO_INT_STATUS
00 = Negative Level Triggered
00 = Negative Level Triggered
01 = Positive Edge Triggered
01 = Positive Edge Triggered
10 = Negative Edge Triggered
10 = Negative Edge Triggered
11 = Positive Level Triggered
11 = Positive Level Triggered
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
0
1
0
0
1
1
0
0
1
Not triggered
Asserted while signal on GPIO pin is low
Pulses low at low-to-high GPIO transition
Not triggered
Pulses low at high-to-low GPIO transition
Not triggered
Asserted while signal on GPIO pin is high
Not triggered
Rev. 0 | Page 30 of 68
AD7147
OUTPUTS
When the GPIO is configured as an output, the voltage level on
the pin is set to either a low level or a high level, as defined by
the GPIO_SETUP bits (see Table 16).
ACSHIELD OUTPUT
The AD7147 measures capacitance between CINx and ground.
Any capacitance to ground on the signal path between the CINx
pins and the sensor is included in the AD7147 conversion result.
The GPIO_INPUT_CONFIG bits in the interrupt enable
register determine the response of the AD7147 to a signal on
the GPIO pin when the GPIO is configured as an input. The
GPIO can be configured as either active high or active low, as
well as either edge triggered or level triggered (see Table 17).
To eliminate stray capacitance to ground, the ACSHIELD signal should
be used to shield the connection between the sensor and CINx,
as shown in Figure 46. The plane around the sensors should also
be connected to ACSHIELD
.
Table 17. GPIO_INPUT_CONFIG Bits
GPIO_INPUT_CONFIG GPIO Configuration
AD7147
CIN0
CIN1
CIN2
CIN3
00
01
10
11
Triggered on negative level (active low)
Triggered on positive edge (active high)
Triggered on negative edge (active low)
Triggered on positive level (active high)
AC
SHIELD
Figure 46. ACSHIELD
When GPIO is configured as an input, it triggers the interrupt
output on the AD7147. Table 15 lists the interrupt output
behavior for each of the GPIO configuration setups.
The ACSHIELD output is the same signal waveform as the
excitation signal on CINx. Therefore, there is no ac current
between CINx and ACSHIELD, and any capacitance between these
pins does not affect the CINx charge transfer.
USING THE GPIO TO TURN ON/OFF AN LED
The GPIO on the AD7147 can be used to turn on and off an
LED by setting the GPIO as either output high or low. Setting
the GPIO output high turns on the LED; setting the GPIO
output low turns off the LED. The GPIO pin connects to a
transistor that provides the drive current for the LED. Suitable
transistors include the KTC3875 from Korea Electronics Co.,
Ltd. (KEC).
Using ACSHIELD eliminates capacitance-to-ground pickup, which
means that the AD7147 can be placed up to 60 cm away from
the sensors. This allows the AD7147 to be placed on a separate
PCB than that of the sensors if the connections between the
sensors and the CINx inputs are correctly shielded using
ACSHIELD
.
GPIO
V
CC
KTC3875
OR SIMILAR
The AD7147 has one GPIO pin. It can be configured as an input or
an output. The GPIO_SETUP Bits [13:12] in the interrupt enable
register determine how the GPIO pin is configured.
AD7147
GPIO
Table 16. GPIO_SETUP Bits
GPIO_SETUP
GPIO Configuration
GPIO disabled
Input
Output low
Output high
Figure 47. Controlling an LED Using the GPIO
00
01
10
11
Rev. 0 | Page 31 of 68
AD7147
SERIAL INTERFACE
The AD7147 is available with an SPI-compatible interface. The
AD7147-1 is available with an I2C-compatible interface. Both
parts are the same, with the exception of the serial interface.
Bits [15:11] of the command word must be set to 11100 to
successfully begin a bus transaction.
Bit 10 is the read/write bit; 1 indicates a read, and 0 indicates a
write.
SPI INTERFACE
Bits [9:0] contain the target register address. When reading or
writing to more than one register, this address indicates the
address of the first register to be written to or read from.
The AD7147 has a 4-wire serial peripheral interface (SPI). The
SPI has a data input pin (SDI) for inputting data to the device, a
data output pin (SDO) for reading data back from the device,
and a data clock pin (SCLK) for clocking data into and out of
Writing Data
CS
the device. A chip select pin ( ) enables or disables the serial
Data is written to the AD7147 in 16-bit words. The first word
written to the device is the command word, with the read/write
bit set to 0. The master then supplies the 16-bit input data-word
on the SDI line. The AD7147 clocks the data into the register
addressed in the command word. If there is more than one
word of data to be clocked in, the AD7147 automatically incre-
ments the address pointer and clocks the subsequent data-word
into the next register.
CS
interface.
is required for correct operation of the SPI. Data is
clocked out of the AD7147 on the negative edge of SCLK, and
data is clocked into the device on the positive edge of SCLK.
SPI Command Word
All data transactions on the SPI bus begin with the master
CS
taking
from high to low and sending out the command
word. This indicates to the AD7147 whether the transaction is a
read or a write and provides the address of the register from
which to begin the data transfer. The following bit map shows
the SPI command word.
The AD7147 continues to clock in data on the SDI line until
CS
either the master finishes the write transition by pulling
high
or the address pointer reaches its maximum value. The AD7147
address pointer does not wrap around. When it reaches its
maximum value, any data provided by the master on the SDI
line is ignored by the AD7147.
MSB
15
1
LSB
14
13
12
11
10
9:0
Register address
1
1
0
0
R/W
16-BIT COMMAND WORD
REGISTER ADDRESS
ENABLE WORD
R/W
16-BIT DATA
CW
15
CW
14
CW
13
CW
12
CW
11
CW
10
CW
9
CW
8
CW
7
CW
6
CW
5
CW
4
CW
3
CW
2
CW
1
CW
0
SDI
D15 D14 D13
D2
D1
D0
t2
t4
t5
SCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
30
31
t8
32
t1
t
3
CS
NOTES
1. SDI BITS ARE LATCHED ON SCLK RISING EDGES. SCLK CAN IDLE HIGH OR LOW BETWEEN WRITE OPERATIONS.
2. ALL 32 BITS MUST BE WRITTEN: 16 BITS FOR THE CONTROL WORD AND 16 BITS FOR THE DATA.
3. 16-BIT COMMAND WORD SETTINGS FOR SERIAL WRITE OPERATION:
CW [15:11] = 11100 (ENABLE WORD)
CW [10] = 0 (R/W)
CW [9:0] = [AD9, AD8, AD7, AD6, AD5, AD4, AD3, AD2, AD1, AD0] (10-BIT MSB-JUSTIFIED REGISTER ADDRESS)
Figure 48. Single Register Write SPI Timing
Rev. 0 | Page 32 of 68
AD7147
16-BIT COMMAND WORD
STARTING REGISTER ADDRESS
DATA FOR STARTING
REGISTER ADDRESS
DATA FOR NEXT
REGISTER ADDRESS
ENABLE WORD
R/W
CW
15
CW
14
CW
13
CW CW CW
12 11 10
CW
9
CW
8
CW
7
CW
6
CW
5
CW
4
CW
3
CW
2
CW
1
CW
0
SDI
D15 D14
D1 D0 D15 D14
D1 D0 D15
SCLK
CS
1
2
3
4
11
12
13
14
5
6
7
8
9
10
15
16
17
18
31
32
33
34
47
48
49
NOTES
1. MULTIPLE SEQUENTIAL REGISTERS CAN BE LOADED CONTINUOUSLY.
2. THE FIRST (LOWEST ADDRESS) REGISTER ADDRESS IS WRITTEN, FOLLOWED BY MULTIPLE 16-BIT DATA-WORDS.
3. THE ADDRESS AUTOMATICALLY INCREMENTS WITH EACH 16-BIT DATA-WORD (ALL 16 BITS MUST BE WRITTEN).
4. CS IS HELD LOW UNTIL THE LAST DESIRED REGISTER HAS BEEN LOADED.
5. 16-BIT COMMAND WORD SETTINGS FOR SEQUENTIAL WRITE OPERATION:
CW [15:11] = 11100 (ENABLE WORD)
CW [10] = 0 (R/W)
CW [9:0] = [AD9, AD8, AD7, AD6, AD5, AD4, AD3, AD2, AD1, AD0] (STARTING MSB-JUSTIFIED REGISTER ADDRESS)
Figure 49. Sequential Register Write SPI Timing
16-BIT COMMAND WORD
ENABLE WORD
R/W
REGISTER ADDRESS
CW
15
CW
14
CW
13
CW
12
CW
11
CW
10
CW
9
CW
8
CW
7
CW
6
CW
5
CW
4
CW
3
CW
2
CW
1
CW
0
SDI
X
X
X
X
X
X
t2
t4
t5
SCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
30
31
t8
32
t1
t3
CS
t6
XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX D15 D14 D13
16-BIT READBACK DATA
t7
SDO
D2
D1
D0
XXX
NOTES
1. SDI BITS ARE LATCHED ON SCLK RISING EDGES. SCLK CAN IDLE HIGH OR LOW BETWEEN WRITE OPERATIONS.
2. THE 16-BIT CONTROL WORD MUST BE WRITTEN ON SDI: 5 BITS FOR ENABLE WORD, 1 BIT FOR R/W, AND 10 BITS FOR REGISTER ADDRESS.
3. THE REGISTER DATA IS READ BACK ON THE SDO PIN.
4. X DENOTES DON’T CARE.
5. XXX DENOTES HIGH IMPEDANCE THREE-STATE OUTPUT.
6. CS IS HELD LOW UNTIL ALL REGISTER BITS HAVE BEEN READ BACK.
7. 16-BIT COMMAND WORD SETTINGS FOR SINGLE READBACK OPERATION:
CW [15:11] = 11100 (ENABLE WORD)
CW [10] = 1 (R/W)
CW [9:0] = [AD9, AD8, AD7, AD6, AD5, AD4, AD3, AD2, AD1, AD0] (10-BIT MSB-JUSTIFIED REGISTER ADDRESS)
Figure 50. Single Register Readback SPI Timing
The AD7147 continues to clock out data on the SDO line if the
master continues to supply the clock signal on SCLK. The read
Reading Data
A read transaction begins when the master writes the command
word to the AD7147 with the read/write bit set to 1. The master
then supplies 16 clock pulses per data-word to be read, and the
AD7147 clocks out data from the addressed register on the SDO
line. The first data-word is clocked out on the first falling edge
of SCLK following the command word, as shown in Figure 50.
CS
transaction finishes when the master takes high. If the AD7147
address pointer reaches its maximum value, the AD7147 repeatedly
clocks out data from the addressed register. The address pointer
does not wrap around.
Rev. 0 | Page 33 of 68
AD7147
16-BIT COMMAND WORD
R/W REGISTER ADDRESS
ENABLE WORD
CW CW CW CW CW CW CW CW CW CW CW CW CW CW CW CW
15 14 13 12 11 10
SDI
X
X
X
X
X
X
X
X
X
9
8
7
6
5
4
3
2
1
0
SCLK
CS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
31
32
33
34
47
48
49
XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX D15 D14
D1
D0 D15 D14
D1
D0
D15
SDO
READBACK DATA FOR
STARTING REGISTER ADDRESS
READBACK DATA FOR
NEXT REGISTER ADDRESS
NOTES
1. MULTIPLE REGISTERS CAN BE READ BACK CONTINUOUSLY.
2. THE 16-BIT CONTROL WORD MUST BE WRITTEN ON SDI: 5 BITS FOR ENABLE WORD, 1 BIT FOR R/W, AND 10 BITS FOR REGISTER ADDRESS.
3. THE ADDRESS AUTOMATICALLY INCREMENTS WITH EACH 16-BIT DATA-WORD BEING READ BACK ON THE SDO PIN.
4. CS IS HELD LOW UNTIL ALL REGISTER BITS HAVE BEEN READ BACK.
5. X DENOTES DON’T CARE.
6. XXX DENOTES HIGH IMPEDANCE THREE-STATE OUTPUT.
7. 16-BIT COMMAND WORD SETTINGS FOR SEQUENTIAL READBACK OPERATION:
CW [15:11] = 11100 (ENABLE WORD)
CW [10] = 1 (R/W)
CW [9:0] = [AD9, AD8, AD7, AD6, AD5, AD4, AD3, AD2, AD1, AD0] (STARTING MSB-JUSTIFIED REGISTER ADDRESS)
Figure 51. Sequential Register Readback SPI Timing
All slave peripherals connected to the serial bus respond to the
start condition and shift in the next eight bits, consisting of a
I2C-COMPATIBLE INTERFACE
The AD7147-1 supports the industry standard 2-wire I2C serial
interface protocol. The two wires associated with the I2C timing
are the SCLK and SDA inputs. The SDA is an I/O pin that allows
both register write and register readback operations. The AD7147-1
is always a slave device on the I2C serial interface bus.
W
7-bit address (MSB first) plus an R/ bit that determines the
direction of the data transfer. The peripheral whose address
corresponds to the transmitted address responds by pulling the
data line low during the ninth clock pulse. This is known as the
acknowledge bit. All other devices on the bus then remain idle
while the selected device waits for data to be read from or written
It has a 7-bit device address, Address 0101 1XX. The lower two
bits are set by tying the ADD0 and ADD1 pins high or low. The
AD7147-1 responds when the master device sends its device
address over the bus. The AD7147-1 cannot initiate data
transfers on the bus.
W
to it. If the R/ bit is 0, the master writes to the slave device. If
W
the R/ bit is 1, the master reads from the slave device.
Data is sent over the serial bus in a sequence of nine clock
pulses—eight bits of data followed by an acknowledge bit from
the slave device. Transitions on the data line must occur during
the low period of the clock signal and remain stable during the
high period, because a low-to-high transition when the clock is
high can be interpreted as a stop signal. The number of data
bytes transmitted over the serial bus in a single read or write
operation is limited only by what the master and slave devices
can handle.
Table 18. AD7147-1 I2C Device Address
ADD1
ADD0
I2C Address
0101 100
0101 101
0101 110
0101 111
0
0
1
1
0
1
0
1
When all data bytes are read or written, a stop condition is
established. A stop condition is defined by a low-to-high
transition on SDA while SCLK remains high. If the AD7147
encounters a stop condition, it returns to its idle condition, and
the address pointer register resets to Address 0x00.
Data Transfer
Data is transferred over the I2C serial interface in 8-bit bytes.
The master initiates a data transfer by establishing a start con-
dition, defined as a high-to-low transition on the serial data
line, SDA, while the serial clock line, SCLK, remains high. This
indicates that an address/data stream follows.
Rev. 0 | Page 34 of 68
AD7147
START
AD7147-1 DEVICE ADDRESS
REGISTER ADDRESS [A15:A8]
REGISTER ADDRESS [A7:A0]
SDA
DEV DEV DEV DEV DEV DEV DEV
R/W ACK A15 A14
A9
A8 ACK A7
A6
A1
A0
A6
A5
A4
A3
A2
A1
A0
t1
t3
SCLK
1
2
3
4
11
5
6
7
8
9
10
16
17
18
19
20
25
26
t2
STOP
START
REGISTER DATA [D15:D8]
ACK D15 D14
REGISTER DATA [D7:D0]
D6 D1
t5
38
AD7147-1 DEVICE ADDRESS
DEV DEV DEV
t8
ACK
ACK
45
D9
D8
t4
D7
D0
A6
A5
A4
t6
t7
1
2
3
27
28
29
34
35
36
37
43
44
46
NOTES
1. A START CONDITION AT THE BEGINNING IS DEFINED AS A HIGH-TO-LOW TRANSITION ON SDA WHILE SCLK REMAINS HIGH.
2. A STOP CONDITION AT THE END IS DEFINED AS A LOW-TO-HIGH TRANSITION ON SDA WHILE SCLK REMAINS HIGH.
3. 7-BIT DEVICE ADDRESS [DEV A6:DEV A0] = [0 1 0 1 1 X X], WHERE X IS A DON’T CARE BIT.
4. 16-BIT REGISTER ADDRESS [A15:A0] = [X, X, X, X, X, X, A9, A8, A7, A6, A5, A4, A3, A2, A1, A0], WHERE X IS A DON’T CARE BIT.
5. REGISTER ADDRESS [A15:A8] AND REGISTER ADDRESS [A7:A0] ARE ALWAYS SEPARATED BY A LOW ACK BIT.
6. REGISTER DATA [D15:D8] AND REGISTER DATA [D7:D0] ARE ALWAYS SEPARATED BY A LOW ACK BIT.
Figure 52. Example of I2C Timing for Single Register Write Operation
Writing Data over the I2C Bus
The process for writing to the AD7147-1 over the I2C bus is
shown in Figure 52 and Figure 54. The device address is sent
address. Therefore, any data written to the AD7147-1 after the
address pointer has reached its maximum value is discarded.
All registers on the AD7147-1 are 16 bits. Two consecutive 8-bit
data bytes are combined and written to the 16-bit registers. To
avoid errors, all writes to the device must contain an even
number of data bytes.
W
over the bus, followed by the R/ bit being set to 0 and then
two bytes of data that contain the 10-bit address of the internal
data register to be written. The following bit map shows the
upper register address bytes. Note that Bit 7 to Bit 2 in the upper
address byte are don’t care bits. The address is contained in the
10 LSBs of the register address bytes.
To finish the transaction, the master generates a stop condition
on SDO, or generates a repeat start condition if the master is to
maintain control of the bus.
Reading Data over the I2C Bus
MSB
7
LSB
6
5
4
3
2
1
0
To read from the AD7147-1, the address pointer register must
first be set to the address of the required internal register. The
master performs a write transaction, and then writes to the
AD7147-1 to set the address pointer. Next, the master outputs a
repeat start condition to keep control of the bus, or if this is not
possible, ends the write transaction with a stop condition. A read
X
X
X
X
X
X
Register Register
Address Address
Bit 9
Bit 8
The following bit map shows the lower register address bytes.
MSB
7
LSB
W
transaction is initiated, with the R/ bit set to 1.
6
5
4
3
2
1
0
Reg
Add
Bit 7
Reg
Add
Bit 6
Reg
Add
Bit 5
Reg
Add
Bit 4
Reg
Add
Bit 3
Reg
Add
Bit 2
Reg
Add
Bit 1
Reg
Add
Bit 0
The AD7147-1 supplies the upper eight bits of data from the
addressed register in the first readback byte, followed by the
lower eight bits in the next byte. This is shown in Figure 53 and
Figure 54.
The third data byte contains the eight MSBs of the data to be
written to the internal register. The fourth data byte contains
the eight LSBs of data to be written to the internal register.
Because the address pointer automatically increments after each
read, the AD7147-1 continues to output readback data until the
master sends a no acknowledge and stop condition to the bus. If
the address pointer reaches its maximum value and the master
continues to read from the part, the AD7147-1 repeatedly sends
data from the last register that was addressed.
The AD7147-1 address pointer register automatically increments
after each write. This allows the master to sequentially write to all
registers on the AD7147-1 in the same write transaction. However,
the address pointer register does not wrap around after the last
Rev. 0 | Page 35 of 68
AD7147
START
AD7147-1 DEVICE ADDRESS
REGISTER ADDRESS [A15:A8]
REGISTER ADDRESS [A7:A0]
SDA
DEV DEV DEV DEV DEV DEV DEV
R/W ACK A15 A14
A9
A8 ACK A7
A6
A1
A0
ACK
27
A6
A5
A4
A3
A2
A1
A0
t1
t3
SCLK
1
2
3
4
5
6
7
8
9
10
11
16
17
18
19
20
25
26
t2
P
AD7147-1 DEVICE ADDRESS
REGISTER DATA [D7:D0]
D6 D1
t5
39
SR
t8
AD7147-1 DEVICE ADDRESS
DEV DEV DEV
DEV DEV
A6 A5
DEV DEV
D7
D0
ACK
ACK
46
R/W
A6
A5
A4
A1
A0
USING
REPEATED START
t4
t6
t7
34
35
36
37
38
44
45
1
2
3
28
29
30
AD7147-1 DEVICE ADDRESS
REGISTER DATA [D7:D0]
D6 D1
t5
39
P
P
S
DEV DEV
A6 A5
DEV DEV
D7
D0 ACK
ACK
R/W
A1
A0
t4
SEPARATE READ AND
WRITE TRANSACTIONS
34
35
36
37
38
44
45
46
28
29
30
NOTES
1. A START CONDITION AT THE BEGINNING IS DEFINED AS A HIGH-TO-LOW TRANSITION ON SDA WHILE SCLK REMAINS HIGH.
2. A STOP CONDITION AT THE END IS DEFINED AS A LOW-TO-HIGH TRANSITION ON SDA WHILE SCLK REMAINS HIGH.
3. THE MASTER GENERATES THE ACK AT THE END OF THE READBACK TO SIGNAL THAT IT DOES NOT WANT ADDITIONAL DATA.
4. 7-BIT DEVICE ADDRESS [DEV A6:DEV A0] = [0 1 0 1 1 X X], WHERE THE TWO LSB Xs ARE DON'T CARE BITS.
5. 16-BIT REGISTER ADDRESS [A15:A0] = [X, X, X, X, X, X, A9, A8, A7, A6, A5, A4, A3, A2, A1, A0], WHERE THE UPPER LSB Xs ARE DON’T CARE BITS.
6. REGISTER ADDRESS [A15:A8] AND REGISTER ADDRESS [A7:A0] ARE ALWAYS SEPARATED BY LOW ACK BITS.
7. REGISTER DATA [D15:D8] AND REGISTER DATA [D7:D0] ARE ALWAYS SEPARATED BY A LOW ACK BIT.
8. THE R/W BIT IS SET TO A1 TO INDICATE A READBACK OPERATION.
Figure 53. Example of I2C Timing for Single Register Readback Operation
WRITE
6-BIT DEVICE
REGISTER ADDR
[15:8]
REGISTER ADDR
[7:0]
WRITE DATA
HIGH BYTE [15:8]
WRITE DATA
LOW BYTE [7:0]
WRITE DATA
HIGH BYTE [15:8]
WRITE DATA
LOW BYTE [7:0]
S
P
W
ADDRESS
READ (USING REPEATED START)
6-BIT DEVICE
ADDRESS
REGISTER ADDR
HIGH BYTE
REGISTER ADDR
LOW BYTE
6-BIT DEVICE
ADDRESS
READ DATA
HIGH BYTE [15:8]
READ DATA
LOW BYTE [7:0]
READ DATA
HIGH BYTE [15:8]
READ DATA
LOW BYTE [7:0]
P
ACK
S
W
READ (WRITE TRANSACTION SETS UP REGISTER ADDRESS)
6-BIT DEVICE
ADDRESS
REGISTER ADDR
HIGH BYTE
REGISTER ADDR
LOW BYTE
6-BIT DEVICE
ADDRESS
READ DATA
HIGH BYTE [15:8]
READ DATA
LOW BYTE [7:0]
READ DATA
HIGH BYTE [15:8]
READ DATA
LOW BYTE [7:0]
P
P
ACK
S
S
W
OUTPUT FROM MASTER
OUTPUT FROM AD7147-1
S = START BIT
P = STOP BIT
SR = REPEATED START BIT
ACK = ACKNOWLEDGE BIT
ACK = NO ACKNOWLEDGE BIT
Figure 54. Example of Sequential I2C Write and Readback Operations
This allows the AD7147 to be connected directly to processors
whose supply voltage is less than the minimum operating
voltage of the AD7147 without the need for external level-
shifters. The VDRIVE pin can be connected to voltage supplies as
VDRIVE INPUT
CS
The supply voltage for the pins (SDO, SDI, SCLK, SDA,
,
2
INT
, and GPIO) associated with both the I C and SPI serial
interfaces is supplied from the VDRIVE pin and is separate from the
main VCC supply.
low as 1.65 V and as high as VCC
.
Rev. 0 | Page 36 of 68
AD7147
PCB DESIGN GUIDELINES
CAPACITIVE SENSOR BOARD MECHANICAL SPECIFICATIONS
Table 19.
Parameter
Symbol
Min
0.1
0
Typ
Max
Unit
mm
mm
mm
Distance from Edge of Any Sensor to Edge of Grounded Metal Object
Distance Between Sensor Edges1
Distance Between Bottom of Sensor Board and Controller Board or Grounded
Metal Casing2
D1
D2 = D3 = D4
D5
1.0
1 The distance is dependent on the application and the position of the switches relative to each other and with respect to the user’s finger position and handling.
Adjacent sensors with no space between them are implemented differentially.
2 The 1.0 mm specification is intended to prevent direct sensor board contact with any conductive material. This specification, however, does not guarantee an absence
of EMI coupling from the controller board to the sensors. To avoid potential EMI-coupling issues place a grounded metal shield between the capacitive sensor board
and the main controller board, as shown in Figure 57.
CAPACITIVE SENSOR BOARD
METAL OBJECT
D
5
GROUNDED METAL SHIELD
CAPACITIVE SENSOR
PRINTED CIRCUIT
8-WAY
SWITCH
CONTROLLER PRINTED CIRCUIT BOARD OR METAL CASING
Figure 57. Capacitive Sensor Board with Grounded Shield
D
4
CHIP SCALE PACKAGES
SLIDER
The lands on the chip scale package (CP-24-3) are rectangular.
The printed circuit board pad for these should be 0.1 mm
longer than the package land length and 0.05 mm wider than
the package land width. Center the land on the pad to maximize
the solder joint size.
BUTTONS
D
3
D
2
The bottom of the chip scale package has a central thermal pad.
The thermal pad on the printed circuit board should be at least
as large as this exposed pad. To avoid shorting, provide a
clearance of at least 0.25 mm between the thermal pad and the
inner edges of the land pattern on the printed circuit board.
D
1
Figure 55. Capacitive Sensor Board, Top View
Thermal vias can be used on the printed circuit board thermal
pad to improve the thermal performance of the package. If vias
are used, they should be incorporated in the thermal pad at a
1.2 mm pitch grid. The via diameter should be between 0.3 mm
and 0.33 mm, and the via barrel should be plated with 1 oz
copper to plug the via.
CAPACITIVE SENSOR BOARD
D
5
CONTROLLER PRINTED CIRCUIT BOARD OR METAL CASING
Connect the printed circuit board thermal pad to GND.
Figure 56. Capacitive Sensor Board, Side View
Rev. 0 | Page 37 of 68
AD7147
POWER-UP SEQUENCE
To power up the AD7147, use the following sequence when
initially developing the AD7147 and μP serial interface:
Address 0x004 = 832
Address 0x005 = interrupt enable register (depends on
required interrupt behavior)
1. Turn on the power supplies to the AD7147.
2. Write to the Bank 2 registers at Address 0x080 through
Address 0x0DF. These registers are contiguous; therefore, a
sequential register write sequence can be applied.
Address 0x006 = interrupt enable register (depends on
required interrupt behavior)
Address 0x007 = interrupt enable register (depends on
required interrupt behavior)
Note that the Bank 2 register values are unique for each
application. Register values come from characterization of
the sensor in the application. The characterization process
is outlined in the AN-929 Application Note, available from
Analog Devices.
4. Write to the Bank 1 register, Address 0x001 = 0x0FFF
(depends on number of conversion stages used).
5. Read back the corresponding interrupt status register at
Address 0x008, Address 0x009, or Address 0x00A. This is
determined by the interrupt output configuration, as
explained in the Interrupt Output section.
3. Write to the Bank 1 registers at Address 0x000 through
Address 0x007 as outlined below. These registers are
contiguous; therefore, a sequential register write sequence
can be applied (see Figure 49 and Figure 54).
Note that the specific registers required to be read back
depend on each application. For buttons, the interrupt
status registers are read back while other sensors read data
back from the AD7147 according to the slider or wheel
algorithm’s requirements. Analog Devices can provide this
information after the user develops the sensor board.
Caution: At this time, Address 0x001 must remain set to
default value 0x0000 during this contiguous write operation.
Register values:
Address 0x000 = 0x82B2
Address 0x001 = 0x000
INT
6. Repeat Step 5 every time
is asserted.
Address 0x002 = 0x3230 (depends on number of
conversion stages used)
Address 0x003 = 0x419
POWER
HOST
SERIAL
INTERFACE
CONVERSION
1
2
3
4
5
6
7
8
9
10 11
0
1
2
9
10 11
0
1
2
9
10 11
0
1
CONVERSION STAGES DISABLED
0
STAGE
AD7147 INT
SECOND CONVERSION
SEQUENCE
THIRD CONVERSION
SEQUENCE
FIRST CONVERSION SEQUENCE
Figure 58. Recommended Start-Up Sequence
Rev. 0 | Page 38 of 68
AD7147
TYPICAL APPLICATION CIRCUITS
V
DRIVE
HOST WITH SPI
INTERFACE
1
2
3
4
5
6
2.2kΩ
CIN6
CIN7
CIN8
CIN9
CIN10
CIN11
GPIO 18
BUTTON
BUTTON
BUTTON
17
INT
INT
16
SCROLL
WHEEL
CS
SS
AD7147
15
SCLK
SCK
MOSI
MISO
14
SDI
13
SDO
BUTTON
V
HOST
SENSOR PCB
10nF
V
2.7V TO 3.6V
CC
1.8V
PLANE AROUND SENSORS CONNECTED TO AC
0.1μF
1μF TO 10μF
(OPTIONAL)
SHIELD
Figure 59. Typical Application Circuit with SPI Interface
V
DRIVE
V
DRIVE
V
2.2kꢀ
DRIVE
2.2kꢀ
2
HOST WITH I C
INTERFACE
1
2
3
4
5
6
BUTTON
BUTTON
BUTTON
18
17
CIN6
CIN7
CIN8
CIN9
CIN10
CIN11
GPIO
INT
2.2kꢀ
INT
16
15
ADD1
SCLK
ADD0
SDA
AD7147-1
SCK
SDO
14
13
2-WAY
SWITCH
10nF
V
2.7V TO 3.6V
CC
0.1μF
1μF TO 10μF
(OPTIONAL)
Figure 60. Typical Application Circuit with I2C Interface
Rev. 0 | Page 39 of 68
AD7147
REGISTER MAP
The AD7147 address space is divided into three register banks,
referred to as Bank 1, Bank 2, and Bank 3. Figure 61 illustrates
the division of these banks.
Bank 3 registers contain the results of each conversion stage.
These registers automatically update at the end of each conversion
sequence. Although these registers are primarily used by the
AD7147 internal data processing, they are accessible by the host
processor for additional external data processing, if desired.
Bank 1 registers contain control registers, CDC conversion
control registers, interrupt enable registers, interrupt status
registers, CDC 16-bit conversion data registers, device ID
registers, and proximity status registers.
Default values are undefined for Bank 2 registers and Bank 3
registers until after power-up and configuration of the Bank 2
registers.
Bank 2 registers contain the configuration registers used to
configure the individual CINx inputs for each conversion stage.
Initialize the Bank 2 configuration registers immediately after
power-up to obtain valid CDC conversion result data.
REGISTER BANK 1
REGISTER BANK 2
REGISTER BANK 3
ADDR 0x000
ADDR 0x001
ADDR 0x080
ADDR 0x088
ADDR 0x0E0
ADDR 0x088
STAGE0 CONFIGURATION
(8 REGISTERS)
STAGE0 RESULTS
(36 REGISTERS)
SETUP CONTROL
(1 REGISTER)
STAGE1 CONFIGURATION
(8 REGISTERS)
STAGE1 RESULTS
(36 REGISTERS)
CALIBRATION AND SETUP
(4 REGISTERS)
ADDR 0x090
ADDR 0x098
ADDR 0x0A0
ADDR 0x0A8
ADDR 0x090
ADDR 0x098
STAGE2 RESULTS
(36 REGISTERS)
STAGE2 CONFIGURATION
(8 REGISTERS)
ADDR 0x005
STAGE3 CONFIGURATION
(8 REGISTERS)
STAGE3 RESULTS
(36 REGISTERS)
INTERRUPT ENABLE
(3 REGISTERS)
ADDR 0x0A0
ADDR 0x0A8
STAGE4 RESULTS
(36 REGISTERS)
STAGE4 CONFIGURATION
(8 REGISTERS)
ADDR 0x008
ADDR 0x00B
ADDR 0x017
INTERRUPT STATUS
(3 REGISTERS)
STAGE5 RESULTS
(36 REGISTERS)
STAGE5 CONFIGURATION
(8 REGISTERS)
ADDR 0x0B0
ADDR 0x0B8
ADDR 0x0C0
ADDR 0x0C8
ADDR 0x0D0
ADDR 0x0D8
ADDR 0x0B0
ADDR 0x0B8
ADDR 0x0C0
ADDR 0x0C8
ADDR 0x0D0
ADDR 0x28F
CDC 16-BIT CONVERSION DATA
(12 REGISTERS)
STAGE6 RESULTS
(36 REGISTERS)
STAGE6 CONFIGURATION
(8 REGISTERS)
STAGE7 RESULTS
(36 REGISTERS)
STAGE7 CONFIGURATION
(8 REGISTERS)
DEVICE ID REGISTER
(1 REGISTER)
ADDR 0x018
ADDR 0x042
STAGE8 RESULTS
(36 REGISTERS)
STAGE8 CONFIGURATION
(8 REGISTERS)
INVALID DO NOT ACCESS
PROXIMITY STATUS REGISTER
(1 REGISTER)
STAGE9 RESULTS
(36 REGISTERS)
STAGE9 CONFIGURATION
(8 REGISTERS)
ADDR 0x043
STAGE10 RESULTS
(36 REGISTERS)
STAGE10 CONFIGURATION
(8 REGISTERS)
INVALID DO NOT ACCESS
STAGE11 RESULTS
(36 REGISTERS)
STAGE11 CONFIGURATION
(8 REGISTERS)
ADDR 0x7F0
Figure 61. Layout of Bank 1, Bank 2, and Bank 3 Registers
Rev. 0 | Page 40 of 68
AD7147
DETAILED REGISTER DESCRIPTIONS
BANK 1 REGISTERS
All addresses and default values are expressed in hexadecimal.
Table 20. PWR_CONTROL Register
Default
Value
Address Data Bit
Type Name
Description
0x000
[1:0]
0
R/W
POWER_MODE
Operating modes
00 = full power mode (normal operation, CDC
conversions approximately every 36 ms)
01 = full shutdown mode (no CDC conversions)
10 = low power mode (automatic wake-up operation)
11 = full shutdown mode (no CDC conversions)
Low power mode conversion delay
00 = 200 ms
01 = 400 ms
10 = 600 ms
11 = 800 ms
[3:2]
[7:4]
0
0
R/W
R/W
LP_CONV_DELAY
SEQUENCE_STAGE_NUM Number of stages in sequence (N + 1)
0000 = 1 conversion stage in sequence
0001 = 2 conversion stages in sequence
……
Maximum value = 1011 = 12 conversion stages per
sequence
[9:8]
0
R/W
DECIMATION
ADC decimation factor
00 = decimate by 256
01 = decimate by 128
10 = decimate by 64
11 = decimate by 64
[10]
[11]
0
0
R/W
R/W
SW_RESET
INT_POL
Software reset control (self-clearing)
1 = resets all registers to default values
Interrupt polarity control
0 = active low
1 = active high
[12]
0
R/W
R/W
EXT_SOURCE
Excitation source control
0 = enable excitation source to CINx pins
1 = disable excitation source to CINx pins
Set to 0
CDC bias current control
00 = normal operation
[13]
[15:14]
0
0
Unused
CDC_BIAS
01 = normal operation + 20%
10 = normal operation + 35%
11 = normal operation + 50%
Rev. 0 | Page 41 of 68
AD7147
Table 21. STAGE_CAL_EN Register
Default
Data Bit Value
Address
Type
Name
Description
0x001
[0]
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W
STAGE0_CAL_EN
STAGE0 calibration enable
0 = disable
1 = enable
STAGE1 calibration enable
0 = disable
1 = enable
STAGE2 calibration enable
0 = disable
1 = enable
STAGE3 calibration enable
0 = disable
1 = enable
STAGE4 calibration enable
0 = disable
1 = enable
STAGE5 calibration enable
0 = disable
1 = enable
STAGE6 calibration enable
0 = disable
1 = enable
STAGE7 calibration enable
0 = disable
1 = enable
STAGE8 calibration enable
0 = disable
1 = enable
STAGE9 calibration enable
0 = disable
1 = enable
STAGE10 calibration enable
0 = disable
1 = enable
STAGE11 calibration enable
0 = disable
1 = enable
Full power mode skip control
00 = skip 3 samples
01 = skip 7 samples
10 = skip 15 samples
11 = skip 31 samples
Low power mode skip control
00 = use all samples
01 = skip one sample
10 = skip two samples
11 = skip three samples
[1]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
STAGE1_CAL_EN
STAGE2_CAL_EN
STAGE3_CAL_EN
STAGE4_CAL_EN
STAGE5_CAL_EN
STAGE6_CAL_EN
STAGE7_CAL_EN
STAGE8_CAL_EN
STAGE9_CAL_EN
STAGE10_CAL_EN
STAGE11_CAL_EN
AVG_FP_SKIP
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
[10]
[11]
[13:12]
[15:14]
0
R/W
AVG_LP_SKIP
Rev. 0 | Page 42 of 68
AD7147
Table 22. AMB_COMP_CTRL0 Register
Default
Data Bit Value
Address
Type
Name
Description
0x002
[3:0]
0
R/W
FF_SKIP_CNT
Fast filter skip control (N + 1)
0000 = no sequence of results is skipped
0001 = one sequence of results is skipped for every one
allowed into fast FIFO
0010 = two sequences of results are skipped for every
one allowed into fast FIFO
1011 = maximum value = 12 sequences of results are
skipped for every one allowed into fast FIFO
[7:4]
F
F
0
R/W
R/W
R/W
FP_PROXIMITY_CNT
LP_PROXIMITY_CNT
PWR_DOWN_TIMEOUT
Calibration disable period in full power mode =
FP_PROXIMITY_CNT × 16 × time for one conversion
sequence in full power mode
Calibration disable period in low power mode =
LP_PROXIMITY_CNT × 4 × time for one conversion
sequence in low power mode
Full power to low power mode timeout control
00 = 1.25 × (FP_PROXIMITY_CNT)
01 = 1.50 × (FP_PROXIMITY_CNT)
10 = 1.75 × (FP_PROXIMITY_CNT)
11 = 2.00 × (FP_PROXIMITY_CNT)
Forced calibration control
[11:8]
[13:12]
[14]
[15]
0
0
R/W
R/W
FORCED_CAL
CONV_RESET
0 = normal operation
1 = forces all conversion stages to recalibrate
Conversion reset control (self-clearing)
0 = normal operation
1 = resets the conversion sequence to STAGE0
Table 23. AMB_COMP_CTRL1 Register
Default
Data Bit Value
Address
Type
Name
Description
0x003
[7:0]
64
R/W
PROXIMITY_RECAL_LVL
Proximity recalibration level. Value is multiplied by 16 to
determine actual recalibration level.
[13:8]
[15:14]
1
R/W
R/W
PROXIMITY_DETECTION_RATE
SLOW_FILTER_UPDATE_LVL
Proximity detection rate. Value is multiplied by 16 to
determine actual detection rate.
Slow filter update level.
0
Table 24. AMB_COMP_CTRL2 Register
Default
Data Bit Value
Address
Type
R/W
R/W
Name
Description
0x004
[9:0]
[15:10]
3FF
3F
FP_PROXIMITY_RECAL
LP_PROXIMITY_RECAL
Full power mode proximity recalibration time control
Low power mode proximity recalibration time control
Rev. 0 | Page 43 of 68
AD7147
Table 25. STAGE_LOW_INT_ENABLE Register
Default
Value
Address Data Bit
Type
Name
Description
0x005
[0]
0
R/W
STAGE0_LOW_INT_ENABLE
STAGE0 low interrupt enable
0 = interrupt source disabled
1 = INT asserted if STAGE0 low threshold is exceeded
STAGE1 low interrupt enable
0 = interrupt source disabled
1 = INT asserted if STAGE1 low threshold is exceeded
STAGE2 low interrupt enable
0 = interrupt source disabled
1 = INT asserted if STAGE2 low threshold is exceeded
STAGE3 low interrupt enable
0 = interrupt source disabled
1 = INT asserted if STAGE3 low threshold is exceeded
STAGE4 low interrupt enable
0 = interrupt source disabled
1 = INT asserted if STAGE4 low threshold is exceeded
STAGE5 low interrupt enable
0 = interrupt source disabled
1 = INT asserted if STAGE5 low threshold is exceeded
STAGE6 low interrupt enable
0 = interrupt source disabled
1 = INT asserted if STAGE6 low threshold is exceeded
STAGE7 low interrupt enable
0 = interrupt source disabled
1 = INT asserted if STAGE7 low threshold is exceeded
STAGE8 low interrupt enable
0 = interrupt source disabled
1 = INT asserted if STAGE8 low threshold is exceeded
STAGE9 low interrupt enable
0 = interrupt source disabled
1 = INT asserted if STAGE9 low threshold is exceeded
STAGE10 low interrupt enable
0 = interrupt source disabled
1 = INT asserted if STAGE10 low threshold is exceeded
STAGE11 low interrupt enable
0 = interrupt source disabled
1 = INT asserted if STAGE11 low threshold is exceeded
GPIO setup
[1]
0
0
0
0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
STAGE1_LOW_INT_ENABLE
STAGE2_LOW_INT_ENABLE
STAGE3_LOW_INT_ENABLE
STAGE4_LOW_INT_ENABLE
STAGE5_LOW_INT_ENABLE
STAGE6_LOW_INT_ENABLE
STAGE7_LOW_INT_ENABLE
STAGE8_LOW_INT_ENABLE
STAGE9_LOW_INT_ENABLE
STAGE10_LOW_INT_ENABLE
STAGE11_LOW_INT_ENABLE
GPIO_SETUP
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
[10]
[11]
[13:12]
00 = disable GPIO pin
01 = configure GPIO as an input
10 = configure GPIO as an active low output
11 = configure GPIO as an active high output
GPIO input configuration
[15:14]
0
R/W
GPIO_INPUT_CONFIG
00 = triggered on negative level
01 = triggered on positive edge
10 = triggered on negative edge
11 = triggered on positive level
Rev. 0 | Page 44 of 68
AD7147
Table 26. STAGE_HIGH_INT_ENABLE Register
Default
Value
Address Data Bit
Type
Name
Description
0x006
[0]
0
R/W
STAGE0_HIGH_INT_ENABLE
STAGE0 high interrupt enable
0 = interrupt source disabled
1 = INT asserted if STAGE0 high threshold is exceeded
STAGE1 high interrupt enable
0 = interrupt source disabled
1 = INT asserted if STAGE1 high threshold is exceeded
STAGE2 high interrupt enable
0 = interrupt source disabled
1 = INT asserted if STAGE2 high threshold is exceeded
STAGE3 high interrupt enable
0 = interrupt source disabled
1 = INT asserted if STAGE3 high threshold is exceeded
STAGE4 high interrupt enable
0 = interrupt source disabled
1 = INT asserted if STAGE4 high threshold is exceeded
STAGE5 high interrupt enable
0 = interrupt source disabled
1 = INT asserted if STAGE5 high threshold is exceeded
STAGE6 high interrupt enable
0 = interrupt source disabled
1 = INT asserted if STAGE6 high threshold is exceeded
STAGE7 high interrupt enable
0 = interrupt source disabled
1 = INT asserted if STAGE7 high threshold is exceeded
STAGE8 high interrupt enable
0 = interrupt source disabled
[1]
0
0
0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
STAGE1_HIGH_INT_ENABLE
STAGE2_HIGH_INT_ENABLE
STAGE3_HIGH_INT_ENABLE
STAGE4_HIGH_INT_ENABLE
STAGE5_HIGH_INT_ENABLE
STAGE6_HIGH_INT_ENABLE
STAGE7_HIGH_INT_ENABLE
STAGE8_HIGH_INT_ENABLE
STAGE9_HIGH_INT_ENABLE
STAGE10_HIGH_INT_ENABLE
STAGE11_HIGH_INT_ENABLE
Unused
[2]
[3]
[4]
[5]
[6]
[7]
[8]
1 = INT asserted if STAGE8 high threshold is exceeded
STAGE9 sensor high interrupt enable
0 = interrupt source disabled
1 = INT asserted if STAGE9 high threshold is exceeded
STAGE10 high interrupt enable
0 = interrupt source disabled
1 = INT asserted if STAGE10 high threshold is exceeded
STAGE11 high interrupt enable
[9]
[10]
[11]
[15:12]
0 = interrupt source disabled
1 = INT asserted if STAGE11 high threshold is exceeded
Set to 0
Rev. 0 | Page 45 of 68
AD7147
Table 27. STAGE_COMPLETE_INT_ENABLE Register
Default
Value
Address Data Bit
Type
Name
Description
0x007
[0]
0
R/W
STAGE0_COMPLETE_INT_ENABLE
STAGE0 conversion interrupt control
0 = interrupt source disabled
1 = INT asserted at completion of STAGE0 conversion
STAGE1 conversion interrupt control
0 = interrupt source disabled
1 = INT asserted at completion of STAGE1 conversion
STAGE2 conversion interrupt control
0 = interrupt source disabled
1 = INT asserted at completion of STAGE2 conversion
STAGE3 conversion interrupt control
0 = interrupt source disabled
1 = INT asserted at completion of STAGE3 conversion
STAGE4 conversion interrupt control
0 = interrupt source disabled
1 = INT asserted at completion of STAGE4 conversion
STAGE5 conversion interrupt control
0 = interrupt source disabled
1 = INT asserted at completion of STAGE5 conversion
STAGE6 conversion interrupt control
0 = interrupt source disabled
1 = INT asserted at completion of STAGE6 conversion
STAGE7 conversion interrupt control
0 = interrupt source disabled
1 = INT asserted at completion of STAGE7 conversion
STAGE8 conversion complete interrupt control
0 = interrupt source disabled
[1]
0
0
0
0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
STAGE1_COMPLETE_INT_ENABLE
STAGE2_COMPLETE_INT_ENABLE
STAGE3_COMPLETE_INT_ENABLE
STAGE4_COMPLETE_INT_ENABLE
STAGE5_COMPLETE_INT_ENABLE
STAGE6_COMPLETE_INT_ENABLE
STAGE7_COMPLETE_INT_ENABLE
STAGE8_COMPLETE_INT_ENABLE
STAGE9_COMPLETE_INT_ENABLE
[2]
[3]
[4]
[5]
[6]
[7]
[8]
1 = INT asserted at completion of STAGE8 conversion
STAGE9 conversion interrupt control
0 = interrupt source disabled
[9]
1 = INT asserted at completion of STAGE9 conversion
[10]
[11]
[12]
[15:13]
STAGE10_COMPLETE_INT_ENABLE STAGE10 conversion interrupt control
0 = interrupt source disabled
1 = INT asserted at completion of STAGE10 conversion
STAGE11_COMPLETE_INT_ENABLE STAGE11 conversion interrupt control
0 = interrupt source disabled
1 = INT asserted at completion of STAGE11 conversion
GPIO_INT_ENABLE
Unused
Interrupt control when GPIO input pin changes level
0 = disabled
1 = enabled
Set to 0
Rev. 0 | Page 46 of 68
AD7147
Table 28. STAGE_LOW_INT_STATUS Register1
Default
Value
Address Data Bit
Type
Name
Description
0x008
[0]
0
R
STAGE0_LOW_INT_STATUS
STAGE0 CDC conversion low limit interrupt result
1 = indicates STAGE0_LOW_THRESHOLD value was
exceeded
[1]
0
0
0
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
R
R
R
STAGE1_LOW_INT_STATUS
STAGE2_LOW_INT_STATUS
STAGE3_LOW_INT_STATUS
STAGE4_LOW_INT_STATUS
STAGE5_LOW_INT_STATUS
STAGE6_LOW_INT_STATUS
STAGE7_LOW_INT_STATUS
STAGE8_LOW_INT_STATUS
STAGE9_LOW_INT_STATUS
STAGE10_LOW_INT_STATUS
STAGE11_LOW_INT_STATUS
Unused
STAGE1 CDC conversion low limit interrupt result
1 = indicates STAGE1_LOW_THRESHOLD value was
exceeded
STAGE2 CDC conversion low limit interrupt result
1 = indicates STAGE2_LOW_THRESHOLD value was
exceeded
STAGE3 CDC conversion low limit interrupt result
1 = indicates STAGE3_LOW_THRESHOLD value was
exceeded
STAGE4 CDC conversion low limit interrupt result
1 = indicates STAGE4_LOW_THRESHOLD value was
exceeded
STAGE5 CDC conversion low limit interrupt result
1 = indicates STAGE5_LOW_THRESHOLD value was
exceeded
STAGE6 CDC conversion low limit interrupt result
1 = indicates STAGE6_LOW_THRESHOLD value was
exceeded
STAGE7 CDC conversion low limit interrupt result
1 = indicates STAGE7_LOW_THRESHOLD value was
exceeded
STAGE8 CDC conversion low limit interrupt result
1 = indicates STAGE8_LOW_THRESHOLD value was
exceeded
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
STAGE9 CDC conversion low limit interrupt result
1 = indicates STAGE9_LOW_THRESHOLD value was
exceeded
STAGE10 CDC Conversion Low Limit Interrupt result
1 = indicates STAGE10_LOW_THRESHOLD value was
exceeded
STAGE11 CDC conversion low limit interrupt result
1 = indicates STAGE11_LOW_THRESHOLD value was
exceeded
[10]
[11]
[15:12]
Set to 0
1 Registers self-clear to 0 after readback if the limits are not exceeded.
Rev. 0 | Page 47 of 68
AD7147
Table 29. STAGE_HIGH_INT_STATUS Register1
Default
Value
Address Data Bit
Type
Name
Description
0x009
[0]
0
R
STAGE0_HIGH_INT_STATUS
STAGE0 CDC conversion high limit interrupt result
1 = indicates STAGE0_HIGH_THRESHOLD value was
exceeded
[1]
0
0
0
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
R
R
R
STAGE1_HIGH_INT_STATUS
STAGE2_HIGH_INT_STATUS
STAGE3_HIGH_INT_STATUS
STAGE4_HIGH_INT_STATUS
STAGE5_HIGH_INT_STATUS
STAGE6_HIGH_INT_STATUS
STAGE7_HIGH_INT_STATUS
STAGE8_HIGH_INT_STATUS
STAGE9_HIGH_INT_STATUS
STAGE10_HIGH_INT_STATUS
STAGE11_HIGH_INT_STATUS
Unused
STAGE1 CDC conversion high limit interrupt result
1 = indicates STAGE1_HIGH_THRESHOLD value was
exceeded
Stage2 CDC conversion high limit interrupt result
1 = indicates STAGE2_HIGH_THRESHOLD value was
exceeded
STAGE3 CDC conversion high limit interrupt result
1 = indicates STAGE3_HIGH_THRESHOLD value was
exceeded
STAGE4 CDC conversion high limit interrupt result
1 = indicates STAGE4_HIGH_THRESHOLD value was
exceeded
STAGE5 CDC conversion high limit interrupt result
1 = indicates STAGE5_HIGH_THRESHOLD value was
exceeded
STAGE6 CDC conversion high limit interrupt result
1 = indicates STAGE6_HIGH_THRESHOLD value was
exceeded
STAGE7 CDC conversion high limit interrupt result
1 = indicates STAGE7_HIGH_THRESHOLD value was
exceeded
STAGE8 CDC conversion high limit interrupt result
1 = indicates STAGE8_HIGH_THRESHOLD value was
exceeded
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
STAGE9 CDC conversion high limit interrupt result
1 = indicates STAGE9_HIGH_THRESHOLD value was
exceeded
STAGE10 CDC conversion high limit interrupt result
1 = indicates STAGE10_HIGH_THRESHOLD value was
exceeded
STAGE11 CDC conversion high limit interrupt result
1 = indicates STAGE11_HIGH_THRESHOLD value was
exceeded
[10]
[11]
[15:12]
Set to 0
1 Registers self-clear to 0 after readback if the limits are not exceeded.
Rev. 0 | Page 48 of 68
AD7147
Table 30. STAGE_COMPLETE_INT_STATUS Register1
Default
Value
Address Data Bit
Type Name
STAGE0_COMPLETE_INT_STATUS
Description
0x00A
[0]
0
R
R
R
R
R
R
R
R
R
R
R
R
R
STAGE0 conversion complete register interrupt status
1 = indicates STAGE0 conversion completed
STAGE1 conversion complete register interrupt status
1 = indicates STAGE1 conversion completed
STAGE2 conversion complete register interrupt status
1 = indicates STAGE2 conversion completed
STAGE3 conversion complete register interrupt status
1 = indicates STAGE3 conversion completed
STAGE4 conversion complete register interrupt status
1 = indicates STAGE4 conversion completed
STAGE5 conversion complete register interrupt status
1 = indicates STAGE5 conversion completed
STAGE6 conversion complete register interrupt status
1 = indicates STAGE6 conversion completed
STAGE7 conversion complete register interrupt status
1 = indicates STAGE7 conversion completed
STAGE8 conversion complete register interrupt status
1 = indicates STAGE8 conversion completed
STAGE9 conversion complete register interrupt status
1 = indicates STAGE9 conversion completed
STAGE10 conversion complete register interrupt status
1 = indicates STAGE10 conversion completed
STAGE11 conversion complete register interrupt status
1 = indicates STAGE11 conversion completed
GPIO input pin status
[1]
0
0
0
0
0
0
0
0
0
0
0
0
STAGE1_COMPLETE_INT_STATUS
STAGE2_COMPLETE_INT_STATUS
STAGE3_COMPLETE_INT_STATUS
STAGE4_COMPLETE_INT_STATUS
STAGE5_COMPLETE_INT_STATUS
STAGE6_COMPLETE_INT_STATUS
STAGE7_COMPLETE_INT_STATUS
STAGE8_COMPLETE_INT_STATUS
STAGE9_COMPLETE_INT_STATUS
STAGE10_COMPLETE_INT_STATUS
STAGE11_COMPLETE_INT_STATUS
GPIO_INT_STATUS
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
[10]
[11]
[12]
[15:13]
1 = indicates level on GPIO pin has changed
Set to 0
Unused
1 Registers self-clear to 0 after readback if the limits are not exceeded.
Table 31. CDC 16-Bit Conversion Data Registers
Default
Value
Address Data Bit
Type
R
R
R
R
R
R
R
R
R
R
R
R
Name
Description
0x00B
0x00C
0x00D
0x00E
0x00F
0x010
0x011
0x012
0x013
0x014
0x015
0x016
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
0
0
0
0
0
0
0
0
0
0
0
0
CDC_RESULT_S0
CDC_RESULT_S1
CDC_RESULT_S2
CDC_RESULT_S3
CDC_RESULT_S4
CDC_RESULT_S5
CDC_RESULT_S6
CDC_RESULT_S7
CDC_RESULT_S8
CDC_RESULT_S9
CDC_RESULT_S10
CDC_RESULT_S11
STAGE0 CDC 16-bit conversion data
STAGE1 CDC 16-bit conversion data
STAGE2 CDC 16-bit conversion data
STAGE3 CDC 16-bit conversion data
STAGE4 CDC 16-bit conversion data
STAGE5 CDC 16-bit conversion data
STAGE6 CDC 16-bit conversion data
STAGE7 CDC 16-bit conversion data
STAGE8 CDC 16-bit conversion data
STAGE9 CDC 16-bit conversion data
STAGE10 CDC 16-bit conversion data
STAGE11 CDC 16-bit conversion data
Rev. 0 | Page 49 of 68
AD7147
Table 32. Device ID Register
Default
Value
Address Data Bit
Type
Name
Description
0x017
[3:0]
[15:4]
0
147
R
R
REVISION_CODE
DEVID
Revision code
Device ID = 0001 0100 0111
Table 33. Proximity Status Register
Default
Value
Address Data Bit
Type
Name
Description
0x042
[0]
0
R
STAGE0_PROXIMITY_STATUS
STAGE0 proximity status register
1 = indicates proximity has been detected on STAGE0
STAGE1 proximity status register
1 = indicates proximity has been detected on STAGE1
STAGE2 proximity status register
1 = indicates proximity has been detected on STAGE2
STAGE3 proximity status register
1 = indicates proximity has been detected on STAGE3
STAGE4 proximity status register
1 = indicates proximity has been detected on STAGE4
STAGE5 proximity status register
1 = indicates proximity has been detected on STAGE5
STAGE6 proximity status register
1 = indicates proximity has been detected on STAGE6
STAGE7 proximity status register
1 = indicates proximity has been detected on STAGE7
STAGE8 proximity status register
1 = indicates proximity has been detected on STAGE8
STAGE9 proximity status register
1 = indicates proximity has been detected on STAGE9
STAGE10 proximity status register
1 = indicates proximity has been detected on STAGE10
STAGE11 proximity status register
1 = indicates proximity has been detected on STAGE11
Set to 0
[1]
0
0
0
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
R
R
R
STAGE1_PROXIMITY_STATUS
STAGE2_PROXIMITY_STATUS
STAGE3_PROXIMITY_STATUS
STAGE4_PROXIMITY_STATUS
STAGE5_PROXIMITY_STATUS
STAGE6_PROXIMITY_STATUS
STAGE7_PROXIMITY_STATUS
STAGE8_PROXIMITY_STATUS
STAGE9_PROXIMITY_STATUS
STAGE10_PROXIMITY_STATUS
STAGE11_PROXIMITY_STATUS
Unused
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
[10]
[11]
[15:12]
Rev. 0 | Page 50 of 68
AD7147
BANK 2 REGISTERS
All address values are expressed in hexadecimal.
Table 34. STAGEx_CONNECTION [6:0] Register Description (x = 0 to 11)
Default
Value
Data Bit
Type
Name
Description
[1:0]
X
R/W
CIN0_CONNECTION_SETUP
CIN0 connection setup
00 = CIN0 not connected to CDC inputs
01 = CIN0 connected to CDC negative input
10 = CIN0 connected to CDC positive input
11 = CIN0 connected to BIAS (connect unused CINx inputs)
CIN1 connection setup
[3:2]
X
X
X
X
X
X
X
R/W
R/W
R/W
R/W
R/W
R/W
CIN1_CONNECTION_SETUP
CIN2_CONNECTION_SETUP
CIN3_CONNECTION_SETUP
CIN4_CONNECTION_SETUP
CIN5_CONNECTION_SETUP
CIN6_CONNECTION_SETUP
Unused
00 = CIN1 not connected to CDC inputs
01 = CIN1 connected to CDC negative input
10 = CIN1 connected to CDC positive input
11 = CIN1 connected to BIAS (connect unused CINx inputs)
CIN2 connection setup
00 = CIN2 not connected to CDC inputs
01 = CIN2 connected to CDC negative input
10 = CIN2 connected to CDC positive input
11 = CIN2 connected to BIAS (connect unused CINx inputs)
CIN3 connection setup
00 = CIN3 not connected to CDC inputs
01 = CIN3 connected to CDC negative input
10 = CIN3 connected to CDC positive input
11 = CIN3 connected to BIAS (connect unused CINx inputs)
CIN4 connection setup
00 = CIN4 not connected to CDC inputs
01 = CIN4 connected to CDC negative input
10 = CIN4 connected to CDC positive input
11 = CIN4 connected to BIAS (connect unused CINx inputs)
CIN5 connection setup
00 = CIN5 not connected to CDC inputs
01 = CIN5 connected to CDC negative input
10 = CIN5 connected to CDC positive input
11 = CIN5 connected to BIAS (connect unused CINx inputs)
CIN6 connection setup
00 = CIN6 not connected to CDC inputs
01 = CIN6 connected to CDC negative input
10 = CIN6 connected to CDC positive input
11 = CIN6 connected to BIAS (connect unused CINx inputs)
Set to 0
[5:4]
[7:6]
[9:8]
[11:10]
[13:12]
[15:14]
Rev. 0 | Page 51 of 68
AD7147
Table 35. STAGEx_CONNECTION [12:7] Register Description (x = 0 to 11)
Default
Value
Data Bit
Type
Name
Description
[1:0]
X
R/W
CIN7_CONNECTION_SETUP
CIN7 connection setup
00 = CIN7 not connected to CDC inputs
01 = CIN7 connected to CDC negative input
10 = CIN7 connected to CDC positive input
11 = CIN7 connected to BIAS (connect unused CINx inputs)
CIN8 connection setup
00 = CIN8 not connected to CDC inputs
01 = CIN8 connected to CDC negative input
10 = CIN8 connected to CDC positive input
11 = CIN8 connected to BIAS (connect unused CINx inputs)
CIN9 connection setup
00 = CIN9 not connected to CDC inputs
01 = CIN9 connected to CDC negative input
10 = CIN9 connected to CDC positive input
11 = CIN9 connected to BIAS (connect unused CINx inputs)
CIN10 connection setup
00 = CIN10 not connected to CDC inputs
01 = CIN10 connected to CDC negative input
10 = CIN10 connected to CDC positive input
11 = CIN10 connected to BIAS (connect unused CINx inputs)
CIN11 connection setup
00 = CIN11 not connected to CDC inputs
01 = CIN11 connected to CDC negative input
10 = CIN11 connected to CDC positive input
11 = CIN11 connected to BIAS (connect unused CINx inputs)
CIN12 connection setup
00 = CIN12 not connected to CDC inputs
01 = CIN12 connected to CDC negative input
10 = CIN12 connected to CDC positive input
11 = CIN12 connected to BIAS (connect unused CINx inputs)
Single-ended measurement connection setup.
00 =Do not use
[3:2]
X
X
X
X
X
X
R/W
R/W
R/W
R/W
R/W
R/W
CIN8_CONNECTION_SETUP
CIN9_CONNECTION_SETUP
CIN10_CONNECTION_SETUP
CIN11_CONNECTION_SETUP
CIN12_CONNECTION_SETUP
SE_CONNECTION_SETUP
[5:4]
[7:6]
[9:8]
[11:10]
[13:12]
01 = Use when one CINx connected to CDC positive input,
single-ended measurements only
10 = Use when one CINx connected to CDC negative input,
single-ended measurements only
11 = Differential connection to CDC
Negative AFE offset enable control
0 = enable
[14]
[15]
X
X
R/W
R/W
NEG_AFE_OFFSET_DISABLE
POS_AFE_OFFSET_DISABLE
1 = disable
Positive AFE offset enable control
0 = enable
1 = disable
Rev. 0 | Page 52 of 68
AD7147
Table 36. STAGEx_AFE_OFFSET Register Description (x = 0 to 11)
Default
Value
Data Bit
Type
Name
Description
[5:0]
X
R/W
NEG_AFE_OFFSET
Negative AFE offset setting (20 pF range)
1 LSB value = 0.32 pF of offset
[6]
[7]
X
X
Unused
Set to 0
R/W
R/W
R/W
NEG_AFE_OFFSET_SWAP
Negative AFE offset swap control
0 = NEG_AFE_OFFSET applied to CDC negative input
1 = NEG_AFE_OFFSET applied to CDC positive input
Positive AFE offset setting (20 pF range)
1 LSB value = 0.32 pF of offset
[13:8]
X
POS_AFE_OFFSET
[14]
[15]
X
X
Unused
Set to 0
POS_AFE_OFFSET_SWAP
Positive AFE offset swap control
0 = POS_AFE_OFFSET applied to CDC positive input
1 = POS_AFE_OFFSET applied to CDC negative input
Table 37. STAGEx_SENSITIVITY Register Description (x = 0 to 11)
Default
Value
Data Bit
Type
Name
Description
[3:0]
X
R/W
NEG_THRESHOLD_SENSITIVITY
Negative threshold sensitivity control
0000 = 25%, 0001 = 29.73%, 0010 = 34.40%, 0011 = 39.08%
0100 = 43.79%, 0101 = 48.47%, 0110 = 53.15%
0111 = 57.83%, 1000 = 62.51%, 1001 = 67.22%
1010 = 71.90%, 1011 = 76.58%, 1100 = 81.28%
1101 = 85.96%, 1110 = 90.64%, 1111 = 95.32%
Negative peak detect setting
[6:4]
X
R/W
NEG_PEAK_DETECT
000 = 40% level, 001 = 50% level, 010 = 60% level
011 = 70% level, 100 = 80% level, 101 = 90% level
Set to 0
[7]
X
X
R/W
R/W
Unused
[11:8]
POS_THRESHOLD_SENSITIVITY
Positive threshold sensitivity control
0000 = 25%, 0001 = 29.73%, 0010 = 34.40%, 0011 = 39.08%
0100 = 43.79%, 0101 = 48.47%, 0110 = 53.15%
0111 = 57.83%, 1000 = 62.51%, 1001 = 67.22%
1010 = 71.90%, 1011 = 76.58%, 1100 = 81.28%
1101 = 85.96%, 1110 = 90.64%, 1111 = 95.32%
Positive peak detect setting
000 = 40% level, 001 = 50% level, 010 = 60% level
011 = 70% level, 100 = 80% level, 101 = 90% level
Set to 0
[14:12]
[15]
X
X
R/W
R/W
POS_PEAK_DETECT
Unused
Rev. 0 | Page 53 of 68
AD7147
Table 38. STAGE0 to Stage12 Configuration Registers
Address
0x080
0x081
0x082
0x083
0x084
0x085
0x086
0x087
0x088
0x089
0x08A
0x08B
0x08C
0x08D
0x08E
0x08F
0x090
0x091
0x092
0x093
0x094
0x095
0x096
0x097
0x098
0x099
0x09A
0x09B
0x09C
0x09D
0x09E
0x09F
0x0A0
0x0A1
0x0A2
0x0A3
0x0A4
0x0A5
0x0A6
0x0A7
0x0A8
0x0A9
0x0AA
0x0AB
0x0AC
0x0AD
0x0AE
0x0AF
Data Bit
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
Default
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Type Name
Description
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
STAGE0_CONNECTION [6:0]
STAGE0_CONNECTION [12:7]
STAGE0_AFE_OFFSET
STAGE0_SENSITIVITY
STAGE0_OFFSET_LOW
STAGE0 CIN [6:0] connection setup (see Table 34)
STAGE0 CIN [12:7] connection setup (see Table 35)
STAGE0 AFE offset control (see Table 36)
STAGE0 sensitivity control (see Table 37)
STAGE0 initial offset low value
STAGE0 initial offset high value
STAGE0 offset high clamp value
STAGE0 offset low clamp value
STAGE0_OFFSET_HIGH
STAGE0_OFFSET_HIGH_CLAMP
STAGE0_ OFFSET_LOW_CLAMP
STAGE1_CONNECTION [6:0]
STAGE1_CONNECTION [12:7]
STAGE1_AFE_OFFSET
STAGE1_SENSITIVITY
STAGE1_OFFSET_LOW
STAGE1_OFFSET_HIGH
STAGE1_OFFSET_HIGH_CLAMP
STAGE1_OFFSET_LOW_CLAMP
STAGE2_CONNECTION [6:0]
STAGE2_CONNECTION [12:7]
STAGE2_AFE_OFFSET
STAGE2_SENSITIVITY
STAGE2_OFFSET_LOW
STAGE2_OFFSET_HIGH
STAGE2_OFFSET_HIGH_CLAMP
STAGE2_OFFSET_LOW_CLAMP
STAGE3_CONNECTION [6:0]
STAGE3_CONNECTION [12:7]
STAGE3_AFE_OFFSET
STAGE3_SENSITIVITY
STAGE3_OFFSET_LOW
STAGE3_OFFSET_HIGH
STAGE3_OFFSET_HIGH_CLAMP
STAGE3_OFFSET_LOW_CLAMP
STAGE4_CONNECTION [6:0]
STAGE4_CONNECTION [12:7]
STAGE4_AFE_OFFSET
STAGE4_SENSITIVITY
STAGE4_OFFSET_LOW
STAGE4_OFFSET_HIGH
STAGE1 CIN [6:0] connection setup (see Table 34)
STAGE1 CIN [12:7] connection setup (see Table 35)
STAGE1 AFE offset control (see Table 36)
STAGE1 sensitivity control (see Table 37)
STAGE1 initial offset low value
STAGE1 initial offset high value
STAGE1 offset high clamp value
STAGE1 offset low clamp value
STAGE2 CIN [6:0] connection setup (see Table 34)
STAGE2 CIN [12:7] connection setup (see Table 35)
STAGE2 AFE offset control (see Table 36)
STAGE2 sensitivity control (see Table 37)
STAGE2 initial offset low value
STAGE2 initial offset high value
STAGE2 offset high clamp value
STAGE2 offset low clamp value
STAGE3 CIN [6:0] connection setup (see Table 34
STAGE3 CIN [12:7] connection setup (see Table 35)
STAGE3 AFE offset control (see Table 36)
STAGE3 sensitivity control (see Table 37)
STAGE3 initial offset low value
STAGE3 initial offset high value
STAGE3 offset high clamp value
STAGE3 offset low clamp value
STAGE4 CIN [6:0] connection setup (see Table 34)
STAGE4 CIN [12:7] connection setup (see Table 35)
STAGE4 AFE offset control (see Table 36)
STAGE4 sensitivity control (see Table 37)
STAGE4 initial offset low value
STAGE4 initial offset high value
STAGE4 offset high clamp value
STAGE4 offset low clamp value
STAGE4_OFFSET_HIGH_CLAMP
STAGE4_OFFSET_LOW_CLAMP
STAGE5_CONNECTION [6:0]
STAGE5_CONNECTION [12:7]
STAGE5_AFE_OFFSET
STAGE5_SENSITIVITY
STAGE5_OFFSET_LOW
STAGE5_OFFSET_HIGH
STAGE5_OFFSET_HIGH_CLAMP
STAGE5_OFFSET_LOW_CLAMP
STAGE5 CIN [6:0] connection setup (see Table 34)
STAGE5 CIN [12:7] connection setup (see Table 35)
STAGE5 AFE offset control (see Table 36)
STAGE5 sensitivity control (see Table 37)
STAGE5 initial offset low value
STAGE5 initial offset high value
STAGE5 offset high clamp value
STAGE5 offset low clamp value
Rev. 0 | Page 54 of 68
AD7147
Address
0x0B0
0x0B1
0x0B2
0x0B3
0x0B4
0x0B5
0x0B6
0x0B7
0x0B8
0x0B9
0x0BA
0x0BB
0x0BC
0x0BD
0x0BE
0x0BF
0x0C0
0x0C1
0x0C2
0x0C3
0x0C4
0x0C5
0x0C6
0x0C7
0x0C8
0x0C9
0x0CA
0x0CB
0x0CC
0x0CD
0x0CE
0x0CF
0x0D0
0x0D1
0x0D2
0x0D3
0x0D4
0x0D5
0x0D6
0x0D7
0x0D8
0x0D9
0x0DA
0x0DB
0x0DC
0x0DD
0x0DE
0x0DF
Data Bit
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
Default
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Type Name
STAGE6_CONNECTION [6:0]
Description
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
STAGE6 CIN [6:0] connection setup (see Table 34)
STAGE6 CIN [12:7]connection setup (see Table 35)
STAGE6 AFE offset control (see Table 36)
STAGE6 sensitivity control (see Table 37)
STAGE6 initial offset low value
STAGE6 initial offset high value
STAGE6 offset high clamp value
STAGE6 offset low clamp value
STAGE6_CONNECTION [12:7]
STAGE6_AFE_OFFSET
STAGE6_SENSITIVITY
STAGE6_OFFSET_LOW
STAGE6_OFFSET_HIGH
STAGE6_OFFSET_HIGH_CLAMP
STAGE6_OFFSET_LOW_CLAMP
STAGE7_CONNECTION [6:0]
STAGE7_CONNECTION[12:7]
STAGE7_AFE_OFFSET
STAGE7_SENSITIVITY
STAGE7_OFFSET_LOW
STAGE7_OFFSET_HIGH
STAGE7_OFFSET_HIGH_CLAMP
STAGE7_OFFSET_LOW_CLAMP
STAGE8_CONNECTION [6:0]
STAGE8_CONNECTION [12:7]
STAGE8_AFE_OFFSET
STAGE8_SENSITIVITY
STAGE8_OFFSET_LOW
STAGE8_OFFSET_HIGH
STAGE8_OFFSET_HIGH_CLAMP
STAGE8_OFFSET_LOW_CLAMP
STAGE9_CONNECTION [6:0]
STAGE9_CONNECTION [12:7]
STAGE9_AFE_OFFSET
STAGE9_SENSITIVITY
STAGE9_OFFSET_LOW
STAGE9_OFFSET_HIGH
STAGE9_OFFSET_HIGH_CLAMP
STAGE9_OFFSET_LOW_CLAMP
STAGE10_CONNECTION [6:0]
STAGE10_CONNECTION [12:7]
STAGE10_AFE_OFFSET
STAGE7 CIN [6:0] connection setup (see Table 34)
STAGE7 CIN [12:7] connection setup (see Table 35)
STAGE7 AFE offset control (see Table 36)
STAGE7 sensitivity control (see Table 37)
STAGE7 initial offset low value
STAGE7 initial offset high value
STAGE7 offset high clamp value
STAGE7 offset low clamp value
STAGE8 CIN [6:0] connection setup (see Table 34)
STAGE8 CIN [12:7]connection setup (see Table 35)
STAGE8 AFE offset control (see Table 36)
STAGE8 sensitivity control (see Table 37)
STAGE8 initial offset low value
STAGE8 initial offset high value
STAGE8 offset high clamp value
STAGE8 offset low clamp value
STAGE9 CIN [6:0] connection setup (see Table 34)
STAGE9 CIN [12:7]connection setup (see Table 35)
STAGE9 AFE offset control (see Table 36)
STAGE9 sensitivity control (see Table 37)
STAGE9 initial offset low value
STAGE9 initial offset high value
STAGE9 offset high clamp value
STAGE9 offset low clamp value
STAGE10 CIN [6:0] connection setup (see Table 34)
STAGE10 CIN [12:7]connection setup (see Table 35)
STAGE10 AFE offset control (see Table 36)
STAGE10 sensitivity control (see Table 37)
STAGE10 initial offset low value
STAGE10 initial offset high value
STAGE10 offset high clamp value
STAGE10 offset low clamp value
STAGE10_SENSITIVITY
STAGE10_OFFSET_LOW
STAGE10_OFFSET_HIGH
STAGE10_OFFSET_HIGH_CLAMP
STAGE10_OFFSET_LOW_CLAMP
STAGE11_CONNECTION [6:0]
STAGE11_CONNECTION[12:7]
STAGE11_AFE_OFFSET
STAGE11 CIN [6:0] connection setup (see Table 34)
STAGE11 CIN [12:7] connection setup (see Table 35)
STAGE11 AFE offset control (see Table 36)
STAGE11 sensitivity control (see Table 37)
STAGE11 initial offset low value
STAGE11 initial offset high value
STAGE11 offset high clamp value
STAGE11 offset low clamp value
STAGE11_SENSITIVITY
STAGE11_OFFSET_LOW
STAGE11_OFFSET_HIGH
STAGE11_OFFSET_HIGH_CLAMP
STAGE11_OFFSET_LOW_CLAMP
Rev. 0 | Page 55 of 68
AD7147
BANK 3 REGISTERS
All address values are expressed in hexadecimal.
Table 39. STAGE0 Results Registers
Default
Value
Address Data Bit
Type
Name
Description
0x0E0
[15:0]
X
R/W
STAGE0_CONV_DATA
STAGE0 CDC 16-bit conversion data
(copy of CDC_RESULT_S0 register)
STAGE0 fast FIFO WORD0
0x0E1
0x0E2
0x0E3
0x0E4
0x0E5
0x0E6
0x0E7
0x0E8
0x0E9
0x0EA
0x0EB
0x0EC
0x0ED
0x0EE
0x0EF
0x0F0
0x0F1
0x0F2
0x0F3
0x0F4
0x0F5
0x0F6
0x0F7
0x0F8
0x0F9
0x0FA
0x0FB
0x0FC
0x0FD
0x0FE
0x0FF
0x100
0x101
0x102
0x103
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
STAGE0_FF_WORD0
STAGE0_FF_WORD1
STAGE0_FF_WORD2
STAGE0_FF_WORD3
STAGE0_FF_WORD4
STAGE0_FF_WORD5
STAGE0_FF_WORD6
STAGE0_FF_WORD7
STAGE0_SF_WORD0
STAGE0_SF_WORD1
STAGE0_SF_WORD2
STAGE0_SF_WORD3
STAGE0_SF_WORD4
STAGE0_SF_WORD5
STAGE0_SF_WORD6
STAGE0_SF_WORD7
STAGE0_SF_AMBIENT
STAGE0_FF_AVG
STAGE0_PEAK_DETECT_WORD0
STAGE0_PEAK_DETECT_WORD1
STAGE0_MAX_WORD0
STAGE0_MAX_WORD1
STAGE0_MAX_WORD2
STAGE0_MAX_WORD3
STAGE0_MAX_AVG
STAGE0_HIGH_THRESHOLD
STAGE0_MAX_TEMP
STAGE0_MIN_WORD0
STAGE0_MIN_WORD1
STAGE0_MIN_WORD2
STAGE0_MIN_WORD3
STAGE0_MIN_AVG
STAGE0 fast FIFO WORD1
STAGE0 fast FIFO WORD2
STAGE0 fast FIFO WORD3
STAGE0 fast FIFO WORD4
STAGE0 fast FIFO WORD5
STAGE0 fast FIFO WORD6
STAGE0 fast FIFO WORD7
STAGE0 slow FIFO WORD0
STAGE0 slow FIFO WORD1
STAGE0 slow FIFO WORD2
STAGE0 slow FIFO WORD3
STAGE0 slow FIFO WORD4
STAGE0 slow FIFO WORD5
STAGE0 slow FIFO WORD6
STAGE0 slow FIFO WORD7
STAGE0 slow FIFO ambient value
STAGE0 fast FIFO average value
STAGE0 peak FIFO WORD0 value
STAGE0 peak FIFO WORD1 value
STAGE0 maximum value FIFO WORD0
STAGE0 maximum value FIFO WORD1
STAGE0 maximum value FIFO WORD2
STAGE0 maximum value FIFO WORD3
STAGE0 average maximum FIFO value
STAGE0 high threshold value
STAGE0 temporary maximum value
STAGE0 minimum value FIFO WORD0
STAGE0 minimum value FIFO WORD1
STAGE0 minimum value FIFO WORD2
STAGE0 minimum value FIFO WORD3
STAGE0 average minimum FIFO value
STAGE0 low threshold value
STAGE0 temporary minimum value
Set to 0
STAGE0_LOW_THRESHOLD
STAGE0_MIN_TEMP
Unused
Rev. 0 | Page 56 of 68
AD7147
Table 40. STAGE1 Results Registers
Default
Value
Address Data Bit
Type
Name
Description
0x104
[15:0]
X
R/W
STAGE1_CONV_DATA
STAGE1 CDC 16-bit conversion data
(copy of CDC_RESULT_S1 register
0x105
0x106
0x107
0x108
0x109
0x10A
0x10B
0x10C
0x10D
0x10E
0x10F
0x110
0x111
0x112
0x113
0x114
0x115
0x116
0x117
0x118
0x119
0x11A
0x11B
0x11C
0x11D
0x11E
0x11F
0x120
0x121
0x122
0x123
0x124
0x125
0x126
0x127
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
STAGE1_FF_WORD0
STAGE1_FF_WORD1
STAGE1_FF_WORD2
STAGE1_FF_WORD3
STAGE1_FF_WORD4
STAGE1_FF_WORD5
STAGE1_FF_WORD6
STAGE1_FF_WORD7
STAGE1_SF_WORD0
STAGE1_SF_WORD1
STAGE1_SF_WORD2
STAGE1_SF_WORD3
STAGE1_SF_WORD4
STAGE1_SF_WORD5
STAGE1_SF_WORD6
STAGE1_SF_WORD7
STAGE1_SF_AMBIENT
STAGE1_FF_AVG
STAGE1_PEAK_DETECT_WORD0
STAGE1_PEAK_DETECT_WORD1
STAGE1_MAX_WORD0
STAGE1_MAX_WORD1
STAGE1_MAX_WORD2
STAGE1_MAX_WORD3
STAGE1_MAX_AVG
STAGE1_HIGH_THRESHOLD
STAGE1_MAX_TEMP
STAGE1_MIN_WORD0
STAGE1_MIN_WORD1
STAGE1_MIN_WORD2
STAGE1_MIN_WORD3
STAGE1_MIN_AVG
STAGE1 fast FIFO WORD0
STAGE1 fast FIFO WORD1
STAGE1 fast FIFO WORD2
STAGE1 fast FIFO WORD3
STAGE1 fast FIFO WORD4
STAGE1 fast FIFO WORD5
STAGE1 fast FIFO WORD6
STAGE1 fast FIFO WORD7
STAGE1 slow FIFO WORD0
STAGE1 slow FIFO WORD1
STAGE1 slow FIFO WORD2
STAGE1 slow FIFO WORD3
STAGE1 slow FIFO WORD4
STAGE1 slow FIFO WORD5
STAGE1 slow FIFO WORD6
STAGE1 slow FIFO WORD7
STAGE1 slow FIFO ambient value
STAGE1 fast FIFO average value
STAGE1 peak FIFO WORD0 value
STAGE1 peak FIFO WORD1 value
STAGE1 maximum value FIFO WORD0
STAGE1 maximum value FIFO WORD1
STAGE1 maximum value FIFO WORD2
STAGE1 maximum value FIFO WORD3
STAGE1 average maximum FIFO value
STAGE1 high threshold value
STAGE1 temporary maximum value
STAGE1 minimum value FIFO WORD0
STAGE1 minimum value FIFO WORD1
STAGE1 minimum value FIFO WORD2
STAGE1 minimum value FIFO WORD3
STAGE1 average minimum FIFO value
STAGE1 low threshold value
STAGE1 temporary minimum value
Set to 0
STAGE1_LOW_THRESHOLD
STAGE1_MIN_TEMP
Unused
Rev. 0 | Page 57 of 68
AD7147
Table 41. STAGE2 Results Registers
Default
Value
Address Data Bit
Type
Name
Description
0x128
[15:0]
X
R/W
STAGE2_CONV_DATA
STAGE2 CDC 16-bit conversion data
(copy of CDC_RESULT_S2 register)
0x129
0x12A
0x12B
0x12C
0x12D
0x12E
0x12F
0x130
0x131
0x132
0x133
0x134
0x135
0x136
0x137
0x138
0x139
0x13A
0x13B
0x13C
0x13D
0x13E
0x13F
0x140
0x141
0x142
0x143
0x144
0x145
0x146
0x147
0x148
0x149
0x14A
0x14B
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
STAGE2_FF_WORD0
STAGE2_FF_WORD1
STAGE2_FF_WORD2
STAGE2_FF_WORD3
STAGE2_FF_WORD4
STAGE2_FF_WORD5
STAGE2_FF_WORD6
STAGE2_FF_WORD7
STAGE2_SF_WORD0
STAGE2_SF_WORD1
STAGE2_SF_WORD2
STAGE2_SF_WORD3
STAGE2_SF_WORD4
STAGE2_SF_WORD5
STAGE2_SF_WORD6
STAGE2_SF_WORD7
STAGE2_SF_AMBIENT
STAGE2_FF_AVG
STAGE2_PEAK_DETECT_WORD0
STAGE2_PEAK_DETECT_WORD1
STAGE2_MAX_WORD0
STAGE2_MAX_WORD1
STAGE2_MAX_WORD2
STAGE2_MAX_WORD3
STAGE2_MAX_AVG
STAGE2_HIGH_THRESHOLD
STAGE2_MAX_TEMP
STAGE2_MIN_WORD0
STAGE2_MIN_WORD1
STAGE2_MIN_WORD2
STAGE2_MIN_WORD3
STAGE2_MIN_AVG
STAGE2 fast FIFO WORD0
STAGE2 fast FIFO WORD1
STAGE2 fast FIFO WORD2
STAGE2 fast FIFO WORD3
STAGE2 fast FIFO WORD4
STAGE2 fast FIFO WORD5
STAGE2 fast FIFO WORD6
STAGE2 fast FIFO WORD7
STAGE2 slow FIFO WORD0
STAGE2 slow FIFO WORD1
STAGE2 slow FIFO WORD2
STAGE2 slow FIFO WORD3
STAGE2 slow FIFO WORD4
STAGE2 slow FIFO WORD5
STAGE2 slow FIFO WORD6
STAGE2 slow FIFO WORD7
STAGE2 slow FIFO ambient value
STAGE2 fast FIFO average value
STAGE2 peak FIFO WORD0 value
STAGE2 peak FIFO WORD1 value
STAGE2 maximum value FIFO WORD0
STAGE2 maximum value FIFO WORD1
STAGE2 maximum value FIFO WORD2
STAGE2 maximum value FIFO WORD3
STAGE2 average maximum FIFO value
STAGE2 high threshold value
STAGE2 temporary maximum value
STAGE2 minimum value FIFO WORD0
STAGE2 minimum value FIFO WORD1
STAGE2 minimum value FIFO WORD2
STAGE2 minimum value FIFO WORD3
STAGE2 average minimum FIFO value
STAGE2 low threshold value
STAGE2 temporary minimum value
Set to 0
STAGE2_LOW_THRESHOLD
STAGE2_MIN_TEMP
Unused
Rev. 0 | Page 58 of 68
AD7147
Table 42. STAGE3 Results Registers
Default
Value
Address Data Bit
Type
Name
Description
0x14C
[15:0]
X
R/W
STAGE3_CONV_DATA
STAGE3 CDC 16-bit conversion data
(copy of CDC_RESULT_S3 register)
0x14D
0x14E
0x14F
0x150
0x151
0x152
0x153
0x154
0x155
0x156
0x157
0x158
0x159
0x15A
0x15B
0x15C
0x15D
0x15E
0x15F
0x160
0x161
0x162
0x163
0x164
0x165
0x166
0x167
0x168
0x169
0x16A
0x16B
0x16C
0x16D
0x16E
0x16F
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
STAGE3_FF_WORD0
STAGE3_FF_WORD1
STAGE3_FF_WORD2
STAGE3_FF_WORD3
STAGE3_FF_WORD4
STAGE3_FF_WORD5
STAGE3_FF_WORD6
STAGE3_FF_WORD7
STAGE3_SF_WORD0
STAGE3_SF_WORD1
STAGE3_SF_WORD2
STAGE3_SF_WORD3
STAGE3_SF_WORD4
STAGE3_SF_WORD5
STAGE3_SF_WORD6
STAGE3_SF_WORD7
STAGE3_SF_AMBIENT
STAGE3_FF_AVG
STAGE3_PEAK_DETECT_WORD0
STAGE3_PEAK_DETECT_WORD1
STAGE3_MAX_WORD0
STAGE3_MAX_WORD1
STAGE3_MAX_WORD2
STAGE3_MAX_WORD3
STAGE3_MAX_AVG
STAGE3_HIGH_THRESHOLD
STAGE3_MAX_TEMP
STAGE3_MIN_WORD0
STAGE3_MIN_WORD1
STAGE3_MIN_WORD2
STAGE3_MIN_WORD3
STAGE3_MIN_AVG
STAGE3 fast FIFO WORD0
STAGE3 fast FIFO WORD1
STAGE3 fast FIFO WORD2
STAGE3 fast FIFO WORD3
STAGE3 fast FIFO WORD4
STAGE3 fast FIFO WORD5
STAGE3 fast FIFO WORD6
STAGE3 fast FIFO WORD7
STAGE3 slow FIFO WORD0
STAGE3 slow FIFO WORD1
STAGE3 slow FIFO WORD2
STAGE3 slow FIFO WORD3
STAGE3 slow FIFO WORD4
STAGE3 slow FIFO WORD5
STAGE3 slow FIFO WORD6
STAGE3 slow FIFO WORD7
STAGE3 slow FIFO ambient value
STAGE3 fast FIFO average value
STAGE3 peak FIFO WORD0 value
STAGE3 peak FIFO WORD1 value
STAGE3 maximum value FIFO WORD0
STAGE3 maximum value FIFO WORD1
STAGE3 maximum value FIFO WORD2
STAGE3 maximum value FIFO WORD3
STAGE3 average maximum FIFO value
STAGE3 high threshold value
STAGE3 temporary maximum value
STAGE3 minimum value FIFO WORD0
STAGE3 minimum value FIFO WORD1
STAGE3 minimum value FIFO WORD2
STAGE3 minimum value FIFO WORD3
STAGE3 average minimum FIFO value
STAGE3 low threshold value
STAGE3 temporary minimum value
Set to 0
STAGE3_LOW_THRESHOLD
STAGE3_MIN_TEMP
Unused
Rev. 0 | Page 59 of 68
AD7147
Table 43. STAGE4 Results Registers
Default
Value
Address Data Bit
Type
Name
Description
0x170
[15:0]
X
R/W
STAGE4_CONV_DATA
STAGE4 CDC 16-bit conversion data
(copy of CDC_RESULT_S4 register)
0x171
0x172
0x173
0x174
0x175
0x176
0x177
0x178
0x179
0x17A
0x17B
0x17C
0x17D
0x17E
0x17F
0x180
0x181
0x182
0x183
0x184
0x185
0x186
0x187
0x188
0x189
0x18A
0x18B
0x18C
0x18D
0x18E
0x18F
0x190
0x191
0x192
0x193
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
STAGE4_FF_WORD0
STAGE4_FF_WORD1
STAGE4_FF_WORD2
STAGE4_FF_WORD3
STAGE4_FF_WORD4
STAGE4_FF_WORD5
STAGE4_FF_WORD6
STAGE4_FF_WORD7
STAGE4_SF_WORD0
STAGE4_SF_WORD1
STAGE4_SF_WORD2
STAGE4_SF_WORD3
STAGE4_SF_WORD4
STAGE4_SF_WORD5
STAGE4_SF_WORD6
STAGE4_SF_WORD7
STAGE4_SF_AMBIENT
STAGE4_FF_AVG
STAGE4_PEAK_DETECT_WORD0
STAGE4_PEAK_DETECT_WORD1
STAGE4_MAX_WORD0
STAGE4_MAX_WORD1
STAGE4_MAX_WORD2
STAGE4_MAX_WORD3
STAGE4_MAX_AVG
STAGE4_HIGH_THRESHOLD
STAGE4_MAX_TEMP
STAGE4_MIN_WORD0
STAGE4_MIN_WORD1
STAGE4_MIN_WORD2
STAGE4_MIN_WORD3
STAGE4_MIN_AVG
STAGE4 fast FIFO WORD0
STAGE4 fast FIFO WORD1
STAGE4 fast FIFO WORD2
STAGE4 fast FIFO WORD3
STAGE4 fast FIFO WORD4
STAGE4 fast FIFO WORD5
STAGE4 fast FIFO WORD6
STAGE4 fast FIFO WORD7
STAGE4 slow FIFO WORD0
STAGE4 slow FIFO WORD1
STAGE4 slow FIFO WORD2
STAGE4 slow FIFO WORD3
STAGE4 slow FIFO WORD4
STAGE4 slow FIFO WORD5
STAGE4 slow FIFO WORD6
STAGE4 slow FIFO WORD7
STAGE4 slow FIFO ambient value
STAGE4 fast FIFO average value
STAGE4 peak FIFO WORD0 value
STAGE4 peak FIFO WORD1 value
STAGE4 maximum value FIFO WORD0
STAGE4 maximum value FIFO WORD1
STAGE4 maximum value FIFO WORD2
STAGE4 maximum value FIFO WORD3
STAGE4 average maximum FIFO value
STAGE4 high threshold value
STAGE4 temporary maximum value
STAGE4 minimum value FIFO WORD0
STAGE4 minimum value FIFO WORD1
STAGE4 minimum value FIFO WORD2
STAGE4 minimum value FIFO WORD3
STAGE4 average minimum FIFO value
STAGE4 low threshold value
STAGE4 temporary minimum value
Set to 0
STAGE4_LOW_THRESHOLD
STAGE4_MIN_TEMP
Unused
Rev. 0 | Page 60 of 68
AD7147
Table 44. STAGE5 Results Registers
Default
Value
Address Data Bit
Type
Name
Description
0x194
[15:0]
X
R/W
STAGE5_CONV_DATA
STAGE5 CDC 16-bit conversion data
(copy of CDC_RESULT_S5 register)
0x195
0x196
0x197
0x198
0x199
0x19A
0x19B
0x19C
0x19D
0x19E
0x19F
0x1A0
0x1A1
0x1A2
0x1A3
0x1A4
0x1A5
0x1A6
0x1A7
0x1A8
0x1A9
0x1AA
0x1AB
0x1AC
0x1AD
0x1AE
0x1AF
0x1B0
0x1B1
0x1B2
0x1B3
0x1B4
0x1B5
0x1B6
0x1B7
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
STAGE5_FF_WORD0
STAGE5_FF_WORD1
STAGE5_FF_WORD2
STAGE5_FF_WORD3
STAGE5_FF_WORD4
STAGE5_FF_WORD5
STAGE5_FF_WORD6
STAGE5_FF_WORD7
STAGE5_SF_WORD0
STAGE5_SF_WORD1
STAGE5_SF_WORD2
STAGE5_SF_WORD3
STAGE5_SF_WORD4
STAGE5_SF_WORD5
STAGE5_SF_WORD6
STAGE5_SF_WORD7
STAGE5_SF_AMBIENT
STAGE5_FF_AVG
STAGE5_PEAK_DETECT_WORD0
STAGE5_PEAK_DETECT_WORD1
STAGE5_MAX_WORD0
STAGE5_MAX_WORD1
STAGE5_MAX_WORD2
STAGE5_MAX_WORD3
STAGE5_MAX_AVG
STAGE5_HIGH_THRESHOLD
STAGE5_MAX_TEMP
STAGE5_MIN_WORD0
STAGE5_MIN_WORD1
STAGE5_MIN_WORD2
STAGE5_MIN_WORD3
STAGE5_MIN_AVG
STAGE5 fast FIFO WORD0
STAGE5 fast FIFO WORD1
STAGE5 fast FIFO WORD2
STAGE5 fast FIFO WORD3
STAGE5 fast FIFO WORD4
STAGE5 fast FIFO WORD5
STAGE5 fast FIFO WORD6
STAGE5 fast FIFO WORD7
STAGE5 slow FIFO WORD0
STAGE5 slow FIFO WORD1
STAGE5 slow FIFO WORD2
STAGE5 slow FIFO WORD3
STAGE5 slow FIFO WORD4
STAGE5 slow FIFO WORD5
STAGE5 slow FIFO WORD6
STAGE5 slow FIFO WORD7
STAGE5 slow FIFO ambient value
STAGE5 fast FIFO average value
STAGE5 peak FIFO WORD0 value
STAGE5 peak FIFO WORD1 value
STAGE5 maximum value FIFO WORD0
STAGE5 maximum value FIFO WORD1
STAGE5 maximum value FIFO WORD2
STAGE5 maximum value FIFO WORD3
STAGE5 average maximum FIFO value
STAGE5 high threshold value
STAGE5 temporary maximum value
STAGE5 minimum value FIFO WORD0
STAGE5 minimum value FIFO WORD1
STAGE5 minimum value FIFO WORD2
STAGE5 minimum value FIFO WORD3
STAGE5 average minimum FIFO value
STAGE5 low threshold value
STAGE5 temporary minimum value
Set to 0
STAGE5_LOW_THRESHOLD
STAGE5_MIN_TEMP
Unused
Rev. 0 | Page 61 of 68
AD7147
Table 45. STAGE6 Results Registers
Default
Value
Address Data Bit
Type
Name
Description
0x1B8
[15:0]
X
R/W
STAGE6_CONV_DATA
STAGE6 CDC 16-bit conversion data
(copy of CDC_RESULT_S6 register)
0x1B9
0x1BA
0x1BB
0x1BC
0x1BD
0x1BE
0x1BF
0x1C0
0x1C1
0x1C2
0x1C3
0x1C4
0x1C5
0x1C6
0x1C7
0x1C8
0x1C9
0x1CA
0x1CB
0x1CC
0x1CD
0x1CE
0x1CF
0x1D0
0x1D1
0x1D2
0x1D3
0x1D4
0x1D5
0x1D6
0x1D7
0x1D8
0x1D9
0x1DA
0x1DB
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
STAGE6_FF_WORD0
STAGE6_FF_WORD1
STAGE6_FF_WORD2
STAGE6_FF_WORD3
STAGE6_FF_WORD4
STAGE6_FF_WORD5
STAGE6_FF_WORD6
STAGE6_FF_WORD7
STAGE6_SF_WORD0
STAGE6_SF_WORD1
STAGE6_SF_WORD2
STAGE6_SF_WORD3
STAGE6_SF_WORD4
STAGE6_SF_WORD5
STAGE6_SF_WORD6
STAGE6_SF_WORD7
STAGE6_SF_AMBIENT
STAGE6_FF_AVG
STAGE6_PEAK_DETECT_WORD0
STAGE6_PEAK_DETECT_WORD1
STAGE6_MAX_WORD0
STAGE6_MAX_WORD1
STAGE6_MAX_WORD2
STAGE6_MAX_WORD3
STAGE6_MAX_AVG
STAGE6_HIGH_THRESHOLD
STAGE6_MAX_TEMP
STAGE6_MIN_WORD0
STAGE6_MIN_WORD1
STAGE6_MIN_WORD2
STAGE6_MIN_WORD3
STAGE6_MIN_AVG
STAGE6 fast FIFO WORD0
STAGE6 fast FIFO WORD1
STAGE6 fast FIFO WORD2
STAGE6 fast FIFO WORD3
STAGE6 fast FIFO WORD4
STAGE6 fast FIFO WORD5
STAGE6 fast FIFO WORD6
STAGE6 fast FIFO WORD7
STAGE6 slow FIFO WORD0
STAGE6 slow FIFO WORD1
STAGE6 slow FIFO WORD2
STAGE6 slow FIFO WORD3
STAGE6 slow FIFO WORD4
STAGE6 slow FIFO WORD5
STAGE6 slow FIFO WORD6
STAGE6 slow FIFO WORD7
STAGE6 slow FIFO ambient value
STAGE6 fast FIFO average value
STAGE6 peak FIFO WORD0 value
STAGE6 peak FIFO WORD1 value
STAGE6 maximum value FIFO WORD0
STAGE6 maximum value FIFO WORD1
STAGE6 maximum value FIFO WORD2
STAGE6 maximum value FIFO WORD3
STAGE6 average maximum FIFO value
STAGE6 high threshold value
STAGE6 temporary maximum value
STAGE6 minimum value FIFO WORD0
STAGE6 minimum value FIFO WORD1
STAGE6 minimum value FIFO WORD2
STAGE6 minimum value FIFO WORD3
STAGE6 average minimum FIFO value
STAGE6 low threshold value
STAGE6 temporary minimum value
Set to 0
STAGE6_LOW_THRESHOLD
STAGE6_MIN_TEMP
Unused
Rev. 0 | Page 62 of 68
AD7147
Table 46. STAGE7 Results Registers
Default
Value
Address Data Bit
Type
Name
Description
0x1DC
[15:0]
X
R/W
STAGE7_CONV_DATA
STAGE7 CDC 16-bit conversion data
(copy of CDC_RESULT_S7 register)
0x1DD
0x1DE
0x1DF
0x1E0
0x1E1
0x1E2
0x1E3
0x1E4
0x1E5
0x1E6
0x1E7
0x1E8
0x1E9
0x1EA
0x1EB
0x1EC
0x1ED
0x1EE
0x1EF
0x1F0
0x1F1
0x1F2
0x1F3
0x1F4
0x1F5
0x1F6
0x1F7
0x1F8
0x1F9
0x1FA
0x1FB
0x1FC
0x1FD
0x1FE
0x1FF
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
STAGE7_FF_WORD0
STAGE7_FF_WORD1
STAGE7_FF_WORD2
STAGE7_FF_WORD3
STAGE7_FF_WORD4
STAGE7_FF_WORD5
STAGE7_FF_WORD6
STAGE7_FF_WORD7
STAGE7_SF_WORD0
STAGE7_SF_WORD1
STAGE7_SF_WORD2
STAGE7_SF_WORD3
STAGE7_SF_WORD4
STAGE7_SF_WORD5
STAGE7_SF_WORD6
STAGE7_SF_WORD7
STAGE7_SF_AMBIENT
STAGE7_FF_AVG
STAGE7_PEAK_DETECT_WORD0
STAGE7_PEAK_DETECT_WORD1
STAGE7_MAX_WORD0
STAGE7_MAX_WORD1
STAGE7_MAX_WORD2
STAGE7_MAX_WORD3
STAGE7_MAX_AVG
STAGE7_HIGH_THRESHOLD
STAGE7_MAX_TEMP
STAGE7_MIN_WORD0
STAGE7_MIN_WORD1
STAGE7_MIN_WORD2
STAGE7_MIN_WORD3
STAGE7_MIN_AVG
STAGE7 fast FIFO WORD0
STAGE7 fast FIFO WORD1
STAGE7 fast FIFO WORD2
STAGE7 fast FIFO WORD3
STAGE7 fast FIFO WORD4
STAGE7 fast FIFO WORD5
STAGE7 fast FIFO WORD6
STAGE7 fast FIFO WORD7
STAGE7 slow FIFO WORD0
STAGE7 slow FIFO WORD1
STAGE7 slow FIFO WORD2
STAGE7 slow FIFO WORD3
STAGE7 slow FIFO WORD4
STAGE7 slow FIFO WORD5
STAGE7 slow FIFO WORD6
STAGE7 slow FIFO WORD7
STAGE7 slow FIFO ambient value
STAGE7 fast FIFO average value
STAGE7 peak FIFO WORD0 value
STAGE7 peak FIFO WORD1 value
STAGE7 maximum value FIFO WORD0
STAGE7 maximum value FIFO WORD1
STAGE7 maximum value FIFO WORD2
STAGE7 maximum value FIFO WORD3
STAGE7 average maximum FIFO value
STAGE7 high threshold value
STAGE7 temporary maximum value
STAGE7 minimum value FIFO WORD0
STAGE7 minimum value FIFO WORD1
STAGE7 minimum value FIFO WORD2
STAGE7 minimum value FIFO WORD3
STAGE7 average minimum FIFO value
STAGE7 low threshold value
STAGE7 temporary minimum value
Set to 0
STAGE7_LOW_THRESHOLD
STAGE7_MIN_TEMP
Unused
Rev. 0 | Page 63 of 68
AD7147
Table 47. STAGE8 Results Registers
Default
Value
Address Data Bit
Type
Name
Description
0x200
[15:0]
X
R/W
STAGE8_CONV_DATA
STAGE8 CDC 16-bit conversion data
(copy of CDC_RESULT_S8 register)
0x201
0x202
0x203
0x204
0x205
0x206
0x207
0x208
0x209
0x20A
0x20B
0x20C
0x20D
0x20E
0x20F
0x210
0x211
0x212
0x213
0x214
0x215
0x216
0x217
0x218
0x219
0x21A
0x21B
0x21C
0x21D
0x21E
0x21F
0x220
0x221
0x222
0x223
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
STAGE8_FF_WORD0
STAGE8_FF_WORD1
STAGE8_FF_WORD2
STAGE8_FF_WORD3
STAGE8_FF_WORD4
STAGE8_FF_WORD5
STAGE8_FF_WORD6
STAGE8_FF_WORD7
STAGE8_SF_WORD0
STAGE8_SF_WORD1
STAGE8_SF_WORD2
STAGE8_SF_WORD3
STAGE8_SF_WORD4
STAGE8_SF_WORD5
STAGE8_SF_WORD6
STAGE8_SF_WORD7
STAGE8_SF_AMBIENT
STAGE8_FF_AVG
STAGE8_PEAK_DETECT_WORD0
STAGE8_PEAK_DETECT_WORD1
STAGE8_MAX_WORD0
STAGE8_MAX_WORD1
STAGE8_MAX_WORD2
STAGE8_MAX_WORD3
STAGE8_MAX_AVG
STAGE8_HIGH_THRESHOLD
STAGE8_MAX_TEMP
STAGE8_MIN_WORD0
STAGE8_MIN_WORD1
STAGE8_MIN_WORD2
STAGE8_MIN_WORD3
STAGE8_MIN_AVG
STAGE8 fast FIFO WORD0
STAGE8 fast FIFO WORD1
STAGE8 fast FIFO WORD2
STAGE8 fast FIFO WORD3
STAGE8 fast FIFO WORD4
STAGE8 fast FIFO WORD5
STAGE8 fast FIFO WORD6
STAGE8 fast FIFO WORD7
STAGE8 slow FIFO WORD0
STAGE8 slow FIFO WORD1
STAGE8 slow FIFO WORD2
STAGE8 slow FIFO WORD3
STAGE8 slow FIFO WORD4
STAGE8 slow FIFO WORD5
STAGE8 slow FIFO WORD6
STAGE8 slow FIFO WORD7
STAGE8 slow FIFO ambient value
STAGE8 fast FIFO average value
STAGE8 peak FIFO WORD0 value
STAGE8 peak FIFO WORD1 value
STAGE8 maximum value FIFO WORD0
STAGE8 maximum value FIFO WORD1
STAGE8 maximum value FIFO WORD2
STAGE8 maximum value FIFO WORD3
STAGE8 average maximum FIFO value
STAGE8 high threshold value
STAGE8 temporary maximum value
STAGE8 minimum value FIFO WORD0
STAGE8 minimum value FIFO WORD1
STAGE8 minimum value FIFO WORD2
STAGE8 minimum value FIFO WORD3
STAGE8 average minimum FIFO value
STAGE8 low threshold value
STAGE7 temporary minimum value
Set to 0
STAGE8_LOW_THRESHOLD
STAGE8_MIN_TEMP
Unused
Rev. 0 | Page 64 of 68
AD7147
Table 48. STAGE9 Results Registers
Default
Value
Address Data Bit
Type
Name
Description
0x224
[15:0]
X
R/W
STAGE9_CONV_DATA
STAGE9 CDC 16-bit conversion data
(copy of CDC_RESULT_S9 register)
0x225
0x226
0x227
0x228
0x229
0x22A
0x22B
0x22C
0x22D
0x22E
0x22F
0x230
0x231
0x232
0x233
0x234
0x235
0x236
0x237
0x238
0x239
0x23A
0x23B
0x23C
0x23D
0x23E
0x23F
0x240
0x241
0x242
0x243
0x244
0x245
0x246
0x247
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
STAGE9_FF_WORD0
STAGE9_FF_WORD1
STAGE9_FF_WORD2
STAGE9_FF_WORD3
STAGE9_FF_WORD4
STAGE9_FF_WORD5
STAGE9_FF_WORD6
STAGE9_FF_WORD7
STAGE9_SF_WORD0
STAGE9_SF_WORD1
STAGE9_SF_WORD2
STAGE9_SF_WORD3
STAGE9_SF_WORD4
STAGE9_SF_WORD5
STAGE9_SF_WORD6
STAGE9_SF_WORD7
STAGE9_SF_AMBIENT
STAGE9_FF_AVG
STAGE9_PEAK_DETECT_WORD0
STAGE9_PEAK_DETECT_WORD1
STAGE9_MAX_WORD0
STAGE9_MAX_WORD1
STAGE9_MAX_WORD2
STAGE9_MAX_WORD3
STAGE9_MAX_AVG
STAGE9_HIGH_THRESHOLD
STAGE9_MAX_TEMP
STAGE9_MIN_WORD0
STAGE9_MIN_WORD1
STAGE9_MIN_WORD2
STAGE9_MIN_WORD3
STAGE9_MIN_AVG
STAGE9 fast FIFO WORD0
STAGE9 fast FIFO WORD1
STAGE9 fast FIFO WORD2
STAGE9 fast FIFO WORD3
STAGE9 fast FIFO WORD4
STAGE9 fast FIFO WORD5
STAGE9 fast FIFO WORD6
STAGE9 fast FIFO WORD7
STAGE9 slow FIFO WORD0
STAGE9 slow FIFO WORD1
STAGE9 slow FIFO WORD2
STAGE9 slow FIFO WORD3
STAGE9 slow FIFO WORD4
STAGE9 slow FIFO WORD5
STAGE9 slow FIFO WORD6
STAGE9 slow FIFO WORD7
STAGE9 slow FIFO ambient value
STAGE9 fast FIFO average value
STAGE9 peak FIFO WORD0 value
STAGE9 peak FIFO WORD1 value
STAGE9 maximum value FIFO WORD0
STAGE9 maximum value FIFO WORD1
STAGE9 maximum value FIFO WORD2
STAGE9 maximum value FIFO WORD3
STAGE9 average maximum FIFO value
STAGE9 high threshold value
STAGE9 temporary maximum value
STAGE9 minimum value FIFO WORD0
STAGE9 minimum value FIFO WORD1
STAGE9 minimum value FIFO WORD2
STAGE9 minimum value FIFO WORD3
STAGE9 average minimum FIFO value
STAGE9 low threshold value
STAGE9 temporary minimum value
Set to 0
STAGE9_LOW_THRESHOLD
STAGE9_MIN_TEMP
Unused
Rev. 0 | Page 65 of 68
AD7147
Table 49. STAGE10 Results Registers
Default
Value
Address Data Bit
Type
Name
Description
0x248
[15:0]
X
R/W
STAGE10_CONV_DATA
STAGE10 CDC 16-bit conversion data
(copy of CDC_RESULT_S10 register)
0x249
0x24A
0x24B
0x24C
0x24D
0x24E
0x24F
0x250
0x251
0x252
0x253
0x254
0x255
0x256
0x257
0x258
0x259
0x25A
0x25B
0x25C
0x25D
0x25E
0x25F
0x260
0x261
0x262
0x263
0x264
0x265
0x266
0x267
0x268
0x269
0x26A
0x26B
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
STAGE10_FF_WORD0
STAGE10_FF_WORD1
STAGE10_FF_WORD2
STAGE10_FF_WORD3
STAGE10_FF_WORD4
STAGE10_FF_WORD5
STAGE10_FF_WORD6
STAGE10_FF_WORD7
STAGE10_SF_WORD0
STAGE10_SF_WORD1
STAGE10_SF_WORD2
STAGE10_SF_WORD3
STAGE10_SF_WORD4
STAGE10_SF_WORD5
STAGE10_SF_WORD6
STAGE10_SF_WORD7
STAGE10_SF_AMBIENT
STAGE10_FF_AVG
STAGE10_PEAK_DETECT_WORD0
STAGE10_PEAK_DETECT_WORD1
STAGE10_MAX_WORD0
STAGE10_MAX_WORD1
STAGE10_MAX_WORD2
STAGE10_MAX_WORD3
STAGE10_MAX_AVG
STAGE10_HIGH_THRESHOLD
STAGE10_MAX_TEMP
STAGE10_MIN_WORD0
STAGE10_MIN_WORD1
STAGE10_MIN_WORD2
STAGE10_MIN_WORD3
STAGE10_MIN_AVG
STAGE10 fast FIFO WORD0
STAGE10 fast FIFO WORD1
STAGE10 fast FIFO WORD2
STAGE10 fast FIFO WORD3
STAGE10 fast FIFO WORD4
STAGE10 fast FIFO WORD5
STAGE10 fast FIFO WORD6
STAGE10 fast FIFO WORD7
STAGE10 slow FIFO WORD0
STAGE10 slow FIFO WORD1
STAGE10 slow FIFO WORD2
STAGE10 slow FIFO WORD3
STAGE10 slow FIFO WORD4
STAGE10 slow FIFO WORD5
STAGE10 slow FIFO WORD6
STAGE10 slow FIFO WORD7
STAGE10 slow FIFO ambient value
STAGE10 fast FIFO average value
STAGE10 peak FIFO WORD0 value
STAGE10 peak FIFO WORD1 value
STAGE10 maximum value FIFO WORD0
STAGE10 maximum value FIFO WORD1
STAGE10 maximum value FIFO WORD2
STAGE10 maximum value FIFO WORD3
STAGE10 average maximum FIFO value
STAGE10 high threshold value
STAGE10 temporary maximum value
STAGE10 minimum value FIFO WORD0
STAGE10 minimum value FIFO WORD1
STAGE10 minimum value FIFO WORD2
STAGE10 minimum value FIFO WORD3
STAGE10 average minimum FIFO value
STAGE10 low threshold value
STAGE10 temporary minimum value
Set to 0
STAGE10_LOW_THRESHOLD
STAGE10_MIN_TEMP
Unused
Rev. 0 | Page 66 of 68
AD7147
Table 50. STAGE11 Results Registers
Default
Value
Address Data Bit
Type
Name
Description
0x26C
[15:0]
X
R/W
STAGE11_CONV_DATA
STAGE11 CDC 16-bit conversion data
(copy of CDC_RESULT_S11 register)
0x26D
0x26E
0x26F
0x270
0x271
0x272
0x273
0x274
0x275
0x276
0x277
0x278
0x279
0x27A
0x27B
0x27C
0x27D
0x27E
0x27F
0x280
0x281
0x282
0x283
0x284
0x285
0x286
0x287
0x288
0x289
0x28A
0x28B
0x28C
0x28D
0x28E
0x28F
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
STAGE11_FF_WORD0
STAGE11_FF_WORD1
STAGE11_FF_WORD2
STAGE11_FF_WORD3
STAGE11_FF_WORD4
STAGE11_FF_WORD5
STAGE11_FF_WORD6
STAGE11_FF_WORD7
STAGE11_SF_WORD0
STAGE11_SF_WORD1
STAGE11_SF_WORD2
STAGE11_SF_WORD3
STAGE11_SF_WORD4
STAGE11_SF_WORD5
STAGE11_SF_WORD6
STAGE11_SF_WORD7
STAGE11_SF_AMBIENT
STAGE11_FF_AVG
STAGE11_PEAK_DETECT_WORD0
STAGE11_PEAK_DETECT_WORD1
STAGE11_MAX_WORD0
STAGE11_MAX_WORD1
STAGE11_MAX_WORD2
STAGE11_MAX_WORD3
STAGE11_MAX_AVG
STAGE11_HIGH_THRESHOLD
STAGE11_MAX_TEMP
STAGE11_MIN_WORD0
STAGE11_MIN_WORD1
STAGE11_MIN_WORD2
STAGE11_MIN_WORD3
STAGE11_MIN_AVG
STAGE11 fast FIFO WORD0
STAGE11 fast FIFO WORD1
STAGE11 fast FIFO WORD2
STAGE11 fast FIFO WORD3
STAGE11 fast FIFO WORD4
STAGE11 fast FIFO WORD5
STAGE11 fast FIFO WORD6
STAGE11 fast FIFO WORD7
STAGE11 slow FIFO WORD0
STAGE11 slow FIFO WORD1
STAGE11 slow FIFO WORD2
STAGE11 slow FIFO WORD3
STAGE11 slow FIFO WORD4
STAGE11 slow FIFO WORD5
STAGE11 slow FIFO WORD6
STAGE11 slow FIFO WORD7
STAGE11 slow FIFO ambient value
STAGE11 fast FIFO average value
STAGE11 peak FIFO WORD0 value
STAGE11 peak FIFO WORD1 value
STAGE11 maximum value FIFO WORD0
STAGE11 maximum value FIFO WORD1
STAGE11 maximum value FIFO WORD2
STAGE11 maximum value FIFO WORD3
STAGE11 average maximum FIFO value
STAGE11 high threshold value
STAGE11 temporary maximum value
STAGE11 minimum value FIFO WORD0
STAGE11 minimum value FIFO WORD1
STAGE11 minimum value FIFO WORD2
STAGE11 minimum value FIFO WORD3
STAGE11 average minimum FIFO value
STAGE11 low threshold value
STAGE11 temporary minimum value
Set to 0
STAGE11_LOW_THRESHOLD
STAGE11_MIN_TEMP
Unused
Rev. 0 | Page 67 of 68
AD7147
OUTLINE DIMENSIONS
0.60 MAX
4.00
BSC SQ
0.60 MAX
PIN 1
INDICATOR
1
24
19
18
0.50
BSC
PIN 1
INDICATOR
2.65
2.50 SQ
2.35
TOP
VIEW
3.75
BSC SQ
EXPOSED
PA D
(BOTTOMVIEW)
0.50
0.40
0.30
6
13
7
12
0.23 MIN
0.80 MAX
0.65 TYP
2.50 REF
1.00
0.85
0.80
12° MAX
0.05 MAX
0.02 NOM
0.30
0.23
0.18
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-8
Figure 62. 24-Lead Frame Chip Scale Package [LFCSP_VQ]
4 mm × 4 mm Very Thin Quad
(CP-24-3)
Dimensions shown in millimeters
ORDERING GUIDE
Model
Temperature Range
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
Serial Interface Description
SPI Interface
Package Description
24-Lead LFCSP_VQ
24-Lead LFCSP_VQ
24-Lead LFCSP_VQ
24-Lead LFCSP_VQ
Evaluation Board
Package Option
CP-24-3
CP-24-3
CP-24-3
CP-24-3
AD7147ACPZ-REEL1
AD7147ACPZ-500RL71
AD7147ACPZ-1REEL1
AD7147ACPZ-1500RL71
EVAL-AD7147EBZ1
EVAL-AD7147-1EBZ1
SPI Interface
I2C Interface
I2C Interface
SPI Interface
I2C Interface
Evaluation Board
1 Z = RoHS Compliant Part.
©2007 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06663-0-9/07(0)
Rev. 0 | Page 68 of 68
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