EVAL-AD7626EDZ [ADI]
16-Bit, 10 MSPS, PulSAR Differential ADC; 16位， 10 MSPS ， PulSAR系列ADC差分
| 型号： | EVAL-AD7626EDZ |
| 厂家： | 
ADI |
| 描述： | 16-Bit, 10 MSPS, PulSAR Differential ADC |
| 文件： | 总28页 (文件大小：1345K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
16-Bit, 10 MSPS, PulSAR
Differential ADC
AD7626
FEATURES
FUNCTIONAL BLOCK DIAGRAM
REFIN REF VCM
Throughput: 10 MSPS
SNR: 91.5 dB
16-bit no missing codes
INL: 0.45 LSB
1.2V
BAND GAP
VIO
÷2
CLOCK
LOGIC
IN+
IN–
CAP
DAC
CNV+, CNV–
DNL: 0.35 LSB
Power dissipation: 136mW
32-lead LFCSP (5 mm × 5 mm)
SAR architecture
D+, D–
SERIAL
LVDS
SAR
DCO+, DCO–
CLK+, CLK–
AD7626
No latency/no pipeline delay
16-bit resolution with no missing codes
Zero error: 1LSB
Figure 1.
GENERAL DESCRIPTION
Differential input range: 4.096 V
Serial LVDS interface
Self-clocked mode
Echoed-clock mode
LVDS or CMOS option for conversion control (CNV signal)
Reference options
Internal: 4.096 V
External (1.2 V) buffered to 4.096 V
External: 4.096 V
The AD7626 is a 16-bit, 10 MSPS, charge redistribution
successive approximation register (SAR) based architecture
analog-to-digital converter (ADC). SAR architecture allows
unmatched performance both in noise (91.5 dB SNR) and in
linearity ( 0.ꢀ5 ꢁSB INꢁ). The AD7626 contains a high speed,
16-bit sampling ADC, an internal conversion clock, and an
internal buffered reference. On the CNV edge, it samples the
voltage difference between the IN+ and IN− pins. The voltages
on these pins swing in opposite phase between 0 V and REF.
The ꢀ.096 V reference voltage, REF, can be generated internally
or applied externally.
APPLICATIONS
Digital imaging systems
Digital X-ray
Digital MRI
All converted results are available on a single ꢁVDS self-clocked
or echoed-clock serial interface, reducing external hardware
connections.
CCD and IR cameras
High speed data acquisition
High dynamic range telecommunications receivers
Spectrum analysis
The AD7626 is housed in a 32-lead, 5 mm × 5 mm ꢁFCSP with
operation specified from −ꢀ0°C to +85°C.
Test equipment
Table 1. Fast PulSAR® ADC Selection
Input Type
Resolution (Bits)
1 MSPS to <2 MSPS
AD7653
2 MSPS to 3 MSPS
6 MSPS
10 MSPS
Differential (Ground Sense)
16
AD7667
AD7980
AD7983
True Bipolar
Differential (Antiphase)
16
16
AD7671
AD7677
AD7621
AD7622
AD7641
AD7625
AD7626
AD7623
AD7643
Differential (Antiphase)
18
AD7982
AD7984
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2009 Analog Devices, Inc. All rights reserved.
AD7626
TABLE OF CONTENTS
Features .............................................................................................. 1
Theory of Operation ...................................................................... 15
Circuit Information.................................................................... 15
Converter Information .............................................................. 15
Transfer Functions ..................................................................... 16
Analog Inputs ............................................................................. 16
Typical Connection Diagram ................................................... 17
Driving the AD7626................................................................... 18
Voltage Reference Options........................................................ 20
Power Supply............................................................................... 21
Digital Interface.......................................................................... 22
Applications Information.............................................................. 2ꢀ
ꢁayout, Decoupling, and Grounding....................................... 2ꢀ
Outline Dimensions....................................................................... 25
Ordering Guide .......................................................................... 25
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Specifications .................................................................. 5
Timing Diagrams.......................................................................... 6
Absolute Maximum Ratings............................................................ 7
Thermal Resistance ...................................................................... 7
ESD Caution.................................................................................. 7
Pin Configuration and Function Descriptions............................. 8
Typical Performance Characteristics ........................................... 10
Terminology .................................................................................... 1ꢀ
REVISION HISTORY
9/09—Revision 0: Initial Version
Rev. 0 | Page 2 of 28
AD7626
SPECIFICATIONS
VDD1 = 5 V; VDD2 = 2.5 V; VIO = 2.5 V; REF = ꢀ.096 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
RESOLUTION
16
Bits
ANALOG INPUT
Voltage Range
VIN+ − VIN−
−VREF
+VREF
V
Operating Input Voltage
Common-Mode Input Range
CMRR
VIN+, VIN− to AGND
−0.1
VREF/2 − 0.05
VREF + 0.1
VREF/2 + 0.05
V
V
dB
μA
VREF/2
68
168
fIN = 1 MHz
Midscale input
Input Current
THROUGHPUT
Complete Cycle
Throughput Rate
DC ACCURACY
100
10
ns
MSPS
0.1
Integral Linearity Error
No Missing Codes
Differential Linearity Error
Transition Noise
Zero Error, TMIN to TMAX
Zero Error Drift
−1.5
16
−0.5
0.45
+1.5
+0.5
+6
LSB
Bits
LSB
LSB
LSB
ppm/°C
LSB
0.35
0.6
1
0.5
8
−6
Gain Error, TMIN to TMAX
20
Gain Error Drift
Power Supply Sensitivity1
0.7
0.4
0.2
ppm/°C
LSB
LSB
VDD1 = 5 V 5%
VDD2 = 2.5 V 5%
AC ACCURACY
fIN = 20 kHz, −0.5 dBFS
Dynamic Range
Signal-to-Noise Ratio
90.5
90
91.5
91
105
−105.5
91
dB
dB
dB
dB
dB
Spurious-Free Dynamic Range
Total Harmonic Distortion
Signal-to-(Noise + Distortion)
fIN = 100 kHz, −0.5 dBFS
Signal-to-Noise Ratio
Spurious-Free Dynamic Range
Total Harmonic Distortion
Signal-to-(Noise + Distortion)
fIN = 2.4 MHz, −1 dBFS
Signal-to-Noise Ratio
Spurious-Free Dynamic Range
Total Harmonic Distortion
Signal-to-(Noise + Distortion)
fIN = 2.4 MHz, −6 dBFS
Signal-to-Noise Ratio
Spurious-Free Dynamic Range
Total Harmonic Distortion
Signal-to-(Noise + Distortion)
−3 dB Input Bandwidth
Aperture Jitter
89.5
91.3
dB
dB
dB
dB
104.5
−102.5
91
88.5
84
−86
85
dBFS
dB
dB
dB
89
84
−93
88
95
dBFS
dB
dB
dB
MHz
ps rms
0.25
INTERNAL REFERENCE
Output Voltage
Temperature Drift
REFIN @ 25°C
−40°C to +85°C
1.18
1.19
15
1.2
V
ppm/°C
Rev. 0 | Page 3 of 28
AD7626
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
REFERENCE BUFFER
REFIN Input Voltage Range
REF Output Voltage Range
Line Regulation
1.18
4.076
1.2
4.096
5
1.22
4.116
V
V
mV
REF @ 25°C, EN0 = EN1 = 1
VDD1 5%, VDD2 5%
EXTERNAL REFERENCE
Voltage Range
REF
4.096
REF/2
5
V
VCM PIN
VCM Output
VCM Error
Output Impedance
LVDS I/O (ANSI-644)
Data Format
−0.015
+0.015
V
kΩ
Serial LVDS twos complement
Differential Output Voltage, VOD
Common-Mode Output Voltage, VOCM RL = 100 Ω
Differential Input Voltage, VID
Common-Mode Input Voltage, VICM
RL = 100 Ω
245
9802
100
800
290
1130
454
1375
650
mV
mV
mV
mV
1575
POWER SUPPLIES
Specified Performance
VDD1
VDD2
VIO
4.75
2.37
2.37
5
2.5
2.5
5.25
2.63
2.63
V
V
V
Operating Currents
Static—Not Converting
VDD1
VDD2
VIO
3.5
16.7
11.6
4.5
21.2
13.5
mA
mA
mA
With Internal Reference
VDD1
VDD2
10 MSPS throughput
10.4
23.5
15.8
11.2
27.8
17.8
mA
mA
mA
VIO
Echoed-clock mode
10 MSPS throughput
With External Reference
VDD1
VDD2
VIO
Power-Down
VDD1
7.5
23
16.4
8.8
28
18.5
mA
mA
mA
Echoed-clock mode
EN0 = 0, EN1 = 0
0.6
0.8
1
4
10
5
μA
μA
μA
VDD2
VIO
Power Dissipation3
Static—Not Converting
With Internal Reference
With External Reference
Power-Down
Energy per Conversion
TEMPERATURE RANGE
Specified Performance
88
107
170
160
58
mW
mW
mW
μW
10 MSPS throughput
10 MSPS throughput
150
136
8
10 MSPS throughput
TMIN to TMAX
13.6
nJ/sample
−40
+85
°C
1 Using an external reference.
2 The ANSI-644 LVDS specification has a minimum output common mode (VOCM) of 1125 mV.
3 Power dissipation is for the AD7626 device only. In self-clocked interface mode, 0.9 mW is dissipated in the 100 Ω terminator. In echoed-clock interface mode, 1.8 mW
is dissipated in two 100 Ω terminators.
Rev. 0 | Page 4 of 28
AD7626
TIMING SPECIFICATIONS
VDD1 = 5 V; VDD2 = 2.5 V; VIO = 2.37 V to 2.63 V; REF = ꢀ.096 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter
Symbol
tCYC
tCNVH
tMSB
tCLKL
tCLK
fCLK
tDCO
tD
Min
100
10
Typ
Max
Unit
ns
ns
ns
ns
ns
MHz
ns
ns
ns
Time Between Conversions1
10,000
40
100
72
(tCYC − tMSB + tCLKL)/n
300
7
1
7
CNV High Time
CNV to D (MSB) Ready
CNV to Last CLK (LSB) Delay
CLK Period2
3.33
0
4
250
4
0
4
CLK Frequency
CLK to DCO Delay (Echoed-Clock Mode)
DCO to D Delay (Echoed-Clock Mode)
CLK to D Delay
tCLKD
0
1 The maximum time between conversions is 10,000 ns. If CNV is left idle for a time greater than the maximum value of tCYC, the subsequent conversion result is invalid.
2 For the maximum CLK period, the window available to read data is tCYC − tMSB + tCLKL. Divide this time by the number of bits (n) to be read giving the maximum CLK
frequency that can be used for a given conversion CNV frequency. In echoed-clock interface mode, n = 16; in self-clocked interface mode, n = 18.
Rev. 0 | Page 5 of 28
AD7626
TIMING DIAGRAMS
SAMPLE N
SAMPLE N + 1
tCYC
tCNVH
CNV–
CNV+
ACQUISITION
ACQUISITION
ACQUISITION
tCLKL
15
tCLK
15
16
1
2
16
1
2
3
CLK–
CLK+
tDCO
1
15
16
1
2
15
16
2
3
DCO–
DCO+
tMSB
tD
tCLKD
D+
D–
D1
N – 1
D0
N – 1
D15
N
D14
N
D1
N
D0
N
D15
N + 1
D14
D13
0
0
N + 1 N + 1
Figure 2. Echoed-Clock Interface Mode Timing Diagram
SAMPLE N
SAMPLE N + 1
tCYC
tCNVH
CNV–
CNV+
ACQUISITION
tCLK
ACQUISITION
ACQUISITION
tCLKL
1
17
18
1
2
3
4
17
18
2
3
CLK–
CLK+
tMSB
tCLKD
D+
D–
D15
N + 1
D14
N
D1
N
D0
N
D1
N – 1
D0
N – 1
D15
N
0
1
0
0
1
0
Figure 3. Self-Clocked Interface Mode Timing Diagram
Rev. 0 | Page 6 of 28
AD7626
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 4.
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Parameter
Rating
Analog Inputs/Outputs
IN+, IN− to GND1
−0.3 V to REF + 0.3 V or
130 mA
−0.3 V to +6 V
−0.3 V to +6 V
−0.3 V to +2.7 V
Table 5. Thermal Resistance
REF2 to GND
Package Type
θJA
θJC
Unit
32-Lead LFCSP_VQ
40
4
°C/W
VCM, CAP2 to GND
CAP1, REFIN to GND
Supply Voltage
VDD1
VDD2, VIO
Digital Inputs to GND
Digital Outputs to GND
ESD CAUTION
−0.3 V to +6 V
−0.3 V to +3 V
−0.3 V to VIO + 0.3 V
−0.3 V to VIO + 0.3 V
10 mA
Input Current to Any Pin Except
Supplies3
Operating Temperature Range
(Commercial)
−40°C to +85°C
Storage Temperature Range
Junction Temperature
ESD
−65°C to +150°C
150°C
1 kV
1 See the Analog Inputs section.
2 Keep CNV low for any external REF voltage > 4.3 V applied to the REF pin.
3 Transient currents of up to 100 mA do not cause SCR latch-up.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev. 0 | Page 7 of 28
AD7626
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
GND
IN+
IN–
VCM
VDD1
VDD1
VDD1
VDD2
CAP1
REFIN
EN0
EN1
VDD2
CNV–
1
2
3
4
5
6
7
8
24
23
22
21
20
19
PIN 1
INDICATOR
AD7626
TOP VIEW
(Not to Scale)
18 VDD2
17 CLK+
NOTES
1. CONNECT THE EXPOSED PAD TO THE GROUND
PLANE OF THE PCB USING MULTIPLE VIAS.
Figure 4. Pin Configuration
Table 6. Pin Function Descriptions
Pin No.
Mnemonic
Type1
Description
1
2
VDD1
VDD2
P
P
Analog 5 V Supply. Decouple the 5 V supply with a 100 nF capacitor.
Analog 2.5 V Supply. Decouple this pin with a 100 nF capacitor. The 2.5 V supply source should
supply this pin first, then be traced to the other VDD2 pins (Pin 7 and Pin 18).
3
4
CAP1
REFIN
AO
AI/O
Connect this pin to a 10 nF capacitor.
Prebuffer Reference Voltage. When using the internal reference, this pin outputs the band gap voltage
and is nominally at 1.2 V. It can be overdriven with an external reference voltage such as the ADR280.
In either internal or external reference mode, a 10 ꢀF capacitor is required. If using an external 4.096 V
reference (connected to REF), this pin is a no connect and does not require any capacitor.
5, 6
EN0, EN1
DI
Enable. The logic levels of these pins set the operation of the device as follows:
EN1 = 0, EN0 = 0: power-down mode.
EN1 = 0, EN0 = 1: external 1.2 V reference applied to the REFIN pin is required.
EN1 = 1, EN0 = 0: external 4.096 V reference applied to the REF pin required.
EN1 = 1, EN0 = 1: internal reference and internal reference buffer in use.
7
VDD2
P
Digital 2.5 V Supply. Decouple this pin with a 100 nF capacitor.
8, 9
CNV−, CNV+
DI
Convert Input. These pins act as the conversion control pin. On the rising edge of these pins, the
analog inputs are sampled and a conversion cycle is initiated. CNV+ works as a CMOS input when
CNV− is grounded; otherwise, CNV+ and CNV− are differential LVDS inputs.
10, 11
12
13
D−, D+
VIO
GND
DO
P
P
LVDS Data Outputs. The conversion data is output serially on these pins.
Input/Output Interface Supply. Use a 2.5 V supply and decouple this pin with a 100 nF capacitor.
Ground. Return path for the 100 nF capacitor connected to Pin 12.
14, 15
DCO−, DCO+ DO
LVDS Buffered Clock Outputs. When DCO+ is grounded, the self-clocked interface mode is selected.
In this mode, the 16-bit results on D are preceded by an initial 0 (which is output at the end of the
previous conversion), followed by a 2-bit header (10) to allow synchronization of the data by the
digital host with extra logic. The 1 in this header provides the reference to acquire the subsequent
conversion result correctly. When DCO+ is not grounded, the echoed-clock interface mode is
selected. In this mode, DCO is a copy of CLK . The data bits are output on the falling edge of DCO+
and can be captured in the digital host on the next rising edge of DCO+.
16, 17
18
CLK−, CLK+
VDD2
DI
P
LVDS Clock Inputs. This clock shifts out the conversion results on the falling edge of CLK+.
Analog 2.5 V Supply. Decouple this pin with a 100 nF capacitor.
19, 20
VDD1
P
Analog 5 V Supply. Isolate these pins from Pin 1 with a ferrite bead and decouple them with a 100 nF
capacitor.
21
VCM
AO
Common-Mode Output. When using any reference scheme, this pin produces one-half the voltage
present on the REF pin, which can be useful for driving the common mode of the input amplifiers.
22
23
IN−
IN+
AI
AI
Differential Negative Analog Input. Referenced to and must be driven 180° out of phase with IN+.
Differential Positive Analog Input. Referenced to and must be driven 180° out of phase with IN−.
Rev. 0 | Page 8 of 28
AD7626
Pin No.
Mnemonic
Type1
P
Description
24
GND
Ground.
25, 26, 28 CAP2
AO
Connect all three CAP2 pins together and decouple them with the shortest trace possible to a single
10 ꢀF, low ESR, low ESL capacitor. The other side of the capacitor must be placed close to Pin 27 (GND).
27
GND
P
Ground. Return path for the 10 ꢀF capacitor connected to Pin 25, Pin 26, and Pin 28.
29, 30, 32 REF
AI/O
Buffered Reference Voltage. When using the internal reference or the 1.2 V external reference (REFIN
input), the 4.096 V system reference is produced at this pin. When using an external reference, such
as the ADR434 or the ADR444, the internal reference buffer must be disabled. In either case, connect
all three REF pins together and decouple them with the shortest trace possible to a single 10 ꢀF, low
ESR, low ESL capacitor. The other side of the capacitor must be placed close to Pin 31 (GND).
31
EP
GND
Exposed pad
P
Ground. Return path for the 10 ꢀF capacitor connected to Pin 29, Pin 30, and Pin 32.
The exposed pad is located on the underside of the package. Connect the exposed pad to the
ground plane of the PCB using multiple vias. See the Exposed Paddle section for more information.
1 AI = analog input; AI/O = bidirectional analog; AO = analog output; DI = digital input; DO = digital output; P = power.
Rev. 0 | Page 9 of 28
AD7626
TYPICAL PERFORMANCE CHARACTERISTICS
VDD1 = 5 V; VDD2 = 2.5 V; VIO = 2.5 V; REF = ꢀ.096 V; all plots at 10 MSPS unless otherwise noted. FFT plots for 2 MHz, 3 MHz, and
5 MHz input tones use band pass filter ( ꢀ00 kHz pass bandwidth around fundamental frequency).
0
0
INPUT FREQUENCY = 10.37kHz
SNR = 91.85dB
INPUT FREQUENCY = 100kHz
SNR = 91.323dB
–20
–20
SINAD = 91.8dB
SINAD = 91.047dB
THD = –112.1dB
SFDR = 112.85dB
32k SAMPLES
THD = –102.543dB
SFDR = 104.529dB
–40
–40
–60
–60
–80
–80
–100
–120
–140
–160
–180
–100
–120
–140
–160
–180
0
10
30
50
70
90
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
FREQUENCY (kHz)
FREQUENCY (MHz)
Figure 5. 10 kHz, −0.5 dB Input Tone, Zoomed View
Figure 8.100 kHz, −0.5 dB Input Tone FFT, Full Frequency View
0
–20
0
INPUT FREQUENCY = 2.0026MHz
–0.5dB INPUT AMPLITUDE
SNR = 87.4dBFS
INPUT FREQUENCY = 2.0026MHz
–6dB INPUT AMPLITUDE
SNR = 87.6dBFS
SINAD = 87.6dBFS
THD = –101.6dB
SFDR = 101.9dB
64k SAMPLES
–20
–40
SINAD = 84.8dBFS
THD = –87.9dB
SFDR = 88.1dB
64k SAMPLES
–40
–60
–60
THIRD
HARMONIC
–80
–80
FIFTH
HARMONIC
SECOND
HARMONIC
FIFTH
HARMONIC
THIRD
HARMONIC
SECOND
–100
–120
–140
–160
–180
–100
–120
–140
–160
–180
HARMONIC
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 6. FFT, 2 MHz, −0.5 dB Input Tone, Wide View
Figure 9. FFT, 2 MHz, −6 dB Input Tone, Wide View
0
–20
0
–20
INPUT FREQUENCY = 3.00125MHz
–6dB INPUT AMPLITUDE
SNR = 88.48dBFS
INPUT FREQUENCY = 3.00125MHz
–0.5dB INPUT AMPLITUDE
SNR = 87.1dBFS
SINAD = 88.3dBFS
THD = –97.2dB
SINAD = 81.2dBFS
THD = –82.0dB
SFDR = 98.3dB
64k SAMPLES
SFDR = 82.1dB
64k SAMPLES
–40
–40
–60
–60
THIRD
HARMONIC
FIFTH
HARMONIC
–80
–80
SECOND
HARMONIC
THIRD
HARMONIC
SECOND
HARMONIC
FIFTH
FOURTH
HARMONIC
–100
–120
–140
–160
–180
–100
–120
–140
–160
–180
HARMONIC
FOURTH
HARMONIC
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 7. FFT, 3 MHz, −0.5 dB Input Tone, Wide View
Figure 10. FFT, 3 MHz, −6 dB Input Tone, Wide View
Rev. 0 | Page 10 of 28
AD7626
0
–20
0
–20
INPUT FREQUENCY = 5.00656128MHz
–0.5dB INPUT AMPLITUDE
SNR = 86.7dBFS
INPUT FREQUENCY = 5.00656128MHz
–0.5dB INPUT AMPLITUDE
SNR = 86.7dBFS
SINAD = 83.2dBFS
SINAD = 83.2dBFS
FUNDAMENTAL
THD = –85.3dB
THD = –85.3dB
SFDR = 86.1dB
SFDR = 86.1dB
–40
–40
64k SAMPLES
64k SAMPLES
–60
–60
THIRD
HARMONIC
THIRD
HARMONIC
–80
–80
FIFTH
HARMONIC
FIFTH
HARMONIC
SECOND
HARMONIC
–100
–120
–140
–160
–180
–100
–120
–140
–160
–180
FOURTH
HARMONIC
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
4.50 4.55 4.60 4.65 4.70 4.75 4.80 4.85 4.90 4.95 5.00
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 11. FFT, 5 MHz, −0.5 dB Input Tone, Wide View
Figure 14. FFT, 5 MHz, −0.5 dB Input Tone Zoomed View
0
–20
0
INPUT FREQUENCY = 5.00656128MHz
–6dB INPUT AMPLITUDE
SNR = 88.4dBFS
INPUT FREQUENCY = 5.00656128MHz
–6dB INPUT AMPLITUDE
SNR = 88.4dBFS
SINAD = 88.0dBFS
THD = –92.4dB
SFDR = 92.8dB
64k SAMPLES
–20
SINAD = 88.0dBFS
FUNDAMENTAL
FUNDAMENTAL
THD = –92.4dB
SFDR = 92.8dB
64k SAMPLES
–40
–40
–60
–60
THIRD
HARMONIC
THIRD
–80
–80
HARMONIC
SECOND
HARMONIC
FIFTH HARMONIC
–100
–120
–140
–160
–180
–100
–120
–140
–160
–180
FIFTH
FOURTH
HARMONIC
HARMONIC
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
4.50 4.55 4.60 4.65 4.70 4.75 4.80 4.85 4.90 4.95 5.00
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 12. FFT, 5 MHz, −6 dB Input Tone, Wide View
Figure 15. FFT, 5 MHz, −0.5 dB Input Tone Zoomed View
–75
–80
94
92
90
88
86
84
82
80
–50
–60
9.7MHz
–85
5MHz
–70
–90
SNR
–95
–80
–90
1MHz
–100
–105
–110
–115
–100
3MHz
THD
2MHz
–15
–110
10M
–18
–12
–9
–6
–3
0
10k
100k
1M
INPUT AMPLITUDE (dBFS)
INPUT FREQUENCY (Hz)
Figure 13. THD vs. Input Amplitudes at Input Frequency Tones of
10 kHz to 9.7 MHz
Figure 16. THD and SNR vs. Input Frequency (−0.5 dB Input Tone)
Rev. 0 | Page 11 of 28
AD7626
92.0
91.8
91.6
91.4
91.2
91.0
90.8
90.6
90.4
90.2
92.0
91.8
91.6
91.4
91.2
91.0
90.8
90.6
90.4
90.2
90.0
EXTERNAL REFERENCE
EXTERNAL REFERENCE
INTERNAL REFERENCE
INTERNAL REFERENCE
90.0
–40
–20
0
20
40
60
80
–40
–20
0
20
40
60
80
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 17. SNR vs. Temperature (−0.5 dB, 20 kHz Input Tone)
Figure 20. SINAD vs. Temperature (−0.5 dB, 20 kHz Input Tone)
0.35
7
6
0.30
0.25
0.20
0.15
0.10
0.05
0
5
4
GAIN ERROR
+INPUT CURRENT
3
2
–INPUT CURRENT
1
0
ZERO ERROR
–20
–0.05
–0.10
–1
–40
–6
–4
–2
0
2
4
6
0
20
40
60
80
INPUT COMMON-MODE VOLTAGE (V)
TEMPERATURE (°C)
Figure 18. Input Current (IN+, IN−) vs. Differential Input Voltage (10 MSPS)
Figure 21. Zero Error and Gain Error vs. Temperature
–103.0
–103.5
250,000
200,000
150,000
100,000
50,000
0
262,144 SAMPLES
STD DEVIATION = 0.4829
201,320
–104.0
–104.5
–105.0
–105.5
–106.0
–106.5
–107.0
EXTERNAL REFERENCE
INTERNAL REFERENCE
30,651
FEC9
30,073
FECB
54
46
0
0
–40
–20
0
20
40
60
80
FEC7
FEC8
FECA
FECC
FECD
TEMPERATURE (°C)
CODE (HEX)
Figure 19. THD vs. Temperature (−0.5 dB, 20 kHz Input Tone)
Figure 22. Histogram of 262,144 Conversions of a DC Input
at the Code Center (Internal Reference)
Rev. 0 | Page 12 of 28
AD7626
250,000
200,000
150,000
100,000
50,000
0
0.30
0.25
0.20
0.15
0.10
0.05
0
262,144 SAMPLES
STD DEVIATION = 0.4814
201,614
–0.05
–0.10
–0.15
–0.20
–0.25
–0.30
30,250
30,206
FECA
41
33
0
0
FEC8
FEC9
FECB
FECC
FECD
FECE
0
16,384
32,768
CODE
49,152
65,536
CODE (HEX)
Figure 23. Histogram of 262,144 Conversions of a DC Input
at the Code Center (External Reference)
Figure 25. Differential Nonlinearity vs. Code (25ºC)
140,000
0.8
0.6
129,601
262,144 SAMPLES
STD DEVIATION = 0.5329
+85°C
128,084
+25°C
–40°C
120,000
100,000
80,000
60,000
40,000
20,000
0
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
2329
0
2130
0
FEC6
FEC7
FEC8
FEC9
FECA
FECB
0
16,384
32,768
CODE
49,152
65,536
CODE (HEX)
Figure 24. Histogram of 262,144 Conversions of a DC Input
at the Code Transition
Figure 26. Integral Nonlinearity vs. Code vs. Temperature
Rev. 0 | Page 13 of 28
AD7626
TERMINOLOGY
Power Supply Rejection Ratio (PSRR)
Common-Mode Rejection Ratio (CMRR)
Variations in power supply affect the full-scale transition but not
the linearity of the converter. PSRR is the maximum change in
the full-scale transition point due to a change in power supply
voltage from the nominal value.
CMRR is defined as the ratio of the power in the ADC output
at full-scale frequency, f, to the power of a 100 mV p-p sine
wave applied to the common-mode voltage of VIN+ and VIN−
at frequency, fS.
Reference Voltage Temperature Coefficient
CMRR (dB) = 10 log(Pf/PfS)
The reference voltage temperature coefficient is derived from the
typical shift of output voltage at 25°C on a sample of parts at the
maximum and minimum reference output voltage (VREF) meas-
ured at TMIN, T(25°C), and TMAX. It is expressed in ppm/°C as
where:
Pf is the power at frequency, f, in the ADC output.
PfS is the power at frequency, fS, in the ADC output.
Differential Nonlinearity (DNL) Error
V
REF (Max)–VREF (Min)
TCVREF (ppm/°C) =
×106
In an ideal ADC, code transitions are 1 ꢁSB apart. Differential
nonlinearity is the maximum deviation from this ideal value. It
is often specified in terms of resolution for which no missing
codes are guaranteed.
VREF (25°C) × (TMAX –TMIN
)
where:
V
V
V
T
T
REF (Max) = maximum VREF at TMIN, T(25°C), or TMAX.
REF (Min) = minimum VREF at TMIN, T(25°C), or TMAX
REF (25°C) = VREF at 25°C.
.
Integral Nonlinearity (INL) Error
ꢁinearity error refers to the deviation of each individual code
from a line drawn from negative full scale through positive full
scale. The point used as negative full scale occurs ½ ꢁSB before
the first code transition. Positive full scale is defined as a level
1½ ꢁSB beyond the last code transition. The deviation is meas-
ured from the middle of each code to the true straight line.
MAX = +85°C.
MIN = −ꢀ0°C.
Signal-to-Noise Ratio (SNR)
SNR is the ratio of the rms value of the actual input signal to
the rms sum of all other spectral components below the Nyquist
frequency, excluding harmonics and dc. The value for SNR is
expressed in decibels.
Dynamic Range
Dynamic range is the ratio of the rms value of the full scale to
the rms noise measured for an input typically at −60 dB. The
value for dynamic range is expressed in decibels.
Signal-to-(Noise + Distortion) Ratio (SINAD)
SINAD is the ratio of the rms value of the actual input signal to
the rms sum of all other spectral components below the Nyquist
frequency, including harmonics but excluding dc. The value for
SINAD is expressed in decibels.
Effective Number of Bits (ENOB)
ENOB is a measurement of the resolution with a sine wave
input. It is related to SINAD and is expressed in bits by
Spurious-Free Dynamic Range (SFDR)
SFDR is the difference, in decibels, between the rms amplitude
of the input signal and the peak spurious signal (including
harmonics).
ENOB = [(SINADdB − 1.76)/6.02]
Gain Error
The first transition (from 100 … 000 to 100 …001) should occur
at a level ½ ꢁSB above nominal negative full scale (−ꢀ.0959375 V
for the ꢀ.096 V range). The last transition (from 011 … 110 to
011 … 111) should occur for an analog voltage 1½ ꢁSB below
the nominal full scale (+ꢀ.0959375 V for the ꢀ.096 V range).
The gain error is the deviation of the difference between the
actual level of the last transition and the actual level of the first
transition from the difference between the ideal levels.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of the first five harmonic
components to the rms value of a full-scale input signal and
is expressed in decibels.
Zero Error
Zero error is the difference between the ideal midscale input
voltage (0 V) and the actual voltage producing the midscale
output code.
Gain Error Drift
The ratio of the gain error change due to a temperature change
of 1°C and the full-scale range (2N). It is expressed in parts per
million.
Zero Error Drift
The ratio of the zero error change due to a temperature change
of 1°C and the full scale code range (2N). It is expressed in parts
per million.
Least Significant Bit (LSB)
The least significant bit, or ꢁSB, is the smallest increment that
can be represented by a converter. For a fully differential input
ADC with N bits of resolution, the ꢁSB expressed in volts is
VINp-p
LSB (V) =
2N
Rev. 0 | Page 14 of 28
AD7626
THEORY OF OPERATION
IN+
GND
LSB
SWITCHES
CONTROL
SW+
MSB
32,768C 16,384C
4C
4C
2C
2C
C
C
C
C
REF
(4.096V)
CLK+, CLK–
DCO+, DCO–
D+, D–
DATA TRANSFER
CONTROL
LOGIC
COMP
GND
OUTPUT CODE
32,768C 16,384C
MSB
SW–
LSB
CNV+, CNV–
LVDS INTERFACE
GND
CONVERSION
CONTROL
IN–
Figure 27. ADC Simplified Schematic
CIRCUIT INFORMATION
When the conversion phase begins, SW+ and SW− are opened
first. The two capacitor arrays are then disconnected from the
inputs and connected to the GND input. Therefore, the differential
voltage between the inputs (IN+ and IN−) captured at the end
of the acquisition phase is applied to the comparator inputs,
causing the comparator to become unbalanced. By switching
each element of the capacitor array between GND and ꢀ.096 V
(the reference voltage), the comparator input varies by binary
weighted voltage steps (VREF/2, VREF/ꢀ … VREF/65,536). The
control logic toggles these switches, MSB first, to bring the
comparator back into a balanced condition. At the completion
of this process, the control logic generates the ADC output code.
The AD7626 is a 10 MSPS, high precision, power effi-
cient, 16-bit ADC that uses SAR-based architecture to
provide a performance of 91.5 dB SNR, 0.ꢀ5 ꢁSB INꢁ,
and 0.35 ꢁSB DNꢁ.
The AD7626 is capable of converting 10,000,000 samples per
second (10 MSPS). The device typically consumes 136 mW of
power. The AD7626 offers the added functionality of a high
performance on-chip reference and on-chip reference buffer.
The AD7626 is specified for use with 5 V and 2.5 V supplies
(VDD1, VDD2). The interface from the digital host to the
AD7626 uses 2.5 V logic only. The AD7626 uses an ꢁVDS
interface to transfer data conversions. The CNV+ and CNV−
inputs to the part activate the conversion of the analog input.
The CNV+ and CNV− pins can be applied using a CMOS or
ꢁVDS source.
The AD7626 digital interface uses low voltage differential
signaling (ꢁVDS) to enable high data transfer rates.
The AD7626 conversion result is available for reading after
tMSB (time from the conversion start until MSB is available) has
elapsed. The user must apply a burst ꢁVDS CꢁK signal to the
AD7626 to transfer data to the digital host.
The AD7626 is housed in a space-saving, 32-lead, 5 mm ×
5 mm ꢁFCSP.
CONVERTER INFORMATION
The CꢁK signal outputs the ADC conversion result onto the
data output D . The bursting of the CꢁK signal is illustrated
in Figure ꢀ1 and Figure ꢀ2 and is characterized as follows:
The AD7626 is a 10 MSPS ADC that uses SAR-based archi-
tecture to incorporate a charge redistribution DAC. Figure 27
shows a simplified schematic of the ADC. The capacitive DAC
consists of two identical arrays of 16 binary weighted capacitors
that are connected to the two comparator inputs.
•
The differential voltage on CꢁK should be held steady
state in the time between tCꢁKꢁ and tMSB
.
•
The AD7626 has two data read modes. For more
information about the echoed-clock and self-clocked
interface modes, see the Digital Interface section.
During the acquisition phase, the terminals of the array tied
to the input of the comparator are connected to GND via SW+
and SW−. All independent switches are connected to the analog
inputs. In this way, the capacitor arrays are used as sampling
capacitors and acquire the analog signal on the IN+ and IN−
inputs. A conversion phase is initiated when the acquisition
phase is complete and the CNV input goes high. Note that the
AD7626 can receive a CMOS or ꢁVDS format CNV signal.
Rev. 0 | Page 15 of 28
AD7626
TRANSFER FUNCTIONS
ANALOG INPUTS
The AD7626 uses a ꢀ.096 V reference. The AD7626 converts
the differential voltage of the antiphase analog inputs (IN+
and IN−) into a digital output. The analog inputs, IN+ and IN−,
require a 2.0ꢀ8 V common-mode voltage (REF/2).
The analog inputs, IN+ and IN−, applied to the AD7626 must be
180° out of phase with each other. Figure 29 shows an equivalent
circuit of the input structure of the AD7626.
The two diodes provide ESD protection for the analog inputs,
IN+ and IN−. Care must be taken to ensure that the analog input
signal does not exceed the reference voltage by more than 0.3 V.
If the analog input signal exceeds this level, the diodes become
forward-biased and start conducting current. These diodes can
handle a forward-biased current of 130 mA maximum. However,
if the supplies of the input buffer (for example, the supplies of
the ADAꢀ899-1 in Figure 33) are different from those of the
reference, the analog input signal may eventually exceed the
supply rails by more than 0.3 V. In such a case (for example, an
input buffer with a short circuit), the current limitation can be
used to protect the part.
The 16-bit conversion result is in MSB first, twos complement
format.
The ideal transfer functions for the AD7626 are shown
in Figure 28 and Table 7.
011 ... 111
011 ... 110
011 ... 101
CNV
VDD1
25pF
67Ω
IN+
OR IN–
100 ... 010
100 ... 001
100 ... 000
–FSR
–FSR + 1LSB
+FSR – 1LSB
+FSR – 1.5LSB
–FSR + 0.5LSB
Figure 29. Equivalent Analog Input Circuit
ANALOG INPUT
The analog input structure allows the sampling of the true
differential signal between IN+ and IN−. By using these differ-
ential inputs, signals common to both inputs are rejected. The
AD7626 shows some degradation in THD with higher analog
input frequencies.
Figure 28. ADC Ideal Transfer Functions (FSR = Full-Scale Range)
Table 7. Output Codes and Ideal Input Voltages
Analog Input
(IN+ − IN−)
Digital Output Code
Description
REF = 4.096 V
Twos Complement (Hex)
75
FSR − 1 LSB
+4.095875V
0x7FFF
0x0001
0x0000
0xFFFF
0x8001
0x8000
Midscale + 1 LSB +125 ꢀV
Midscale 0 V
Midscale − 1 LSB −125 ꢀV
−FSR + 1 LSB
−FSR
70
65
60
55
50
45
−4.095875 V
− 4.096 V
1
10
100
1k
10k
100k
1M
10M
INPUT COMMON-MODE FREQUENCY (Hz)
Figure 30. Analog Input CMRR vs. Frequency
Rev. 0 | Page 16 of 28
AD7626
TYPICAL CONNECTION DIAGRAM
8
V+
ADR434
ADR444
CAPACITOR ON OUTPUT
FOR STABILITY
C
10µF
REF
1, 2
1
10µF
VDD1
(5V)
100nF
VDD2
(2.5V)
32
31
30
29
28
27
26
25
100nF
24
GND
1
2
VDD1
VDD2
CAP1
REFIN
EN0
10nF
23
22
IN+
IN–
IN+
IN–
8
ADR280
PADDLE
SEE THE DRIVING
THE AD7625 SECTION
7
3
4
10µF
VCM
21
20
VCM
VIO
AD7626
3
10kΩ
10kΩ
5
6
VDD1
(5V)
CONTROL FOR
ENABLE
VDD1
FERRITE
BEAD
PINS
100nF
6
EN1
19
18
VDD1
VDD2
VDD2
(2.5V)
7
VDD2
VDD2
(2.5V)
100nF
100nF
4
CONVERSION
CONTROL
CMOS (CNV+ ONLY)
OR
8
9
10
11
12
13
14
15
16
100Ω
17
LVDS CNV+ AND CNV–
USING 100Ω
5
TERMINATION RESISTOR
100Ω
VIO
(2.5V)
100Ω
100Ω
DIGITAL INTERFACE SIGNALS
DIGITAL HOST
LVDS TRANSMIT AND RECEIVE
1
2
3
SEE THE LAYOUT, DECOUPLING, AND GROUNDING SECTION.
IS USUALLY A 10µF CERAMIC CAPACITOR WITH LOW ESR AND ESL.
USE PULL-UP OR PULL-DOWN RESISTORS TO CONTROL EN0 AND EN1 DURING POWER-UP. EN0 AND EN1 INPUTS CAN BE
FIXED IN HARDWARE OR CONTROLLED USING A DIGITAL HOST (EN0 = 0 AND EN1 = 0 PUTS THE ADC IN POWER-DOWN).
OPTION TO USE A CMOS (CNV+) OR LVDS (CNV±) INPUT TO CONTROL CONVERSIONS.
TO ENABLE SELF-CLOCKED MODE, TIE DCO+ TO GND.
CONNECT PIN 19 AND PIN 20 TO VDD1 SUPPLY; ISOLATE THE TRACE TO PIN 19 AND PIN 20 FROM THE TRACE TO PIN 1 USING A
FERRITE BEAD SIMILAR TO WURTH 74279266.
C
REF
4
5
6
7
8
SEE THE DRIVING THE AD7626 SECTION FOR DETAILS ON AMPLIFIER CONFIGURATIONS.
SEE THE VOLTAGE REFERENCE OPTIONS SECTION FOR DETAILS.
Figure 31. Typical Application Diagram
Rev. 0 | Page 17 of 28
AD7626
DRIVING THE AD7626
Differential Analog Input Source
ADA4899-1
U1
ANALOG INPUT
(UNIPOLAR 0V TO 4.096V)
Figure 33 shows an ADAꢀ899-1 driving each differential input
to the AD7626.
590Ω
590Ω
20Ω
Single-Ended-to-Differential Driver
56pF
For applications using unipolar analog signals, a single-
ended-to-differential driver (as shown in Figure 32) allows
for a differential input into the part. This configuration, when
provided with an input signal of 0 V to ꢀ.096 V, produces a
differential ꢀ.096 V with midscale at 2.0ꢀ8 V. The one-pole
filter using R = 20 Ω and C = 56 pF provides a corner frequency
of 1ꢀ0 MHz. The VCM output of the AD7626 can be buffered
and then used to provide the required 2.0ꢀ8 V common-mode
voltage.
IN+
AD7626
IN–
VCM
20Ω
ADA4899-1
U2
56pF
100nF
100nF
V+
V–
50Ω
Single-Ended or Fully Differential High Frequency Driver
In applications that require higher input frequency tones, the
ADAꢀ932-1 can be used to drive the inputs to the AD7626. The
ADAꢀ932-1 is a differential driver, which also allows the user
the option of single-ended-to-differential conversion.
AD8031, AD8032
Figure 32. Single-Ended-to-Differential Driver Circuit Using ADA4899-1
Figure 3ꢀ shows the typical circuit for a 50 ꢂ source impedance
(ac-coupled in this example). The input to the ADAꢀ932-1 is
configured to be balanced to the source impedance (in this case
50 ꢂ). Further information on balancing the input impedance
to the source impedance can be found on the ADAꢀ932-1
datasheet. The circuit shown in Figure 3ꢀ operates with an
overall gain of ~0.5 when the termination input termination
is taken into account.
Alternatively, the ADAꢀ932-1 can be used with a fully diffe-
rential source—it acts as an inverting differential driver.
1
1
REF
REF
C
10µF
C
10µF
REF
REF
2
2
+V
S
20Ω
0V TO V
REF
REFIN
REF
56pF
IN+
IN–
–V
ADA4899-1
S
AD7626
+V
S
VCM
2.048V
20Ω
GND
V
TO 0V
REF
56pF
–V
S
ADA4899-1
VCM
+V
–V
S
BUFFERED VCM PIN OUTPUT
GIVES THE REQUIRED 2.048V
COMMON-MODE SUPPLY FOR
ANALOG INPUTS.
0.1µF
AD8031, AD8032
S
1
2
SEE THE VOLTAGE REFERENCE OPTIONS SECTION. CONNECTION TO EXTERNAL REFERENCE SIGNALS
IS DEPENDENT ON THE EN1 AND EN0 SETTINGS.
C
IS USUALLY A 10µF CERAMIC CAPACITOR WITH LOW ESL AND ESR.
REF
DECOUPLE REF AND REFIN PINS AS PER THE EN1 AND EN0 RECOMMENDATIONS
Figure 33. Driving the AD7626 from a Differential Analog Source Using ADA4899-1
Rev. 0 | Page 18 of 28
AD7626
499Ω
R35
SINGLE-ENDED
ANALOG INPUT
AC-COUPLED
50Ω SOURCE
499Ω
AD8031
C22
0.1µF
C24
0.1µF
+7.25V
53.6Ω
GND
GND
VDRV+
VCM
100nF
GND
GND
56pF
+V
S
V
20Ω
VCM
OCM
FB–
IN–
IN+
1
2
3
+IN
–IN
PD
11
10
4
C
499Ω
–OUT
+OUT
FB+
ADA4932-1
AD7626
12
20Ω
50Ω
53.6Ω
–V
S
PAD
56pF
–2.5V
GND
GND
C15
0.1µF
GND
499Ω
Figure 34. High Frequency Input Drive Circuit Using the ADA4932-1; Single-Ended-to Differential Configuration
Rev. 0 | Page 19 of 28
AD7626
Table 8. Voltage Reference Options
VOLTAGE REFERENCE OPTIONS
Option EN1
EN0
Reference Mode
The AD7626 allows flexible options for creating and buffering
the reference voltage. The AD7626 conversions refer to ꢀ.096 V
only. The various options creating this ꢀ.096 V reference are
controlled by the EN1 and EN0 pins (see Table 8).
A
1
1
Power-up
Internal reference and internal
reference buffer in use
External 1.2 V reference applied to
REFIN pin required
External 4.096 V reference applied to
REF pin required.
B
C
0
1
0
1
0
0
Power-down mode
DECOUPLE THE REF AND
REFIN PINS EXTERNALLY.
10µF
10µF
REF REFIN
A
IN+
IN–
AD7626
EN1 = 1 AND EN0 = 1
POWER-UP—INTERNAL REFERENCE AND REFERENCE BUFFER IN USE.
NO EXTERNAL REFERENCE CIRCUITRY REQUIRED.
Figure 35. Powered Up, Internal Reference and Internal Reference Buffer
ADR280
1.2V
(2.4V ≤ V+ ≥ 5.5V)
CONNECT 1.2V EXTERNAL REFERENCE TO REFIN PIN.
V
V+
V+
OUT
1.2V REFIN INPUT IS BUFFERED INTERNALLY.
IT CREATES A 4.096V REFERENCE FOR THE ADC.
DECOUPLE THE REF AND REFIN PINS EXTERNALLY
10µF
10µF
0.1µF
0.1µF
V–
REF REFIN
B
IN+
IN–
AD7626
EN1 = 0 AND EN0 = 1
EXTERNAL 1.2V REFERENCE CONNECTED TO REFIN PIN IS REQUIRED.
Figure 36. External 1.2 V Reference Using Internal Reference Buffer
V+
ADR434/
ADR444
V
(6.1V ≤ V ≥ 18V)
IN
4.096V
0.1µF
CONNECT BUFFERED 4.096V SIGNAL TO REF PIN.
DECOUPLE THE REF PIN EXTERNALLY.
REFIN IS A NO CONNECT.
V
10µF
VIN
IN
OUT
AD8031
10µF
0.1µF
GND
NO CONNECT
REF REFIN
C
IN+
IN–
AD7626
EN1 = 1 AND EN0 = 0
EXTERNAL 4.096V REFERENCE CONNECTED TO REF PIN IS REQUIRED.
Figure 37. External 4.096 V Reference Applied to REF Pin
Rev. 0 | Page 20 of 28
AD7626
Power-Up
Wake-Up Time from EN1= 0, EN0 = 0
As is best practice for all ADCs, the core supplies should be
powered on prior to applying an external reference (where
applicable). Lastly, apply the analog inputs.
The AD7626 powers down when EN1 and EN0 are both set to
0. Selecting the correct reference choice from power-down, the
user sets EN1 and EN0 to the required value shown in Table 8.
The user may immediately apply CNV pulses to receive data
conversion results. Typical wake-up times for the selected
reference settings are shown in Table 9. Each time represents
the duration from the EN1, EN0 logic transition to when the
output of the ADC is settled to 0.5 LSB accuracy.
When powering up the AD7626 device, apply 5 V (VDD1)
and 2.5 V(VDD2, VIO) to the device. Set the reference confi-
guration pins, EN0 and EN1, to the correct values. In the case
where an external reference is preferred (governed by EN1 and
EN0 values), apply the external reference of 1.2 V to the REFIN
pin or 4.096 V to the REF pin. EN0 = 0 and EN1 = 0 means that
the AD7626 is in power-down mode.
Table 9. Wake-Up Time from EN1=0, EN0 = 0
Wake-Up
25
Time (0.5 LSB
EN1 EN0 Accuracy)
VDD2 INTERNAL
REFERENCE
Reference Mode
A
Power-up
Internal reference and inter-
nal reference buffer in use
External 1.2 V reference
applied to REFIN pin
External 4.096 V reference
applied to REF pin
1
1
9.5 sec
20
VDD2 EXTERNAL
REFERENCE
VIO INTERNAL
REFERENCE
15
B
C
0
1
1
0
25 ms
65 μs
VIO EXTERNAL
REFERENCE
10
VDD1 INTERNAL
REFERENCE
5
POWER SUPPLY
VDD1 EXTERNAL
REFERENCE
The AD7626 uses both 5 V (VDD1) and 2.5 V (VDD2) power
supplies, as well as a digital input/output interface supply (VIO).
VIO allows a direct interface with 2.5 V logic only. VIO and
VDD2 can be taken from the same 2.5 V source; however, it is
best practice to isolate the VIO and VDD2 pins using separate
traces as well as to decouple each pin separately.
0
0
2
4
6
8
10
THROUGHPUT (MSPS)
Figure 39. Current Consumption vs. Sampling Rate
160
140
120
100
80
The 5 V and 2.5 V supplies required for the AD7626 can be
generated using Analog Devices, Inc., LDOs such as the
ADP3330-2.5, ADP3330-5, ADP3334, and ADP1708.
90
INTERNAL REFERENCE
EXTERNAL REFERENCE
VDD2
85
80
60
VDD1
75
40
70
65
60
55
20
0
0
1
2
3
4
5
6
7
8
9
10
THROUGHPUT (MSPS)
Figure 40. Power Dissipation vs. Sampling Rate
INTERNAL REFERENCE USED
50
1
10
100
1k
10k
SUPPLY FREQUENCY (Hz)
Figure 38. PSRR vs. Supply Frequency
(350 mV pp Ripple on VDD2, 600 mV Ripple on VDD1)
Rev. 0 | Page 21 of 28
AD7626
The clock DCO is a buffered copy of CꢁK and is synchronous
to the data, D , which is updated on the falling edge of DCO +
(tD). By maintaining good propagation delay matching between
D and DCO through the board and the digital host, DCO
can be used to latch D with good timing margin for the shift
register.
DIGITAL INTERFACE
Conversion Control
All analog-to-digital conversions are controlled by the CNV
signal. This signal can be applied in the form of a CNV+/CNV−
ꢁVDS signal, or it can be applied in the form of a 2.5 V CMOS
logic signal to the CNV+ pin. The conversion is initiated by the
rising edge of the CNV signal.
Conversions are initiated by a rising edge CNV pulse. The
CNV pulse must be returned low (≤ tCNVH maximum) for
valid operation. After a conversion begins, it continues until
completion. Additional CNV pulses are ignored during the
conversion phase. After the time, tMSB, elapses, the host should
begin to burst the CꢁK . Note that, tMSB, is the maximum time
for the MSB of the new conversion result and should be used as
the gating device for CꢁK . The echoed clock, DCO , and the
data, D, are driven in phase with D being updated on the
falling edge of DCO+; the host should use the rising edge of
DCO+ to capture D . The only requirement is that the 16
CꢁK pulses finish before the time (tCꢁKꢁ) elapses of the next
conversion phase or the data is lost. From the tCꢁKꢁ to tMSB, D
and DCO are driven to 0. Set CꢁK to idle low between CꢁK
bursts.
After the AD7626 is powered up, the first conversion result
generated is invalid. Subsequent conversion results are valid
provided that the time between conversions does not exceed
the maximum specification for tCYC
.
The two methods for acquiring the digital data output of the
AD7626 via the ꢁVDS interface are described in the following
sections.
Echoed-Clock Interface Mode
The digital operation of the AD7626 in echoed-clock interface
mode is shown in Figure ꢀ1. This interface mode, requiring
only a shift register on the digital host, can be used with many
digital hosts (such as FPGA, shift register, and microprocessor).
It requires three ꢁVDS pairs (D , CꢁK , and DCO ) between
each AD7626 and the digital host.
SAMPLE N
SAMPLE N + 1
tCYC
tCNVH
CNV–
CNV+
ACQUISITION
ACQUISITION
ACQUISITION
tCLKL
tCLK
15
16
1
2
15
16
1
2
3
CLK–
CLK+
tDCO
1
15
16
1
2
15
16
2
3
DCO–
DCO+
tMSB
tD
tCLKD
D+
D–
D1
N – 1
D0
N – 1
D15
N
D14
N
D1
N
D0
N
D15
N + 1
D14
D13
0
0
N + 1 N + 1
Figure 41. Echoed-Clock Interface Mode Timing Diagram
Rev. 0 | Page 22 of 28
AD7626
Self-Clocked Mode
The AD7626 data captured on each phase of the state
machine clock is then compared. The location of the 1 in
the header in each set of data acquired allows the user to
choose the state machine clock phase that occurs during
the data valid window of D .
The digital operation of the AD7626 in self-clocked interface
mode is shown in Figure ꢀ2. This interface mode reduces the
number of traces between the ADC and the digital host to two
ꢁVDS pairs (CꢁK and D ) or to a single pair if sharing a
common CꢁK . Multiple AD7626 devices can share a common
CꢁK signal. This can be useful in reducing the number of
ꢁVDS connections to the digital host.
The self-clocked mode data capture method allows the digital
host to adapt its result capture timing to accommodate
variations in propagation delay through any AD7626.For
example, where data is captured from multiple AD7626s
sharing a common input clock.
When the self-clocked interface mode is used, each ADC
data-word is preceded by a 010 sequence. The first zero is
automatically on D once tMSB has elapsed. The 2-bit header
is then clocked out by the first two CꢁK falling edges. This
header is used to synchronize D of each conversion in the
digital host because, in this mode, there is no data clock output
synchronous to the data (D ) to allow the digital host to
acquire the data output.
Conversions are initiated by a CNV pulse. The CNV pulse
must be returned low (tCNVH maximum) for valid operation.
After a conversion begins, it continues until completion.
Additional CNV pulses are ignored during the conversion
phase. After the time, tMSB, elapses, the host begins to burst
the CꢁK signal to the AD7626. All 18 CꢁK pulses are to be
applied in the time window framed by tMSB and the subsequent
tCꢁKꢁ. The required 18 CꢁK pulses must finish before tCꢁKꢁ
(referenced to the next conversion phase) elapses. Otherwise,
the data is lost because it is overwritten by the next conversion
result.
Synchronization of the D data to the digital host’s acquisition
clock is accomplished by using one state machine per AD7626
device. For example, using a state machine that runs at the
same speed as CꢁK incorporates three phases of this clock
frequency (120º apart). Each phase acquires the data D as
output by the ADC.
Set CꢁK to idle high between bursts of 18 CꢁK pulses. The
header bit and conversion data of the next ADC result are
output on subsequent falling edges of CꢁK during the next
burst of the CꢁK signal.
SAMPLE N
SAMPLE N + 1
tCYC
tCNVH
CNV–
CNV+
ACQUISITION
tCLK
ACQUISITION
ACQUISITION
tCLKL
1
17
18
1
2
3
4
17
18
2
3
CLK–
CLK+
tMSB
tCLKD
D+
D–
D15
N + 1
D14
N
D1
N
D0
N
D1
N – 1
D0
N – 1
D15
N
0
1
0
0
1
0
Figure 42. Self-Clocked Interface Mode Timing Diagram
Rev. 0 | Page 23 of 28
AD7626
APPLICATIONS INFORMATION
LAYOUT, DECOUPLING, AND GROUNDING
VIO Supply Decoupling
Decouple the VIO supply applied to Pin 12 to ground at Pin 13.
Layout and Decoupling of Pin 25 to Pin 32
When laying out the printed circuit board (PCB) for the AD7626,
follow the practices described in this section to obtain the maxi-
mum performance from the converter.
Connect the outputs of Pin 25, Pin 26, and Pin 28 together and
decouple them to Pin 27 using a 10 μF capacitor with low ESR
and low ESꢁ.
Exposed Paddle
The AD7626 has an exposed paddle on the underside of the
package.
Reduce the inductance of the path connecting Pin 25, Pin 26,
and Pin 28 by widening the PCB traces connecting these pins.
•
•
Solder the paddle directly to the PCB.
Connect the paddle to the ground plane of the board using
multiple vias, as shown in Figure ꢀ3.
Take a similar approach in the connections used for the
reference pins of the AD7626. Connect Pin 29, Pin 30, and
Pin 32 together using widened PCB traces to reduce inductance.
In internal or external reference mode, a ꢀ.096 V reference voltage
is output on Pin 29, Pin 30, and Pin 32. Decouple these pins to
Pin 31 using a 10 μF capacitor with low ESR and low ESꢁ.
•
•
Decouple all supply pins except for Pin 12 (VIO) directly to
the paddle, minimizing the current return path.
Pin 13 and Pin 2ꢀ can be connected directly to the paddle.
Use vias to ground at the point where these pins connect to
the paddle.
Figure ꢀ3 shows an example of the recommended layout for
the underside of the AD7626 device. Note the extended signal
trace connections and the outline of the capacitors decoupling
the signals applied to the REF pins (Pin 29, Pin 30, and Pin 32)
and to the CAP2 pins (Pin 25, Pin 26, and Pin 28).
VDD1 Supply Routing and Decoupling
The VDD1 supply is connected to Pin 1, Pin 19, and Pin 20.
Decouple the supply using a 100 nF capacitor at Pin 1. The user
can connect this supply trace to Pin 19 and Pin 20. Use a series
ferrite bead to connect the VDD1 supply from Pin 1 to Pin 19
and Pin 20. The ferrite bead isolates any high frequency noise or
ringing on the VDD1 supply. Decouple the VDD1 supply to Pin
19 and Pin 20 using a 100 nF capacitor decoupled to ground at
the exposed paddle.
24 23 22 21 20 19 18 17
25
26
27
28
29
30
31
32
16
15
14
13
12
11
10
9
PADDLE
4.096V
EXTERNAL REFERENCE
(ADR434 OR ADR444)
1
2
3
4
5
6
7
8
Figure 43. PCB Layout and Decoupling Recommendations for Pin 24 to Pin 32
Rev. 0 | Page 24 of 28
AD7626
OUTLINE DIMENSIONS
5.00
BSC SQ
0.60 MAX
0.60 MAX
PIN 1
INDICATOR
25
24
32
1
PIN 1
INDICATOR
0.50
BSC
TOP
VIEW
3.25
3.10 SQ
2.95
EXPOSED
PAD
(BOTTOM VIEW)
4.75
BSC SQ
0.50
0.40
0.30
17
16
8
9
0.25 MIN
0.80 MAX
0.65 TYP
3.50 REF
12° MAX
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.05 MAX
0.02 NOM
1.00
0.85
0.80
0.30
0.23
0.18
COPLANARITY
0.08
0.20 REF
SECTION OF THIS DATA SHEET.
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2
Figure 44. 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
5 mm × 5 mm Body, Very Thin Quad
(CP-32-2)
Dimensions shown in millimeters
ORDERING GUIDE
Model
Temperature Range
−40°C to +85°C
−40°C to +85°C
Package Description
Package Option
CP-32-2
CP-32-2
AD7626BCPZ1
32-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
32-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
Evaluation Board
AD7626BCPZ-RL71
EVAL-AD7626EDZ1, 2
EVAL-CED1Z1, 3
Converter Evaluation and Development Board
1 Z = RoHS Compliant Part.
2 This board can be used as a standalone evaluation board or in conjunction with the EVAL-CEDIZ for evaluation/demonstration purposes.
3 This board allows the PC to control and communicate with all Analog Devices evaluation boards with model numbers ending with the ED designator.
Rev. 0 | Page 25 of 28
AD7626
NOTES
Rev. 0 | Page 26 of 28
AD7626
NOTES
Rev. 0 | Page 27 of 28
AD7626
NOTES
©2009 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07648-0-9/09(0)
Rev. 0 | Page 28 of 28
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