EVAL-AD7879EBZ_技术文档

Low Voltage Controller for Touch Screens

AD7879

FUNCTIONAL BLOCK DIAGRAM

FEATURES

V

/REF

CC

4-wire touch screen interface

1.6 V to 3.6 V operation

X– Y– X+ Y+

Median and averaging filter to reduce noise

Automatic conversion sequencer and timer

User-programmable conversion parameters

Auxiliary analog input/battery monitor (0.5 V to 5 V)

1 optional GPIO

X+

X–

REF–

REF+

Y+

Y–

Interrupt outputs (INT, PENIRQ)

Touch-pressure measurement

Wake-up on touch function

12-BIT

SAR ADC

RESULT

REGISTERS

GND

TEMPERATURE

SENSOR

Shutdown mode: 6 μA maximum

12-ball, 1.6 mm × 2 mm WLCSP

16-lead, 4 mm × 4 mm LFCSP

AD7879/

AD7879-1

CONTROL

REGISTERS

APPLICATIONS

Personal digital assistants

Smart hand-held devices

Touch screen monitors

Point-of-sale terminals

Medical devices

SEQUENCER

AND TIMER

SERIAL PORT

TO

RESULT

REGISTERS

CS/

DIN/ DOUT/ SCL

ADD0 ADD1 SDA

Cell phones

Figure 1.

GENERAL DESCRIPTION

The AD7879 is a 12-bit successive approximation analog-to-

digital converter (ADC) with a synchronous serial interface and

low on-resistance switches for driving 4-wire resistive touch

screens. The AD7879 works with a very low power supply (a

single 1.6 V to 3.6 V) and features throughput rates of 105 kSPS.

The AD7879 has a programmable pin that can operate as an

auxiliary input to the ADC, as a battery monitor, or as a GPIO.

There is also a programmable interrupt output that can operate

in three modes: as a general-purpose interrupt to signal when

INT

new data is available

, as an interrupt to indicate when limits

are exceeded, or as a pen-down interrupt when the screen is

PENIRQ

ment and touch-pressure measurement.

The device includes a shutdown mode that reduces its current

consumption to less than 6 μA.

touched (

). The AD7879 offers temperature measure-

To reduce the effects of noise from LCDs and other sources,

the AD7879 contains a preprocessing block. The preprocessing

function consists of a median and an averaging filter. The com-

bination of these two techniques provides a more robust solution,

discarding the spurious noise in the signal and keeping only

the data of interest. The size of both filters is programmable.

Other user-programmable conversion controls include variable

acquisition time and first conversion delay; up to 16 averages

can be taken per conversion. The AD7879 can run in either

slave or standalone mode, using an automatic conversion

sequencer and timer.

The AD7879 is available in a 12-ball, 1.6 mm × 2 mm WLCSP

and in a 16-lead, 4 mm × 4 mm LFCSP. The part also has either

an SPI (AD7879) or I²C (AD7879-1) interface.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registeredtrademarks arethe property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.461.3113

www.analog.com

AD7879

TABLE OF CONTENTS

Features .............................................................................................. 1

Auxiliary Input ........................................................................... 17

Battery Input ............................................................................... 17

Limit Comparison...................................................................... 17

GPIO ............................................................................................ 17

Register Map ................................................................................... 19

Detailed Register Descriptions ..................................................... 20

Control Registers............................................................................ 24

Control Register 1 ...................................................................... 24

Control Register 2 ...................................................................... 26

Control Register 3 ...................................................................... 27

Interrupts..................................................................................... 28

Synchronizing the AD7879 to the Host CPU......................... 29

Serial Interface ................................................................................ 30

SPI Interface................................................................................ 30

I²C-Compatible Interface .......................................................... 32

Grounding and Layout .................................................................. 35

Chip Scale Packages ................................................................... 35

WLCSP Assembly Considerations........................................... 35

Outline Dimensions....................................................................... 36

Ordering Guide .......................................................................... 36

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description......................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

SPI Timing Specifications (AD7879)......................................... 4

I²C Timing Specifications (AD7879-1) ..................................... 5

Absolute Maximum Ratings............................................................ 6

ESD Caution.................................................................................. 6

Pin Configuration and Function Descriptions............................. 7

Typical Performance Characteristics ............................................. 8

Terminology .................................................................................... 11

Theory of Operation ...................................................................... 12

Touch Screen Principles ............................................................ 12

Measuring Touch Screen Inputs............................................... 13

Touch-Pressure Measurement .................................................. 14

Temperature Measurement ....................................................... 14

Median and Averaging Filters....................................................... 16

AUX/VBAT/GPIO Pin................................................................... 17

REVISION HISTORY

10/08—Revision 0: Initial Version

Rev. 0 | Page 2 of 36

AD7879

SPECIFICATIONS

V_CC= 1.6 V to 3.6 V, T_A= −40°C to +85°C, unless otherwise noted.

Table 1.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

DC ACCURACY

Resolution

12

11

Bits

LSB

No Missing Codes

Integral Nonlinearity (INL)¹

Differential Nonlinearity (DNL)¹

Negative DNL

12

±3

LSB size = 390 μV

−0.99

+2

LSB

Positive DNL

LSB

Offset Error²

±2

±6

LSB

Gain Error²

±±

LSB

Noise³

70

60

2

μV rms

dB

Power Supply Rejection³

Internal Clock Frequency

SWITCH DRIVERS

On Resistance¹

Y+, X+

MHz

6

5

Ω

Y−, X−

ANALOG INPUTS

Input Voltage Ranges

DC Leakage Current

Input Capacitance

Accuracy

0

V_CC

V

±0.1

30

μA

pF

%

0.3

TEMPERATURE MEASUREMENT

Temperature Range

Resolution

−±0

0

+85

°C

0.3

±2

Accuracy²

Calibrated at 25°C

Uncalibrated accuracy

V_IN= 0 V or V_CC

BATTERY MONITOR

Input Voltage Range

Input Impedance³

Accuracy

5

V

16

2

kΩ

%

CS

LOGIC INPUTS (DIN, SCL, , SDA, GPIO)

Input High Voltage, V_INH

Input Low Voltage, V_INL

Input Current, I_IN

0.7 V_CC

V

0.3 V_CC

V

0.01

10

μA

pF

3

Input Capacitance, C_IN

INT

LOGIC OUTPUTS (DOUT, GPIO, SCL, SDA,

Output High Voltage, V_OH

Output Low Voltage, V_OL

Floating-State Leakage Current

Floating-State Output Capacitance²

CONVERSION RATE³

)

V_CC− 0.2

V

0.±

V

±0.1

5

μA

pF

Conversion Time

9.5

μs

Including 2 μs of acquisition time

Throughput Rate

105

kSPS

POWER REQUIREMENTS

V_CC(Specified Performance)

I_CC

1.6

2.6

3.6

V

Digital inputs = 0 V or V_CC

ADC on, PM = 10

Converting Mode

±80

±06

650

μA

Static

ADC and temperature sensor are off; the reference and

oscillator are on; PM = 01, 11

Shutdown Mode

0.5

6

μA

PM = 00

¹See the Terminology section.

²Guaranteed by characterization, not production tested.

³Sample tested at 25°C to ensure compliance.

Rev. 0 | Page 3 of 36

AD7879

SPI TIMING SPECIFICATIONS (AD7879)

T_A= −40°C to +85°C; V_CC= 1.6 V to 3.6 V, unless otherwise noted. Sample tested at 25°C to ensure compliance. All input signals are

specified with t_R= t_F= 5 ns (10% to 90% of V_CC) and timed from a voltage level of 1.4 V.

Table 2.

Parameter¹

Limit at T_MIN, T_MAX

Unit

Description

f_SCLK

t₁

5

MHz max

ns min

ns max

ns min

CS falling edge to first SCL falling edge

SCL high pulse width

SCL low pulse width

DIN setup time

DIN hold time

DOUT access time after SCL falling edge

CS rising edge to DOUT high impedance

SCL rising edge to CS high

t₂

t₃

t_±

t₅

t₆

t₇

20

15

20

16

15

t₈

¹Guaranteed by design, not production tested.

CS

t₁

t₂

t₈

t₃

15

1

2

3

16

1

2

16

SCL

t₄

t₅

LSB

MSB

DIN

t₆

t₇

DOUT

MSB

LSB

Figure 2. Detailed SPI Timing Diagram

Rev. 0 | Page ± of 36

AD7879

I²C TIMING SPECIFICATIONS (AD7879-1)

T_A= −40°C to +85°C; V_CC= 1.6 V to 3.6 V, unless otherwise noted. Sample tested at 25°C to ensure compliance. All input signals are

timed from a voltage level of 1.4 V.

Table 3.

Parameter¹

Limit

±00

0.6

1.3

0.6

100

300

0.6

1.3

Unit

Description

f_SCLK

t₁

t₂

t₃

t_±

t₅

t₆

t₇

t₈

kHz max

μs min

ns min

μs min

ns max

Start condition hold time, t_{HD; STA}

Clock low period, t_LOW

Clock high period, t_HIGH

Data setup time, t_{SU; DAT}

Data hold time, t_{HD; DAT}

Stop condition setup time, t_{SU; STO}

Start condition setup time, t_{SU; STA}

Bus free time between stop and start conditions, t_BUF

Clock/data rise time

t_R

t_F

300

Clock/data fall time

¹Guaranteed by design, not production tested.

t_R

t_F

t₁

t₂

SCL

t₃

t₇

t₁

t₆

t₅

t₄

SDA

t₈

STOP START

START

STOP

Figure 3. Detailed I²C Timing Diagram

Rev. 0 | Page 5 of 36

AD7879

ABSOLUTE MAXIMUM RATINGS

T_A= 25°C, unless otherwise specified.

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

Table 4.

Parameter

Rating

V_CCto GND

−0.3 V to +3.6 V

Analog Input Voltage to GND

AUX/VBAT to GND

Digital Input Voltage to GND

Digital Output Voltage to GND

−0.3 V to V_CC+ 0.3 V

−0.3 V to V_CC+ 5 V

−0.3 V to V_CC+ 0.3 V

−0.3V to V_CC+ 0.3 V

200µA

I

OL

Input Current to Any Pin Except Supplies¹10 mA

ESD Rating (X+, Y+, X−, Y−)

Air Discharge Human Body Model

Contact Human Body Model

ESD Rating (All Other Pins)

Human Body Discharge

Field Induced Charge Device Model

Machine Model

15 kV

10 kV

TO OUTPUT

1.4V

C

50pF

L

200µA

I

OH

± kV

1 kV

0.2 kV

Figure 4. Circuit Used for Digital Timing

Operating Temperature Range

Storage Temperature Range

Junction Temperature

−±0°C to +85°C

−65°C to +150°C

150°C

ESD CAUTION

WLCSP (±-Layer Board)

Power Dissipation

θ_JAThermal Impedance

866 mW

75°C/W

LFCSP (±-Layer Board)

Power Dissipation

2.138 W

θ_JAThermal Impedance

IR Reflow Peak Temperature

Lead Temperature (Soldering 10 sec)

30.±°C/W

260°C (±0.5°C)

300°C

¹Transient currents of up to 100 mA do not cause SCR latch-up.

Rev. 0 | Page 6 of 36

AD7879

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

BALL A1

INDICATOR

BALL A1

INDICATOR

1

2

3

1

2

3

AUX/

VBAT/

GPIO

AUX/

VBAT/

GPIO

V

_CC/REF

V

_CC/REF

X+

A

B

A

B

PENIRQ/

INT/DAV

PENIRQ/

INT/DAV

Y+

ADD0

Y+

CS

DOUT

SCL

DIN

GND

X–

Y–

SDA ADD1

X–

Y–

C

D

C

D

SCL

GND

TOP VIEW

(BALL SIDE DOWN)

Not to Scale

(BALL SIDE DOWN)

Not to Scale

Figure 5. AD7879 WLCSP Pin Configuration

Figure 7. AD7879-1 WLCSP Pin Configuration

PIN 1

INDICATOR

12 PENIRQ/INT/DAV

11 NC

12 PENIRQ/INT/DAV

Y+

NC

X–

1

2

3

4

Y+

NC

X–

1

2

3

4

11 NC

10 NC

AD7879

TOP VIEW

(Not to Scale)

AD7879-1

TOP VIEW

(Not to Scale)

10 NC

9

DOUT

9

SDA

NOTES

1. NC = NO CONNECT

NOTES

1. NC = NO CONNECT

2. THE EXPOSED PAD IS NOT CONNECTED INTERNALLY.

FOR INCREASED RELIABILITY OF THE SOLDER JOINTS

AND MAXIMUM THERMAL CAPABILITY IT IS RECOMMENDED

THAT THE PAD BE SOLDERED TO THE GROUND PLANE.

2. THE EXPOSED PAD IS NOT CONNECTED INTERNALLY.

FOR INCREASED RELIABILITY OF THE SOLDER JOINTS

AND MAXIMUM THERMAL CAPABILITY IT IS RECOMMENDED

THAT THE PAD BE SOLDERED TO THE GROUND PLANE.

Figure 6. AD7879 LFCSP Pin Configuration

Figure 8. AD7879-1 LFCSP Pin Configuration

Table 5. Pin Function Descriptions

Pin No.

WLCSP

LFCSP

Mnemonic

Description

1A

13

AUX/VBAT/GPIO

Pin functionality is programmable to be either an auxiliary input to the ADC, as a battery measurement

input to the ADC, or as a general-purpose digital input/output.

1B

1C

12

9

PENIRQ INT DAV

Interrupt Output. This pin asserts either when the screen is touched, when new data is available in the registers, or

when a measurement exceeds the preprogrammed limits. Active low, internal pull-up resistor of 50 kΩ.

/

DOUT

SDA

SPI Serial Data Output on the AD7879.

Serial Data Input and Output on the AD7879-1.

1D

2A

2B

8

SCL

Serial Interface Clock Input.

15

1±

V_CC/REF

CS

ADD0

Power Supply Input. It is also the ADC reference.

Chip Select for the Serial Interface on the AD7879. Active low.

Address Bit 0 for the AD7879-1. This pin can be tied high or low to determine an address for the AD7879-1.

2C

2D

6

7

DIN

ADD1

SPI Serial Data Input to the AD7879.

Address Bit 1 for the AD7879-1. This pin can be tied high or low to determine an address for the AD7879-1.

GND

Ground. Ground reference point for all circuitry on the AD7879. All analog input signals and any external

reference signal should be referred to this voltage.

3A

16

X+

Y+

X−

Y−

NC

EP

Touch Screen Input Channel.

No Connect.

3B

1

3C

±

3D

N/A

5

2, 3, 10, 11

17

Exposed Pad.

Rev. 0 | Page 7 of 36

AD7879

TYPICAL PERFORMANCE CHARACTERISTICS

T_A= 25°C, V_CC= 2.6 V, f_SAMPLE= 125 kHz, f_DCLK= 16 × f_SAMPLE= 2 MHz, unless otherwise noted.

475

470

465

460

455

450

445

440

1.0

0.8

0.6

0.4

0.2

2.6V

0

3.6V

–0.2

–0.4

–0.6

–0.8

–1.0

1.6V

435

430

425

–40

–25

–10

10

25

40

55

70

85

–40

–25

–10

10

25

40

55

70

85

TEMPERATURE (°C)

Figure 9. Supply Current vs. Temperature

Figure 12. Change in ADC Gain vs. Temperature

700

600

500

400

300

200

100

0

1.0

0.8

0.6

0.4

1.6V

0.2

2.6V

0

–0.2

–0.4

–0.6

–0.8

–1.0

3.6V

1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6

(V)

–40

–25

–10

10

25

40

55

70

85

V

CC

TEMPERATURE (°C)

Figure 10. Supply Current vs. V_CC

Figure 13. Change in ADC Offset vs. Temperature

4.0

3.5

3.0

2.0

1.5

1.0

0.5

2.5

2.0

1.5

1.0

0.5

0

–0.5

–1.0

–1.5

–2.0

–40

–25

–10

10

25

50

75

100

0

512

1024

1536

2048

2560

3072

3584

4096

TEMPERATURE (°C)

CODE

Figure 11. Full Power-Down I_DDvs. Temperature

Figure 14. ADC INL Plot

Rev. 0 | Page 8 of 36

AD7879

1.0

0.8

0.6

0.4

0.2

0

6.0

5.5

5.0

4.5

4.0

3.5

3.0

–0.2

–0.4

X+ TO V

CC

–0.6

–0.8

–1.0

X– TO GND

Y+ TO V

CC

Y– TO GND

1

501

1001 1501

2001 2501 3001 3501 4001

CODE

–40

–25

–10

10

25

40

55

70 85

TEMPERATURE (°C)

Figure 15. ADC DNL Plot

Figure 17 Switch On Resistance vs. Temperature

(X+, Y+: V_CCto Pin; X−, Y−: Pin to GND)

7

6

5

4

3

2

1

0

2370

2369

2368

2367

2366

2365

2364

2363

X+ TO V

Y+ TO V

X– TO GND

Y– TO GND

CC

2362

2361

2360

1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6

(V)

–40 –25 –15 –5

5

15 25 35 45 55 65 75 85

V

TEMPERATURE (°C)

CC

Figure 18. ADC Code vs. Temperature (Fixed Analog Input)

Figure 16. Switch On Resistance vs. V_CC

(X+, Y+: V_CCto Pin; X−, Y−: Pin to GND)

Rev. 0 | Page 9 of 36

AD7879

1400

1200

1000

800

600

400

200

0

MEAN: –1.98893

SD: 0.475534

250

200

150

100

50

0

2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6

(V)

–4

–3

–2

–1

0

V

CC

ERROR (%)

Figure 19. Temperature Code vs. V_CCfor 25°C

Figure 21. Typical Uncalibrated Accuracy for Battery Channel (25°C)

0

–20

–40

SNR = 61.58dB

THD = 72.34dB

–60

–80

–100

–120

–140

–160

FREQUENCY (Hz)

Figure 20. Typical FFT Plot for the Auxiliary Channels at 25 kHz Sampling

Rate and 1 kHz Input Frequency

Rev. 0 | Page 10 of 36

AD7879

TERMINOLOGY

Offset Error

Integral Nonlinearity (INL)

Offset error is the deviation of the first code transition

(00 … 000) to (00 … 001) from the ideal (AGND + 1 LSB).

INL is the maximum deviation from a straight line passing

through the endpoints of the ADC transfer function. The end-

points of the transfer function are zero scale at 1 LSB below the

first code transition and full scale at 1 LSB above the last code

transition.

Gain Error

Gain error is the deviation of the last code transition

(111 … 110) to (111 … 111) from the ideal (V_REF− 1 LSB)

after the offset error has been adjusted out.

Differential Nonlinearity (DNL)

DNL is the difference between the measured and the ideal

1 LSB change between any two adjacent codes in the ADC.

On Resistance

On resistance is a measure of the ohmic resistance between the

drain and the source of the switch drivers.

Rev. 0 | Page 11 of 36

AD7879

THEORY OF OPERATION

PLASTIC FILM WITH

TRANSPARENT, RESISTIVE

COATING ON BOTTOM SIDE

The AD7879 is a complete, 12-bit data acquisition system for

digitizing positional inputs from a 4-wire resistive touch screen.

To support this function, data acquisition on the AD7879 is

highly programmable so as to ensure accurate and noise free

results from the touch screen.

CONDUCTIVE ELECTRODE

ON BOTTOM SIDE

Y+

The core of the AD7879 is a high speed, low power, 12-bit

analog-to-digital converter (ADC) with input multiplexer,

on-chip track-and-hold, and on-chip clock. Conversion

results are stored in on-chip results registers. The results from

the auxiliary input or the battery input can be compared with

high and low limits stored in limit registers to generate an out-

X–

Y–

X+

INT

of-limit

.

The AD7879 also contains low resistance analog switches to

switch the X and Y excitation voltages to the touch screen and

the on-chip temperature sensor. The high speed SPI serial bus

provides control of the devices, as well as communication with

the device. The AD7879-1 is available with an I²C interface.

CONDUCTIVE ELECTRODE

ON TOP SIDE

PLASTIC FILM WITH

TRANSPARENT, RESISTIVE

COATING ON TOP SIDE

LCD SCREEN

Figure 22. Basic Construction of a Touch Screen

The Y layer has conductive electrodes running along the top

and bottom edges, allowing the application of an excitation

voltage down the Y layer from top to bottom.

Operating from a single supply from 1.6 V to 3.6 V, the AD7879

offers a throughput rate of 105 kHz. The device is available in a

1.6 mm × 2 mm 12-ball wafer level chip scale package (WLCSP)

and in a 4 mm × 4 mm 16-lead lead frame chip scale package.

Provided that the layers are of uniform resistivity, the voltage

at any point between the two electrodes is proportional to the

horizontal position for the X layer and the vertical position for

the Y layer.

The AD7879 has an on-chip sequencer that schedules a sequence

of preprogrammed conversions. The conversion sequence starts

automatically when the screen is touched, or at preset intervals,

using the on-board timer.

When the screen is touched, the two layers make contact. If

only the X layer is excited, the voltage at the point of contact,

and therefore the horizontal position, can be sensed at one of

the Y layer electrodes. Similarly, if only the Y layer is excited,

the voltage, and therefore the vertical position, can be sensed

at one of the X layer electrodes. By switching alternately

between X and Y excitation and measuring the voltages, the

X and Y coordinates of the contact point can be found.

To ensure that the AD7879 works well with different touch

screens, the user can select the acquisition time. There is also a

programmable delay to ensure that the voltage on the touch

screen settles before a measurement is taken.

To help reduce noise in the system, the ADC takes up to 16

conversion results from each channel, and writes the average

of the results to the register. To further improve the perfor-

mance of the AD7879, the median filter can also be used if

there is noise present in the system.

In addition to measuring the X and Y coordinates, it is also

possible to estimate the touch pressure by measuring the

contact resistance between the X and Y layers. The AD7879

is designed to facilitate this measurement.

TOUCH SCREEN PRINCIPLES

A 4-wire touch screen consists of two flexible, transparent,

resistive-coated layers that are normally separated by a small

air gap. The X layer has conductive electrodes running down

the left and right edges, allowing the application of an excitation

voltage across the X layer from left to right.

Rev. 0 | Page 12 of 36

AD7879

Figure 23 shows an equivalent circuit of the analog input

structure of the AD7879, showing the touch screen switches,

the main analog multiplexer, the ADC, and the dual 3-to-1

multiplexer that selects the reference source for the ADC.

The voltage seen at the input to the ADC in Figure 24 is

R_{Y −}

V_IN=V_CC

×

(1)

R_YTOTAL

The advantage of the single-ended method is that the touch

screen excitation voltage is switched off once the signal is

acquired. Because a screen can draw over 1 mA, this is a

significant consideration for a battery-powered system.

V

CC

X+

X–

Y+

Y–

The disadvantage of the single-ended method is that voltage

drops across the switches can introduce errors. Touch screens

can have a total end-to-end resistance ranging from 200 Ω to

900 Ω. By taking the lowest screen resistance of 200 Ω and a

X– Y– GND X+ Y+

V

CC

INPUT

MUX

DUAL 3-TO-1 MUX

typical switch resistance of 14 Ω, the user can reduce the apparent

excitation voltage to 200/228 × 100 = 87% of its actual value.

In addition, the voltage drop across the low-side switch adds to

the ADC input voltage. This introduces an offset into the input

voltage; thus, it can never reach zero.

AUX/VBAT/GPIO

REF–

REF+

TEMPERATURE

SENSOR

12-BIT SUCCESSIVE

APPROXIMATION ADC

WITH TRACK-AND-HOLD

IN+

Ratiometric Method

Figure 23. Analog Input Structure

The ratiometric method illustrated in Figure 25 shows the negative

input of the ADC reference tied to Y− and the positive input

connected to Y+. Thus, the screen excitation voltage provides

the reference for the ADC. The input of the ADC is connected

to X+ to determine the Y position.

The AD7879 can be set up to automatically convert either

specific input channels or a sequence of channels. The results

of the ADC conversions are stored in the results registers.

When measuring the ancillary analog inputs (AUX, TEMP, or

VBAT), the ADC uses a V_CCreference and the measurement is

referred to GND.

V

CC

Y+

X+

MEASURING TOUCH SCREEN INPUTS

When measuring the touch screen inputs, it is possible to

measure using V_CCas a reference, or to use the touch screen

excitation voltage as the reference and to perform a ratiometric,

differential measurement. The differential method is the default

REF+

ADC

REF–

INPUT

(VIA MUX)

TOUCH

SCREEN

Y–

DFR

method and is selected by clearing the SER/

bit (Bit 9 in

Control Register 2) to 0. The single-ended method is selected

by setting this bit to 1.

GND

Figure 25. Ratiometric Conversion of Touch Screen Inputs

Single-Ended Method

For greater accuracy, the ratiometric method has two significant

advantages. One is that the reference to the ADC is provided

from the actual voltage across the screen; therefore, any voltage

dropped across the switches has no effect. The other advantage

is that because the measurement is ratiometric, it does not

matter if the voltage across the screen varies in the long term.

However, it must not change after the signal has been acquired.

Figure 24 illustrates the single-ended method for the Y position.

For the X position, the excitation voltage is applied to X+ and

X− and the voltage is measured at Y+.

V

CC

Y+

X+

V

REF

The disadvantage of the ratiometric method is that the screen

must be powered up at all times because it provides the reference

voltage for the ADC.

REF+

ADC

REF–

INPUT

(VIA MUX)

TOUCH

SCREEN

Y–

GND

Figure 24. Single-Ended Conversion of Touch Screen Inputs

Rev. 0 | Page 13 of 36

AD7879

Second Method

TOUCH-PRESSURE MEASUREMENT

The second method requires the user to know the resistance of

the X-plate and Y-plate tablets. Three touch screen conversions

are required: a measurement of the X position (X_POSITION), the

Y position (Y_POSITION), and the Z1 position.

The pressure applied to the touch screen by a pen or finger can

also be measured with the AD7879, using some simple

calculations. The contact resistance between the X and Y plates

is measured providing a good indication of the size of the

depressed area and, therefore, the applied pressure. The area of

the spot that is touched is proportional to the size of the object

touching it. The size of this resistance (R_TOUCH) can be calculated

using two different methods.

The following equation also calculates the R_TOUCH

:

R

_TOUCH= R_XPLATE× (X_POSITION/4096) × [(4096/Z1) − 1] −

_YPLATE× [1 − (Y_POSITION/4096)]

(3)

TEMPERATURE MEASUREMENT

First Method

A temperature measurement option called the single conversion

method is available on the AD7879. The conversion method

requires only a single measurement on ADC Channel 001b.

The results are stored in the results registers with Address 0x0D

(TEMP). The AD7879 does not provide an explicit output of

the temperature reading; the system must perform some

external calculations. This method is based on an on-chip

diode measurement.

The first method requires the user to know the total resistance

of the X-plate tablet (R_X). Three touch screen conversions are

required: measurement of the X position, X_POSITION(Y+ input);

measurement of the Y− input with the excitation voltage applied

to Y+ and X− (Z1 measurement); and measurement of the X+

input with the excitation voltage applied to Y+ and X− (Z2

measurement).

These three measurements are illustrated in Figure 26.

The acquisition time is fixed at 16 ms for temperature

measurement.

The AD7879 has two special ADC channel settings that

configure the X and Y switches for Z1 and Z2 measurement

and store the results in the Z1 and Z2 results registers. The Z1

measurement is ADC Channel 101b, and the result is stored in

register with Read Address 0x0A. The Z2 measurement is ADC

Channel 100b, and the result is stored in register with Read

Address 0x0B.

Conversion Method

The conversion method makes use of the fact that the tem-

perature coefficient of a silicon diode is approximately

−2.1 mV/°C. However, this small change is superimposed

on the diode forward voltage, which can have a wide tolerance.

Therefore, it is necessary to calibrate by measuring the diode

voltage at a known temperature to provide a baseline from

which the change in forward voltage with temperature can be

measured. This method provides a resolution of approximately

0.3°C and a predicted accuracy of 2°C.

The touch resistance can then be calculated using the following

equation:

R

_TOUCH= (R_XPLATE) × (X_POSITION/4096) × [(Z2/Z1) − 1]

(2)

MEASURE

X POSITION

X+

Y+

The temperature limit comparison is performed on the result

in the TEMP results register, which is the measurement of the

diode forward voltage. The values programmed into the high

and low limits should be referenced to the calibrated diode

forward voltage to make accurate limit comparisons.

TOUCH

RESISTANCE

X–

Y+

Y–

X+

MEASURE

Z1 POSITION

TOUCH

RESISTANCE

Y–

Y+

X–

X+

TOUCH

RESISTANCE

Y–

X–

MEASURE

Z2 POSITION

Figure 26. Three Measurements Required for Touch Pressure

Rev. 0 | Page 1± of 36

AD7879

Temperature Calculations

Example

If an explicit temperature reading in degrees Celsius is required,

calculate for the single measurement method by

Using V_CC= 2.5 V as reference,

Degrees per LSB = (2.5/4096)/−2.1 × 10⁻³= −0.291

1. Calculate the scale factor of the ADC in degrees per LSB

The ADC output is 983 decimal at 25°C, equivalent to a diode

forward voltage of 0.6 V.

Degrees per LSB = ADC LSB size/−2.1 mV =

(V_CC/4096)/−2.1 mV

The ADC output at T_AMBis 880.

2. Save the ADC output (D_CAL) at the calibration

ΔT = (880 − 983) × −0.291 = 30°C

temperature, T_CAL

3. Take the ADC reading, D_AMB, at the temperature to be

measured, T_AMB

.

T_AMB= 25 + 30 = 55°C

.

4. Calculate the difference in degrees between T_CALand T_AMBby

ΔT = (D_AMB− D_CAL) × degrees per LSB

5. Add ΔT to T_CAL

.

Rev. 0 | Page 15 of 36

AD7879

MEDIAN AND AVERAGING FILTERS

As explained in the Touch Screen Principles section, touch

screens are composed of two resistive layers, normally placed

over an LCD screen. Because these layers are in close proximity

to the LCD screen, noise can be coupled from the screen onto

these resistive layers, causing errors in the touch screen posi-

tional measurements.

When both filter values are 00, only one measurement is

transferred to the register map.

The number chosen with the M1 and M0 settings must be

equal to or larger than the number chosen with the A1 and

A0 settings. If both settings select the same number, the median

filter is switched off.

The AD7879 contains a filtering block to process the data and

discard the spurious noise before sending the information to

the host. The goal of this block is not just the suppression of

noise; the on-chip filtering also remarkably reduces the host

processing loading.

Table 8. Median Averaging Filters (MAVF) Settings

Function

M = A

M < A

M > A

Median filter does not operate; output is the

average of A converted results

Not possible because the median filter size is

always bigger than the averaging window size

The processing function consists of two filters that are applied

to the converted results: the median filter and the averaging filter.

Output is the average of the middle A values

from the array of M measurements

The median filter suppresses the isolated out-of-range noise and

sets the number of measurements to be taken. These measure-

ments are arranged in a temporary array, where the first value

is the smallest measurement and the last value is the largest

measurement. Bit 6 and Bit 5 in Control Register 2 (M1, M0)

set the window of the median filter, and therefore, the number

of measurements taken.

Example

M1, M0 = 11, A1, A0 = 10; in this example the median filter

has a window size of 16. This means that 16 measurements are

taken and arranged in descending order in a temporary array.

The averaging window size in this case is 8. The output is an

average of the middle 8 values of the 16 measurements taken

with the median filter.

Table 6. Median Filter Size

M1

M0

Function

0

1

0

1

0

1

Median filter does not operate

± measurements

8 measurements

16 measurements

12-BIT SAR

ADC

MEDIAN

FILTER

AVERAGING

FILTER

CONVERTED

RESULTS

16 MEASUREMENTS

ARRANGED

AVERAGE OF

MIDDLE 8 VALUES

6

2

13

4

16

5

15

10

9

1

2

3

4

5

6

7

8

1

2

3

4

5

6

7

8

9

The averaging filter size determines the number of values to

average. Bit 8 and Bit 7 in Control Register 2 (A1, A0) allow the

average of 2, 4, 8, or 16 samples. Only the final averaged result is

written into the results register.

M = 16

A = 8

9

3

11

8

1

12

14

7

10

11

12

13

14

15

16

10

11

12

13

14

15

16

Table 7. Averaging filter Size

A1

A0

Function

0

1

0

1

0

1

Average of 2 middle samples

Average of ± middle samples

Average of 8 middle samples

Average of 16 samples

Figure 27. Median and Averaging Filter Example

Rev. 0 | Page 16 of 36

AD7879

AUX/VBAT/GPIO PIN

Pin 1A (AUX/VBAT/GPIO) on the AD7879 can be programmed

as either an auxiliary input to the ADC, as a battery monitoring

input, or as a general-purpose digital input/output. To select the

auxiliary measurement, set the ADC channel address to 011.

To select a battery measurement, set the ADC channel address

to 010. To select the GPIO, set Bit 13 in Control Register 2

(Address 0x02) to 1.

LIMIT COMPARISON

The AUX measurement and the battery measurement can

be compared with high and low limits stored on-chip. An

out-of-limit result generates an alarm output at the

INT

PENIRQ INT DAV INT

(

/

) provided the

function is enabled.

The high limit for both channels is stored in Register 0x04,

while the low limit is stored in Register 0x05.

AUXILIARY INPUT

After a measurement from either AUX or VBAT is taken, it

is compared with the high and low limits. The out-of-limit

comparison sets a status bit in Control Register 3. There are

separate status bits for both the high and low limits to indicate

which limit was exceeded. The interrupt sources can be masked

by clearing the corresponding enable bit in this register.

The AD7879 has an auxiliary analog input, AUX. When selected,

the signal on the AUX pin (AUX/VBAT/GPIO) is connected

directly to the ADC input. This channel has a full-scale input

range from 0 V to V_CC. The ADC channel addresses for AUX is

011, and the result is stored in Register 0x0C.

BATTERY INPUT

GPIO

The AD7879 can monitor battery voltages from 0.5 V to 5 V

when the BAT measurement is selected. Figure 28 shows a block

diagram of a battery voltage monitored through the VBAT pin.

The voltage to the V_CCpin (V_CC/REF) of the AD7879 is

maintained at the desired supply voltage via the dc-to-dc

regulator while the input to the regulator is monitored. This

voltage on VBAT is divided down by 4 internally, so that a 5 V

battery voltage is presented to the ADC as 1.25 V. To conserve

power, the divider circuit is on only during the sampling of a

voltage on VBAT. Note that the possible maximum input is 5 V.

The AD7879 has one general-purpose logic input/output pin,

GPIO (AUX/VBAT/GPIO). To enable the GPIO, set Bit 13 in

Control Register 2 to 1. If this bit it 0, then the AUX/VBAT

function is active on the pin. The other GPIO configuration bits

have no effect, if the GPIO is not enabled.

The GPIO data bit is located in Bit 12 of the Control Register 2.

Direction (Bit 11, Control Register2, Address 0x02)

Bit 11 sets the direction of the GPIO pin (AUX/VBAT/GPIO).

When GPIO DIR = 0, the pin is an output. Setting or clearing

bits in the GPIO data bit (Register 0x02[12]) outputs a value on

the GPIO pin.

The VBAT input is ADC Channel 010, and the result is stored

in Register 0x0C.

When GPIO DIR = 1, the pin is an input. An input value on the

GPIO pin sets or clears the GPIO data bit (Register 0x02[12]).

GPIO data register bits are read-only when GPIO DIR = 1.

DC-TO-DC

CONVERTER

BATTERY

0.5V TO 5V

V

CC

VBAT

12kΩ

Polarity (Bit 10, Control Register 2, Address 0x02)

SW

0.125V TO 1.25V

When GPIO POL = 0, the GPIO pin is active low. When GPIO

POL = 1, the GPIO pin is active high. How this bit affects the

GPIO operation also depends on the GPIO DIR bit.

ADC

4kΩ

If GPIO POL = 1 and GPIO DIR = 1, a 1 at the input pin sets

the corresponding GPIO data register bit to 1. A 0 at the input

pin clears the corresponding GPIO data bit to 0.

Figure 28. Block Diagram of Battery Measurement Circuit

The maximum battery voltage that the AD7879 can measure

changes when a different reference voltage is used. The maxi-

mum voltage that is measurable is V_CC× 4 because this voltage

gives a full-scale output from the ADC. The battery voltage can

be calculated using the following formula:

If GPIO POL = 1 and GPIO DIR = 0, a 1 in the GPIO data

register bit puts a 1 on the corresponding GPIO output pin. A 0

in the GPIO data register bit puts a 0 on the GPIO output pin.

If GPIO POL = 0 and GPIO DIR = 1, a 1 at the input pin sets

the corresponding GPIO data bit to 0. A 0 at the input pin clears

the corresponding GPIO data bit to 1.

V

_BAT(V) = [(Register Value) × V_CC× 4]/4095

If GPIO POL = 0 and GPIO DIR = 0, a 1 in the GPIO data

register bit puts a 0 on the corresponding GPIO output pin. A 0

in the GPIO data register bit puts a 1 on the GPIO output pin.

Rev. 0 | Page 17 of 36

AD7879

GPIO Interrupt Enable (Bit 12, Control Register 3,

Address 0x03)

INT

is asserted if the GPIO data register bit is set when the

INT

GPIO is configured as an input, provided that

is enabled.

INT

The GPIO pin can operate as an interrupt source to trigger the

is triggered only when the GPIO is configured as an input,

that is, when GPIO DIR = 1.

INT

output. This is controlled by Bit 12 in Control Register 3.

If the GPIO ALERT interrupt enable = 1, the GPIO can trigger

INT INT

is clear only when the GPIO signal or the GPIO enable

changes.

. If this bit = 0, the GPIO cannot trigger

.

Rev. 0 | Page 18 of 36

AD7879

REGISTER MAP

Table 9. Register Table

Default

Value

Address¹Name

Description

Type

R/W

0x00

0x01

Unused

0x0000

Control Register 1

PENIRQ enable, channel selection for manual selection, ADC mode,

acquisition time, and conversion timer

0x02

0x03

Control Register 2

Control Register 3

ADC power management, GPIO control, pen interrupt, averaging,

median filter, software reset, and FCD

0x±0±0

R/W

Status of high/low limit comparisons for TEMP, AUX/VBAT and enable bits to 0x0000

allow them to become interrupts; channel selection for slave/master mode

0x0±

0x05

0x06

0x07

0x08

0x09

0x0A

0x0B

0x0C

0x0D

0x0E

AUX/VBAT high limit

AUX/VBAT low limit

TEMP high limit

TEMP low limit

X+

Y+

X+ (Z1)

Y− (Z2)

AUX/VBAT

TEMP

AUX/VBAT high limit for comparison

AUX/VBAT low limit for comparison

TEMP high limit for comparison

0x0000

R/W

R

TEMP low limit for comparison

X+ measurement for Y position

Y+ measurement for X position

X+ measurement for touch pressure calculation (Z1)

Y− measurement for touch pressure calculation (Z2)

AUX/VBAT measurement

Temperature conversion Measurement

R

Revision and device ID Revision and device ID

0x0379 (AD7879-1)

0x037A (AD7879)

¹Do not write to addresses outside the register map.

Rev. 0 | Page 19 of 36

AD7879

DETAILED REGISTER DESCRIPTIONS

All addresses and default values are expressed in hexadecimal.

Table 10. Control Register 1

Data

Bit

Default

Value

Address Name

Description

0x01

Disable PENIRQ 15

Pen interrupt enable.

0x0000

0 = PENIRQ pin is enabled.

1 = PENIRQ is disabled and INT enabled.

CHNL ADD[2:0] 1±:12 ADC Channel address for manual conversion (mode 01).

111 = X+ input (Y position).

110 = Y+ input (X position).

101 = X+ (Z1) input for touch-pressure calculation.

100 = Y− (Z2) input (used for touch-pressure measurement).

011 = AUX input¹.

010 = VBAT input¹.

001 = temperature measurement.

000 = not applicable.

ADC MODE[1:0] 11:10 ADC mode.

00 = no conversion.

01 = single conversion².

10 = conversion sequence (slave mode)².

11 = conversion sequence (master mode).

ACQ[1:0]

TMR[7:0]

9:8

7:0

ADC acquisition time.

00 = ± clock periods (2 μs).

01 = 8 clock periods (± μs).

10 = 16 clock periods (8 μs).

11 = 32 clock periods (16 μs).

Note that the acquisition time does not apply to the temperature sensor channels; the

temperature channel has a constant settling time of 16 ꢀs.

Conversion interval timer.

Starts at 550 μs and continues to 9.±±0 ms in steps of 35 μs.

Note that in slave mode, the conversion interval timer starts to count as soon as the

conversion sequence is finished; in master mode, it starts to count again only if the screen

remains touched. If the screen is released, the timer stops counting and, on the next screen

touch, a conversion starts immediately.

¹If GPIO is enabled, AUX and VBAT are both ignored. If AUX and VBAT are both selected, and GPIO is disabled, AUX is ignored, and VBAT is measured.

²Note that these settings clear to 00 at the end of the conversion sequence if the conversion interval timer bits in Control Register 1 (0x01) Bits 7:0 = 0x00h at the end of

the conversion sequence.

Rev. 0 | Page 20 of 36

AD7879

Table 11. Control Register 2

Data

Bit

Default

Value

Address Name

Description

0x02

PM[1:0]

15:1±

ADC power management.

0x±0±0

00 = full shutdown, the ADC, oscillator, BIAS, and temperature sensor are all powered down.

01 = analog blocks to be powered down depend on the ADC mode.

If ADC mode is master mode; the ADC, oscillator, BIAS, and temperature sensor are powered

down and must wake up when the user touches the screen.

If ADC mode is slave mode, the ADC and temperature sensor are powered down while not

being used. They wake up automatically when required. The oscillator and BIAS are powered

up because they are needed to measure time. This also applies to the single conversion mode.

10 = ADC, BIAS, the oscillator is powered up continuously, irrespective of ADC mode.

11 = as 01.

GPIO EN

13

GPIO enable.

0 = AUX/VBAT channel active.

1 = GPIO enabled on AUX/VBAT/GPIO.

GPIO data bit.

GPIO DAT 12

GPIO DIR 11

GPIO direction.

0 = output.

1 = input.

GPIO POL 10

GPIO polarity.

0 = the GPIO pin is active low.

1 = the GPIO pin is active high.

SER/DFR.

SER/DFR

A[1:0]

9

Selects normal (single-ended) or conversion.

0 = ratiometric (differential).

1 = normal (single-ended).

ADC averaging.

8:7

00 = 2 middle values averaged (1 measurement when median filter does not operate).

01 = ± middle values averaged.

10 = 8 middle values averaged.

11 = 16 values averaged.

M[1:0]

6:5

Median filter size.

00 = median filter does not operate.

01 = ± measurements.

10 = 8 measurements.

11 = 16 measurements.

SW/RST

±

Software reset; digital part is reset when this bit is set.

ADC first conversion delay¹.

Starts at 128 μs and goes all the way to ±.096 ms in steps of 128 μs.

FCD[3:0]

3:0

¹This delay occurs before conversion of the X and Y coordinate channels (including Z1 and Z2) to allow for screen settling and before the first conversion to allow the

ADC to power up.

Rev. 0 | Page 21 of 36

AD7879

Table 12. Control Register 3

Data

Bit

Default

Value

Address Name

Description

0x03

TEMP MASK

15

1±

13

TEMP mask bit

0x0000

0 = temperature measurement is allowed to cause interrupt

1 = temperature measurement is not allowed to cause interrupt

AUX/VBAT mask bit

AUX/VBAT

MASK

0 = AUX/VBAT measurement is allowed to cause interrupt

1 = AUX/VBAT measurement is not allowed to cause interrupt

DAV/INT mode select

INT MODE

0 = enable DAV mode

1 = enable INT mode

Note that this bit overrides any mask bits associated with individual channels

GPIO interrupt enable

GPIO ALERT

12

0 = GPIO can cause an alert on the INT output

1 = mask GPIO from causing an alert on the INT output

1 = AUX/VBAT below low limit

AUX/VBAT LOW 11

AUX/VBAT HIGH 10

1 = AUX/VBAT above high limit

TEMP LOW

TEMP HIGH

X+

9

8

7

6

5

±

3

2

1

0

1 = TEMP below low limit

1 = TEMP above high limit

1 = include measurement of Y position (X+ input)

1 = include measurement of X position (Y+ input)

1 = include Z1 touch pressure measurement (X+ input)

1 = include measurement of Z2 touch pressure measurement (Y− input)

1 = include measurement of AUX channel¹

1 = include measurement of battery monitor (VBAT)¹

1 = include temperature measurement

Unused

Y+

Z1

Z2

AUX

VBAT

TEMP

Not used

¹If GPIO is enabled, AUX and VBAT are both ignored. If AUX and VBAT are both selected, and GPIO is disabled, AUX is ignored, and VBAT is measured.

Table 13. Limit Registers

Address

Data Bit

Description

Default Value

0x0000

0x0±

0x05

0x06

0x07

15:0

User-programmable AUX/VBAT high limit register

User-programmable AUX/VBAT low limit register

User-programmable TEMP high limit register

User-programmable TEMP low limit register

Rev. 0 | Page 22 of 36

AD7879

Table 14. Measurement Result Registers

Address

Data Bit

Description

Default Value

0x0000

0x08

0x09

0x0A

0x0B

0x0C

15:0

Measured X+ input with Y excitation (Y position)

Measured Y+ input with X excitation (X position)

Measured X+ input with X− and Y+ excitation (touch-pressure calculation Z1)

Measured Y− input with X− and Y+ excitation (touch-pressure calculation Z2)

AUX/VBAT voltage measurement

15:0

0x0000

0x0D

15:0

Temperature conversion measurement

0x0000

Table 15. Revision/Device ID Register

Address

Data Bit

15:12

11:8

Description

Default Value

0x0E

Unused

Revision and device ID bits

Device ID

0x0379 (AD7879-1)

0x037A (AD7879)

7:0

Rev. 0 | Page 23 of 36

AD7879

CONTROL REGISTERS

15

0

DIS

CHNL CHNL CHNL ADC

ADC

ACQ1 ACQ0 TMR7 TMR6 TMR5 TMR4 TMR3 TMR2 TMR1 TMR0

PENIRQ ADD2 ADD1 ADD0 MODE1 MODE0

Figure 29. Control Register 1

CONTROL REGISTER 1

ADC Mode (Control Register 1, Bits[11:10])

Control Register 1 (Address 0x01) contains the ADC channel

address and the ADC mode bits. It sets the acquisition time and

the timer. It also contains a bit to disable the pen interrupt.

Control Register 1 should always be the last register programmed

prior to starting conversions. Its power-on default value is

0x0000. To change any parameter after conversion has begun,

the part should first be put into Mode 00. Make the changes;

then reprogram Control Register 1, ensuring that it is always the

last register programmed before conversions begin.

The mode bits select the operating mode of the ADC. The

AD7879 has three operating modes. These are selected by

writing to the mode bits in Control Register 1. If the mode

bits are 00, no conversion is performed.

Table 18. Control Register 1 Mode Selection

ADC

MODE1 MODE0 Function

ADC

0

1

Do not convert (default)

Single-channel conversion; the AD7879 is

in slave mode

Timer (Control Register 1, Bits[7:0])

1

0

1

Sequence 0; the AD7879 is in slave mode

Sequence 1; the AD7879 is in master mode

The TMR bits in Control Register 1 enable the ADC to repeat-

edly perform a conversion or to perform a conversion sequence

only once or at intervals of 35 μs from 550 μs up to 9.440 ms. In

slave mode, the timer starts as soon as the conversion sequence

is finished. In master mode, the timer starts at the end of a

conversion sequence only if the screen remains touched. If the

touch is released at any stage, then the timer stops. The next

time the screen is touched, a conversion sequence immediately

begins.

If the mode bits are 01, a single conversion is performed on

the channel selected by writing to the channel bits of Control

Register 1 (Bit 12 to Bit 14). At the end of the conversion, if the

TMR bits in Control Register 1 are set to 00000000, the mode

bits revert to 00 and the ADC returns to no convert mode until

a new conversion is initiated by the host. Setting the TMR bits

to a value other than 00000000 causes the conversion to be

repeated.

Table 16. Control Register 1 Timer Selection

TMR

Function

The AD7879 can also be programmed to automatically convert

a sequence of selected channels. The two modes for this type of

conversion are slave mode and master mode.

00000000

00000001

00000010

00000011

…

Convert one time only (default)

Every 550 μs

Every 585 μs

Every 620 μs

…

For slave mode operation, the channels to be digitized are selected

by setting the corresponding bits in Control Register 3. Conver-

sion is initiated by writing 10b to the mode bits of Control

Register 1. The ADC then digitizes the selected channels and

stores the results in the corresponding results registers. At the

end of the conversion, if the TMR bits in Control Register 1 are

set to 00000000, the mode bits revert to 00 and the ADC returns

to no convert mode until a new conversion is initiated by the

host. Setting the TMR bits to a code other than 00000000 causes

the conversion sequence to be repeated.

11111101

11111110

11111111

Every 9.370 ms

Every 9.±05 ms

Every 9.±±0 ms

Acquisition Time (Control Register 1, Bits[9:8])

The ACQ bits in Control Register 1 allow the selection of

acquisition times for the ADC of 2 μs (default), 4 μs, 8 μs,

or 16 μs. The user can program the ADC with an acquisition

time suitable for the type of signal being sampled. For example,

signals with large RC time constants can require longer acquisi-

tion times.

For master mode operation, the channels to be digitized are

written to the Control Register 3. Master mode is then selected

by writing 11 to the mode bits in Control Register 1. In this

mode, the wake-up on touch feature is active; therefore, conver-

sion does not immediately begin. The AD7879 waits until the

screen is touched before beginning the sequence of conversions.

The ADC then digitizes the selected channels; and the results

are written to the result registers. The AD7879 waits for the

screen to be touched again, or for a timer event if the screen

remains touched, before beginning another sequence of

conversions.

Table 17. Acquisition Time Selection

ACQ1

ACQ0

Function

0

1

0

1

0

1

± clock periods (2 μs)

8 clock periods (± μs)

16 clock periods (8 μs)

32 clock periods (16 μs)

Rev. 0 | Page 2± of 36

AD7879

For both single-channel and sequential conversion, a normal

ADC Channel (Control Register 1 Bits[14:12])

DFR

conversion (single-ended) is selected by clearing the SER/

bit in Control Register 2 (Bit 9). Ratiometric (differential)

The ADC channel is selected by Bits[14:12] of Control Register 1

(CHNL ADD2 to CHNL ADD0). A complete list of channel

addresses is given in Table 19.

DFR

conversion is selected by setting the SER/

bit.

Enable (Control Register 1, Bit 15)

The AD7879 has a dual function output that performs as

PENIRQ INT

PENIRQ

For Mode 0 (single-channel) conversion, the channel is selected

by writing the appropriate CHNL ADD2 to CHNL ADD0 code

to Control Register 1.

or

depending on the pen interrupt enable bit

(Bit 15 of Control Register 1). When this bit is set to 0, the

pin is working as a pen interrupt and it goes low whenever the

screen is touched. When the pen interrupt enable bit is set to 1,

For sequential channel conversion, channels to be converted are

selected by setting bits corresponding to the channel number in

the Control Register 3 for slave and master mode sequencing.

INT

the pin interrupt request is disabled and the pin functions as

.

Table 19. Codes for Selecting Input Channel and Normal or Ratiometric Conversion

SER/DFR

Channel

CHNL ADD[2:0] Analog Input

X Switches

Y Switches

+REF

Y+

X+

Y+

V_CC

−REF

Y−

X−

GND

0

1

2

3

±

5

6

0

1

1 1 1

1 1 0

1 0 1

1 0 0

0 1 1

0 1 0

0 0 1

0 0 0

1 1 1

1 1 0

1 0 1

1 0 0

0 1 1

0 1 0

0 0 1

0 0 0

X+ (Y position)

Y+ (X position)

X+ (Z1 touch pressure)

Y− (Z2 touch pressure)

AUX

Off

On

Off

X+ off, X− on

Off

Y+ on, Y− off

Off

VBAT

TEMP

Invalid address

7

8

9

12

13

1±

15

X+ (Y position)

Y+ (X position)

X+ (Z1 touch pressure)

Y− (Z2 touch pressure)

AUX

Off

On

Off

On

Off

V_CC

GND

VBAT

TEMP

Invalid address

Rev. 0 | Page 25 of 36

AD7879

15

PM1 PM0

0

GPIO GPIO GPIO GPIO SER/

EN DAT DIR POL DFR

SW/

RST

AVG1 AVG0 MED1 MED0

FCD3 FCD2 FCD1 FCD0

Figure 30. Control Register 2

Power Management (Control Register 2, Bits[15:14])

CONTROL REGISTER 2

The power management (PM) bits in Control Register 2 allow

the power management features of the ADC to be programmed.

If the PM bits are 00, the ADC is permanently powered down.

This overrides any setting of the mode bits in Control Register 1.

If the PM bits are 01, both the ADC and the reference power

down when the ADC is not converting. If the PM bits are 10 or

11, the analog blocks to be powered down depend on the ADC

mode settings. Power management overrides the ADC modes.

Control Register 2 (Address 0x02) contains the power

DFR

management bits, the GPIO settings, the SER/

bit

(to choose single or differential methods of touch screen

measurement), the averaging and median filter settings, a bit

that allows resetting the part, and the first conversion delay

bits. Its power-on default value is 0x4040. See the Detailed

Register Descriptions section for more information on the

control registers.

Table 21. Power Management Selection

PM1 PM0 Function

First Conversion Delay (Control Register 2, Bits[3:0])

The first conversion delay (FCD) bits in Control Register 2

program a delay from 128 μs (default) up to 4.096 ms before

the first conversion to allow the ADC time to power up. This

delay also occurs before conversion of the X and Y coordinate

channels to allow extra time for screen settling, and after the

0

Full shutdown; ADC, oscillator, BIAS, and

temperature sensor are all turned off. The only

way of coming out of this mode is to write to the

part over the serial interface and change the PM

bits. This setting overrides any other setting on

the part, including the ADC mode bits.

PENIRQ

last conversion in a sequence to precharge

.

0

1

The analog blocks to be powered down depend

on the ADC mode settings. If the ADC mode is set

to master mode, the ADC, BIAS, temperature

sensor, and oscillator are powered down and

must wake up when the user touches the screen.

If the ADC mode is set to slave mode, the ADC

and the TEMP sensor are powered down while

not being used. They wake up automatically

when required. The oscillator and BIAS are

powered up because they are needed to measure

time. This also applies to the single-conversion

mode.

Table 20. First Conversion Delay Selection

FCD

Function

128 μs

256 μs

38± μs

512 μs

6±0 μs

768 μs

896 μs

1.02± ms

1.152 ms

1.280 ms

1.536 ms

1.792 ms

2.0±8 ms

2.560 ms

3.58± ms

±.096 ms

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

1

0

1

ADC, BIAS, and the oscillator are powered up

continuously irrespective of ADC mode.

As 01.

Rev. 0 | Page 26 of 36

AD7879

15

TEMP

0

AUX/

VBAT

MASK

AUX/ AUX/

VBAT VBAT

LOW HIGH

INT GPIO

MODE ALERT

TEMP TEMP

LOW HIGH

NOT

USED

X+

Y+

Z1

Z2

AUX VBAT TEMP

MASK

Figure 31. Control Register 3

CONTROL REGISTER 3

00

IDLE

ADC MODE?

Control Register 3 (Address 0x03) includes the interrupt

register (Bits[15:8]) and Control Register 3 (Bits[7:0]).

01

10

11

Sequencer

MASTER MODE

SINGLE

CONVERSION

SLAVE MODE

The sequencer bits control which channels are converted during

a conversion sequence in both slave and master mode.

WAIT FOR

FIRST TOUCH

CONVERSION

SEQUENCE

To include a measurement in a sequence, the relevant bit must

be set in the sequence. Setting Bit 7 includes a measurement on

the X+ channel (Y position). Setting Bit 6 includes a measure-

ment on the Y+ channel (X position), and so on.

CONVERSION

SEQUENCE

YES

TIMER = 00?

NO

SCREEN

Figure 32 illustrates the correspondence between the bits in

Control Register 3 and the various measurements. Bit 0

is not used.

TOUCHED?

START TIMER

YES

WAIT FOR TIMER

YES

TIMER = 00?

NO

START TIMER

WAIT FOR TIMER

NO

SCREEN

TOUCHED?

YES

Figure 32. Conversion Modes

Rev. 0 | Page 27 of 36

AD7879

START OF

CONVERSION

SEQUENCE

INT

is also reset if a new conver-

resets

sion is started by the AD7879 because the timer expired. The

INT

to a high condition.

SET CHANNEL

host should read the results registers only when

ensure correct operation of the

is low. To

mode when using the SPI

YES

FCD

REQ’D?

DAV

interface it is necessary to write 0x0000 to Register 0x81 after a

set of register reads. This clears the internal data read signal.

START FCD

TIMER

NO

WAIT FOR

FCD

INT

CONV_START = 1

t_CONV

AD7879

STATUS

SETUP

BY HOST

ADC

NEW DATA HOST READS

RESULTS

IDLE

CONVERTING AVAILABLE

IDLE

START ACQUIST TIMER

AND WAIT FOR

INT

Figure 34. Operation of

Output

ACQUISITION

When the on-board timer is programmed to perform automatic

conversions, limited time is available to the host to read the

results registers before another sequence of conversions begins.

CONV_START = 0

COMPARE NEW

READING

CONVERT: WAIT FOR

DATA_READY

INT

The

signal is reset high when the timer expires, and the

INT

host should not access the results registers while

is high.

SHIFT

READINGS

INT

—Out of Limits

YES

MAV FILTER

ENABLED

INT

The

pin operates as an alarm or interrupt output when

NO

Bit 13 in Register 0x03 is set to 1. The output goes low if any

one of the interrupt sources is asserted. The results of high and

low limit comparisons on the AUX, VBAT, and TEMP channels

are interrupt sources. An out-of-limit comparison sets a status

bit in the interrupt register. There are separate status bits for

both the high and low limits on each channel to indicate which

limit was exceeded. The interrupt sources can be masked by

clearing the corresponding enable bit in this register. There is

one enable bit per channel.

MEDIAN

WINDOW

FINISHED?

NO

RUN

AVERAGER

NO FCD

REQ’D

YES

AVG

FINISHED?

NO

RUN FILTER

AVERAGER

YES

TXFER DATA

TO REG. MAP

LIMIT

COMPARISON

PENIRQ

— Pen Interrupt

YES

OUT-OF-

LIMIT?

SET ALERT AND

INTERRUPT

NOTE THAT CONVERSION

SEQUENCE MAY BE 1

CHANNEL ONLY (MODE 01).

PENIRQ

The pen interrupt request output (

ever the screen is touched and the

0 (Control Register 1, Bit 15). When

) goes low when-

enable bit is set to

NO

EOCS

END OF

YES

enable is set to 1,

CONVERSION

SEQUENCE

?

the pen interrupt request output is disabled.

The pen interrupt equivalent output circuitry is outlined in

Figure 35. This is a digital logic output with an internal 50 kΩ

pull-up resistor, which means it does not need an external pull-

Figure 33. Conversion Sequence

INTERRUPTS

PENIRQ

up. The

output idles high, and the

circuitry

INT

The AD7879 has a dual function interrupt output,

, as well

output can be con-

is always enabled in master mode (ADC mode = 11), except

during conversions.

PENIRQ INT

as a pen down interrupt,

. The

figured as a data available interrupt, as an out of limit interrupt, or

as a GPIO interrupt.

V

CC

Y+

V

CC

50kΩ

INT

—Data Available

PENIRQ

X+

The behavior of the interrupt output is controlled by Bit 13 in

INT

X–

TOUCH

SCREEN

Control Register 3. In default mode,

operates as a data

PENIRQ

ENABLE

available interrupt (Bit 13 = 0). When the AD7879 has finished

a conversion or a conversion sequence, the interrupt asserts to

let the host know that new ADC data is available in the result

registers.

Y–

PENIRQ

Figure 35.

Output Equivalent Circuit

INT

While the ADC is idle or is converting,

ADC has finished converting and new data has been written to

INT

is high. When the

the results registers,

goes low. Reading the result registers

Rev. 0 | Page 28 of 36

AD7879

PENIRQ

When the screen is touched,

an interrupt request to the host. When the screen touch ends,

PENIRQ

goes low. This generates

SYNCHRONIZING THE AD7879 TO THE HOST CPU

The two recommended methods for synchronizing the AD7879

to its host CPU are slave mode (in which the mode bits can be

either 01b or 10b) and master mode (in which the mode bits

are 11b).

and if the ADC is idle,

PENIRQ

immediately goes high. If the

goes high when the ADC becomes

operation for these two conditions is shown

ADC is converting,

PENIRQ

idle. The

in Figure 36.

PENIRQ

In master mode (ADC mode bits = 11b),

be used as an interrupt to the host. When

mode can

goes low to

NOT

TOUCHED

NOT

SCREEN

PENIRQ

TOUCHED

indicate that the screen has been touched, the host is awakened.

The host can then program the AD7879 to convert in any mode

and read the results after the conversions are completed.

PENIRQ

DETECTS

TOUCH

PENIRQ

DETECTS

RELEASE

INT DAV

or

In master mode,

can also be used as an interrupt

to the host. The host should first define a conversion sequence

in Control Register 3, initialize the AD7879 in Mode 11b and

ADC

STATUS

ADC IDLE

RELEASE NOT

DETECTED

NOT

TOUCHED

NOT

TOUCHED

INT DAV

enable

or

using Bit 15 in Control Register 1 and Bit 13

SCREEN

PENIRQ

TOUCHED

in Control Register 3. The host can then enter sleep mode to

conserve power. The wake-up on-touch feature of the AD7879

is active in this mode; therefore, when the screen is touched,

the programmed sequence of conversions automatically begins.

PENIRQ

DETECTS

TOUCH

PENIRQ

DETECTS

RELEASE

ADC

CONVERTING

ADC

STATUS

ADC IDLE

INT DAV

When the

or

signal asserts, the host reads the new

PENIRQ

Figure 36.

Operation for ADC Idle and ADC Converting

data available in the AD7879 results registers and returns to

sleep mode. This method can significantly reduce the load on the

host.

PENIRQ

Figure 37 shows how the

up on-touch circuit and the

circuit is enabled. The wake-

PENIRQ

circuit are enabled only in

PENIRQ

master mode (ADC mode = 11). In slave mode, the

DAV INT DAV INT

signals.

/

pin can output only

or

YES

ADC MODE = 11?

MASTER MODE

ENABLE

PENIRQ

DETECTION

CIRCUIT

ENABLE

WAKE UP

ON TOUCH

TOUCH SCREEN TOUCHED

TO THE DIGITAL CORE

TOUCH SCREEN TOUCHED

0

1

DAV

PENIRQ/INT/DAV PIN

(END OF CONVERSION SEQUENCE)

0

1

INT/DAV/GPIO ALERT

INT

(GPIO ALERT/OUT OF LIMITS)

CONTROL REGISTER 1

BIT 15

CONTROL REGISTER 3

BIT 13

Figure 37. Master Mode Operation

Rev. 0 | Page 29 of 36

AD7879

SERIAL INTERFACE

The AD7879 is available with an serial peripheral interface

(SPI). The AD7879-1 is available with an I²C®-compatible

interface. Both parts are the same, with the exception of the

serial interface. It is recommended not to write to addresses

outside the register map.

Bits[15:11] of the command word must be set to 11100 to

successfully begin a bus transaction.

Bit 10 is the read/write bit; 1 indicates a read, and 0 indicates

a write.

Bits[9:0] contain the target register address. When reading or

writing to more than one register, this address indicates the

address of the first register to be written to or read from.

SPI INTERFACE

The AD7879 has a 4-wire SPI. The SPI has a data input pin

(DIN) for inputting data to the device, a data output pin

(DOUT) for reading data back from the device, and a data

clock pin (SCL) for clocking data into and out of the device.

Writing Data

Data is written to the AD7879 in 16-bit words. The first word

written to the device is the command word, with the read/write

bit set to 0. The master then supplies the 16-bit input data-word

on the DIN line. The AD7879 clocks the data into the register

addressed in the command word. If there is more than one word

of data to be clocked in, the AD7879 automatically increments

the address pointer and clocks the next data-word into the

following register.

CS

A chip select pin ( ) enables or disables the serial interface.

CS

is required for correct operation of the SPI interface. Data

is clocked out of the AD7879 on the negative edge of SCL and

data is clocked into the device on the positive edge of SCL.

SPI Command Word

All data transactions on the SPI bus begin with the master

CS

taking

from high to low and sending out the command

The AD7879 continues to clock in data on the SDA line until

word. This indicates to the AD7879 whether the transaction

is a read or a write, and gives the address of the register from

which to begin the data transfer. The bit map in Table 22 shows

the SPI command word.

CS

either the master finishes the write transition by pulling

high, or until the address pointer reaches its maximum value.

The AD7879 address pointer does not wrap around. When it

reaches its maximum value, any data provided by the master

on the DIN line is ignored by the AD7879.

Table 22.

MSB

15

1

LSB

14 13 12 11 10

9:0

1

0

R/W

Register address

16-BIT COMMAND WORD

ENABLE WORD

R/W

REGISTER ADDRESS

16-BIT DATA

CW

15

CW

14

CW

13

CW

12

CW

11

CW

10

CW

9

CW

7

CW

6

CW

5

CW

4

CW

2

CW

1

CW

0

CW

8

CW

3

DIN

D15 D14 D13

D2

D1

D0

t₂

t₄

t₅

SCL

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

30

31

t₈

32

t₁

t₃

CS

NOTES

1. DATA BITS ARE LATCHED ON SCL RISING EDGES. SCL CAN IDLE HIGH OR LOW BETWEEN WRITE OPERATIONS.

2. ALL 32 BITS MUST BE WRITTEN: 16 BITS FOR CONTROL WORD AND 16 BITS FOR DATA.

3. 16-BIT COMMAND WORD SETTINGS FOR SERIAL WRITE OPERATION:

CW[15:11] = 11100 (ENABLE WORD)

CW[10] = 0 (R/W)

CW[9:0] = [AD9, AD8, AD7, AD6, AD5, AD4, AD3, AD2, AD1, AD0] (10-BIT MSB JUSTIFIED REGISTER ADDRESS)

Figure 38. Single Register Write, SPI Timing

Rev. 0 | Page 30 of 36

AD7879

16-BIT COMMAND WORD

R/W STARTING REGISTER ADDRESS

DATA FOR STARTING

REGISTER ADDRESS

DATA FOR NEXT

REGISTER ADDRESS

ENABLE WORD

CW CW CW CW CW CW CW CW CW CW

15 14 13 12 11 10

CW CW

CW

3

CW CW CW

DIN

D15 D14

D1

D0

D15

D1

D0

D14

D15

49

9

8

7

6

5

4

2

1

0

SCL

CS

1

2

3

4

11

12

13

14

5

6

7

8

9

10

15

16

17

18

31

32

33

34

47

48

NOTES

1. MULTIPLE SEQUENTIAL REGISTERS CAN BE LOADED CONTINUOUSLY.

2. THE FIRST (LOWEST ADDRESS) REGISTER ADDRESS IS WRITTEN, FOLLOWED BY MULTIPLE 16-BIT DATA-WORDS.

3. THE ADDRESS AUTOMATICALLY INCREMENTS WITH EACH 16-BIT DATA-WORD (ALL 16 BITS MUST BE WRITTEN).

4. CS IS HELD LOW UNTIL THE LAST DESIRED REGISTER HAS BEEN LOADED.

5. 16-BIT COMMAND WORD SETTINGS FOR SEQUENTIAL WRITE OPERATION:

CW[15:11] = 11100 (ENABLE WORD)

CW[10] = 0 (R/W)

CW[9:0] = [AD9, AD8, AD7, AD6, AD5, AD4, AD3, AD2, AD1, AD0] (STARTING MSB JUSTIFIED REGISTER ADDRESS)

Figure 39. Sequential Register Write SPI Timing

`

16-BIT COMMAND WORD

ENABLE WORD

R/W

REGISTER ADDRESS

CW

15

CW

14

CW

13

CW

12

CW

11

CW

10

CW

9

CW

7

CW

6

CW

5

CW

4

CW

3

CW

2

CW

1

CW

0

CW

8

DIN

X

t₂

t₄

t₅

SCL

CS

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

30

31

32

t₁

t₃

t₈

t₆

D15 D14 D13

16-BIT READBACK DATA

t₇

DOUT

D2

D1

D0

XXX

XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX

NOTES

1. DATA BITS ARE LATCHED ON SCL RISING EDGES. SCL CAN IDLE HIGH OR LOW BETWEEN WRITE OPERATIONS.

2. THE 16-BIT CONTROL WORD MUST BE WRITTEN ON SDI: 5 BITS FOR ENABLE WORD, 1 BIT FOR R/W, AND 10 BITS FOR REGISTER ADDRESS.

3. THE REGISTER DATA IS READ BACK ON THE DOUT PIN.

4. X DENOTES DON’T CARE.

5. XXX DENOTES HIGH IMPEDANCE THREE-STATE OUTPUT.

6. CS IS HELD LOW UNTIL ALL REGISTER BITS HAVE BEEN READ BACK.

7. 16-BIT COMMAND WORD SETTINGS FOR SINGLE READBACK OPERATION:

CW[15:11] = 11100 (ENABLE WORD)

CW[10] = 1 (R/W)

CW[9:0] = [AD9, AD8, AD7, AD6, AD5, AD4, AD3, AD2, AD1, AD0] (10-BIT MSB JUSTIFIED REGISTER ADDRESS)

Figure 40. Single Register Read Back SPI Timing

Reading Data

The AD7879 continues to clock out data on the DOUT line

provided the master continues to supply the clock signal on

SCL. The read transaction finishes when the master takes

A read transaction begins when the master writes the command

word to the AD7879 with the read/write bit set to 1. The master

then supplies 16 clock pulses per data-word to be read, and the

AD7879 clocks out data from the addressed register on the SDA

line. The first data-word is clocked out on the first falling edge

of SCL following the command word, as shown in Figure 40.

CS

high. If the AD7879 address pointer reaches its maximum

value, the AD7879 repeatedly clocks out data from the

addressed register. The address pointer does not wrap around.

Rev. 0 | Page 31 of 36

AD7879

16-BIT COMMAND WORD

R/W REGISTER ADDRESS

ENABLE WORD

CW CW CW CW CW CW CW CW CW CW CW CW CW CW CW CW

15 14 13 12 11 10

DIN

X

9

8

7

6

5

4

3

2

1

0

SCL

CS

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

31

32

33

34

47

48

49

DOUT

XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX D15 D14

D1

D0 D15

D1

D0

D14

D15

READBACK DATA FOR

NEXT REGISTER ADDRESS

READBACK DATA FOR

STARTING REGISTER ADDRESS

NOTES

1. MULTIPLE REGISTERS CAN BE READ BACK CONTINUOUSLY.

2. THE 16-BIT CONTROL WORD MUST BE WRITTEN ON SDA: 5 BITS FOR ENABLE WORD, 1 BIT FOR R/W, AND 10 BITS FOR REGISTER ADDRESS.

3. THE ADDRESS AUTOMATICALLY INCREMENTS WITH EACH 16-BIT DATA-WORD BEING READ BACK ON THE SDA PIN.

4. CS IS HELD LOW UNTIL ALL REGISTER BITS HAVE BEEN READ BACK.

5. X DENOTES DON’T CARE.

6. XXX DENOTES HIGH IMPEDANCE THREE-STATE OUTPUT.

7. 16-BIT COMMAND WORD SETTINGS FOR SEQUENTIAL READBACK OPERATION:

CW[15:11] = 11100 (ENABLE WORD)

CW[10] = 1 (R/W)

CW[9:0] = [AD9, AD8, AD7, AD6, AD5, AD4, AD3, AD2, AD1, AD0] (STARTING MSB JUSTIFIED REGISTER ADDRESS)

Figure 41. Sequential Register Read Back SPI Timing

All slave peripherals connected to the serial bus respond to the

start condition and shift in the next eight bits, consisting of a

I²C-COMPATIBLE INTERFACE

The AD7879-1 supports the industry standard 2-wire I²C serial

interface protocol. The two wires associated with the I²C timing are

the SCL and SDA inputs. The SDA is an I/O pin that allows both

register write and register read back operations. The AD7879-1 is

always a slave device on the I²C serial interface bus.

W

7-bit address (MSB first) plus an R/ bit that determines the

direction of the data transfer. The peripheral whose address

corresponds to the transmitted address responds by pulling the

data line low during the ninth clock pulse. This is known as the

acknowledge bit. All other devices on the bus then remain idle

while the selected device waits for data to be read from, or

It has a 7-bit device address, Address 0101 1XX. The lower two

bits are set by tying the ADD0 and ADD1 pins high or low. The

AD7879-1 responds when the master device sends its device

address over the bus. The AD7879-1 cannot initiate data transfers

on the bus.

W

written to it. If the R/ bit is a 0, the master writes to the slave

W

device. If the R/ bit is a 1, the master reads from the slave

device.

Data is sent over the serial bus in a sequence of nine clock

pulses (eight bits of data followed by an acknowledge bit from

the slave device). Transitions on the data line must occur during

the low period of the clock signal and remain stable during the

high period, because a low-to-high transition when the clock

is high can be interpreted as a stop signal. The number of data

bytes transmitted over the serial bus in a single read or write

operation is limited only by what the master and slave devices

can handle.

Table 23. AD7879-1 I²C Device Address

ADD1

ADD0

I²C Address

0101 100

0101 101

0101 110

0101 111

0

1

0

1

0

1

Data Transfer

Data is transferred over the I²C serial interface in 8-bit bytes. The

master initiates a data transfer by establishing a start condition,

defined as a high-to-low transition on the serial data line, SDA,

while the serial clock line, SCL, remains high. This indicates

that an address/data stream follows.

When all data bytes are read or written, a stop condition is

established. A stop condition is defined by a low-to-high

transition on SDA while SCL remains high. If the AD7879

encounters a stop condition, it returns to its idle condition.

Rev. 0 | Page 32 of 36

AD7879

START

AD7879 DEVICE ADDRESS

REGISTER ADDRESS[A7:A0]

SDA

SCL

DEV DEV DEV DEV

DEV DEV

DEV

A2

R/W ACK

A7

A6

A1

A0

A6

A5

A4

A3

A1

A0

t₁

t₃

1

2

3

4

11

16

5

6

7

8

9

10

17

t₂

STOP

START

REGISTER DATA[D15:D8]

ACK D15 D14 D9

REGISTER DATA[D7:D0]

D1

AD7879 DEVICE ADDRESS

DEV DEV DEV

t₈

D8 ACK

t₄

D7

D0

ACK

36

D6

A6

A5

A4

t₆

t₇

t₅

1

2

3

18

19

20

25

26

27

28

29

34

35

37

NOTES

1. A START CONDITION AT THE BEGINNING IS DEFINED AS A HIGH-TO-LOW TRANSITION ON SDA WHILE SCL REMAINS HIGH.

2. A STOP CONDITION AT THE END IS DEFINED AS A LOW-TO-HIGH TRANSITION ON SDA WHILE SCL REMAINS HIGH.

3. 7-BIT DEVICE ADDRESS [DEV A6:DEV A0] = [0 1 0 1 1 X X], WHERE THE Xs ARE DON'T CARE BITS.

4. REGISTER DATA [D15:D8] AND REGISTER DATA [D7:D0] ARE ALWAYS SEPARATED BY A LOW ACK BIT.

Figure 42. Example of I²C Timing for Single Register Write Operation

Writing Data over the I²C Bus

The process of writing to the AD7879-1 over the I²C bus is

shown in Figure 42 and Figure 44. The device address is sent

All registers on the AD7879-1 have 16 bits. Two consecutive

8-bit data bytes are combined and written to the 16-bit registers.

To avoid errors, all writes to the device must contain an even

number of data bytes.

W

over the bus followed by the R/ bit set to 0. This is followed

To finish the transaction, the master generates a stop condition

on SDA, or generates a repeat start condition if the master is to

maintain control of the bus.

Reading Data Over the I²C Bus

by two bytes of data that contain the 10-bit address of the inter-

nal data register to be written. The address is contained in the

8 LSBs of the register address byte. The bit map in Table 24

shows the register address byte.

To read from the AD7879-1, the address pointer register must

first be set to the address of the required internal register. The

master performs a write transaction and writes to the AD7879-1

to set the address pointer. The master then outputs a repeat start

condition to keep control of the bus, or if this is not possible, the

master ends the write transaction with a stop condition. A read

Table 24.

MSB

LSB

7

6

5

4

3

2

1

0

Register Address

Bit ± Bit 3

Bit 7

Bit 6

Bit 5

Bit 2

Bit 1

Bit 0

The third data byte contains the 8 MSBs of the data to be

written to the internal register. The fourth data byte contains

the 8 LSBs of data to be written to the internal register.

W

transaction is initiated, with the R/ bit set to 1.

The AD7879-1 supplies the upper eight bits of data from the

addressed register in the first read back byte, followed by the

lower eight bits in the next byte. This is shown in Figure 43

and Figure 44.

The AD7879-1 address pointer register automatically increments

after each write. This allows the master to sequentially write to all

registers on the AD7879-1 in the same write transaction. However,

the address pointer register does not wrap around after the last

address.

Because the address pointer automatically increases after each

read, the AD7879-1 continues to output readback data until

the master puts a no acknowledge and a stop condition on the

bus. If the address pointer reaches its maximum value, and the

master continues to read from the part, the AD7879-1 repeat-

edly sends data from the last register addressed.

Any data written to the AD7879-1 after the address pointer has

reached its maximum value is discarded.

Rev. 0 | Page 33 of 36

AD7879

START

AD7879-1 DEVICE ADDRESS

REGISTER ADDRESS[A7:A0]

SDA

SCL

DEV DEV DEV DEV DEV DEV DEV

R/W ACK

A7

A6

A1

A0 ACK

A6

A5

A4

A3

A2

A1

A0

t₁

t₃

1

2

3

4

5

6

7

8

9

10

11

16

17

18

t₂

P

AD7879-1 DEVICE ADDRESS

REGISTER DATA[D7:D0]

D1

D6

t₅

30

SR

t₈

AD7879 DEVICE ADDRESS

DEV DEV DEV

DEV DEV

A6 A5

DEV DEV

D7

D0

ACK

37

ACK

R/W

A1

A0

A6

A5

A4

USING

REPEATED

START

t₄

t₆

t₇

1

2

3

25

26

27

28

29

35

36

19

P

20

21

AD7879-1 DEVICE ADDRESS

REGISTER DATA[D7:D0]

D1

P

S

DEV DEV

A6 A5

DEV DEV

D7

D0

ACK

D6

t₅

30

ACK

R/W

A1

A0

SEPARATE

READ AND

WRITE

TRANSACTIONS

t₄

25

26

27

28

29

35

36

37

19

20

21

NOTES

1. A START CONDITION AT THE BEGINNING IS DEFINED AS A HIGH-TO-LOW TRANSITION ON SDA WHILE SCL REMAINS HIGH.

2. A STOP CONDITION AT THE END IS DEFINED AS A LOW-TO-HIGH TRANSITION ON SDA WHILE SCL REMAINS HIGH.

3. THE MASTER GENERATES THE ACK AT THE END OF THE READBACK TO SIGNAL THAT IT DOES NOT WANT ADDITIONAL DATA.

4. 7-BIT DEVICE ADDRESS [DEV A6:DEV A0] = [0 1 0 1 1 X X], WHERE THE TWO LSB Xs ARE DON'T CARE BITS.

5. REGISTER DATA [D15:D8] AND REGISTER DATA [D7:D0] ARE ALWAYS SEPARATED BY A LOW ACK BIT.

6. THE R/W BIT IS SET TO A1 TO INDICATE A READBACK OPERATION.

Figure 43. Example of I²C Timing for Single Register Read Back Operation

WRITE

6-BIT DEVICE

ADDRESS

REGISTER ADDR

[7:0]

WRITE DATA

HIGH BYTE [15:8]

WRITE DATA

LOW BYTE [7:0]

WRITE DATA

HIGH BYTE [15:8]

WRITE DATA

LOW BYTE [7:0]

. . .

S

P

W

READ (USING REPEATED START)

6-BIT DEVICE

ADDRESS

REGISTER ADDR

[7:0]

6-BIT DEVICE

LOW BYTE

READ DATA

ADDRESS

READ DATA

HIGH BYTE [15:8]

READ DATA

HIGH BYTE [15:8]

READ DATA

LOW BYTE [7:0]

. . .

S

R

P

W

READ (WRITE TRANSACTION SETS UP REGISTER ADDRESS)

6-BIT DEVICE

ADDRESS

REGISTER ADDR

[7:0]

6-BIT DEVICE

ADDRESS

READ DATA

HIGH BYTE [15:8]

READ DATA

LOW BYTE [7:0]

READ DATA

HIGH BYTE [15:8]

READ DATA

LOW BYTE [7:0]

. . .

S

P

S

R

P

W

OUTPUT FROM MASTER S = START BIT

W = WRITE BIT

P = STOP BIT

SR = REPEATED START BIT

R = READ BIT

ACK = ACKNOWLEDGE BIT

ACK = NO ACKNOWLEDGE BIT

OUTPUT FROM AD7879

Figure 44. Example of Sequential I²C Write and Read Back Operation

Rev. 0 | Page 3± of 36

AD7879

GROUNDING AND LAYOUT

ance of at least 0.25 mm between the thermal pad and the inner

edges of the land pattern on the PCB. Thermal vias can be

used on the printed circuit board thermal pad to improve thermal

performance of the package. If vias are used, they should be

incorporated in the thermal pad at a 1.2 mm pitch grid. The via

diameter should be between 0.3 mm and 0.33 mm, and the via

barrel should be plated with 1 oz. of copper to plug the via.

For detailed information on grounding and layout considera-

tions for the AD7879, refer to the AN-577 Application Note,

Layout and Grounding Recommendations for Touch Screen

Digitizers.

CHIP SCALE PACKAGES

The lands on the chip scale package (CP-16-10) are rectangular.

The printed circuit board (PCB) pad for these should be 0.1 mm

longer than the package land length, and 0.05 mm wider than

the package land width. Center the land on the pad to maximize

the solder joint size.

Connect the PCB thermal pad to GND.

WLCSP ASSEMBLY CONSIDERATIONS

For detailed information on the WLCSP PCB assembly and

reliability, see the AN-617 Application Note, MicroCSP™ Wafer

Level Chip Scale Package.

The bottom of the chip scale package has a central thermal pad.

The thermal pad on the printed circuit board should be at least

as large as this exposed pad. To avoid shorting, provide a clear-

VOLTAGE

REGULATOR

MAIN

BATTERY

0.1µF

0.1µF TO 10µF

(OPTIONAL)

16

15 14

13

HOST

CS

12

1

2

INT

Y+

NC

X–

PENIRQ/INT/DAV

NC

AD7879

11

SCLK

MISO

MOSI

10

9

3

4

NC

DOUT

TOUCH

SCREEN

5

6

7

8

NC = NO CONNECT

Figure 45. Typical Application Circuit

Rev. 0 | Page 35 of 36

AD7879

OUTLINE DIMENSIONS

0.65

0.59

0.53

1.67

1.61

1.55

SEATING

PLANE

3

2

1

A

B

C

D

0.36

0.32

0.28

BALL 1

IDENTIFIER

2.07

2.01

1.95

TOP VIEW

(BALL SIDE DOWN)

0.50 BSC

BALL PITCH

0.28

0.24

0.20

0.17

0.15

0.13

BOTTOM

VIEW

(BALL SIDE UP)

Figure 46. 12-Ball Wafer Level Chip Scale Package [WLCSP]

(CB-12-1)

Dimensions shown in millimeters

4.00

BSC SQ

0.60 MAX

0.65 BSC

PIN 1

INDICATOR

13

16

1

12

9

PIN 1

INDICATOR

2.50

2.35 SQ

2.20

TOP

VIEW

EXPOSED

3.75

BSC SQ

PAD

(BOTTOM VIEW)

0.50

0.40

0.30

4

8

5

0.25 MIN

0.80 MAX

0.65 TYP

12° MAX

1.95 BSC

0.05 MAX

0.02 NOM

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

1.00

0.85

0.80

0.35

0.30

0.25

0.20 REF

COPLANARITY

0.08

SECTION OF THIS DATA SHEET.

SEATING

PLANE

COMPLIANT TO JEDEC STANDARDS MO-220-VGGC

Figure 47. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

4 mm x 4mm Very Thin Quad

(CP-16-10)

Dimensions shown in millimeters

ORDERING GUIDE

Model

Temperature Range

−±0°C to +85°C

Serial Interface Description

SPI Interface

Package Description

12-Ball WLCSP

16-Lead LFCSP_VQ

12-Ball WLCSP

Package Option

CB-12-1

CP-16-10

CB-12-1

CP-16-10

Branding

T2Y

AD7879ACBZ-RL¹

AD7879ACBZ-500R7¹

AD7879ACPZ-RL¹

AD7879ACPZ-500R7¹

AD7879-1ACBZ-RL¹

AD7879-1ACBZ-500R7¹

AD7879-1ACPZ-RL¹

AD7879-1ACPZ-500R7¹

EVAL-AD7879EBZ¹

EVAL-AD7879-1EBZ¹

SPI Interface

I²C Interface

T0Q

I²C Interface

12-Ball WLCSP

I²C Interface

16-Lead LFCSP_VQ

Evaluation Board

I²C Interface

SPI Interface

I²C Interface

¹Z = RoHS Compliant Part.

registered trademarks are the property of their respective owners.

D07667-0-10/08(0)

Rev. 0 | Page 36 of 36


型号：	EVAL-AD7879EBZ
厂家：	ADI
描述：	Low Voltage Controller for Touch Screens 低电压控制器的触摸屏控制器
文件：	总36页 (文件大小：526K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

EVAL-AD7879EBZ [ADI]

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