EVAL-ADF4113HVEB1Z [ADI]
High Voltage Charge Pump, PLL Synthesizer; 高电压电荷泵， PLL合成器
| 型号： | EVAL-ADF4113HVEB1Z |
| 厂家： | 
ADI |
| 描述： | High Voltage Charge Pump, PLL Synthesizer |
| 文件： | 总20页 (文件大小：489K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
High Voltage
Charge Pump, PLL Synthesizer
ADF4113HV
FEATURES
GENERAL DESCRIPTION
High voltage charge pump (15 V)
2.7 V to 5.5 V power supply
200 MHz to 4.0 GHz frequency range
Pin compatible with ADF4110, ADF4111, ADF4112, ADF4113
ADF4106, and ADF4002 synthesizers
Two selectable charge pump currents
Digital lock detect
The ADF4113HV is an integer-N frequency synthesizer with a
high voltage charge pump (15 V). The synthesizer is designed
for use with voltage controlled oscillators (VCOs) that have
high tuning voltages (up to 15 V). Active loop filters are often
used to achieve high tuning voltages, but the ADF4113HV
charge pump can drive a high voltage VCO directly with a
passive-loop filter. The ADF4113HV can be used to implement
local oscillators in the upconversion and downconversion
sections of wireless receivers and transmitters. It consists of a
low noise digital phase frequency detector (PFD), a precision
high voltage charge pump, a programmable reference divider,
programmable A and B counters, and a dual-modulus prescaler
(P/P + 1).
Power-down mode
Loop filter design possible with ADIsimPLL™
APPLICATIONS
Applications using high voltage VCOs
IF/RF local oscillator (LO) generation in base stations
Point-to-point radio LO generation
Clock for analog-to-digital and digital-to-analog converters
Wireless LANs, PMR
A simple 3-wire interface controls all of the on-chip registers.
The devices operate with a power supply ranging from 2.7 V to
5.5 V and can be powered down when not in use.
Communications test equipment
FUNCTIONAL BLOCK DIAGRAM
AV
DV
V
R
SET
DD
DD
P
CPGND
REFERENCE
14-BIT
R COUNTER
REF
IN
PHASE
CHARGE
PUMP
CP
FREQUENCY
DETECTOR
14
R COUNTER
LATCH
CURRENT
SETTING
LOCK
DETECT
CLK
DATA
LE
24-BIT
INPUT REGISTER
FUNCTION
LATCH
22
A, B COUNTER
LATCH
SD
OUT
HIGH Z
FROM
FUNCTION
LATCH
19
AV
DD
MUX
MUXOUT
13
N = BP + A
SD
13-BIT
B COUNTER
OUT
LOAD
RF
RF
A
B
IN
PRESCALER
P/P + 1
M3 M2 M1
IN
LOAD
6-BIT
A COUNTER
ADF4113HV
6
CE
AGND
DGND
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2007 Analog Devices, Inc. All rights reserved.
ADF4113HV
TABLE OF CONTENTS
Features .............................................................................................. 1
Prescaler (P/P + 1) ........................................................................9
A and B Counters..........................................................................9
R Counter .......................................................................................9
Phase Frequency Detector (PFD) and Charge Pump............ 10
Muxout and Lock Detect........................................................... 10
Input Shift Register .................................................................... 10
Function Latch............................................................................ 13
Applications..................................................................................... 15
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Characteristics ................................................................ 4
Absolute Maximum Ratings............................................................ 5
Transistor Count ........................................................................... 5
Thermal Resistance ...................................................................... 5
ESD Caution.................................................................................. 5
Pin Configurations and Function Descriptions ........................... 6
Typical Performance Characteristics ............................................. 7
Circuit Description........................................................................... 9
Reference Input Section............................................................... 9
RF Input Stage............................................................................... 9
Using a Digitial-to-Analog Converter to Drive
the RSET Pin.................................................................................. 15
Interfacing ................................................................................... 15
PCB Design Guidelines for Chip Scale Package .................... 16
Outline Dimensions....................................................................... 17
Ordering Guide .......................................................................... 17
REVISION HISTORY
1/07—Revision 0: Initial Version
Rev. 0 | Page 2 of 20
ADF4113HV
SPECIFICATIONS
AVDD = DVDD = 3 V 10ꢀ, 5 V 10ꢀꢁ 13.5 V < VP ≤ 16.5 Vꢁ AGND = DGND = CPGND = 0 Vꢁ RSET = 4.7 kΩꢁ dBm referred to 50 Ωꢁ
TA = TMIN to TMAX, unless otherwise noted. Operating temperature range for B version: −40°C to +85°C.
Table 1.
Parameter
B Version
B Chips1
Unit
Test Conditions/Comments
RF CHARACTERISTICS (3 V)
RF Input Sensitivity
RF Input Frequency
Prescaler Output Frequency2
RF CHARACTERISTICS (5 V)
RF Input Sensitivity
−15/0
0.2/3.7
165
−15/0
0.2/3.7
165
dBm min/max
GHz min/max
MHz max
For lower frequencies, ensure SR > 130 V/μs
−10/0
0.2/3.7
0.2/4.0
200
−10/0
0.2/3.7
0.2/4.0
200
dBm min/max
GHz min/max
GHz min/max
MHz max
RF Input Frequency
For lower frequencies, ensure SR > 130 V/ꢀs
Input level = −5 dBm
Prescaler Output Frequency
REFIN CHARACTERISTICS
REFIN Input Frequency
5/150
0.4/AVDD
1.0/AVDD
10
5/150
0.4/AVDD
1.0/AVDD
10
MHz min/max
V p-p min/max
V p-p min/max
pF max
ꢀA max
MHz max
For f < 5 MHz, ensure SR > 100 V/ꢀs
AVDD = 3.3 V, biased at AVDD/23
For f ≥ 10 MHz, AVDD = 5 V, biased at AVDD/23, 4
Reference Input Sensitivity
REFIN Input Capacitance
REFIN Input Current
PHASE DETECTOR FREQUENCY
CHARGE PUMP
100
100
5
5
ICP Sink/Source
RSET = 4.7 kΩ
High Value
Low Value
640
80
2.5
3.9/10
5
3
1.5
2
640
80
2.5
3.9/10
5
3
1.5
2
μA typ
ꢀA typ
% typ
kΩ typ
nA max
% typ
% typ
% typ
Absolute Accuracy
RSET Range
ICP Three-State Leakage Current
Sink and Source Current Matching
ICP vs. VCP
1 V ≤ VCP ≤ VP – 1 V
1 V ≤ VCP ≤ VP – 1 V
VCP = VP/2
ICP vs. Temperature
LOGIC INPUTS
VINH, Input High Voltage
VINL, Input Low Voltage
IINH/IINL, Input Current
CIN, Input Capacitance
LOGIC OUTPUTS
VOH, Output High Voltage
VOL, Output Low Voltage
POWER SUPPLIES
AVDD
0.8 × DVDD
0.2 × DVDD
1
10
0.8 × DVDD
0.2 × DVDD
1
10
V min
V max
ꢀA max
pF max
DVDD − 0.4
0.4
DVDD − 0.4
0.4
V min
V max
IOH = 500 ꢀA
IOL = 500 ꢀA
2.7/5.5
AVDD
13.5/16.5
16
0.25
1
2.7/5.5
AVDD
13.5/16.5
11
0.25
1
V min/V max
DVDD
VP
IDD5 (AIDD + DIDD)
V min/V max
mA max
mA max
ꢀA typ
11 mA typical
TA = 25°C
IP
Low Power Sleep Mode
NOISE CHARACTERISTICS
Normalized Phase Noise Floor6
−212
−212
dBc/Hz typ
1 The B chip specifications are given as typical values.
2 This is the maximum operating frequency of the CMOS counters. The prescaler value should be chosen to ensure that the RF input is divided down to a frequency that
is less than this value.
3 AC coupling ensures AVDD/2 bias.
4 Guaranteed by characterization.
5 TA = 25oC; AVDD = DVDD = 5.5 V; P = 16; RFIN = 900 MHz.
6 The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO, PNTOT, and subtracting 20logN (where N is the N divider
value) and 10logfPFD: PNSYNTH = PNTOT − 10logfPFD − 20logN.
Rev. 0 | Page 3 of 20
ADF4113HV
TIMING CHARACTERISTICS
Guaranteed by design but not production tested. AVDD = DVDD = 3 V 10ꢀ, 5 V 10ꢀꢁ 13.5 V ≤ VP ≤ 16.5 Vꢁ
AGND = DGND = CPGND = 0 Vꢁ RSET = 4.7 kΩꢁ TA = TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter
Limit at TMIN to TMAX (B Version)
Unit
Test Conditions/Comments
LE setup time
DATA to CLK setup time
DATA to CLK hold time
CLK high duration
CLK low duration
t1
t2
t3
t4
t5
t6
t7
20
10
10
25
25
10
20
ns min
ns min
ns min
ns min
ns min
ns min
ns min
CLK to LE setup time
LE pulse width
Timing Diagram
t4
t5
CLK
t2
t3
DB1
(CONTROL BIT C2)
DB0 (LSB)
DB23 (MSB)
DB22
DB2
DATA
LE
(CONTROL BIT C1)
t7
t1
t6
LE
Figure 2. Timing Diagram
Rev. 0 | Page 4 of 20
ADF4113HV
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 3.
TRANSISTOR COUNT
The transistor count is 12,150 (CMOS) and 348 (bipolar).
Parameter
AVDD to GND1
Rating
THERMAL RESISTANCE
Table 4. Thermal Resistance
Package Type
−0.3 V to +7 V
−0.3 V to +0.3 V
−0.3 V to +18 V
−0.3 V to VDD + 0.3 V
−0.3 V to VP + 0.3 V
−0.3 V to VDD + 0.3 V
320 mV
AVDD to DVDD
VP to GND
Digital I/O Voltage to GND
Analog I/O Voltage to GND
REFIN, RFINA, RFINB to GND
RFINA to RFINB
θJA
Unit
°C/W
°C/W
°C/W
TSSOP
150.4
122
216
LFCSP (Paddle Soldered)
LFCSP (Paddle Not Soldered)
ESD CAUTION
Operating Temperature Range
Industrial (B Version)
Storage Temperature Range
Maximum Junction Temperature
Lead Temperature, Soldering
Vapor Phase (60 sec)
Infrared (15 sec)
−40°C to +85°C
−65°C to +150°C
150°C
215°C
220°C
1 GND = AGND = DGND = 0 V.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating onlyꢁ functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
This device is a high performance RF integrated circuit with an
ESD rating of <1 kV, and it is ESD sensitive. Proper precautions
should be taken for handling and assembly.
Rev. 0 | Page 5 of 20
ADF4113HV
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
R
V
SET
P
DV
CP
DD
CPGND
AGND
MUXOUT
LE
PIN 1
ADF4113HV
INDICATOR
TOP VIEW
CPGND
AGND
AGND
1
2
3
4
5
15 MUXOUT
14 LE
13 DATA
12 CLK
11 CE
(Not to Scale)
ADF4113HV
R
R
B
DATA
CLK
FIN
FIN
TOP VIEW
RF
RF
B
A
IN
IN
(Not to Scale)
A
AV
CE
DD
REF
DGND
IN
Figure 3. TSSOP Pin Configuration
Figure 4. LFCSP Pin Configuration
Table 5. Pin Function Descriptions
TSSOP
Pin No.
LFCSP
Pin No.
Mnemonic Description
1
19
RSET
Connecting a resistor between this pin and CPGND sets the maximum charge pump output current.
The nominal voltage potential at the RSET pin is 0.56 V for the ADF4113HV. The relationship between
ICP and RSET is ICPmax = 3/RSET. Therefore, with RSET = 4.7 kΩ, ICPmax = 640 μA.
2
20
CP
Charge Pump Output. When enabled, this pin provides ICP to the external loop filter; in turn, this
drives the external VCO.
3
4
5
1
2, 3
4
CPGND
AGND
RFINB
Charge Pump Ground. CPGND is the ground return path for the charge pump.
Analog Ground. This is the ground return path of the prescaler.
Complementary Input to the RF Prescaler. This point should be decoupled to the ground plane with
a small bypass capacitor, typically 100 pF.
6
7
5
6, 7
RFINA
AVDD
Input to the RF Prescaler. This small-signal input is ac-coupled from the VCO.
Analog Power Supply. The power supply can range from 2.7 V to 5.5 V. Decoupling capacitors to the
analog ground plane should be placed as close as possible to this pin. AVDD must be the same value
as DVDD.
8
8
REFIN
Reference Input. This pin is a CMOS input with a nominal threshold of VDD/2, and an equivalent
input resistance of 100 kΩ. This input can be driven from a TTL or CMOS crystal oscillator, or can be
ac-coupled.
9
10
9, 10
11
DGND
CE
Digital Ground.
Chip Enable. A Logic low on this pin powers down the device and puts the charge pump output
into three-state mode. Taking the pin high powers up the device depending on the status of the
Power-Down Bit PD1.
11
12
CLK
Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is
latched into the 24-bit shift register on the CLK rising edge. This input is a high impedance CMOS
input.
12
13
14
15
13
DATA
LE
Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits. This
input is a high impedance CMOS input.
Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into
one of the four latches; the latch is selected using the control bits.
Multiplexer Output. This multiplexer output allows either the lock detect, the scaled RF, or the
scaled reference frequency to be externally accessed.
Digital Power Supply. This can range from 2.7 V to 5.5 V. Decoupling capacitors to the digital ground
plane (1ꢀF, 1nF) should be placed as close as possible to this pin. For best performance, the 1 ꢀF
capacitor should be placed within 2 mm of the pin. The placing of the 1nF capacitor is less critical
but should still be within 5 mm of the pin. DVDD must have the same value as AVDD.
14
15
MUXOUT
DVDD
16, 17
16
18
VP
Charge Pump Power Supply. VP can range from 13.5 V to 16.5 V and should be decoupled
appropriately.
Rev. 0 | Page 6 of 20
ADF4113HV
TYPICAL PERFORMANCE CHARACTERISTICS
Loop bandwidth = 25 kHz, reference = 10 MHz reference from Agilent E4440A PSA, VCO = Sirenza VCO190-1500T(Y), evaluation
board = EVAL-ADF4113HVEBZ1.
5
FREQ
PARAM
DATA
–FORMAT
KEYWORD
IMPEDANCE
–OHMS
–UNIT –TYPE
–5
GHz
S
MA
R
50
FREQ MAGS11
ANGS11
FREQ MAGS11
ANGS11
–15
–25
–35
–45
–55
–65
–75
–85
–95
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
0.45
0.50
0.55
0.60
0.65
0.70
0.75
0.80
0.85
0.90
0.95
1.00
0.89207
0.8886
–2.0571
–4.4427
–6.3212
–2.1393
–12.13
1.05
1.10
1.15
1.20
1.25
1.30
1.35
1.40
1.45
1.50
1.55
1.60
1.65
1.70
1.75
1.80
0.9512
–40.134
–43.747
–44.393
–46.937
–49.6
0.93458
0.94782
0.96875
0.92216
0.93755
0.96178
0.94354
0.95189
0.97647
0.98619
0.95459
0.97945
0.98864
0.97399
0.97216
0.89022
0.96323
0.90566
0.90307
0.89318
0.89806
0.89565
0.88538
0.89699
0.89927
0.87797
0.90765
0.88526
0.81267
0.90357
0.92954
0.92087
0.93788
–13.52
–51.884
–51.21
–15.746
–18.056
–19.693
–22.246
–24.336
–25.948
–28.457
–29.735
–31.879
–32.681
–31.522
–34.222
–36.961
–39.343
–53.55
–56.786
–58.781
–60.545
–61.43
–61.241
–64.051
–66.19
–63.775
1MHz
–92.428dBc
FREQUENCY (Hz)
Figure 5. S-Parameter Data for the ADF4113HV RF Input (Up to 1.8 GHz)
Figure 8. Reference Spurs (RF = 1000 MHz, PFD = 1 MHz)
0
–5
–70
–80
–90
–10
–15
1kHz
–86.33dBc/Hz
–100
–110
–120
–130
–140
–150
–160
–170
–20
CARRIER POWER: –0.88dBm
+85°C
–25
+25°C
–30
–40°C
–35
–40
–45
0
1k
2k
3k
4k
5k
6k
100
1k
10k
FREQUENCY OFFSET (Hz)
100k
1M
RF INPUT FREQUENCY (MHz)
Figure 6. Input Sensitivity
Figure 9. Integrated Phase Noise
(RF = 1800 MHz, PFD= 1 MHz, VTUNE = 13.1 V, RMS Noise = 1.16°)
0
–10
–20
–30
–40
–50
–60
–70
–70
–80
–90
–100
–110
–120
–130
–140
–150
–160
–170
1kHz
–91.08dBc/Hz
CARRIER POWER: –5.09dBm
1MHz
–87.264dBc
–80
–90
–100
100
1k
10k
100k
1M
FREQUENCY OFFSET (Hz)
FREQUENCY (Hz)
Figure 7. Integrated Phase Noise
(RF = 1000 MHz, PFD = 1 MHz, VTUNE = 1.8 V, RMS Noise = 0.93°)
Figure 10. Reference Spurs (RF = 1800 MHz, PFD = 1 MHz)
Rev. 0 | Page 7 of 20
ADF4113HV
0
800
600
V
V
= 3V
= 15V
DD
P
–20
400
–40
200
–60
0
–200
–400
–600
–800
–80
–100
–120
0
2
4
6
8
10
12
14
16
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
TUNING VOLTAGE (V)
V
(V)
CP
Figure 11. PFD Spurs (1 MHz) vs. VTUNE
Figure 13. Charge Pump Output Characteristics
–50
–60
–70
–80
–90
V
V
= 3V
= 15V
DD
P
–40
–20
0
20
40
60
80
100
TEMPERATURE (°C)
Figure 12. Phase Noise vs. Temperature
(RF = 1500 MHz, PFD = 1 MHz)
Rev. 0 | Page 8 of 20
ADF4113HV
CIRCUIT DESCRIPTION
REFERENCE INPUT SECTION
A AND B COUNTERS
The reference input stage is shown in Figure 14. SW1 and SW2
are normally closed switches (NC in Figure 14). SW3 is normally
open (NO in Figure 14). When power-down is initiated, SW3 is
closed and SW1 and SW2 are opened. This ensures that there is
no loading of the REFIN pin on power-down.
The A and B CMOS counters combine with the dual-modulus
prescaler to allow a wide ranging division ratio in the PLL
feedback counter. The counters are specified to work when the
prescaler output is 200 MHz or less (for AVDD = 5 V). Thus,
with an RF input frequency of 2.5 GHz, a prescaler value of
16/17 is valid but a value of 8/9 is not.
POWER-DOWN
CONTROL
Pulse Swallow Function
100kΩ
SW2
NC
The A and B counters, in conjunction with the dual-modulus
prescaler, make it possible to generate output frequencies that
are spaced only by the reference frequency divided by R. The
equation for the VCO frequency is
REF
TO R COUNTER
IN
NC
SW1
BUFFER
SW3
NO
f
VCO = [(P × B) + A]fREFIN/R
where:
VCO = output frequency of external voltage controlled
Figure 14. Reference Input Stage
RF INPUT STAGE
f
The RF input stage is shown in Figure 15. It is followed by a
two-stage limiting amplifier to generate the current-mode logic
(CML) clock levels needed for the prescaler.
oscillator (VCO).
P = preset modulus of dual-modulus prescaler.
B = preset divide ratio of binary 13-bit counter (3 to 8191).
A = preset divide ratio of binary 6-bit swallow counter (0 to 63).
1.6V
BIAS
GENERATOR
AV
DD
f
REFIN = output frequency of the external reference frequency
500Ω
500Ω
oscillator.
RF
RF
A
B
IN
R = preset divide ratio of binary 14-bit programmable reference
counter (1 to 16,383).
IN
N = BP + A
TO PFD
13-BIT B
COUNTER
AGND
Figure 15. RF Input Stage
FROM RF
INPUT STAGE
LOAD
LOAD
PRESCALER
P/P + 1
PRESCALER (P/P + 1)
6-BIT A
COUNTER
MODULUS
CONTROL
Together with the A and B counters, the dual-modulus prescaler
(P/P + 1) enables the large division ratio, N, to be realized by
N = BP + A
Figure 16. A and B Counters
The dual-modulus prescaler, operating at CML levels, takes the
clock from the RF input stage and divides it down to a manageable
frequency for the CMOS A and CMOS B counters. The pre-
scaler is programmableꢁ it can be set in software to 8/9, 16/17,
32/33, or 64/65. It is based on a synchronous 4/5 core.
R COUNTER
The 14-bit R counter allows the input reference frequency to be
divided down to produce the reference clock to the phase fre-
quency detector (PFD). Division ratios from 1 to 16,383 are
allowed.
Rev. 0 | Page 9 of 20
ADF4113HV
DV
DD
PHASE FREQUENCY DETECTOR (PFD) AND
CHARGE PUMP
The PFD takes inputs from the R counter and N counter and
produces an output proportional to the phase and frequency
difference between them. Figure 17 is a simplified schematic.
The PFD includes a programmable delay element that controls
the width of the antibacklash pulse. This pulse ensures that
there is no dead zone in the PFD transfer function and mini-
mizes phase noise and reference spurs. Two bits in the reference
counter latch, ABP2 and ABP1, control the width of the pulse.
See Figure 20. The only recommended setting for the antiback-
lash pulse width is 7.2 ns.
ANALOG LOCK DETECT
DIGITAL LOCK DETECT
R COUNTER OUTPUT
N COUNTER OUTPUT
SDOUT
MUXOUT
MUX
CONTROL
DGND
Figure 18. MUXOUT Circuit
Lock Detect
MUXOUT can be programmed for two types of lock detect:
digital lock detect and analog lock detect.
V
P
CHARGE
PUMP
UP
Digital lock detect is active high. When LDP in the AB counter
latch is set to 0, digital lock detect is set high when the phase
error on five consecutive phase detector (PD) cycles is less than
10 ns. With LDP set to 1, five consecutive cycles of less than
3 ns are required to set the lock detect. It stays high until a phase
error greater than 25 ns is detected on any subsequent PD cycle.
HIGH
D1
Q1
U1
R DIVIDER
CLR1
PROGRAMMABLE
DELAY
CP
U3
Operate the N-channel, open-drain, analog lock detect with a
10 kΩ nominal external pull-up resistor. When lock has been
detected, this output is high with narrow low-going pulses.
ABP1
ABP2
CLR2
U2
DOWN
HIGH
D2
Q2
INPUT SHIFT REGISTER
The ADF4113HV digital section includes a 24-bit input shift
register, a 14-bit R counter, and a 19-bit N counter comprising
a 6-bit A counter and a 13-bit B counter. Data is clocked into
the 24-bit shift register on each rising edge of CLK, MSB first.
Data is transferred from the shift register to one of three latches
on the rising edge of LE. The destination latch is determined by
the state of the two control bits (C2, C1) in the shift register.
These are the two LSBs, DB1 and DB0, as shown in Figure 2.
The truth table for these bits is shown in Table 6. Figure 19
shows a summary of how the latches are programmed.
N DIVIDER
CPGND
R DIVIDER
N DIVIDER
CP OUTPUT
Figure 17. PFD Simplified Schematic and Timing (in Lock)
Table 6. C2, C1 Truth Table
Control Bits
MUXOUT AND LOCK DETECT
The output multiplexer on the ADF4113HV allows the user to
access various internal points on the chip. The state of MUXOUT
is controlled by M3, M2, and M1 in the function latch. Figure 22
shows the full truth table (function latch map). Figure 18 shows
the MUXOUT section in block diagram form.
C2
0
C1
0
Data Latch
R counter
0
1
1
0
N counter (A and B)
Function latch (including prescaler)
Rev. 0 | Page 10 of 20
ADF4113HV
Latch Summary
REFERENCE COUNTER LATCH
ANTI-
BACKLASH
PULSE
CONTROL
BITS
RESERVED
14-BIT REFERENCE COUNTER
WIDTH
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
0
0
0
ABP2 ABP1 R14 R13 R12 R11 R10 R9
R8
R7
R6
R5
R4
R3
R2
R1 C2(0) C1(0)
N COUNTER LATCH
13-BIT B COUNTER
CONTROL
BITS
6-BIT A COUNTER
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
L1
0
B13 B12 B11 B10 B9
B8
B7
B6
B5
B4
B3
B2
B1
A6
A5
A4
A3
A2
A1 C2(0) C1(1)
FUNCTION LATCH
RESERVED
PRE-
SCALER
VALUE
CURRENT
SETTING
MUXOUT
CONTROL
CONTROL
BITS
RESERVED
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
P2
P1
0
0
0
0
CP3 CP2 CP1
0
0
0
0
0
0
F4
F3
M3
M2
M1
F2
F1 C2(1) C1(0)
Figure 19. Latch Summary Tables
Reference Counter Latch Map
ANTI-
BACKLASH
PULSE
CONTROL
BITS
RESERVED
14-BIT REFERENCE COUNTER
WIDTH
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
ABP2 ABP1 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 C2(0) C1(0)
0
0
0
0
0
0
THESE BITS MUST BE SET AS
INDICATED FOR NORMAL OPERATION
ANTI-BACKLASH
R14
R13
R12
..........
..........
..........
..........
..........
..........
..........
..........
..........
..........
..........
..........
R3
0
0
0
1
.
R2
0
1
1
0
.
R1
DIVIDE RATIO
ABP2
1
ABP1
0
PULSE WIDTH
0
0
0
0
.
0
0
0
0
.
0
0
0
0
.
1
0
1
0
.
1
7.2ns (ONLY ALLOWED
SETTING)
2
3
4
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
16380
16381
16382
16383
Figure 20. Reference Counter Latch Bit Map
Rev. 0 | Page 11 of 20
ADF4113HV
AB Counter Latch Map
CONTROL
BITS
13-BIT B COUNTER
6-BIT A COUNTER
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
1
0
B13 B12 B11 B10 B9
B8
B7
B6
B5
B4
B3
B2
B1
A6
A5
A4
A3
A2
A1 C2(0) C1(1)
A6
A5
A2
A1
A COUNTER DIVIDE RATIO
0
0
0
0
.
0
0
0
0
.
..........
..........
..........
..........
..........
..........
..........
..........
..........
..........
0
0
0
1
.
0
1
0
1
.
0
1
2
L2
0
LOCK DETECT PRECISION
3
10ns
3ns
.
1
.
.
.
.
.
.
.
.
.
.
1
1
1
1
1
1
0
1
1
1
0
1
61
62
63
B13
B12
B11
B3
B2
B1
B COUNTER DIVIDE RATIO
0
0
0
0
.
0
0
0
0
.
0
0
0
0
.
..........
..........
..........
..........
..........
..........
..........
..........
..........
..........
..........
0
0
0
1
.
0
0
1
1
.
0
1
0
1
.
NOT ALLOWED
NOT ALLOWED
NOT ALLOWED
3
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
8188
8189
8190
8191
Figure 21. B Counter Latch Map
Rev. 0 | Page 12 of 20
ADF4113HV
Function Latch Map
PRE-
SCALER
VALUE
CURRENT
SETTING
MUXOUT
CONTROL
CONTROL
BITS
RESERVED
RESERVED
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
P2
P1
0
0
0
0
CP3 CP2 CP1
0
0
0
0
0
0
F4
F3
M3
M2
M1
F2
F1 C2(1) C1(0)
COUNTER
F1
CHARGE PUMP
OUTPUT
F4
OPERATION
I
(µA)
CP
0
1
NORMAL
0
1
NORMAL
4.7kΩ
80
CPI3
CPI2
CPI1
THREE-STATE
0
1
0
1
0
1
R, A, B COUNTERS
HELD IN RESET
640
PHASE DETECTOR
POLARITY
F3
PD1
0
OPERATION
P2
0
P1
0
PRESCALER VALUE
0
1
POSITIVE
NEGATIVE
NORMAL
8/9
1
POWER DOWN
0
1
16/17
32/33
64/65
1
0
1
1
M3
0
M2
0
M1
0
OUTPUT
THREE-STATE OUTPUT
0
0
1
DIGITAL LOCK DETECT
(ACTIVE HIGH)
0
0
1
1
1
1
1
1
0
0
1
1
0
1
0
1
0
1
N DIVIDER OUTPUT
DV
DD
R DIVIDER OUTPUT
ANALOG LOCK DETECT
SERIAL DATA OUTPUT
DGND
Figure 22. Function Latch Map
FUNCTION LATCH
•
•
•
The RFINA and RFINB inputs are debiased.
The on-chip function latch is programmed with C2 and C1 set
to 1,0, respectively. Figure 22 shows the input data format for
programming the function latch.
The reference input buffer circuitry is disabled.
The input register remains active and capable of loading
and latching data.
Counter Reset
DB2 (F1) is the counter reset bit. When DB2 is 1, the R counter
and the AB counters are reset. For normal operation, this bit
should be 0. Upon powering up, the F1 bit must be disabled,
and the N counter resumes counting in close alignment with
the R counter. (The maximum error is one prescaler cycle.)
MUXOUT Control
The on-chip multiplexer is controlled by M3, M2, and M1 on
the ADF4113HV. Figure 22 shows the truth table.
Charge Pump Currents
CPI3, CPI2, and CPI1 program the current setting for the
charge pump. The truth table is given in Figure 22.
Power-Down
DB3 (F2) in the function latch provides a software power-down
for the ADF4113HV. The device powers down immediately
after latching a 1 into Bit F2.
Prescaler Value
P2 and P1 in the function latch set the prescaler values. The
prescaler value should be chosen so that the prescaler output
frequency is always less than or equal to 200 MHz. Thus, with
an RF frequency of 2 GHz, a prescaler value of 16/17 is valid,
but a value of 8/9 is not.
When the CE pin is low, the device immediately powers down
regardless of the state of the power-down bit (F2).
When a power-down is activated (either through software or
a CE pin activated power-down), the following events occur:
PD Polarity
•
•
All active dc current paths are removed.
This bit sets the phase detector polarity bit. See Figure 22.
The R, N, and timeout counters are forced to their load
state conditions.
CP Three-State
This bit controls the CP output pin. With the bit set high, the
CP output is put into three-state. With the bit set low, the CP
output is enabled.
•
•
The charge pump is forced into three-state mode.
The digital clock detect circuitry is reset.
Rev. 0 | Page 13 of 20
ADF4113HV
grammed each time the device is disabled and enabled as long
as it has been programmed at least once after VDD was initially
applied.
DEVICE PROGRAMMING AFTER INITIAL
POWER-UP
After initial power-up of the device, there are two ways to
program the device.
Counter Reset Method
1. Apply VDD
.
CE Pin Method
2. Conduct a function latch load (10 in 2 LSBs). As part of
this, load 1 to the F1 bit. This enables the counter reset.
1. Apply VDD
.
2. Bring CE low to put the device into power-down. This is an
asynchronous power-down in that it happens immediately.
3. Conduct an R counter load (00 in 2 LSBs).
4. Conduct an AB counter load (01 in 2 LSBs).
3. Program the function latch (10). Program the R counter
latch (00). Program the AB counter latch (01).
5. Conduct a function latch load (10 in 2 LSBs). As part of
this, load 0 to the F1 bit. This disables the counter reset.
4. Bring CE high to take the device out of power-down. The R
and AB counters resume counting in close alignment.
This sequence provides the same close alignment as the initiali-
zation method. It offers direct control over the internal reset.
Note that counter reset holds the counters at load point and
three-states the charge pump, but does not trigger synchronous
power-down.
After CE goes high, a duration of 1 μs is sometimes required for
the prescaler band gap voltage and oscillator input buffer bias to
reach steady state.
CE can be used to power the device up and down to check for
channel activity. The input register does not need to be repro-
Rev. 0 | Page 14 of 20
ADF4113HV
APPLICATIONS
RF
OUT
100pF
18Ω
18Ω
VCO
100pF
18Ω
LOOP
FILTER
2
CP
8
INPUT OUTPUT
FREF
REF
IN
IN
GND
ADF4113HV
CE
CLK
DATA
LE
LOCK
DETECT
14
MUXOUT
1
R
SET
100pF
6
5
RF
RF
A
B
IN
2.7kΩ
51Ω
IN
100pF
AD5320
12-BIT
V-OUT DAC
SPI-COMPATIBLE SERIAL BUS
NOTES
1. POWER SUPPLY CONNECTIONS AND DECOUPLING
CAPACITORS ARE OMITTED FOR CLARITY.
Figure 23. Driving the RSET Pin with a Digital-to-Analog Converter
microcontroller. The MicroConverter is set up for SPI master
mode with CPHA = 0. To initiate the operation, the I/O port
driving LE is brought low. Each latch of the ADF4113HV needs
a 24-bit word. This is accomplished by writing three 8-bit bytes
from the MicroConverter to the device. When the third byte
has been written, the LE input should be brought high to
complete the transfer.
USING A DIGITIAL-TO-ANALOG CONVERTER TO
DRIVE THE RSET PIN
A digital-to-analog converter (DAC) can be used to drive the
RSET pin of the ADF4113HV, thus increasing the level of control
over the charge pump current (ICP). This can be advantageous in
wideband applications where the sensitivity of the VCO varies
over the tuning range. To compensate for this, ICP can be varied
to maintain good phase margin and ensure loop stability. See
Figure 23 for this configuration.
I/O port lines on the ADuC812 are also used to control power-
down (CE input), and to detect lock (MUXOUT configured as
lock detect and polled by the port input).
INTERFACING
When the ADuC812 is operating in the SPI master mode, the
maximum SCLOCK rate of the ADuC812 is 4 MHz. This
means that the maximum rate at which the output frequency
can be changed is 166 kHz.
The ADF4113HV has a simple SPI®-compatible serial interface
for writing to the device. CLK, DATA, and LE control the data
transfer. When latch enable (LE) goes high, the 24 bits that have
been clocked into the input register on each rising edge of CLK
are transferred to the appropriate latch. See Figure 2 for the
timing diagram and Table 6 for the latch truth table.
CLK
DATA
LE
SCLOCK
MOSI
ADuC812
The maximum allowable serial clock rate is 20 MHz. This
means that the maximum update rate possible for the device
is 833 kHz, or one update every 1.2 μs. This rate is more than
adequate for systems that have typical lock times in the
hundreds of microseconds.
ADF4113HV
I/O PORTS
CE
MUXOUT
(LOCK DETECT)
ADuC812 Interface
Figure 24. ADuC812 to ADF4113HV Interface
Figure 24 shows the interface between the ADF4113HV and the
ADuC812 MicroConverter®. Because the ADuC812 is based on
an 8051 core, this interface can be used with any 8051-based
Rev. 0 | Page 15 of 20
ADF4113HV
ADSP-21xx Interface
PCB DESIGN GUIDELINES FOR CHIP SCALE
PACKAGE
Figure 25 shows the interface between the ADF4113HV and the
ADSP-21xx digital signal processor. The ADF4113HV needs a
24-bit serial word for each latch write. The easiest way to
accomplish this using the ADSP-21xx family is to use the auto
buffered transmit mode of operation with alternate framing.
This provides a means for transmitting an entire block of serial
data before an interrupt is generated.
The lands on the chip scale package (CP-20-1) are rectangular.
The printed circuit board pad for these should be 0.1 mm
longer than the package land length, and 0.05 mm wider than
the package land width. The land should be centered on the pad
to ensure that the solder joint size is maximized.
The bottom of the chip scale package has a central thermal pad.
The thermal pad on the printed circuit board should be at least
as large as this exposed pad. On the printed circuit board, provide
a clearance of at least 0.25 mm between the thermal pad and the
inner edges of the pad pattern. This ensures that shorting is
avoided.
CLK
SCLK
DT
DATA
ADSP-21xx
ADF4113HV
TFS
LE
CE
I/O FLAGS
MUXOUT
Thermal vias can be used on the printed circuit board thermal
pad to improve thermal performance of the package. If vias are
used, they should be incorporated in the thermal pad at a 1.2 mm
pitch grid. The via diameter should be between 0.3 mm and
0.33 mm, and the via barrel should be plated with 1 oz. copper
to plug the via.
(LOCK DETECT)
Figure 25. ADSP-21xx to ADF4113HV Interface
Set up the word length for eight bits and use three memory
locations for each 24-bit word. To program each 24-bit latch,
store the three 8-bit bytes, enable the auto buffered mode, and
then write to the transmit register of the DSP. This last opera-
tion initiates the autobuffer transfer.
The user should connect the printed circuit board thermal pad
to AGND.
Rev. 0 | Page 16 of 20
ADF4113HV
OUTLINE DIMENSIONS
0.60
4.00
PIN 1
MAX
BSC SQ
INDICATOR
0.60
MAX
20
1
16
15
PIN 1
INDICATOR
2.25
TOP
VIEW
3.75
BCS SQ
2.10 SQ
1.95
11
10
5
6
0.75
0.55
0.35
0.25 MIN
0.80 MAX
0.65 TYP
0.30
0.23
0.18
12° MAX
1.00
0.85
0.80
0.05 MAX
0.02 NOM
0.20
REF
COPLANARITY
0.08
SEATING
PLANE
0.50
BSC
COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-1
Figure 26. 20-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
4 mm x 4 mm Body, Very Thin Quad
(CP-20-1)
Dimensions shown in millimeters
5.10
5.00
4.90
16
9
8
4.50
4.40
4.30
6.40
BSC
1
PIN 1
1.20
MAX
0.15
0.05
0.20
0.09
0.75
8°
0°
0.60
0.45
0.30
0.19
0.65
BSC
SEATING
PLANE
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-153-AB
Figure 27. 16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Dimensions shown in millimeters
ORDERING GUIDE
Model
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
Package Option
RU-16
RU-16
ADF4113HVBRUZ1
ADF4113HVBRUZ-RL1
ADF4113HVBRUZ-RL71
ADF4113HVBCPZ1
ADF4113HVBCPZ-RL1
ADF4113HVBCPZ-RL71
EVAL-ADF4113HVEB1Z1
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Thin Shrink Small Outline Package [TSSOP]
20-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
20-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
20-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
Evaluation Board
RU-16
CP-20-1
CP-20-1
CP-20-1
1 Z = Pb-free part.
Rev. 0 | Page 17 of 20
ADF4113HV
NOTES
Rev. 0 | Page 18 of 20
ADF4113HV
NOTES
Rev. 0 | Page 19 of 20
ADF4113HV
NOTES
©2007 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06223-0-1/07(0)
Rev. 0 | Page 20 of 20
相关型号：
EVAL-ADF4158EB1Z
Direct Modulation/Waveform Generating, 6.1 GHz Fractional-N Frequency Synthesizer
ADI
©2020 ICPDF网 联系我们和版权申明