EVAL-ADM1069LQEBZ_技术文档

Super Sequencer with Margining Control

ADM1069

FUNCTIONAL BLOCK DIAGRAM

FEATURES

REFIN REFOUT REFGND

SDA SCL A1

A0

Complete supervisory and sequencing solution for up to

8 supplies

ADM1069

SMBus

INTERFACE

VREF

8 supply fault detectors enable supervision of supplies to

<0.5% accuracy at all voltages at 25°C

<1.0% accuracy across all voltages and temperatures

4 selectable input attenuators allow supervision of supplies to

14.4 V on VH

12-BIT

SAR ADC

EEPROM

CLOSED-LOOP

MARGINING SYSTEM

PDO1

PDO2

PDO3

PDO4

PDO5

PDO6

CONFIGURABLE

OUTPUT

DRIVERS

6 V on VP1 to VP3 (VPx)

DUAL-

FUNCTION

INPUTS

VX1

VX2

VX3

VX4

4 dual-function inputs, VX1 to VX4 (VXx)

High impedance input to supply fault detector with

thresholds between 0.573 V and 1.375 V

General-purpose logic input

8 programmable driver outputs, PDO1 to PDO8 (PDOx)

Open-collector with external pull-up

Push/pull output, driven to VDDCAP or VPx

Open-collector with weak pull-up to VDDCAP or VPx

Internally charge-pumped high drive for use with external

N-FET (PDO1 to PDO6 only)

(LOGIC INPUTS

OR

(HV CAPABLE OF

DRIVING GATES

OF N-FET)

SFDs)

SEQUENCING

ENGINE

VP1

VP2

VP3

VH

CONFIGURABLE

OUTPUT

DRIVERS

PROGRAMMABLE

RESET

GENERATORS

PDO7

PDO8

(LV CAPABLE

OF DRIVING

LOGIC SIGNALS)

(SFDs)

AGND

PDOGND

VDDCAP

VDD

ARBITRATOR

V_OUTV_OUTV_OUTV_OUT

DAC

Sequencing engine (SE) implements state machine control of

PDO outputs

DAC1 DAC2 DAC3 DAC4

VCCP

GND

Figure 1.

State changes conditional on input events

Enables complex control of boards

Power-up and power-down sequence control

Fault event handling

Interrupt generation on warnings

Watchdog function can be integrated in SE

Program software control of sequencing through SMBus

Complete voltage margining solution for 4 voltage rails

4 voltage output 8-bit DACs (0.300 V to 1.551 V) allow voltage

adjustment via dc-to-dc converter trim/feedback node

12-bit ADC for readback of all supervised voltages

Reference input (REFIN) has 2 input options

Driven directly from 2.048 V ( 0.25%) REFOUT pin

More accurate external reference for improved ADC

performance

Device powered by the highest of VPx, VH for improved

redundancy

User EEPROM: 256 bytes

Industry-standard 2-wire bus interface (SMBus)

Guaranteed PDO low with VH, VPx = 1.2 V

Available in 32-lead, 7 mm × 7 mm LQFP and 40-lead,

6 mm × 6 mm LFCSP packages

APPLICATIONS

Central office systems

Servers/routers

Multivoltage system line cards

DSP/FPGA supply sequencing

In-circuit testing of margined supplies

GENERAL DESCRIPTION

The ADM1069 Super Sequencer® is a configurable supervisory/

sequencing device that offers a single-chip solution for supply

monitoring and sequencing in multiple supply systems. In addition

to these functions, the ADM1069 integrates a 12-bit ADC and

four 8-bit voltage output DACs. These circuits can be used to

implement a closed-loop margining system that enables supply

adjustment by altering either the feedback node or reference of

a dc-to-dc converter using the DAC outputs.

For more information about the ADM1069 register map,

refer to the AN-721 Application Note at www.analog.com

Rev. C

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registeredtrademarks arethe property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

www.analog.com

ADM1069

TABLE OF CONTENTS

Features .............................................................................................. 1

SMBus Jump (Unconditional Jump)........................................ 17

Sequencing Engine Application Example............................... 18

Fault and Status Reporting........................................................ 19

Voltage Readback............................................................................ 20

Supply Supervision with the ADC........................................... 20

Supply Margining ........................................................................... 21

Overview ..................................................................................... 21

Open-Loop Supply Margining ................................................. 21

Closed-Loop Supply Margining............................................... 21

Writing to the DACs .................................................................. 22

Choosing the Size of the Attenuation Resistor....................... 22

DAC Limiting and Other Safety Features ............................... 22

Applications Diagram.................................................................... 23

Communicating with the ADM1069........................................... 24

Configuration Download at Power-Up................................... 24

Updating the Configuration ..................................................... 24

Updating the Sequencing Engine............................................. 25

Internal Registers........................................................................ 25

EEPROM ..................................................................................... 25

Serial Bus Interface..................................................................... 25

SMBus Protocols for RAM and EEPROM.............................. 28

Write Operations........................................................................ 28

Read Operations......................................................................... 30

Outline Dimensions....................................................................... 31

Ordering Guide .......................................................................... 31

Functional Block Diagram .............................................................. 1

Applications....................................................................................... 1

General Description......................................................................... 1

Revision History ............................................................................... 2

Detailed Block Diagram .................................................................. 3

Specifications..................................................................................... 4

Absolute Maximum Ratings............................................................ 7

Thermal Resistance ...................................................................... 7

ESD Caution.................................................................................. 7

Pin Configurations and Function Descriptions ........................... 8

Typical Performance Characteristics ........................................... 10

Powering the ADM1069................................................................ 13

Inputs................................................................................................ 14

Supply Supervision..................................................................... 14

Programming the Supply Fault Detectors............................... 14

Input Comparator Hysteresis.................................................... 14

Input Glitch Filtering ................................................................. 15

Supply Supervision with VXx Inputs....................................... 15

VXx Pins as Digital Inputs ........................................................ 15

Outputs ............................................................................................ 16

Supply Sequencing Through Configurable Output Drivers. 16

Default Output Configuration.................................................. 16

Sequencing Engine ......................................................................... 17

Overview...................................................................................... 17

Warnings...................................................................................... 17

REVISION HISTORY

6/11—Rev. B to Rev. C

Changes to Ordering Guide.......................................................... 31

Change to Serial Bus Timing Parameter in Table 1 ..................... 4

Changes to Ordering Guide .......................................................... 31

10/06—Rev. 0 to Rev. A

Changes to Features ..........................................................................1

Changes to Figure 2...........................................................................3

Changes to Table 1.............................................................................4

Changes to Table 2.............................................................................7

Changes to Table 3.............................................................................8

Inserted Table 4; Renumbered Sequentially ..................................8

Changes to Programming the Supply Fault Detectors Section ..... 13

Changes to Outputs Section.......................................................... 16

Changes to Fault Reporting Section ............................................ 21

Changes to Table 9.......................................................................... 22

Inserted Table 11............................................................................. 28

Changes to Ordering Guide.......................................................... 33

8/08—Rev. A to Rev. B

Added 40-Lead LFCSP.......................................................Universal

Changes to Table 1............................................................................ 4

Moved Absolute Maximum Ratings Section, Changes to Table 3... 7

Added Figure 4, Renumbered Sequentially; Changes to Table 4..... 8

Changes to Powering the ADM1069 Section ............................. 13

Changes to Default Output Configuration Section ................... 16

Changes to Sequence Detector Section ....................................... 18

Changes to Figure 32...................................................................... 21

Changes to Configuration Download at Power-Up Section..... 24

Changes to Table 11........................................................................ 25

Changes to Figure 45 and Error Correction Section ................. 30

Updated Outline Dimensions....................................................... 31

3/05—Revision 0: Initial Version

Rev. C | Page 2 of 32

ADM1069

The logical core of the device is a sequencing engine (SE). This

state machine-based construction provides up to 63 different states.

This design enables very flexible sequencing of the outputs, based

on the condition of the inputs.

Supply margining can be performed with a minimum of external

components. The margining loop can be used for in-circuit

testing of a board during production (for example, to verify

board functionality at −5% of nominal supplies), or it can be

used dynamically to accurately control the output voltage of

a dc-to-dc converter.

The ADM1069 is controlled via configuration data that can be

programmed into an EEPROM. The entire configuration can

be programmed using an intuitive GUI-based software package

provided by Analog Devices, Inc.

The device also provides up to eight programmable inputs for

monitoring undervoltage faults, overvoltage faults, or out-of-

window faults on up to eight supplies. In addition, there are eight

programmable outputs that can be used as logic enables. Six of

these programmable outputs can also provide up to a 12 V output

for driving the gate of an N-FET that can be placed in the path

of a supply.

DETAILED BLOCK DIAGRAM

REFIN

REFOUT

REFGND SDA SCL A1

SMBus

VREF

A0

ADM1069

INTERFACE

OSC

12-BIT

SAR ADC

DEVICE

CONTROLLER

EEPROM

GPI SIGNAL

CONDITIONING

CONFIGURABLE

OUTPUT DRIVER

(HV)

PDO1

VX1

VX2

VX3

VX4

SFD

PDO2

PDO3

PDO4

PDO5

GPI SIGNAL

CONDITIONING

CONFIGURABLE

OUTPUT DRIVER

(HV)

PDO6

SEQUENCING

ENGINE

SFD

SELECTABLE

ATTENUATOR

VP1

VP2

VP3

CONFIGURABLE

OUTPUT DRIVER

(LV)

PDO7

CONFIGURABLE

OUTPUT DRIVER

(LV)

SELECTABLE

ATTENUATOR

VH

SFD

PDO8

AGND

PDOGND

REG 5.25V

CHARGE PUMP

V

OUT

DAC

OUT

DAC

VDDCAP

VDD

ARBITRATOR

GND

VCCP

DAC1 DAC2 DAC3 DAC4

Figure 2. Detailed Block Diagram

Rev. C | Page 3 of 32

ADM1069

SPECIFICATIONS

VH = 3.0 V to 14.4 V,¹VPx = 3.0 V to 6.0 V,¹T_A= −40°C to +85°C, unless otherwise noted.

Table 1.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

POWER SUPPLY ARBITRATION

VH, VPx

VPx

VH

VDDCAP

C_VDDCAP

3.0

V

Minimum supply required on one of VH, VPx

Maximum VDDCAP = 5.1 V, typical

VDDCAP = 4.75 V

Regulated LDO output

Minimum recommended decoupling

capacitance

6.0

14.4

5.4

2.7

10

4.75

μF

POWER SUPPLY

Supply Current, I_VH, I_VPx

4.2

1

6

2

mA

VDDCAP = 4.75 V, PDO1 to PDO8 off, DACs off,

ADC off

Additional Currents

All PDO FET Drivers On

mA

VDDCAP = 4.75 V, PDO1 to PDO6 loaded with

1 μA each, PDO7 to PDO8 off

Maximum additional load that can be drawn

from all PDO pull-ups to VDDCAP

Current Available from VDDCAP

DAC Supply Currents

ADC Supply Current

EEPROM Erase Current

SUPPLY FAULT DETECTORS

VH Pin

2.2

1

10

mA

Four DACs on with 100 μA maximum load on each

Running round-robin loop

1 ms duration only, VDDCAP = 3 V

Input Impedance

Input Attenuator Error

Detection Ranges

High Range

52

0.05

kΩ

%

Midrange and high range

6

2.5

14.4

6

V

Midrange

VPx Pins

Input Impedance

Input Attenuator Error

Detection Ranges

Midrange

Low Range

Ultralow Range

VXx Pins

Input Impedance

Detection Ranges

Ultralow Range

Absolute Accuracy

52

0.05

kΩ

%

Low range and midrange

No input attenuation error

2.5

1.25

0.573

6

3

V

1.375

1

MΩ

0.573

1.375

1

V

%

VREF error + DAC nonlinearity + comparator

offset error

Threshold Resolution

Digital Glitch Filter

8

0

100

Bits

μs

Minimum programmable filter length

Maximum programmable filter length

Rev. C | Page 4 of 32

ADM1069

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

ANALOG-TO-DIGITAL CONVERTER

Signal Range

0

V_REFIN

V

The ADC can convert signals presented to the

VH, VPx, and VXx pins; VPx and VH input signals

are attenuated depending on the selected

range; a signal at the pin corresponding to the

selected range is from 0.573 V to 1.375 V at the

ADC input

Input Reference Voltage on REFIN Pin, V_REFIN

Resolution

INL

Gain Error

Conversion Time

2.048

12

V

Bits

LSB

%

ms

LSB

2.5

0.05

Endpoint corrected, V_REFIN= 2.048 V

V_REFIN= 2.048 V

One conversion on one channel

All eight channels selected, averaging enabled

V_REFIN= 2.048 V

0.44

84

Offset Error

2

Input Noise

0.25

8

LSB_rmsDirect input (no attenuator)

BUFFERED VOLTAGE OUTPUT DACs

Resolution

Bits

Code 0x80 Output Voltage

Four DACs are individually selectable for

centering on one of four output voltage ranges

Range 1

Range 2

Range 3

Range 4

Output Voltage Range

LSB Step Size

0.592

0.796

0.996

1.246

0.6

0.8

1

1.25

601.25

2.36

0.603

0.803

1.003

1.253

V

mV

Same range, independent of center point

Endpoint corrected

INL

0.75 LSB

DNL

Gain Error

0.4

LSB

%

1

Maximum Load Current (Source)

Maximum Load Current (Sink)

Maximum Load Capacitance

Settling Time into 50 pF Load

Load Regulation

PSRR

100

μA

pF

μs

mV

dB

50

2

2.5

60

40

Per mA

DC

100 mV step in 20 ns with 50 pF load

REFERENCE OUTPUT

Reference Output Voltage

Load Regulation

2.043

1

2.048

−0.25

+0.25

2.053

V

No load

mV

μF

dB

Sourcing current, I_DACxMAX= −100 μA

Sinking current, I_DACxMAX= +100 μA

Capacitor required for decoupling, stability

DC

Minimum Load Capacitance

PSRR

60

PROGRAMMABLE DRIVER OUTPUTS

High Voltage (Charge Pump) Mode

(PDO1 to PDO6)

Output Impedance

V_OH

500

12.5

12

kΩ

V

11

10.5

14

13.5

I_OH= 0 μA

I_OH= 1 μA

I_OUTAVG

20

μA

2 V < V_OH< 7 V

Rev. C | Page 5 of 32

ADM1069

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

Standard (Digital Output) Mode (PDO1 to PDO8)

V_OH

2.4

V

mA

kΩ

mA

V_PU(pull-up to VDDCAP or VPx) = 2.7 V, I_OH= 0.5 mA

V_PUto VPx = 6.0 V, I_OH= 0 mA

V_PU≤ 2.7 V, I_OH= 0.5 mA

4.5

V_PU− 0.3

0

V_OL

0.50

20

60

29

2

I_OL= 20 mA

2

I_OL

Maximum sink current per PDOx pin

Maximum total sink for all PDOx pins

Internal pull-up

Current load on any VPx pull-ups, that is, total

source current available through any number of

PDO pull-up switches configured onto any one

VPx pin

2

I_SINK

R_PULL-UP

I_SOURCE(VPx)²

16

20

Three-State Output Leakage Current

Oscillator Frequency

10

110

μA

kHz

V_PDO= 14.4 V

All on-chip time delays derived from this clock

90

2.0

−1

100

DIGITAL INPUTS (VXx, A0, A1)

Input High Voltage, V_IH

Input Low Voltage, V_IL

Input High Current, I_IH

Input Low Current, I_IL

V

μA

pF

μA

Maximum V_IN= 5.5 V

V_IN= 5.5 V

0.8

1

V_IN= 0 V

Input Capacitance

Programmable Pull-Down Current, I_PULL-DOWN

5

20

VDDCAP = 4.75 V, T_A= 25°C, if known logic state

is required

SERIAL BUS DIGITAL INPUTS (SDA, SCL)

Input High Voltage, V_IH

2.0

V

Input Low Voltage, V_IL

0.8

0.4

2

Output Low Voltage, V_OL

I_OUT= −3.0 mA

SERIAL BUS TIMING³

Clock Frequency, f_SCLK

Bus Free Time, t_BUF

Start Setup Time, t_SU;STA

Stop Setup Time, t_SU;STO

Start Hold Time, t_HD;STA

SCL Low Time, t_LOW

SCL High Time, t_HIGH

SCL, SDA Rise Time, t_R

SCL, SDA Fall Time, t_F

Data Setup Time, t_SU;DAT

Data Hold Time, t_HD;DAT

Input Low Current, I_IL

SEQUENCING ENGINE TIMING

State Change Time

400

kHz

μs

ns

μA

1.3

0.6

1.3

0.6

300

100

5

1

V_IN= 0 V

10

μs

¹At least one of the VH, VPx pins must be ≥ 3.0 V to maintain the device supply on VDDCAP.

²Specification is not production tested but is supported by characterization data at initial product release.

³Timing specifications are guaranteed by design and supported by characterization data.

Rev. C | Page 6 of 32

ADM1069

ABSOLUTE MAXIMUM RATINGS

Table 2.

THERMAL RESISTANCE

Parameter

Rating

θ_JAis specified for the worst-case conditions, that is, a device

soldered in a circuit board for surface-mount packages.

Voltage on VH Pin

Voltage on VPx Pins

Voltage on VXx Pins

16 V

7 V

−0.3 V to +6.5 V

Table 3. Thermal Resistance

Package Type

32-Lead LQFP

40-Lead LFCSP

θ_JA

54

25

Unit

°C/W

Voltage on A0, A1 Pins

Voltage on REFIN, REFOUT Pins

Voltage on VDDCAP, VCCP Pins

Voltage on DACx Pins

Voltage on PDOx Pins

Voltage on SDA, SCL Pins

−0.3 V to +7 V

5 V

6.5 V

16 V

7 V

ESD CAUTION

Voltage on GND, AGND, PDOGND,

REFGND Pins

−0.3 V to +0.3 V

Input Current at Any Pin

Package Input Current

5 ꢀA

20 ꢀA

Maxiꢀuꢀ Junction Teꢀperature (T_Jꢀax)

Storage Teꢀperature Range

Lead Teꢀperature

150°C

−65°C to +150°C

Soldering Vapor Phase, 60 sec

ESD Rating, All Pins

215°C

2000 V

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

Rev. C | Page 7 of 32

ADM1069

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

25

32

1

24

VX1

VX2

VX3

VX4

VP1

VP2

VP3

VH

PDO1

PDO2

PDO3

PDO4

PDO5

PDO6

PDO7

PDO8

PIN 1

INDICATOR

PIN 1

NC

VX1

VX2

VX3

VX4

NC

VP1

VP2

VP3

VH

1

2

30 PDO1

INDICATOR

29

28

27

PDO2

PDO3

PDO4

3

ADM1069

TOP VIEW

(Not to Scale)

4

ADM1069

5

26 PDO5

25 PDO6

24 PDO7

23 PDO8

22 NC

6

TOP VIEW

7

(Not to Scale)

8

9

8

17

21 NC

10

9

16

NOTES

1. NC = NO CONNECT.

2. THE LFCSP HAS AN EXPOSED PAD ON THE BOTTOM.

THIS PAD IS A NO CONNECT (NC). IF POSSIBLE, THIS

PAD SHOULD BE SOLDERED TO THE BOARD FOR

IMPROVED MECHANICAL STABILITY.

Figure 3. LQFP Pin Configuration

Figure 4. LFCSP Pin Configuration

Table 4. Pin Function Descriptions

Pin No.

LFCSP¹

Mnemonic

Description

LQFP

1, 6, 15,

16, 21,

NC

No Connect.

22, 37, 38

1 to 4

5 to 7

2 to 5

VX1 to VX4 (VXx) High Iꢀpedance Inputs to Supply Fault Detectors. Fault thresholds can be set froꢀ 0.573 V

to 1.375 V. Alternatively, these pins can be used as general-purpose digital inputs.

VP1 to VP3 (VPx) Low Voltage Inputs to Supply Fault Detectors. Three input ranges can be set by altering the input

attenuation on a potential divider connected to these pins, the output of which connects to a supply

fault detector. These pins allow thresholds froꢀ 2.5 V to 6.0 V, froꢀ 1.25 V to 3.00 V, and froꢀ 0.573 V

to 1.375 V.

7 to 9

8

10

VH

High Voltage Input to Supply Fault Detectors. Three input ranges can be set by altering the input

attenuation on a potential divider connected to this pin, the output of which connects to a supply

fault detector. This pin allows thresholds froꢀ 6.0 V to 14.4 V and froꢀ 2.5 V to 6.0 V.

9

10

11

12

13

AGND²

REFGND²

REFIN

Ground Return for Input Attenuators.

Ground Return for On-Chip Reference Circuits.

Reference Input for ADC. Noꢀinally, 2.048 V. This pin ꢀust be driven by a reference voltage. The

on-board reference can be used by connecting the REFOUT pin to the REFIN pin. This is the norꢀal

configuration.

12

14

REFOUT

2.048 V Reference Output. A reservoir capacitor ꢀust be connected between this pin and GND.

A 10 μF capacitor is recoꢀꢀended for this purpose.

13 to 16 17 to 20

17 to 24 23 to 30

DAC1 to DAC4

PDO8 to PDO1

PDOGND²

Voltage Output DACs. These pins default to high iꢀpedance at power-up.

Prograꢀꢀable Output Drivers.

Ground Return for Output Drivers.

Central Charge-Puꢀp Voltage of 5.25 V. A reservoir capacitor ꢀust be connected between this

pin and GND. A 10 μF capacitor is recoꢀꢀended for this purpose.

25

26

31

32

VCCP

27

28

29

30

33

34

35

36

A0

A1

SCL

SDA

Logic Input. This pin sets the seventh bit of the SMBus interface address.

Logic Input. This pin sets the sixth bit of the SMBus interface address.

SMBus Clock Pin. Bidirectional open drain requires external resistive pull-up.

SMBus Data Pin. Bidirectional open drain requires external resistive pull-up.

Rev. C | Page 8 of 32

ADM1069

Pin No.

LFCSP¹

Mnemonic

Description

LQFP

31

39

VDDCAP

Device Supply Voltage. Linearly regulated froꢀ the highest of the VPx, VH pins to a typical of 4.75 V.

Note that a capacitor ꢀust be connected between this pin and GND. A 10 μF capacitor is recoꢀ-

ꢀended for this purpose.

32

40

GND²

Supply Ground.

1

The LFCSP has an exposed pad on the bottoꢀ. This pad is a no connect (NC). If possible, this pad should be soldered to the board for iꢀproved ꢀechanical stability.

²In a typical application, all ground pins are connected together.

Rev. C | Page 9 of 32

ADM1069

TYPICAL PERFORMANCE CHARACTERISTICS

180

160

140

120

100

80

6

5

4

3

2

1

0

60

40

20

0

1

2

3

4

5

6

0

1

2

3

4

5

6

16

6

V

(V)

V

(V)

VP1

Figure 5. V_VDDCAPvs. V_VP1

Figure 8. I_VP1vs. V_VP1(VP1 Not as Supply)

6

5

4

3

2

1

0

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

2

4

6

8

10

12

14

0

2

4

6

8

10

12

14

16

V

(V)

V

(V)

VH

Figure 6. V_VDDCAPvs. V_VH

Figure 9. I_VHvs. V_VH(VH as Supply)

350

300

250

200

150

100

50

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

1

2

3

4

5

6

1

2

3

4

5

V

(V)

V

(V)

VP1

VH

Figure 7. I_VP1vs. V_VP1(VP1 as Supply)

Figure 10. I_VHvs. V_VH(VH Not as Supply)

Rev. C | Page 10 of 32

ADM1069

14

12

10

8

1.0

0.8

0.6

0.4

0.2

0

6

–0.2

–0.4

–0.6

–0.8

–1.0

4

2

0

2.5

5.0

7.5

(µA)

10.0

12.5

15.0

0

1000

2000

3000

4000

CODE

I

LOAD

Figure 11. Charge-Pumped V_PDO1(FET Drive Mode) vs. I_LOAD

Figure 14. DNL for ADC

5.0

4.5

4.0

3.5

1.0

0.8

0.6

0.4

3.0

0.2

VP1 = 5V

2.5

2.0

0

VP1 = 3V

–0.2

–0.4

–0.6

–0.8

–1.0

1.5

1.0

0.5

0

1

2

3

4

5

6

0

1000

2000

3000

4000

I

(mA)

CODE

LOAD

Figure 12. V_PDO1(Strong Pull-Up to VPx) vs. I_LOAD

Figure 15. INL for ADC

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

12000

10000

8000

6000

4000

2000

0

9894

VP1 = 5V

VP1 = 3V

25

81

0

10

20

30

(µA)

40

50

60

2047

2048

2049

CODE

I

LOAD

Figure 16. ADC Noise, Midcode Input, 10,000 Reads

Figure 13. V_PDO1(Weak Pull-Up to VPx) vs. I_LOAD

Rev. C | Page 11 of 32

ADM1069

1.005

1.004

1.003

1.002

1.001

1.000

0.999

0.998

0.997

0.996

0.995

VP1 = 3.0V

DAC

BUFFER

OUTPUT

20kΩ

47pF

PROBE

POINT

VP1 = 4.75V

1

CH1 200mV

M1.00µs

CH1

756mV

–40

–20

0

20

40

60

80

100

TEMPERATURE (°C)

Figure 19. DAC Output vs. Temperature

Figure 17. Transient Response of DAC Code Change into Typical Load

2.058

2.053

2.048

2.043

2.038

VP1 = 3.0V

DAC

BUFFER

OUTPUT

100kΩ

1V

VP1 = 4.75V

PROBE

POINT

1

CH1 200mV

M1.00µs

CH1

944mV

–40

–20

0

20

40

60

80

100

TEMPERATURE (°C)

Figure 20. REFOUT vs. Temperature

Figure 18. Transient Response of DAC to Turn-On from High-Z State

Rev. C | Page 12 of 32

ADM1069

POWERING THE ADM1069

The ADM1069 is powered from the highest voltage input on

either the positive-only supply inputs (VPx) or the high voltage

supply input (VH). This technique offers improved redundancy

because the device is not dependent on any particular voltage rail

to keep it operational. The same pins are used for supply fault

detection (see the Supply Supervision section). A V_DDarbitrator

on the device chooses which supply to use. The arbitrator can

be considered an OR’ing of four low dropout regulators (LDOs)

together. A supply comparator chooses the highest input to

provide the on-chip supply. There is minimal switching loss

with this architecture (~0.2 V), resulting in the ability to power

the ADM1069 from a supply as low as 3.0 V. Note that the

supply on the VXx pins cannot be used to power the device.

When two or more supplies are within 100 mV of each other,

the supply that first takes control of V_DDkeeps control. For

example, if VP1 is connected to a 3.3 V supply, V_DDpowers up

to approximately 3.1 V through VP1. If VP2 is then connected

to another 3.3 V supply, VP1 still powers the device unless VP2

goes 100 mV higher than VP1.

VDDCAP

VP1

VP2

VP3

VH

IN

OUT

4.75V

LDO

EN

IN

OUT

4.75V

LDO

EN

IN

OUT

4.75V

LDO

An external capacitor to GND is required to decouple the on-

chip supply from noise. This capacitor should be connected to

the VDDCAP pin, as shown in Figure 21. The capacitor has

another use during brownouts (momentary loss of power).

Under these conditions, when the input supply (VPx or VH)

dips transiently below V_DD, the synchronous rectifier switch

immediately turns off so that it does not pull V_DDdown. The

EN

IN

INTERNAL

DEVICE

SUPPLY

OUT

4.75V

LDO

EN

SUPPLY

COMPARATOR

V_DDcapacitor can then act as a reservoir to keep the device

active until the next highest supply takes over the powering

of the device. A 10 μF capacitor is recommended for this

reservoir/decoupling function.

Figure 21. V_DDArbitrator Operation

The VH input pin can accommodate supplies up to 14.4 V, which

allows the ADM1069 to be powered using a 12 V backplane supply.

In cases where this 12 V supply is hot swapped, it is recommended

that the ADM1069 not be connected directly to the supply. Suitable

precautions, such as the use of a hot swap controller, should be

taken to protect the device from transients that could cause

damage during hot swap events.

Rev. C | Page 13 of 32

ADM1069

INPUTS

SUPPLY SUPERVISION

The threshold value required is given by

The ADM1069 has eight programmable inputs. Four of these

are dedicated supply fault detectors (SFDs). These dedicated

inputs are called VH and VPx (VP1 to VP3) by default. The

other four inputs are labeled VXx (VX1 to VX4) and have dual

functionality. They can be used either as SFDs, with functionality

similar to the VH and VPx, or as CMOS-/TTL-compatible logic

inputs to the device. Therefore, the ADM1069 can have up to

eight analog inputs, a minimum of four analog inputs and four

digital inputs, or a combination thereof. If an input is used as

an analog input, it cannot be used as a digital input. Therefore,

a configuration requiring eight analog inputs has no available

digital inputs. Table 6 shows the details of each input.

V_T= (V_R× N)/255 + V_B

where:

V_Tis the desired threshold voltage (undervoltage or overvoltage).

V_Ris the voltage range.

N is the decimal value of the 8-bit code.

V_Bis the bottom of the range.

Reversing the equation, the code for a desired threshold is

given by

N = 255 × (V_T− V_B)/V_R

For example, if the user wants to set a 5 V overvoltage threshold

on VP1, the code to be programmed in the PS1OVTH register

(as discussed in the AN-721 Application Note at www.analog.com)

is given by

PROGRAMMING THE SUPPLY FAULT DETECTORS

The ADM1069 can have up to eight SFDs on its eight input

channels. These highly programmable reset generators enable

the supervision of up to eight supply voltages. The supplies can

be as low as 0.573 V and as high as 14.4 V. The inputs can be

configured to detect an undervoltage fault (the input voltage

drops below a preprogrammed value), an overvoltage fault (the

input voltage rises above a preprogrammed value), or an out-of-

window fault (the input voltage is outside a preprogrammed

range). The thresholds can be programmed to an 8-bit resolution

in registers provided in the ADM1069. This translates to a voltage

resolution that is dependent on the range selected. The resolution

is given by

N = 255 × (5 − 2.5)/3.5

Therefore, N = 182 (1011 0110 or 0xB6).

INPUT COMPARATOR HYSTERESIS

The UV and OV comparators shown in Figure 22 are always

monitoring VPx. To avoid chatter (multiple transitions when

the input is very close to the set threshold level), these compara-

tors have digitally programmable hysteresis. The hysteresis can

be programmed up to the values shown in Table 6.

RANGE

SELECT

ULTRA

OV

LOW

COMPARATOR

+

–

VPx

Step Size = Threshold Range/255

GLITCH

FILTER

FAULT

OUTPUT

VREF

Therefore, if the high range is selected on VH, the step size can

be calculated as follows:

+

–

LOW

MID

(14.4 V − 6.0 V)/255 = 32.9 mV

UV

FAULT TYPE

SELECT

COMPARATOR

Table 5 lists the upper and lower limits of each available range,

the bottom of each range (V_B), and the range itself (V_R).

Figure 22. Supply Fault Detector Block

Table 5. Voltage Range Limits

Voltage Range (V)

0.573 to 1.375

1.25 to 3.00

2.5 to 6.0

6.0 to 14.4

V_B(V)

0.573

1.25

2.5

V_R(V)

0.802

1.75

3.5

The hysteresis is added after a supply voltage goes out of

tolerance. Therefore, the user can program the amount above

the undervoltage threshold to which the input must rise before

an undervoltage fault is deasserted. Similarly, the user can program

the amount below the overvoltage threshold to which an input

must fall before an overvoltage fault is deasserted.

6.0

8.4

Table 6. Input Functions, Thresholds, and Ranges

Input Function Voltage Range (V)

Maximum Hysteresis

425 ꢀV

1.02 V

97.5 ꢀV

212 ꢀV

425 ꢀV

Voltage Resolution (mV)

Glitch Filter (μs)

0 to 100

VH

High voltage analog input

2.5 to 6.0

13.7

32.9

3.14

6.8

13.7

3.14

N/A

6.0 to 14.4

0.573 to 1.375

1.25 to 3.00

2.5 to 6.0

VPx

Positive analog input

VXx

High-Z analog input

Digital input

0.573 to 1.375

0 to 5.0

97.5 ꢀV

N/A

Rev. C | Page 14 of 32

ADM1069

The hysteresis value is given by

An additional supply supervision function is available when the

VXx pins are selected as digital inputs. In this case, the analog

function is available as a second detector on each of the dedi-

cated analog inputs, VPx and VH. The analog function of VX1

is mapped to VP1, VX2 is mapped to VP2, and so on. VX4 is

mapped to VH. In this case, these SFDs can be viewed as secondary

or warning SFDs.

V

_HYST= V_R× N_THRESH/255

where:

V

_HYSTis the desired hysteresis voltage.

N_THRESHis the decimal value of the 5-bit hysteresis code.

Note that N_THRESHhas a maximum value of 31. The maximum

hysteresis for the ranges is listed in Table 6.

The secondary SFDs are fixed to the same input range as the

primary SFDs. They are used to indicate warning levels rather

than failure levels. This allows faults and warnings to be gener-

ated on a single supply using only one pin. For example, if VP1

is set to output a fault when a 3.3 V supply drops to 3.0 V, VX1 can

be set to output a warning at 3.1 V. Warning outputs are available

for readback from the status registers. They are also OR’ed together

and fed into the SE, allowing warnings to generate interrupts on

the PDOs. Therefore, in this example, if the supply drops to 3.1 V,

a warning is generated, and remedial action can be taken before

the supply drops out of tolerance.

INPUT GLITCH FILTERING

The final stage of the SFDs is a glitch filter. This block provides

time-domain filtering on the output of the SFD comparators,

which allows the user to remove any spurious transitions such

as supply bounce at turn-on. The glitch filter function is in addition

to the digitally programmable hysteresis of the SFD comparators.

The glitch filter timeout is programmable up to 100 μs.

For example, when the glitch filter timeout is 100 μs, any pulse

appearing on the input of the glitch filter block that is less than

100 μs in duration is prevented from appearing on the output of

the glitch filter block. Any input pulse that is longer than 100 μs

appears on the output of the glitch filter block. The output is

delayed with respect to the input by 100 μs. The filtering

process is shown in Figure 23.

VXx PINS AS DIGITAL INPUTS

As discussed in the Supply Supervision with VXX Inputs

section, the VXx input pins on the ADM1069 have dual

functionality. The second function is as a digital logic input to

the device. Therefore, the ADM1069 can be configured for up to

four digital inputs. These inputs are TTL-/CMOS-compatible.

Standard logic signals can be applied to the pins: RESET from

reset generators, PWRGD signals, fault flags, manual resets, and

so on. These signals are available as inputs to the SE and, therefore,

can be used to control the status of the PDOs. The inputs can be

configured to detect either a change in level or an edge.

INPUT PULSE SHORTER

THAN GLITCH FILTER TIMEOUT

INPUT PULSE LONGER

THAN GLITCH FILTER TIMEOUT

PROGRAMMED

TIMEOUT

PROGRAMMED

TIMEOUT

INPUT

When configured for level detection, the output of the digital

block is a buffered version of the input. When configured for

edge detection, a pulse of programmable width is output from

the digital block once the logic transition is detected. The width

is programmable from 0 μs to 100 μs.

t₀

t_GF

t₀

t_GF

OUTPUT

The digital blocks feature the same glitch filter function that is

available on the SFDs. This enables the user to ignore spurious

transitions on the inputs. For example, the filter can be used to

debounce a manual reset switch.

t₀

t_GF

t₀

t_GF

Figure 23. Input Glitch Filter Function

When configured as digital inputs, each VXx pin has a weak

(10 μA) pull-down current source available for placing the input

into a known condition, even if left floating. The current source,

if selected, weakly pulls the input to GND.

SUPPLY SUPERVISION WITH VXx INPUTS

The VXx inputs have two functions. They can be used as either

supply fault detectors or digital logic inputs. When selected as

analog (SFD) inputs, the VXx pins have functionality that is very

similar to the VH and VPx pins. The primary difference is that the

VXx pins have only one input range: 0.573 V to 1.375 V. Therefore,

these inputs can directly supervise only the very low supplies.

However, the input impedance of the VXx pins is high, allowing

an external resistor divide network to be connected to the pin.

Thus, potentially any supply can be divided down into the input

range of the VXx pin and supervised. This enables the ADM1069

t o m on i t or ot h e r s u pp l i e s , s u c h a s + 2 4 V, + 4 8 V, a n d − 5 V.

VXx

+

(DIGITAL INPUT)

TO

GLITCH

FILTER

SEQUENCING

ENGINE

DETECTOR

–

VREF = 1.4V

Figure 24. VXx Digital Input Function

Rev. C | Page 15 of 32

ADM1069

OUTPUTS

The data driving each of the PDOs can come from one of three

sources. The source can be enabled in the PDOxCFG configuration

register (see the AN-721 Application Note for details).

SUPPLY SEQUENCING THROUGH

CONFIGURABLE OUTPUT DRIVERS

Supply sequencing is achieved with the ADM1069 using the

programmable driver outputs (PDOs) on the device as control

signals for supplies. The output drivers can be used as logic

enables or as FET drivers.

The data sources are as follows:

•

Output from the SE.

Directly from the SMBus. A PDO can be configured so that

the SMBus has direct control over it. This enables software

control of the PDOs. Therefore, a microcontroller can be

used to initiate a software power-up/power-down sequence.

On-chip clock. A 100 kHz clock is generated on the device.

This clock can be made available on any of the PDOs. It can

be used, for example, to clock an external device such as

an LED.

The sequence in which the PDOs are asserted (and, therefore, the

supplies are turned on) is controlled by the sequencing engine (SE).

The SE determines what action is taken with the PDOs based on

the condition of the ADM1069 inputs. Therefore, the PDOs can be

set up to assert when the SFDs are in tolerance, the correct input

signals are received on the VXx digital pins, no warnings are

received from any of the inputs of the device, and at other times.

The PDOs can be used for a variety of functions. The primary

function is to provide enable signals for LDOs or dc-to-dc

converters that generate supplies locally on a board. The PDOs

can also be used to provide a PWRGD signal, when all the SFDs

are in tolerance, or a RESET output if one of the SFDs goes out

of specification (this can be used as a status signal for a DSP,

FPGA, or other microcontroller).

•

DEFAULT OUTPUT CONFIGURATION

All of the internal registers in an unprogrammed ADM1069 device

from the factory are set to 0. Because of this, the PDOx pins are

pulled to GND by a weak (20 kΩ) on-chip pull-down resistor.

As the input supply to the ADM1069 ramps up on VPx or VH,

all PDOx pins behave as follows:

•

Input supply = 0 V to 1.2 V. The PDOs are high impedance.

Input supply = 1.2 V to 2.7 V. The PDOs are pulled to GND

by a weak (20 kΩ) on-chip pull-down resistor.

The PDOs can be programmed to pull up to a number of

different options. The outputs can be programmed as follows:

•

Open-drain (allowing the user to connect an external pull-

up resistor).

•

Supply > 2.7 V. Factory programmed devices continue to

pull all PDOs to GND by a weak (20 kΩ) on-chip pull-down

resistor. Programmed devices download current EEPROM

configuration data, and the programmed setup is latched. The

PDO then goes to the state demanded by the configuration.

This provides a known condition for the PDOs during

power-up.

•

Open-drain with weak pull-up to V_DD

.

Open-drain with strong pull-up to V_DD

Open-drain with weak pull-up to VPx.

Open-drain with strong pull-up to VPx.

Strong pull-down to GND.

Internally charge-pumped high drive

(12 V, PDO1 to PDO6 only) .

.

The internal pull-down can be overdriven with an external pull-up

of suitable value tied from the PDOx pin to the required pull-up

voltage. The 20 kΩ resistor must be accounted for in calculating

a suitable value. For example, if PDOx must be pulled up to 3.3 V,

and 5 V is available as an external supply, the pull-up resistor

value is given by

The last option (available only on PDO1 to PDO6) allows the

user to directly drive a voltage high enough to fully enhance an

external N-FET, which is used to isolate, for example, a card-

side voltage from a backplane supply (a PDO can sustain greater

than 10.5 V into a 1 μA load). The pull-down switches can also

be used to drive status LEDs directly.

3.3 V = 5 V × 20 kΩ/(R_UP+ 20 kΩ)

Therefore,

R

_UP= (100 kΩ − 66 kΩ)/3.3 V = 10 kΩ

VFET (PDO1 TO PDO6 ONLY)

V

DD

VP4

VP1

SEL

CFG4 CFG5 CFG6

SE DATA

SMBus DATA

CLK DATA

PDO

Figure 25. Programmable Driver Output

Rev. C | Page 16 of 32

ADM1069

SEQUENCING ENGINE

OVERVIEW

MONITOR

FAULT

The ADM1069 sequencing engine (SE) provides the user with

powerful and flexible control of sequencing. The SE implements

a state machine control of the PDO outputs, with state changes

conditional on input events. SE programs can enable complex

control of boards such as power-up and power-down sequence

control, fault event handling, interrupt generation on warnings,

and so on. A watchdog function that verifies the continued

operation of a processor clock can be integrated into the SE

program. The SE can also be controlled via the SMBus, giving

software or firmware control of the board sequencing.

STATE

TIMEOUT

SEQUENCE

Figure 26. State Cell

The ADM1069 offers up to 63 state definitions. The signals

monitored to indicate the status of the input pins are the

outputs of the SFDs.

The SE state machine comprises 63 state cells. Each state has the

following attributes:

WARNINGS

The SE also monitors warnings. These warnings can be generated

when the ADC readings violate their limit register value or when

the secondary voltage monitors on VPx and VH are triggered.

The warnings are OR’ed together and are available as a single

warning input to each of the three blocks that enable exiting

a state.

•

Monitors signals indicating the status of the eight input

pins, VP1 to VP3, VH, and VX1 to VX4.

•

Can be entered from any other state.

Three exit routes move the state machine onto a next state:

sequence detection, fault monitoring, and timeout.

Delay timers for the sequence and timeout blocks can be

programmed independently, and changed with each state

change. The range of timeouts is from 0 ms to 400 ms.

Output condition of the eight PDO pins is defined and

fixed within a state.

Transition from one state to the next is made in less than

20 μs, which is the time needed to download a state

definition from EEPROM to the SE.

•

SMBus JUMP (UNCONDITIONAL JUMP)

The SE can be forced to advance to the next state uncondition-

ally. This enables the user to force the SE to advance. Examples

of the use of this feature include moving to a margining state or

debugging a sequence. The SMBus jump or go-to command can

be seen as another input to sequence and timeout blocks to

provide an exit from each state.

•

Table 7. Sample Sequence State Entries

State

IDLE1

IDLE2

EN3V3

Sequence

Timeout

Monitor

If VX1 is low, go to State IDLE2.

If VP1 is okay, go to State EN3V3.

If VP2 is okay, go to State EN2V5.

If VP2 is not okay after 10 ꢀs,

go to State DIS3V3.

If VP1 is not okay, go to State IDLE1.

DIS3V3

EN2V5

If VX1 is high, go to State IDLE1.

If VP3 is okay, go to State PWRGD.

If VP3 is not okay after 20 ꢀs,

go to State DIS2V5.

If VP1 or VP2 is not okay, go to State FSEL2.

DIS2V5

FSEL1

FSEL2

If VX1 is high, go to State IDLE1.

If VP3 is not okay, go to State DIS2V5.

If VP2 is not okay, go to State DIS3V3.

If VX1 is high, go to State DIS2V5.

If VP1 or VP2 is not okay, go to State FSEL2.

If VP1 is not okay, go to State IDLE1.

If VP1, VP2, or VP3 is not okay, go to State FSEL1.

PWRGD

Rev. C | Page 17 of 32

ADM1069

If a timer delay is specified, the input to the sequence detector

must remain in the defined state for the duration of the timer

delay. If the input changes state during the delay, the timer is reset.

SEQUENCING ENGINE APPLICATION EXAMPLE

The application in this section demonstrates the operation of

the SE. Figure 28 shows how the simple building block of a

single SE state can be used to build a power-up sequence for

a three-supply system. Table 8 lists the PDO outputs for each

state in the same SE implementation. In this system, a good 5 V

supply on VP1 and the VX1 pin held low are the triggers required

to start a power-up sequence. The sequence next turns on the 3.3 V

supply, then the 2.5 V supply (assuming successful turn-on of the

3.3 V supply). When all three supplies have turned on correctly,

the PWRGD state is entered, where the SE remains until a fault

occurs on one of the three supplies, or until it is instructed to go

through a power-down sequence by VX1 going high.

The sequence detector can also help to identify monitoring faults.

In the sample application shown in Figure 28, the FSEL1 and

FSEL2 states first identify which of the VP1, VP2, or VP3 pins

has faulted, and then they take appropriate action.

SEQUENCE

STATES

IDLE1

VX1 = 0

Faults are dealt with throughout the power-up sequence on a

case-by-case basis. The following three sections (the Sequence

Detector section, the Monitoring Fault Detector section, and

the Timeout Detector section) describe the individual blocks

and use the sample application shown in Figure 28 to demonstrate

the actions of the state machine.

IDLE2

VP1 = 1

MONITOR FAULT

STATES

TIMEOUT

STATES

EN3V3

10ms

VP1 = 0

Sequence Detector

The sequence detector block is used to detect when a step in a

sequence has been completed. It looks for one of the SE inputs

to change state, and is most often used as the gate for successful

progress through a power-up or power-down sequence. A timer

block that is included in this detector can insert delays into

a power-up or power-down sequence, if required. Timer delays

can be set from 10 μs to 400 ms. Figure 27 is a block diagram of

the sequence detector.

VP2 = 1

EN2V5

DIS3V3

20ms

(VP1 + VP2) = 0

VX1 = 1

VP3 = 1

PWRGD

DIS2V5

VP2 = 0

(VP1 + VP2 + VP3) = 0

VX1 = 1

SUPPLY FAULT

DETECTION

FSEL1

(VP1 +

VP1

SEQUENCE

DETECTOR

VP2) = 0

VP3 = 0

FSEL2

LOGIC INPUT CHANGE

OR FAULT DETECTION

VX4

VP1 = 0

TIMER

VP2 = 0

WARNINGS

INVERT

FORCE FLOW

(UNCONDITIONAL JUMP)

Figure 28. Sample Application Flow Diagram

SELECT

Figure 27. Sequence Detector Block Diagram

Table 8. PDO Outputs for Each State

PDO Outputs

PDO1 = 3V3ON

PDO2 = 2V5ON

PDO3 = FAULT

IDLE1

IDLE2

EN3V3

EN2V5

DIS3V3

DIS2V5

PWRGD

FSEL1

FSEL2

0

1

0

1

0

1

0

1

0

1

Rev. C | Page 18 of 32

ADM1069

Monitoring Fault Detector

Timeout Detector

The monitoring fault detector block is used to detect a failure on an

input. The logical function implementing this is a wide OR gate

that can detect when an input deviates from its expected condition.

The clearest demonstration of the use of this block is in the

PWRGD state, where the monitor block indicates that a failure

on one or more of the VP1, VP2, or VP3 inputs has occurred.

The timeout detector allows the user to trap a failure to ensure

proper progress through a power-up or power-down sequence.

In the sample application shown in Figure 28, the timeout next-

state transition is from the EN3V3 and EN2V5 states. For the

EN3V3 state, the signal 3V3ON is asserted on the PDO1 output

pin upon entry to this state to turn on a 3.3 V supply.

No programmable delay is available in this block because the

triggering of a fault condition is likely to be caused by a supply

falling out of tolerance. In this situation, the device needs to react as

quickly as possible. Some latency occurs when moving out of this

state because it takes a finite amount of time (~20 μs) for the state

configuration to download from EEPROM into the SE. Figure 29

is a block diagram of the monitoring fault detector.

This supply rail is connected to the VP2 pin, and the sequence

detector looks for the VP2 pin to go above its undervoltage

threshold, which is set in the supply fault detector (SFD)

attached to that pin.

The power-up sequence progresses when this change is detected.

If, however, the supply fails (perhaps due to a short circuit over-

loading this supply), the timeout block traps the problem. In this

example, if the 3.3 V supply fails within 10 ms, the SE moves to

the DIS3V3 state and turns off this supply by bringing PDO1

low. It also indicates that a fault has occurred by taking PDO3

high. Timeout delays of 100 μs to 400 ms can be programmed.

MONITORING FAULT

DETECTOR

1-BIT FAULT

DETECTOR

FAULT

SUPPLY FAULT

DETECTION

VP1

FAULT AND STATUS REPORTING

MASK

SENSE

The ADM1069 has a fault latch for recording faults. Two registers,

FSTAT1 and FSTAT2, are set aside for this purpose. A single bit

is assigned to each input of the device, and a fault on that input

sets the relevant bit. The contents of the fault register can be

read out over the SMBus to determine which input(s) faulted.

The fault register can be enabled/disabled in each state. To latch

data from one state, ensure that the fault latch is disabled in the

following state. This ensures that only real faults are captured

and not, for example, undervoltage conditions that may be present

during a power-up or power-down sequence.

1-BIT FAULT

DETECTOR

FAULT

LOGIC INPUT CHANGE

OR FAULT DETECTION

VX4

MASK

SENSE

1-BIT FAULT

DETECTOR

FAULT

WARNINGS

The ADM1069 also has a number of status registers. These

include more detailed information, such as whether an under-

voltage or overvoltage fault is present on a particular input. The

status registers also include information on ADC limit faults.

Note that the data in the status registers is not latched in any

way and, therefore, is subject to change at any time.

MASK

Figure 29. Monitoring Fault Detect or Block Diagram

See the AN-721 Application Note at www.analog.com for full

details about the ADM1069 registers.

Rev. C | Page 19 of 32

ADM1069

VOLTAGE READBACK

The ADM1069 has an on-board, 12-bit, accurate ADC for voltage

readback over the SMBus. The ADC has an 8-channel analog

mux on the front end. The eight channels consist of the eight

SFD inputs (VH, VPx, and VXx). Any or all of these inputs can be

selected to be read, in turn, by the ADC. The circuit controlling

this operation is called the round-robin circuit. This circuit can be

selected to run through its loop of conversions once or conti-

nuously. Averaging is also provided for each channel. In this case,

the round-robin circuit runs through its loop of conversions

16 times before returning a result for each channel. At the end

of this cycle, the results are written to the output registers.

Table 9. ADC Input Voltage Ranges

SFD Input

Range (V)

Attenuation

Factor

ADC Input Voltage

Range (V)

0.573 to 1.375

1.25 to 3.00

2.5 to 6.0

1

0 to 2.048

0 to 4.46

0 to 6.0¹

2.181

4.363

10.472

6.0 to 14.4

0 to 14.4¹

¹The upper liꢀit is the absolute ꢀaxiꢀuꢀ allowed voltage on the VPx and

VH pins.

The typical way to supply the reference to the ADC on the

REFIN pin is to connect the REFOUT pin to the REFIN pin.

REFOUT provides a 2.048 V reference. As such, the supervising

range covers less than half the normal ADC range. It is possible,

however, to provide the ADC with a more accurate external

reference for improved readback accuracy.

The ADC samples single-sided inputs with respect to the AGND

pin. A 0 V input gives out Code 0, and an input equal to the

voltage on REFIN gives out full code (4095 decimal).

The inputs to the ADC come directly from the VXx pins and from

the back of the input attenuators on the VPx and VH pins,

as shown in Figure 30 and Figure 31.

Supplies can also be connected to the input pins purely for ADC

readback, even though these pins may go above the expected

supervisory range limits (but not above the absolute maximum

ratings on these pins). For example, a 1.5 V supply connected to

the VX1 pin can be correctly read out as an ADC code of approxi-

mately 3/4 full scale, but it always sits above any supervisory limits

that can be set on that pin. The maximum setting for the REFIN

pin is 2.048 V.

DIGITIZED

VOLTAGE

READING

NO ATTENUATION

12-BIT

ADC

VXx

2.048V VREF

Figure 30. ADC Reading on VXx Pins

SUPPLY SUPERVISION WITH THE ADC

In addition to the readback capability, another level of supervision

is provided by the on-chip 12-bit ADC. The ADM1069 has limit

registers with which the user can program a maximum or mini-

mum allowable threshold. Exceeding the threshold generates a

warning that can either be read back from the status registers

or input into the SE to determine what sequencing action the

ADM1069 should take. Only one register is provided for each

input channel. Therefore, either an undervoltage threshold or

overvoltage threshold (but not both) can be set for a given channel.

The round-robin circuit can be enabled via an SMBus write, or

it can be programmed to turn on in any state in the SE program.

For example, it can be set to start after a power-up sequence is

complete, and all supplies are known to be within expected

tolerance limits.

ATTENUATION NETWORK

VPx/VH

(DEPENDS ON RANGE SELECTED)

DIGITIZED

VOLTAGE

READING

12-BIT

ADC

2.048V VREF

Figure 31. ADC Reading on VPx/VH Pins

The voltage at the input pin can be derived from the following

equation:

ADCCode

V =

× Attenuation Factor × V_REFIN

4095

where V_REFIN= 2.048 V when the internal reference is used (that is,

the REFIN pin is connected to the REFOUT pin).

Note that a latency is built into this supervision, dictated by the

conversion time of the ADC. With all 12 channels selected, the

total time for the round-robin operation (averaging off) is approx-

imately 6 ms (500 μs per channel selected). Supervision using

the ADC, therefore, does not provide the same real-time response

as the SFDs.

The ADC input voltage ranges for the SFD input ranges are

listed in Table 9.

Rev. C | Page 20 of 32

ADM1069

SUPPLY MARGINING

OVERVIEW

CLOSED-LOOP SUPPLY MARGINING

A more accurate and comprehensive method of margining is to

implement a closed-loop system (see Figure 33). The voltage on

the rail to be margined can be read back to accurately margin the

rail to the target voltage. The ADM1069 incorporates all the circuits

required to do this, with the 12-bit successive approximation ADC

used to read back the level of the supervised voltages, and the

six voltage output DACs, implemented as described in the Open-

Loop Supply Margining section, used to adjust supply levels.

These circuits can be used along with other intelligence, such as

a microcontroller, to implement a closed-loop margining system

that allows any dc-to-dc converter or LDO supply to be set to

any voltage, accurate to within 0.5% of the target.

It is often necessary for the system designer to adjust supplies,

either to optimize their level or force them away from nominal

values to characterize the system performance under these

conditions. This is a function typically performed during an

in-circuit test (ICT), such as when a manufacturer wants to

guarantee that a product under test functions correctly at

nominal supplies minus 10%.

OPEN-LOOP SUPPLY MARGINING

The simplest method of margining a supply is to implement

an open-loop technique (see Figure 32). A popular way to do

this is to switch extra resistors into the feedback node of a power

module, such as a dc-to-dc converter or low dropout regulator

(LDO). The extra resistor alters the voltage at the feedback or

trim node and forces the output voltage to margin up or down

by a certain amount.

To implement closed-loop margining,

1. Disable the four DACx outputs.

2. Set the DAC output voltage equal to the voltage on the

feedback node.

The ADM1069 can perform open-loop margining for up to four

supplies. The four on-board voltage DACs (DAC1 to DAC4) can

drive into the feedback pins of the power modules to be margined.

The simplest circuit to implement this function is an attenuation

resistor that connects the DACx pin to the feedback node of a

dc-to-dc converter. When the DACx output voltage is set equal

to the feedback voltage, no current flows into the attenuation

resistor, and the dc-to-dc converter output voltage does not change.

Taking DACx above the feedback voltage forces current into the

feedback node, and the output of the dc-to-dc converter is forced

to fall to compensate for this. The dc-to-dc converter output can be

forced high by setting the DACx output voltage lower than the

feedback node voltage. The series resistor can be split in two, and

the node between them can be decoupled with a capacitor to

ground. This can help to decouple any noise picked up from the

board. Decoupling to a ground local to the dc-to-dc converter

is recommended.

3. Enable the DAC.

4. Read the voltage at the dc-to-dc converter output that

is connected to one of the VPx, VH, or VXx pins.

5. If necessary, modify the DACx output code up or down

to adjust the dc-to-dc converter output voltage. Otherwise,

stop because the target voltage has been reached.

6. Set the DAC output voltage to a value that alters the supply

output by the required amount (for example, 5%).

7. Repeat Step 4 through Step 6 until the measured supply

reaches the target voltage.

Step 1 to Step 3 ensure that when the DACx output buffer is

turned on, it has little effect on the dc-to-dc converter output.

The DAC output buffer is designed to power up without

glitching by first powering up the buffer to follow the pin

voltage. It does not drive out onto the pin at this time. Once the

output buffer is properly enabled, the buffer input is switched

over to the DAC, and the output stage of the buffer is turned on.

Output glitching is negligible.

The ADM1069 can be commanded to margin a supply up or

down over the SMBus by updating the values on the relevant

DAC output.

VIN

MICROCONTROLLER

V

OUT

ADM1069

DEVICE

CONTROLLER

(SMBus)

OUTPUT

DC-TO-DC

ATTENUATION

RESISTOR, R3

CONVERTER

R1

R2

DACx

FEEDBACK

DAC

PCB

GND

TRACE NOISE

DECOUPLING

CAPACITOR

Figure 32. Open-Loop Margining System Using the ADM1069

Rev. C | Page 21 of 32

ADM1069

MICROCONTROLLER

VIN

ADM1069

MUX

VH/VPx/VXx

DACx

DC-TO-DC

CONVERTER

ADC

ATTENUATION

RESISTOR

OUTPUT

FEEDBACK

GND

DEVICE

CONTROLLER

(SMBus)

DAC

PCB

TRACE NOISE

DECOUPLING

CAPACITOR

Figure 33. Closed-Loop Margining System Using the ADM1069

the current flowing through R3. Therefore, a direct relationship

exists between the extra voltage drop across R1 during margining

WRITING TO THE DACS

Four DAC ranges are offered. They can be placed with midcode

(Code 0x7F) at 0.6 V, 0.8 V, 1.0 V, and 1.25 V. These voltages are

placed to correspond to the most common feedback voltages.

Centering the DAC outputs in this way provides the best use of

the DAC resolution. For most supplies, it is possible to place the

DAC midcode at the point where the dc-to-dc converter output

is not modified, thereby giving half of the DAC range to margin

up and the other half to margin down.

and the voltage drop across R3.

This relationship is given by the following equation:

R1

R3

ΔV_OUT

=

(V_FB− V_DACOUT)

where:

ΔV_OUTis the change in V_OUT

V_FBis the voltage at the feedback node of the dc-to-dc converter.

_DACOUTis the voltage output of the margining DAC.

.

The DAC output voltage is set by the code written to the DACx

register. The voltage is linear with the unsigned binary number

in this register. Code 0x7F is placed at the midcode voltage, as

described previously. The output voltage is given by

V

This equation demonstrates that if the user wants the output

voltage to change by 300 mV, then R1 = R3. If the user wants

the output voltage to change by 600 mV, R1 = 2 × R3, and so on.

DAC Output = (DACx − 0x7F)/255 × 0.6015 + V_OFF

where V_OFFis one of the four offset voltages.

It is best to use the full DAC output range to margin a supply.

Choosing the attenuation resistor in this way provides the most

resolution from the DAC, meaning that with one DAC code

change, the smallest effect on the dc-to-dc converter output

voltage is induced. If the resistor is sized up to use a code such

as 27 decimal to 227 decimal to move the dc-to-dc converter

output by 5%, it takes 100 codes to move 5% (each code moves

the output by 0.05%). This is beyond the readback accuracy of

the ADC, but it should not prevent the user from building a

circuit to use the most resolution.

There are 256 DAC settings available. The midcode value is

located at DAC Code 0x7F, as close as possible to the middle

of the 256 code range. The full output swing of the DACs is

+302 mV (+128 codes) and −300 mV (−127 codes) around the

selected midcode voltage. The voltage range for each midcode

voltage is shown in Table 10.

Table 10. Ranges for Midcode Voltages

Midcode

Voltage (V)

Minimum Voltage

Output (V)

Maximum Voltage

Output (V)

DAC LIMITING AND OTHER SAFETY FEATURES

Limit registers (called DPLIMx and DNLIMx) on the device

offer the user some protection from firmware bugs that can

cause catastrophic board problems by forcing supplies beyond

their allowable output ranges. Essentially, the DAC code written

into the DACx register is clipped such that the code used to set

the DAC voltage is given by

0.6

0.8

1.0

1.25

0.300

0.500

0.700

0.950

0.902

1.102

1.302

1.552

CHOOSING THE SIZE OF THE ATTENUATION

RESISTOR

DAC Code

= DACx, DACx ≥ DNLIMx and DACx ≤ DPLIMx

The size of the attenuation resistor, R3, determines how much

the DAC voltage swing affects the output voltage of the dc-to-dc

converter that is being margined (see Figure 33).

= DNLIMx,

= DPLIMx,

DACx < DNLIMx

DACx > DPLIMx

In addition, the DAC output buffer is three-stated if DNLIMx >

DPLIMx. By programming the limit registers this way, the user

can make it very difficult for the DAC output buffers to be turned

on during normal system operation. The limit registers are among

the registers downloaded from EEPROM at startup.

Because the voltage at the feedback pin remains constant, the

current flowing from the feedback node to GND through R2 is

a constant. In addition, the feedback node itself is high impedance.

This means that the current flowing through R1 is the same as

Rev. C | Page 22 of 32

ADM1069

APPLICATIONS DIAGRAM

12V IN

5V IN

3V IN

12V OUT

5V OUT

3V OUT

IN

DC-TO-DC1

EN

OUT

3.3V OUT

VH

ADM1069

PDO1

PDO2

5V OUT

3V OUT

3.3V OUT

VP1

VP2

VP3

IN

DC-TO-DC2

EN OUT

PDO3

PDO4

PDO5

1.25V OUT

1.2V OUT

0.9V OUT

VX1

VX2

VX3

PWRGD

PDO6

PDO7

SYSTEM RESET

IN

DC-TO-DC3

EN OUT

POWRON

1.2V OUT

0.9V OUT

VX4

PDO8

DAC1

3.3V OUT

IN

REFOUT

REFIN VCCP VDDCAP GND

OUT

10µF 10µF 10µF

EN

TRIM

DC-TO-DC4

*ONLY ONE MARGINING CIRCUIT

SHOWN FOR CLARITY. DAC1 TO DAC4

ALLOW MARGINING FOR UP TO

FOUR VOLTAGE RAILS.

Figure 34. Applications Diagram

Rev. C | Page 23 of 32

ADM1069

COMMUNICATING WITH THE ADM1069

The ADM1069 provides several options that allow the user to

update the configuration over the SMBus interface. The

following three options are controlled in the UPDCFG register.

CONFIGURATION DOWNLOAD AT POWER-UP

The configuration of the ADM1069 (undervoltage/overvoltage

thresholds, glitch filter timeouts, PDO configurations, and so on)

is dictated by the contents of the RAM. The RAM comprises

digital latches that are local to each of the functions on the device.

The latches are double-buffered and have two identical latches,

Latch A and Latch B. Therefore, when an update to a function

occurs, the contents of Latch A are updated first, and then the

contents of Latch B are updated with identical data. The advantages

of this architecture are explained in detail in the Updating the

Configuration section.

Option 1

Update the configuration in real time. The user writes to the RAM

across the SMBus, and the configuration is updated immediately.

Option 2

Update the Latch As without updating the Latch Bs. With this

method, the configuration of the ADM1069 remains unchanged

and continues to operate in the original setup until the instruction

is given to update the Latch Bs.

The two latches are volatile memory and lose their contents at

power-down. Therefore, the configuration in the RAM must be

restored at power-up by downloading the contents of the EEPROM

(nonvolatile memory) to the local latches. This download occurs

in steps, as follows:

Option 3

Change the EEPROM register contents without changing the RAM

contents, and then download the revised EEPROM contents to the

RAM registers. With this method, the configuration of the

ADM1069 remains unchanged and continues to operate in the

original setup until the instruction is given to update the RAM.

1. With no power applied to the device, the PDOs are all high

impedance.

2. When 1.2 V appears on any of the inputs connected to the

VDD arbitrator (VH or VPx), the PDOs are all weakly pulled

to GND with a 20 kΩ resistor.

3. When the supply rises above the undervoltage lockout of

the device (UVLO is 2.5 V), the EEPROM starts to

download to the RAM.

4. The EEPROM downloads its contents to all Latch As.

5. When the contents of the EEPROM are completely

downloaded to the Latch As, the device controller signals

all Latch As to download to all Latch Bs simultaneously,

completing the configuration download.

6. At 0.5 ms after the configuration download completes, the

first state definition is downloaded from the EEPROM into

the SE.

The instruction to download from the EEPROM in Option 3 is

also a useful way to restore the original EEPROM contents if

revisions to the configuration are unsatisfactory. For example,

if the user needs to alter an overvoltage threshold, the RAM

register can be updated, as described in Option 1. However,

if the user is not satisfied with the change and wants to revert to

the original programmed value, the device controller can issue

a command to download the EEPROM contents to the RAM

again, as described in Option 3, restoring the ADM1069 to its

original configuration.

The topology of the ADM1069 makes this type of operation

possible. The local, volatile registers (RAM) are all double-

buffered latches. Setting Bit 0 of the UPDCFG register to 1

leaves the double-buffered latches open at all times. If Bit 0 is set

to 0 when a RAM write occurs across the SMBus, only the first

side of the double-buffered latch is written to. The user must

then write a 1 to Bit 1 of the UPDCFG register. This generates a

pulse to update all the second latches at once. EEPROM writes

occur in a similar way.

Note that any attempt to communicate with the device prior to

the completion of the download causes the ADM1069 to issue

a no acknowledge (NACK).

UPDATING THE CONFIGURATION

After power-up, with all the configuration settings loaded from

the EEPROM into the RAM registers, the user may need to alter

the configuration of functions on the ADM1069, such as

changing the undervoltage or overvoltage limit of an SFD,

changing the fault output of an SFD, or adjusting the rise time

delay of one of the PDOs.

The final bit in this register can enable or disable EEPROM page

erasure. If this bit is set high, the contents of an EEPROM page

can all be set to 1. If low, the contents of a page cannot be erased,

even if the command code for page erasure is programmed across

the SMBus. The bit map for the UPDCFG register is shown in

the AN-721 Application Note at www.analog.com. A flow diagram

for download at power-up and subsequent configuration updates

is shown in Figure 35.

Rev. C | Page 24 of 32

ADM1069

SMBus

POWER-UP

CC

DEVICE

(V > 2.5V)

CONTROLLER

E

P

R

O

M

L

R

A

M

L

U

P

D

A

T

D

A

LATCH A

LATCH B

FUNCTION

(OV THRESHOLD

ON VP1)

D

EEPROM

Figure 35. Configuration Update Flow Diagram

The major differences between the EEPROM and other

registers are as follows:

UPDATING THE SEQUENCING ENGINE

Sequencing engine (SE) functions are not updated in the same

way as regular configuration latches. The SE has its own dedicated

512-byte EEPROM for storing state definitions, providing 63

individual states, each with a 64-bit word (one state is reserved).

At power-up, the first state is loaded from the SE EEPROM into

the engine itself. When the conditions of this state are met, the

next state is loaded from the EEPROM into the engine, and so

on. The loading of each new state takes approximately 10 μs.

•

An EEPROM location must be blank before it can be

written to. If it contains data, the data must first be erased.

Writing to the EEPROM is slower than writing to the RAM.

Writing to the EEPROM should be restricted because it has

a limited write/cycle life of typically 10,000 write operations,

due to the usual EEPROM wear-out mechanisms.

•

The first EEPROM is split into 16 (0 to 15) pages of 32 bytes each.

Page 0 to Page 6, starting at Address 0xF800, hold the configuration

data for the applications on the ADM1069 (such as the SFDs

and PDOs). These EEPROM addresses are the same as the RAM

register addresses, prefixed by F8. Page 7 is reserved. Page 8 to

Page 15 are for customer use.

To alter a state, the required changes must be made directly to

the EEPROM. RAM for each state does not exist. The relevant

alterations must be made to the 64-bit word, which is then

uploaded directly to the EEPROM.

INTERNAL REGISTERS

Data can be downloaded from the EEPROM to the RAM in one

of the following ways:

The ADM1069 contains a large number of data registers.

The principal registers are the address pointer register and

the configuration registers.

•

At power-up, when Page 0 to Page 6 are downloaded.

By setting Bit 0 of the UDOWNLD register (0xD8), which

performs a user download of Page 0 to Page 6.

Address Pointer Register

The address pointer register contains the address that selects one

of the other internal registers. When writing to the ADM1069,

the first byte of data is always a register address that is written to

the address pointer register.

SERIAL BUS INTERFACE

The ADM1069 is controlled via the serial system management

bus (SMBus) and is connected to this bus as a slave device,

under the control of a master device. It takes approximately

1 ms after power-up for the ADM1069 to download from its

EEPROM. Therefore, access to the ADM1069 is restricted until

the download is complete.

Configuration Registers

The configuration registers provide control and configuration

for various operating parameters of the ADM1069.

EEPROM

Identifying the ADM1069 on the SMBus

The ADM1069 has two 512-byte cells of nonvolatile, electrically

erasable, programmable read-only memory (EEPROM), from

Register Address 0xF800 to Register Address 0xFBFF. The

EEPROM is used for permanent storage of data that is not lost

when the ADM1069 is powered down. One EEPROM cell contains

the configuration data of the device; the other contains the state

definitions for the SE. Although referred to as read-only memory,

the EEPROM can be written to, as well as read from, using the

serial bus in exactly the same way as the other registers.

The ADM1069 has a 7-bit serial bus slave address (see Table 11).

The device is powered up with a default serial bus address. The

five MSBs of the address are set to 10011; the two LSBs are

determined by the logical states of Pin A1 and Pin A0. This

allows the connection of four ADM1069s to one SMBus.

Table 11. Serial Bus Slave Address

A1 Pin

A0 Pin

Hex Address

7-Bit Address

1001100x¹

1001101x¹

1001110x¹

1001111x¹

Low

High

Low

High

Low

0x98

0x9A

0x9C

0x9E

High

¹x = Read/write bit. The address is shown only as the first 7 MSBs.

Rev. C | Page 25 of 32

ADM1069

The device also has several identification registers (read-only)

that can be read across the SMBus. Table 12 lists these registers

with their values and functions.

All other devices on the bus remain idle while the selected device

W

waits for data to be read from or written to it. If the R/ bit is a 0,

W

the master writes to the slave device. If the R/ bit is a 1, the

master reads from the slave device.

Table 12. Identification Register Values and Functions

Name

MANID 0xF4

REVID 0xF5

MARK1 0xF6

MARK2 0xF7

Address Value Function

Step 2

0x41

0x02

0x00

Manufacturer ID for Analog Devices

Silicon revision

Software brand

Data is sent over the serial bus in sequences of nine clock pulses:

eight bits of data followed by an acknowledge bit from the slave

device. Data transitions on the data line must occur during the

low period of the clock signal and remain stable during the high

period because a low-to-high transition when the clock is high

could be interpreted as a stop signal. If the operation is a write

operation, the first data byte after the slave address is a command

byte. This command byte tells the slave device what to expect next.

It may be an instruction telling the slave device to expect a block

write, or it may be a register address that tells the slave where

subsequent data is to be written. Because data can flow in only

Software brand

General SMBus Timing

Figure 36, Figure 37, and Figure 38 are timing diagrams for

general read and write operations using the SMBus. The SMBus

specification defines specific conditions for different types of

read and write operations, which are discussed in the Write

Operations and Read Operations sections.

The general SMBus protocol operates as follows:

W

one direction, as defined by the R/ bit, sending a command

to a slave device during a read operation is not possible. Before

a read operation, it may be necessary to perform a write operation

to tell the slave what sort of read operation to expect and/or the

address from which data is to be read.

Step 1

The master initiates data transfer by establishing a start condition,

defined as a high-to-low transition on the serial data line SDA,

while the serial clock line SCL remains high. This indicates that

a data stream follows. All slave peripherals connected to the serial

bus respond to the start condition and shift in the next eight bits,

Step 3

When all data bytes have been read or written, stop conditions

are established. In write mode, the master pulls the data line high

during the 10th clock pulse to assert a stop condition. In read

mode, the master device releases the SDA line during the low

period before the ninth clock pulse, but the slave device does not

pull it low. This is known as a no acknowledge. The master then

takes the data line low during the low period before the 10th clock

pulse and then high during the 10th clock pulse to assert a stop

condition.

W

consisting of a 7-bit slave address (MSB first) plus an R/ bit.

This bit determines the direction of the data transfer, that is,

whether data is written to or read from the slave device (0 = write,

1 = read).

The peripheral whose address corresponds to the transmitted

address responds by pulling the data line low during the low period

before the ninth clock pulse, known as the acknowledge bit, and

by holding it low during the high period of this clock pulse.

1

9

1

9

SCL

SDA

1

0

1

A1

A0 R/W

D7

D6 D5 D4

D3 D2 D1

D0

ACK. BY

SLAVE

ACK. BY

SLAVE

START BY

MASTER

FRAME 1

SLAVE ADDRESS

FRAME 2

COMMAND CODE

1

9

1

9

SCL

(CONTINUED)

SDA

(CONTINUED)

D7 D6

D5 D4

D3 D2

D1

D7

D6 D5 D4

D3 D2 D1

D0

STOP

BY

MASTER

ACK. BY

SLAVE

ACK. BY

SLAVE

FRAME 3

FRAME N

DATA BYTE

Figure 36. General SMBus Write Timing Diagram

Rev. C | Page 26 of 32

ADM1069

1

9

1

9

SCL

SDA

1

0

1

A1

A0 R/W

D7

D6 D5 D4

D3 D2 D1

D0

ACK. BY

SLAVE

ACK. BY

MASTER

START BY

MASTER

FRAME 1

SLAVE ADDRESS

FRAME 2

DATA BYTE

1

9

1

9

SCL

(CONTINUED)

SDA

(CONTINUED)

D7 D6

D5 D4

D3 D2

D1

D7

D6 D5 D4

D3 D2 D1

D0

NO ACK.

D0

STOP

BY

MASTER

ACK. BY

MASTER

FRAME 3

FRAME N

DATA BYTE

Figure 37. General SMBus Read Timing Diagram

t_R

t_F

t_HD;STA

t_LOW

t_HD;STA

t_HD;DAT

SCL

SDA

t_HIGH

t_SU;STA

t_SU;STO

t_SU;DAT

t_BUF

P

S

P

Figure 38. Serial Bus Timing Diagram

Rev. C | Page 27 of 32

ADM1069

In the ADM1069, the send byte protocol is used for the following

two purposes:

SMBus PROTOCOLS FOR RAM AND EEPROM

The ADM1069 contains volatile registers (RAM) and nonvola-

tile registers (EEPROM). User RAM occupies Address 0x00 to

Address 0xDF; the EEPROM occupies Address 0xF800 to

Address 0xFBFF.

•

To write a register address to the RAM for a subsequent

single byte read from the same address, or for a block read

or a block write starting at that address, as shown in Figure 39.

1

2

3

4

5

6

Data can be written to and read from both the RAM and the

EEPROM as single data bytes. Data can be written only to

unprogrammed EEPROM locations. To write new data to a

programmed location, the location contents must first be erased.

EEPROM erasure cannot be done at the byte level. The EEPROM

is arranged as 32 pages of 32 bytes each, and an entire page must

be erased.

RAM

SLAVE

S

W

A

ADDRESS

A

P

ADDRESS

(0x00 TO 0xDF)

Figure 39. Setting a RAM Address for Subsequent Read

•

To erase a page of EEPROM memory. EEPROM memory

can be written to only if it is unprogrammed. Before writing

to one or more EEPROM memory locations that are already

programmed, the page(s) containing those locations must

first be erased. EEPROM memory is erased by writing a

command byte.

Page erasure is enabled by setting Bit 2 in the UPDCFG register

(Address 0x90) to 1. If this bit is not set, page erasure cannot

occur, even if the command byte (0xFE) is programmed across

the SMBus.

The master sends a command code telling the slave device to

erase the page. The ADM1069 command code for a page

erasure is 0xFE (1111 1110). Note that, for a page erasure

to take place, the page address must be given in the previous

write word transaction (see the Write Byte/Word section).

In addition, Bit 2 in the UPDCFG register (Address 0x90)

must be set to 1.

WRITE OPERATIONS

The SMBus specification defines several protocols for different

types of read and write operations. The following abbreviations

are used in Figure 39 to Figure 47:

•

S = Start

P = Stop

R = Read

W = Write

A = Acknowledge

1

2

3

4

5

6

COMMAND

BYTE

(0xFE)

SLAVE

ADDRESS

S

W

A

P

Figure 40. EEPROM Page Erasure

= No acknowledge

A

As soon as the ADM1069 receives the command byte,

page erasure begins. The master device can send a stop

command as soon as it sends the command byte. Page

erasure takes approximately 20 ms. If the ADM1069 is

accessed before erasure is complete, it responds with a

no acknowledge (NACK).

The ADM1069 uses the following SMBus write protocols.

Send Byte

In a send byte operation, the master device sends a single

command byte to a slave device, as follows:

1. The master device asserts a start condition on SDA.

2. The master sends the 7-bit slave address followed by the

write bit (low).

3. The addressed slave device asserts an acknowledge (ACK)

on SDA.

4. The master sends a command code.

5. The slave asserts ACK on SDA.

6. The master asserts a stop condition on SDA and the

transaction ends.

Rev. C | Page 28 of 32

ADM1069

Write Byte/Word

Block Write

In a write byte/word operation, the master device sends a

command byte and one or two data bytes to the slave device,

as follows:

In a block write operation, the master device writes a block of

data to a slave device. The start address for a block write must

have been set previously. In the ADM1069, a send byte opera-

tion sets a RAM address, and a write byte/word operation sets

an EEPROM address, as follows:

1. The master device asserts a start condition on SDA.

2. The master sends the 7-bit slave address followed by the

write bit (low).

3. The addressed slave device asserts an ACK on SDA.

4. The master sends a command code.

5. The slave asserts an ACK on SDA.

6. The master sends a data byte.

7. The slave asserts an ACK on SDA.

8. The master sends a data byte (or asserts a stop condition).

9. The slave asserts an ACK on SDA.

10. The master asserts a stop condition on SDA to end the

transaction.

1. The master device asserts a start condition on SDA.

2. The master sends the 7-bit slave address followed by

the write bit (low).

3. The addressed slave device asserts an ACK on SDA.

4. The master sends a command code that tells the slave

device to expect a block write. The ADM1069 command

code for a block write is 0xFC (1111 1100).

5. The slave asserts an ACK on SDA.

6. The master sends a data byte that tells the slave device how

many data bytes are being sent. The SMBus specification

allows a maximum of 32 data bytes in a block write.

7. The slave asserts an ACK on SDA.

In the ADM1069, the write byte/word protocol is used for the

following three purposes:

8. The master sends N data bytes.

•

To write a single byte of data to the RAM. In this case, the

command byte is RAM Address 0x00 to RAM Address 0xDF,

and the only data byte is the actual data, as shown in Figure 41.

9. The slave asserts an ACK on SDA after each data byte.

10. The master asserts a stop condition on SDA to end the

transaction.

1

2

3

4

5

6

7

8

1

2

3

4

5

6

7

8

9

10

P

RAM

SLAVE

ADDRESS

SLAVE

ADDRESS

COMMAND 0xFC

(BLOCK WRITE)

BYTE

COUNT

DATA

1

DATA

2

DATA

A

N

S

W

A

ADDRESS

A

DATA

A

P

S

W

A

(0x00 TO 0xDF)

Figure 41. Single Byte Write to the RAM

Figure 44. Block Write to the EEPROM or RAM

•

To set up a 2-byte EEPROM address for a subsequent read,

write, block read, block write, or page erasure. In this case,

the command byte is the high byte of EEPROM Address 0xF8

to EEPROM Address 0xFB. The only data byte is the low byte

of the EEPROM address, as shown in Figure 42.

Unlike some EEPROM devices that limit block writes to within

a page boundary, there is no limitation on the start address

when performing a block write to EEPROM, except when

•

There are fewer than N locations from the start address to

the highest EEPROM address (0xFBFF), which results in

writing to invalid addresses.

1

2

3

4

5

6

7

8

EEPROM

ADDRESS

HIGH BYTE

(0xF8 TO 0xFB)

EEPROM

ADDRESS

LOW BYTE

(0x00 TO 0xFF)

SLAVE

ADDRESS

S

W

A

P

•

An address crosses a page boundary. In this case, both

pages must be erased before programming.

Figure 42. Setting an EEPROM Address

Note that the ADM1069 features a clock extend function for

writes to EEPROM. Programming an EEPROM byte takes

approximately 250 μs, which limits the SMBus clock for

repeated or block write operations. The ADM1069 pulls SCL

low and extends the clock pulse when it cannot accept any

more data.

Because a page consists of 32 bytes, only the three MSBs of

the address low byte are important for page erasure. The

lower five bits of the EEPROM address low byte specify the

addresses within a page and are ignored during an erase

operation.

•

To write a single byte of data to the EEPROM. In this case, the

command byte is the high byte of EEPROM Address 0xF8

to EEPROM Address 0xFB. The first data byte is the low

byte of the EEPROM address, and the second data byte is

the actual data, as shown in Figure 43.

1

2

3

4

5

6

7

8

9

10

EEPROM

ADDRESS

HIGH BYTE

(0xF8 TO 0xFB)

EEPROM

ADDRESS

LOW BYTE

(0x00 TO 0xFF)

SLAVE

ADDRESS

S

W

A

DATA

A

P

Figure 43. Single Byte Write to the EEPROM

Rev. C | Page 29 of 32

ADM1069

9. The ADM1069 sends a byte-count data byte that tells the

master how many data bytes to expect. The ADM1069

always returns 32 data bytes (0x20), which is the maximum

allowed by the SMBus Version 1.1 specification.

10. The master asserts an ACK on SDA.

READ OPERATIONS

The ADM1069 uses the following SMBus read protocols.

Receive Byte

In a receive byte operation, the master device receives a single

byte from a slave device, as follows:

11. The master receives 32 data bytes.

12. The master asserts an ACK on SDA after each data byte.

13. The master asserts a stop condition on SDA to end the

transaction.

1. The master device asserts a start condition on SDA.

2. The master sends the 7-bit slave address followed by the

read bit (high).

3. The addressed slave device asserts an ACK on SDA.

4. The master receives a data byte.

1

2

3

4

5

6

7

8

9

10 11 12

SLAVE

ADDRESS

COMMAND 0xFD

(BLOCK READ)

SLAVE

ADDRESS

BYTE

COUNT

DATA

1

S

W

A

S

R A

A

5. The master asserts a NACK on SDA.

6. The master asserts a stop condition on SDA, and the

transaction ends.

13

P

DATA

32

A

In the ADM1069, the receive byte protocol is used to read a

single byte of data from a RAM or EEPROM location whose

address has previously been set by a send byte or write byte/

word operation, as shown in Figure 45.

Figure 46. Block Read from the EEPROM or RAM

Error Correction

The ADM1069 provides the option of issuing a packet error

correction (PEC) byte after a write to the RAM, a write to the

1

2

3

4

5

6

SLAVE

ADDRESS

S

R

A

DATA

A

P

EEPROM, a block write to the RAM/EEPROM, or a block read

from the RAM/ EEPROM. This option enables the user to verify

that the data received by or sent from the ADM1069 is correct.

The PEC byte is an optional byte sent after the last data byte has

been written to or read from the ADM1069. The protocol is the

same as a block read for Step 1 to Step 12 and then proceeds as

follows:

Figure 45. Single Byte Read from the EEPROM or RAM

Block Read

In a block read operation, the master device reads a block of

data from a slave device. The start address for a block read must

have been set previously. In the ADM1069, this is done by a

send byte operation to set a RAM address, or a write byte/word

operation to set an EEPROM address. The block read operation

itself consists of a send byte operation that sends a block read

command to the slave, immediately followed by a repeated start

and a read operation that reads out multiple data bytes, as

follows:

13. The ADM1069 issues a PEC byte to the master. The master

checks the PEC byte and issues another block read, if the

PEC byte is incorrect.

14. A NACK is generated after the PEC byte to signal the end

of the read.

15. The master asserts a stop condition on SDA to end the

transaction.

1. The master device asserts a start condition on SDA.

2. The master sends the 7-bit slave address followed by the

write bit (low).

3. The addressed slave device asserts an ACK on SDA.

4. The master sends a command code that tells the slave

device to expect a block read. The ADM1069 command

code for a block read is 0xFD (1111 1101).

5. The slave asserts an ACK on SDA.

Note that the PEC byte is calculated using CRC-8. The frame

check sequence (FCS) conforms to CRC-8 by the polynomial

C(x) = x⁸+ x²+ x¹+ 1

See the SMBus Version 1.1 specification for details.

An example of a block read with the optional PEC byte is shown

in Figure 47.

6. The master asserts a repeat start condition on SDA.

7. The master sends the 7-bit slave address followed by the

read bit (high).

1

2

3

4

5

6

7

8

9

10 11 12

SLAVE

ADDRESS

COMMAND 0xFD

(BLOCK READ)

SLAVE

ADDRESS

BYTE

COUNT

DATA

1

S

W

A

S

R A

A

8. The slave asserts an ACK on SDA.

13 14 15

DATA

32

A

PEC A P

Figure 47. Block Read from the EEPROM or RAM with PEC

Rev. C | Page 30 of 32

ADM1069

OUTLINE DIMENSIONS

0.75

0.60

0.45

1.60

MAX

9.00

BSC SQ

32

25

1

24

PIN 1

7.00

BSC SQ

TOP VIEW

(PINS DOWN)

1.45

1.40

1.35

0.20

0.09

7°

8

17

3.5°

0°

0.15

0.05

9

16

SEATING

PLANE

0.10 MAX

COPLANARITY

0.45

0.37

0.30

0.80

BSC

VIEW A

LEAD PITCH

VIEW A

° CCW

ROTATED 90

COMPLIANT TO JEDEC STANDARDS MS-026-BBA

Figure 48. 32-Lead Low Profile Quad Flat Package [LQFP]

(ST-32-2)

Dimensions shown in millimeters

6.00

BSC SQ

0.60 MAX

PIN 1

INDICATOR

31

40

1

30

PIN 1

INDICATOR

0.50

BSC

TOP

VIEW

4.25

4.10 SQ

3.95

5.75

BSC SQ

EXPOSED

PAD

(BOT TOM VIEW)

0.50

0.40

0.30

21

10

20

11

0.25 MIN

4.50

REF

12° MAX

0.80 MAX

0.65 TYP

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

0.05 MAX

0.02 NOM

1.00

0.85

0.80

0.30

0.23

0.18

COPLANARITY

0.08

0.20 REF

SECTION OF THIS DATA SHEET.

SEATING

PLANE

COMPLIANT TO JEDEC STANDARDS MO-220-VJJD-2

Figure 49. 40-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

6 mm × 6 mm Body, Very Thin Quad

(CP-40-1)

Dimensions shown in millimeters

ORDERING GUIDE

Model¹

ADM1069ASTZ

ADM1069ASTZ-REEL

ADM1069ASTZ-REEL7

ADM1069ACPZ

ADM1069ACPZ-REEL

ADM1069ACPZ-REEL7

EVAL-ADM1069LQEBZ

Temperature Range

−40°C to +85°C

Package Description

32-Lead LQFP

Package Option

ST-32-2

CP-40-1

32-Lead LQFP

40-Lead LFCSP_VQ

Evaluation Board (LQFP Version)

¹Z = RoHS Coꢀpliant Part.

Rev. C | Page 31 of 32

ADM1069

NOTES

registered trademarks are the property of their respective owners.

D04735-0-6/11(C)

Rev. C | Page 32 of 32


型号：	EVAL-ADM1069LQEBZ
厂家：	ADI
描述：	Super Sequencer with Margining Control 超音序器与控制余量
文件：	总32页 (文件大小：537K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

EVAL-ADM1069LQEBZ [ADI]

相关型号：

EVAL-ADM1073EB

EVAL-ADM1073MEB

EVAL-ADM1073MEBZ

EVAL-ADM1075EBZ

EVAL-ADM1087EB

EVAL-ADM1168LQEBZ

EVAL-ADM1184

EVAL-ADM1184EBZ

EVAL-ADM1186-1EBZ

EVAL-ADM1186-1MBZ

EVAL-ADM1186-2EBZ

EVAL-ADM1186-2MBZ