EVAL-ADM1073MEBZ [ADI]
Full-Feature â48 V Hot Swap Controller; 全功能的???? 48 V热插拔控制器
| 型号： | EVAL-ADM1073MEBZ |
| 厂家： | 
ADI |
| 描述： | Full-Feature â48 V Hot Swap Controller |
| 文件： | 总24页 (文件大小：376K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Full-Feature −48 V Hot Swap Controller
Data Sheet
ADM1073
FEATURES
FUNCTIONAL BLOCK DIAGRAM
Precision inrush linear current limit
Soft start inrush current limit profiling
Precision maximum on-time in current limit
Maximum on-time modulated by FET drain voltage for
additional SOA protection
Adjustable PWM retry scheme and multiple device cascading
capability for charging large capacitive loads
Limited number of PWM cycles for FET SOA protection under
short circuit condition
Ability to configure device as continuous autoretry with a
5-second cooling period
Shunt regulator topology to allow very large transient input
supplies
V
SPLYGD
IN
PWRGD
DRAIN
V
AND
CC
FOLDBACK
AND PWRGD
REFERENCE
GENERATOR
OVERVOLTAGE
DETECTOR
OV
UV
V
IN
UNDERVOLTAGE
DETECTOR
50∝A
100mV(MAX)
GATE
SOFT START
CONTROL
SS
SENSE
tON CONTROL
TIMER
FAULT TIMER
AND CONTROL
V
EE
5 SECOND
SHUTDOWN
Separate UV and OV pins for programming allowable input
supply window
PWM
TIMEOUT
OSCILLATOR
Programmable OV hysteresis using current source into pin
when supply is high
SHDN
RESTART
LATCHED
Programmable UV hysteresis using current sink from pin
when supply is low
Figure 1.
output indicates when capacitor charging complete
PWRGD
APPLICATIONS
output indicates when supply is within
Central office switching
SPLYGD
valid window
Telecommunication and data communication equipment
−48 V distributed power systems
Negative power supply control
High availability servers
output indicates the end of the retry cycle before
LATCHED
load capacitance is charged
input for user-commanded shutdown
SHDN
input for user-triggered 5-second shutdown and
autorestart— virtual card reseat
RESTART
−48 V power supply modules
Disk arrays
GENERAL DESCRIPTION
The ADM1073 is a full-feature, negative voltage, hot swap
controller that allows boards to be safely inserted and removed
from a live −48 V backplane. The part provides precise and
robust current limiting, and protection against both transient
and nontransient short circuits in overvoltage and undervoltage
conditions. The ADM1073 can operate from a negative voltage
of −18 V to −80 V and can tolerate transient voltages of up to
−200 V.
A built-in soft start function allows control of the inrush
current profile by an external capacitor on the soft start (SS)
pin.
An external capacitor on the TIMER pin determines the time
for which the FET gate is controlled to be high when maximum
inrush current flows. The ADM1073 employs a limited consec-
utive retry scheme, whereby, if the load capacitance is not fully
charged within one attempt, the FET gate is pulled low and
retries after a cooling period.
Inrush current is limited to a programmable value by control-
ling the gate drive of an external N-channel FET. The maximum
(continued on Page 3)
current limit is set by the choice of the sense resistor, RSENSE
.
Rev. B
Document Feedback
Information furnishedby Analog Devices is believedto be accurate andreliable. However, no
responsibilityisassumedbyAnalog Devices for its use, nor for anyinfringements of patents or other
rightsofthird partiesthat may result from its use. Specifications subject to change without notice. No
license isgrantedbyimplication or otherwise under anypatent or patent rights of Analog Devices.
Trademarks andregisteredtrademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2004–2013 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
ADM1073
Data Sheet
TABLE OF CONTENTS
General Description ......................................................................... 3
Timing Control—TIMER ......................................................... 15
Drain ............................................................................................ 16
Specifications..................................................................................... 4
Absolute Maximum Ratings............................................................ 6
Thermal Characteristics .............................................................. 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Descriptions............................. 7
Typical Performance Characteristics ............................................. 8
Functional Description.................................................................. 13
Hot Circuit Insertion ................................................................. 13
Initial Startup .............................................................................. 13
Board Removal ........................................................................... 14
Controlling the Current............................................................. 14
Sense............................................................................................. 15
Sense Resistor.............................................................................. 15
Soft Start (SS Pin) ....................................................................... 15
GATE............................................................................................ 15
VIN................................................................................................. 15
VEE................................................................................................. 15
PWRGD
....................................................................................... 16
LATCHED
................................................................................... 16
SPLYGD
RESTART
....................................................................................... 16
..................................................................................... 16
........................................................................................... 16
SHDN
Undervoltage/Overvoltage Detection ..................................... 16
Functionality and Timing.............................................................. 18
Live Insertion.............................................................................. 18
Overvoltage and Undervoltage Faults ..................................... 18
Soft Start ...................................................................................... 19
Current Faults ............................................................................. 20
Logic Inputs................................................................................. 21
Kelvin Sense Resistor Connection ........................................... 21
Outline Dimensions....................................................................... 22
Ordering Guide .......................................................................... 22
REVISION HISTORY
7/13—Rev. A to Rev. B
Changes to Figure 15...................................................................... 10
Changes to Figure 32...................................................................... 13
Changes to VOV Equation .............................................................. 17
2/12—Rev. 0 to Rev. A
Updated Outline Dimensions....................................................... 22
Changes to Ordering Guide .......................................................... 22
4/04—Revision 0: Initial Version
Rev. B | Page 2 of 24
Data Sheet
ADM1073
GENERAL DESCRIPTION
(continued from Page 1)
(typically −36 V) is detected on the UV pin, or if greater than
the overvoltage threshold (typically −80 V) is detected on the
OV pin. The operating voltage window of the ADM1073 is
programmable via resistor networks on the UV and OV pins.
The hysteresis levels on the undervoltage and overvoltage
detectors can also be altered (see the Undervoltage/Overvoltage
Further control of the inrush current is provided by modulating
the width of the pulses, depending on the drain-source voltage
across the FET. This allows maximum charge transfer to the
load capacitance while maintaining the FET in its safe operating
area (SOA).
The default duty cycle of the pulse train is 6%, decreasing to
2.5% with maximum FET drain-source voltage, with a
maximum of seven successive autorestarts. After seven
successive autorestarts, the fault is latched and the part goes into
shutdown, with the result that the external FET is disabled until
SPLYGD
Detection section). The
output signal indicates when
the backplane supply is within the externally programmable
operating voltage range.
Other functions include
LATCHED
the power is reset. The
the seven retries are complete.
output signal indicates when
PWRGD
•
output, which can be used to enable a power
module (the DRAIN pin is monitored to determine when
the load capacitance is fully charged)
Further programmability is offered by allowing alteration of the
default 6% ratio. An extra resistor between the TIMER pin and
EE allows the ratio of on-time to off-time to be decreased,
SHDN
•
•
input to manually disable the GATE drive
RESTART
input to remotely initiate a 5 second shutdown
V
The ADM1073 is fabricated using BiCMOS technology for
minimal power consumption and is available in a 14-lead
TSSOP package.
while a resistor between TIMER and VIN allows the ratio to be
increased.
The ADM1073 has separate UV and OV pins for undervoltage
and overvoltage detection. The FET is turned off, if a
nontransient voltage less than the undervoltage threshold
Rev. B | Page 3 of 24
ADM1073
Data Sheet
SPECIFICATIONS
VDD = 0 V, VEE = −48 V; TA = −40°C to +85°C, unless otherwise noted.
Table 1.
Parameter
Min
Typ Max
Unit
Test Conditions
BOARD SUPPLY (Not Connected Directly to Device)
Maximum Voltage Range
Limited by external components
−200 −48 −18
V
V
Typical Operating Voltage Range
VIN PIN—SHUNT REGULATOR
Operating Supply Voltage Range
Quiescent Supply Current
Maximum Shunt Supply Voltage
Undervoltage Lockout, VLKO
Power-On Reset Delay
−80
11.7
−48 −35
12.3 12.9
V
μA
V
V
ms
IIN = 0.6 mA to 2 mA
VIN = 11.7 V
IIN = 10 mA
300 500
14
8
150
UV, OV PINS—UNDERVOLTAGE AND OVERVOLTAGE DETECTION
Undervoltage Falling Threshold, VUVF
Undervoltage Hysteresis Current
Undervoltage Fault Filter
Overvoltage Rising Threshold, VOVR
Overvoltage Hysteresis Current
Overvoltage Fault Filter
825
868 910
5
0.6
1.93 2.00
5
5
mV
μA
ms
V
μA
μs
1.86
Input Current
0.2
μA
GATE PIN—FET DRIVER
Maximum Gate Voltage
Minimum Gate Voltage
Pull-Up Current
11.5
VIN(MAX)
100
V
IGATE = −1.0 μA
IGATE = 1.0 μA
VGATE = 0 V to 8 V; VSS = 2 V
VGATE = 0 V to 8 V; VSS = 0 V
VGATE > 2 V
10
−50
−36
mV
μA
μA
mA
mA
Pull-Down Current
20
50
VGATE > 5 V
SENSE PIN—CURRENT SENSE—SOFT START
Current Limit Control Loop Threshold, VACL
Circuit Breaker Limit Voltage, VCB
Fast Current Limit Voltage, VFCL
Control Loop Transconductance
Soft Start Pin Current
97
86
100 103
mV
mV
mV
μA/mV
μA
IGATE = 0 mA
90
110
4.5
5
TIMER PIN—PWM CONTROL
Minimum TIMER Pull-Up Current
18
16
37
34
19
19
39
39
1
20
20
41
41
μA
μA
μA
μA
IPWRGD < 4 μA; TA = 25°C to 85°C
IPWRGD < 4 μA
Maximum TIMER Pull-Up Current
IPWRGD = 24 μA; TA = 25°C to 85°C
IPWRGD = 24 μA
TIMER Pull-Down Current
TIMER Low Voltage Trip Point
TIMER High Voltage Trip Point
μA
V
V
0.45
2.34
0.50 0.55
2.42 2.50
Current Limit On-Time, tON
6
3
7
0.6
ms
ms
IDRAIN = 4 μA; CTIMER = 47 nF
IDRAIN = 20 μA; CTIMER = 47 nF
Current Limit On-Time, tON, with Foldback
Number of Consecutive PWM Retry Cycles
Continuous Short-Circuit Time before Latched Shutdown
s
CTIMER = 47 nF
Rev. B | Page 4 of 24
Data Sheet
ADM1073
Parameter
Min
Typ Max
Unit
Test Conditions
DRAIN (FOLDBACK) AND PWRGD
DRAIN Voltage at Which PWRGD Asserts
Maximum DRAIN Pin Current Allowable, IDRAIN(MAX)
PWRGD Output Voltage Low
1.9
2
2.1
V
RDRAIN = 3.75 M to 20 M
36
1
µA
V
VDS = 80 V; RDRAIN = 3.25 M
2
I
I
PWRGD = 2.5 mA
PWRGD = 0.5 mA
0.2
6
0.4
V
PWRGD Internal Pull-Up Current
PWRGD Output Voltage High
µA
V
VIN
RESTART
Time before Restart
Input Threshold
Glitch Filter
Internal Pull-Up Current
SHDN
5
s
V
µs
µA
1.35
1.35
1.45 1.55
5
6
Glitch Filter
5
µs
V
µA
Input Threshold
Internal Pull-Up Current
LATCHED AND SPLYGD
Output Voltage Low
1.45 1.55
6
1
2
V
V
I
I
LATCHED, ISPLYGD = 2.5 mA
LATCHED, ISPLYGD = 0.5 mA
0.2
0.4
Internal Pull-Up Current
Output Voltage High
6
VIN
µA
V
Rev. B | Page 5 of 24
ADM1073
Data Sheet
ABSOLUTE MAXIMUM RATINGS
All voltages referred to VEE, TA = 25°C, unless otherwise noted.
Table 2.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or
any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Parameter
Rating
Supply Voltage (VDD − VEE)
Maximum Shunt Supply Voltage, VSS
SENSE Pin
GATE Pin
UV Pin
OV Pin
SS Pin
TIMER Pin
DRAIN Pin
−0.3 V to −200.0 V
16 V
−2 V to +2 V
−0.3 V to +16 V
−0.3 V to +6 V
−0.3 V to +6 V
−0.3 V to +6 V
−0.3 V to +6 V
−0.3 V to +6 V
−0.3 V to +16 V
−0.3 V to +16 V
−0.3 V to +16 V
−0.3 V to +16 V
−0.3 V to +16 V
125°C
THERMAL CHARACTERISTICS
14-lead TSSOP Package:
θJA = 240°C/W
θ
JC = 43°C/W
SHDN Pin
SPLYGD Pin
LATCHED Pin
PWRGD Pin
RESTART Pin
Maximum Junction Temperature
Operating Temperature Range
Continuous Power Dissipation
Storage Temperature Range
Lead Temperature (Soldering, 10 s)
−40°C to +85°C
180 mW
−65°C to +150°C
300°C
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. B | Page 6 of 24
Data Sheet
ADM1073
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
RESTART
1
2
3
4
5
6
7
14 SHDN
13 TIMER
12 UV
V
IN
PWRGD
SS
ADM1073
11 OV
TOP VIEW
(Not to Scale)
SENSE
10 DRAIN
V
9
8
GATE
EE
LATCHED
SPLYGD
Figure 2. Pin Configuration
Table 3. Pin Function Descriptions
Pin Number Mnemonic
Function
Input Pin. Edge-triggered 5-second shutdown and automatic restart.
1
2
RESTART
VIN
Shunt Regulated Positive Supply to Chip. Connect to the positive supply rail via shunt resistor. A 1 µF
capacitor to VEE is recommended on the VIN pin.
3
4
PWRGD
SS
Open Drain Output. Signals that the hot swap is complete.
Analog Pin for Soft Start. An external capacitor on this pin sets the ramp rate of the inrush current
profile. This pin can be overdriven to alter the current limit control loop threshold.
5
6
7
8
SENSE
VEE
LATCHED
SPLYGD
Voltage Input from External Sense Resistor.
Ground Supply to Chip (usually a −48 V system supply). Also low-side sense resistor connection.
Open Drain Output. Signals the end of the PWM retry period after a current fault.
Open Drain Output. Signals that the device is not in reset and that the supply is in operating voltage
window.
9
GATE
DRAIN
OV
UV
TIMER
Output to External FET Gate Drive.
10
11
12
13
Analog Input for Monitoring of FET Drain Voltage.
Input Pin for Overvoltage Detection Circuitry.
Input Pin for Undervoltage Detection Circuitry.
Analog Pin. An external capacitor on this pin sets the maximum allowable time in current limit, the
PWM on-time, and the PWM duty cycle.
14
SHDN
Input Pin. Level-triggered device shutdown and reset.
Rev. B | Page 7 of 24
ADM1073
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
500
14.5
14.0
13.5
13.0
12.5
12.0
11.5
11.0
450
400
350
300
250
200
150
100
50
0
–50
–35
–20
–5
10
25
40
55
70
85
–50
–35
–20
–5
10
25
40
55
70
85
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 3. IIN vs. Temperature
Figure 6. VIN vs. Temperature
100.0
12
10
8
10.0
1.0
6
4
T
= –40°C
A
T
= +25°C
A
2
T
= +85°C
A
0.1
0
–50
1.5
3.5
5.5
4.5
7.5
8.5
9.5
11.5
13.5
–35
–20
–5
–10
25
40
55
70
85
0.5
2.5
6.5
10.5
12.5
14.5
TEMPERATURE (°C)
V
(V)
IN
Figure 4. IIN vs. VIN
Figure 7. Undervoltage Lockout, VLKO, vs. Temperature
10
9
8
7
6
5
4
3
2
1
0
400
350
300
250
200
150
100
50
0
–50
–50
–35
–20
–5
10
25
40
55
70
85
–35
–20
–50
10
25
40
55
70
85
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 8. POR Delay vs. Temperature
Figure 5. RZ (VIN Forward Voltage) vs. Temperature
Rev. B | Page 8 of 24
Data Sheet
ADM1073
100
90
80
70
60
50
40
30
20
10
0
50
45
40
35
30
25
20
15
10
5
SS = 2V
SS = 0V
0
8.0
–50
–35
–20
–5
10
25
40
55
70
85
8.5
9.0
9.5
10.0
10.5
11.0
11.5
12.0
TEMPERATURE (°C)
V
(V)
GATE
Figure 9. VGATEL vs. Temperature
Figure 12. IGATE (Source) vs. VGATE
14.0
13.5
13.0
12.5
12.0
11.5
11.0
10.5
10.0
60
50
40
30
20
10
0
–50
–35
–20
–5
10
25
40
55
70
85
–50
–35
–20
–5
10
25
40
55
70
85
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 10. VGATEH vs. Temperature
Figure 13. IGATE (FCL, Sink) vs. Temperature (VGATE = 2 V)
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
SS = 2V
SS = 0V
1
2
3
4
5
6
7
8
9
10
11
12
–50
–35
–20
–5
10
25
40
55
70
85
V
(V)
TEMPERATURE (°C)
GATE
Figure 11. IGATE (Source) vs. Temperature
Figure 14. IGATE (FCL, Sink) vs. VGATE
Rev. B | Page 9 of 24
ADM1073
Data Sheet
1000
980
960
940
920
900
880
860
840
820
800
10
9
8
7
6
5
4
3
2
1
0
–50
–35
–20
–5
10
25
40
55
70
70
70
85
85
85
–50
–35
–20
–5
10
25
40
55
70
85
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 15. UV Threshold vs. Temperature
Figure 18. OV Voltage Fault Filter Time vs. Temperature
2.00
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
1.98
1.96
1.94
1.92
1.90
1.88
1.86
1.84
1.82
1.80
–50
–35
–20
–50
10
25
40
55
–50
–35
–20
–5
10
25
40
55
70
85
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 16. OV Threshold vs. Temperature
Figure 19. ISENSE vs. Temperature (VSENSE = 50 mV)
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
80
60
40
20
0
–20
–40
–60
–80
–2
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
2.0
–50
–35
–20
–5
10
25
40
55
V
(V)
TEMPERATURE (°C)
SENSE
Figure 17. UV Voltage Fault Filter Time vs. Temperature
Figure 20. ISENSE vs. (VSENSE − VEE)
Rev. B | Page 10 of 24
Data Sheet
ADM1073
14
12
10
8
120
82.0nF
115
100.0nF
V
FCL
68.0nF
110
105
100
95
47.0nF
33.0nF
V
ACL
6
1.0nF
22.0nF
4
90
V
CB
2
85
10.0nF
4.7nF
50
0
80
–50
0
10
20
30
40
60
(nF)
70
80
90
100
–35
–20
–5
10
25
40
55
70
85
C
TEMPERATURE (°C)
TIMER
Figure 21. Voltage Limits for Load Current Control vs. Temperature
Figure 24. Current Limit On-Time vs. CTIMER (1 nF − 100 nF)
3.0
10
9
8
7
6
5
4
3
2
1
V
(HIGH)
TMR
2.5
2.0
1.5
1.0
0.5
0
V
(LOW)
TMR
0
–50
–35
–20
–5
10
25
40
55
70
85
–50
–35
–20
–5
10
25
40
55
70
85
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 22. High and Low TIMER Thresholds vs. Temperature
Figure 25. Current Limit PWM vs. Temperature
50
20
18
16
14
12
10
8
45
40
35
30
25
20
15
10
5
6
4
2
0
0
–50
0
1
2
3
4
5
6
7
8
9
10
–35
–20
–5
10
25
40
55
70
85
R
(MΩ)
TEMPERATURE (°C)
TIMER
Figure 23. Maximum Current Limit On-Time vs. Temperature
(IDRAIN = 4 µA, CTIMER = 47 nF)
Figure 26. Current Limit PWM vs. RTIMER
Rev. B | Page 11 of 24
ADM1073
Data Sheet
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
10.0nF
6.8nF
4.7nF
3.3nF
2.2nF
1.5nF
1.0nF
0
1
2
3
4
5
(nF)
6
7
8
9
10
–50
–35
–20
–5
10
25
40
55
70
85
C
TEMPERATURE (°C)
SS
Figure 27. Continuous Short Circuit Time before Shutdown vs. Temperature
Figure 29. Soft Start Ramp Time vs. CSS
10
9
8
7
6
5
4
3
2
1
0
10
9
8
7
6
5
4
3
2
1
0
–50
–35
–20
–5
10
25
40
55
70
85
–50
–35
–20
–5
10
25
40
55
70
85
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 30. IUV/OV vs. Temperature
RESTART
Figure 28.
Time vs. Temperature
Rev. B | Page 12 of 24
Data Sheet
ADM1073
FUNCTIONAL DESCRIPTION
HOT CIRCUIT INSERTION
INITIAL STARTUP
Inserting circuit boards into a live −48 V backplane can cause
large transient currents to be drawn as the board capacitance
charges up. These transient currents can cause glitches on the
system power supply and can permanently damage the board
connectors and components.
The ADM1073 hot swap controller normally resides on a
removable circuit board and controls the manner in which
power is applied to the board upon connection. This is achieved
using a FET, Q1, in the power path (see Figure 31). By
controlling the gate voltage of the transistor, the surge of current
to charge load capacitance can be limited to a safe value when
the board makes connection. The ADM1073 can also reside on
the backplane itself and perform the same function from there.
The ADM1073 is designed to control the manner in which a
board’s supply voltage is applied so that harmful transient
currents do not occur and the board can be safely inserted or
removed from a live backplane. Undervoltage, overvoltage, and
overcurrent protection are other features of the part. The
ADM1073 ensures that the input voltage is stable and within
tolerance before being applied to the power module.
Figure 32 shows a typical ADM1073 application circuit. When
the plug-in board is inserted into the live backplane, the −48 V
and 0 V lines connect to the live supply. This powers up the
device with the voltage on VIN exceeding VLKO. When the
voltage on the UV pin exceeds the undervoltage rising
threshold (0.868 V), it is now inside the programmed operating
voltage window. It must stay inside this window for the duration
of the power-on reset delay time, tPOR (150 ms).
PLUG-IN BOARD
SHDN
RESTART
0V
V +
IN
R
DROP
R1
R2
R3
R4
LATCHED
SPLYGD
PWRGD
LIVE
BACKPLANE
DC-DC
CONVERTER
C
ADM1073
LOAD
C
TIMER
R
C
DRAIN
SS
–48V
V
–
IN
R
FET
SENSE
Figure 31. ADM1073 Topology
V
EE
–48V RTN
5V
3.3V
2.8V
...etc.
GND
R
DROP
DC-DC
CONVERTER
V
SPLYGD
IN
PWRGD
R1
R3
V
AND
CC
FOLDBACK
AND PWRGD
R
DRAIN
REFERENCE
GENERATOR
DRAIN
OVERVOLTAGE
DETECTOR
OV
UV
V
IN
UNDERVOLTAGE
DETECTOR
50∝A
100mV(MAX)
FET
R2
R4
SOFT START
CONTROL
GATE
SS
TIMER CONTROL
SENSE
FAULT TIMER
TIMER
R
SENSE
AND CONTROL
C
SS
V
5 SECOND
SHUTDOWN
EE
PWM
TIMEOUT
OSCILLATOR
C
SHDN
RESTART
LATCHED
TIMER
R
*
TIMER
–48V
*R
IS AN OPTIONAL COMPONENT
TIMER
Figure 32. ADM1073 Application Diagram
Rev. B | Page 13 of 24
ADM1073
Data Sheet
When the device detects that the supply voltage is valid, it
ramps up the GATE voltage until the FET turns on and the load
current increases. The ADM1073 monitors the level of the
current flowing through the FET by sensing the voltage across
the external sense resistor, RSENSE. When the SENSE voltage
reaches 100 mV, the GATE pin is actively controlled, limiting
the load current. In this way, the maximum current permitted
end of the tON period the load capacitance is still demanding
maximum current. The ADM1073 now controls the FET gate to
zero for a time tOFF, determined by the time taken for the on-
chip current sink to discharge the TIMER capacitance to 0.5 V.
At the end of time tOFF, the device retries, again following the
soft start current profile. In this way, a large load capacitance
can be charged using consecutive current limit periods. The
external components should be chosen to ensure that the
capacitance is fully charged within seven TIMER periods, if the
default limited consecutive retry mode is used.
to flow through the load is set by the choice of RSENSE
.
If a change in the level of the supply voltage causes the voltage
on UV to fall below the undervoltage falling threshold (VUVF),
or the voltage on OV to rise above the overvoltage rising
threshold (VOVR), then the gate drive is disabled.
Startup into a Short Circuit or over Current Fault
The load might demand large currents at initial connection.
The ADM1073 follows the Soft Start current profile as
described for startup into a nominal load. The current is limited
at IMAX for time tON following which the FET gate is pulled low.
The FET gate is held low for time tOFF, before retrying, again
with the soft start current profile. The ADM1073 cycles through
7 retries, after which it latches the FET off, assuming the default
limited consecutive retry mode is used.
BOARD REMOVAL
If the board is removed from a card cage, the voltage on the UV
pin falls to zero (that is, outside operating range) and the GATE
drive is de-asserted, turning off the FET.
CONTROLLING THE CURRENT
The ADM1073 features the following current control functions:
Voltage Step during Normal Operation
•
•
•
•
•
Precision maximum current limit
Controlled time in current limit
Limited number of consecutive maximum current events
Current limit profiling—soft start
Overcurrent fast limit
Once the load capacitance is charged at initial board insertion
PWRGD
and a
signal is issued by the ADM1073, the load
begins to demand current. Therefore, following a step increase
in the magnitude of the supply voltage, not all the FET current
is available for charging of the load capacitance. Because the
FET is fully on following a step in the supply voltage, the
current increases immediately from ILOAD to supply charge to
the load capacitance. If the current remains below the fast
current limit, the FET gate drive amplifier controls it back to
In the following sections, five distinct system operating
conditions are described with reference to the current control
features.
Startup into Nominal Load Capacitance
I
MAX. If the current exceeds the fast current limit, the FET gate is
Once the supply voltage has exceeded the UV threshold, and
following the 0.6 ms UV filter time, the current to the load
ramps up linearly as the capacitor on the Soft Start (SS) pin is
charged to 2.5 V. At the same time, current is sourced into the
capacitor on the TIMER pin, both from an on-chip source and
via the drain resistor. Once the soft start voltage has reached
2.5 V, the current to the load is limited to IMAX (100 mV/RSENSE).
Assuming that the values of RSENSE and the TIMER capacitance
have been chosen to allow the load capacitance to charge within
one ON period (tON period), the load capacitor is fully charged
before the voltage on TIMER reaches 2.5 V. At this point, the
current to the load decreases, and the FET gate voltage increases
to VSS, connecting the supply to the load.
strongly pulled down and back into regulation with the current
at IMAX. The size of the voltage step and the headroom between
the load current and IMAX determine the time required at IMAX to
charge the load capacitance. External components should be
chosen to ensure that any expected step size leads to a
requirement of less than time tON to charge the load capacitance.
Short Circuit or Overcurrent Fault during Operation
If a short circuit or an overcurrent fault occurs during normal
operation, the FET is fully on and initially allows increased
current to flow. If the current remains below the fast current
limit, the FET gate drive amplifier controls it back to IMAX. If the
current exceeds the fast current limit, the FET gate is strongly
pulled down and back into regulation with the current at IMAX
Following a period, tON, the ADM1073 pulls the FET gate low
for a time tOFF, then retries following the soft start current
profile. If the fault persists, the ADM1073 cycles through 7
retries before latching off. If the fault clears within the 7-retry
period, the ADM1073 controls the FET gate high to allow
normal operation to continue.
.
Startup into Load with Large Capacitance
If the load capacitance is sufficiently large that to charge it fully
in one attempt would compromise the FET’s SOA, consecutive
maximum current events may be used. The use of this tech-
nique assumes that the load is not yet enabled, so negligible
load current is demanded. The initial current profiling is
identical to that for startup into a nominal load capacitance. If
the charge passed to the load in time tON with maximum current
flowing is insufficient to fully charge the load capacitance, at the
Rev. B | Page 14 of 24
Data Sheet
ADM1073
GATE
SENSE
Analog output for driving the external FET gate. This pin is
switched to VEE when the FET is off, is linearly controlled when
the FET is at the programmed inrush current limit, and is
switched to VIN when the FET is fully enhanced. The source
current capability is small to provide slow controlled turn-on,
and the sink current capability is large to provide fast turn-off.
The SENSE pin is used for sensing the voltage across an
external power sense resistor. This voltage is differentially
measured with respect to VEE, and used to control the GATE.
If SENSE is lower than 100 mV (after the soft start time), the
GATE pin is allowed to increase up to 12 V to provide
maximum FET enhancement. If the current increases such that
the SENSE pin tries to go above 100 mV, the GATE pin is
controlled in a feedback loop to ensure that the voltage across
the sense resistor is regulated at exactly 100 mV.
VIN
Positive supply pin. This current-driven supply is shunt-
regulated at 12.3 V internally, and should be connected to the
most positive input supply terminal (usually −48 V RTN or 0 V)
through a dropper resistor. The resistor should be chosen such
that it always supplies enough current to overcome the
SENSE RESISTOR
The ADM1073’s current limiting function can operate at
different current levels. The current limit is determined by
selection of the sense resistor, RSENSE. Table 4 shows how the
maximum allowable load current (ILOAD(MAX)) and the minimum
and maximum inrush currents (ILIMIT(MIN) and ILIMIT(MAX)) are
maximum quiescent supply current of the chip. Default RDROP
=
30 kΩ.
VEE
related to the value of RSENSE
.
Negative supply input. This pin should be connected directly to
the most negative input supply terminal (−48 V). This pin is
also used for differentially sensing across the external power
resistor, and should, therefore, be connected as close to the
sense resistor as possible. (See the Kelvin Sense Resistor
Connection section.)
Table 4. Minumum and Maximum Inrush Current and Load
Current Levels for Different Values of RSENSE
RSENSE (mΩ)
ILOAD(MAX) (A)
17.20
8.60
5.73
4.78
3.91
2.61
1.83
1.69
ILIMIT(MIN) (A) ILIMIT(MAX) (A)
5
19.40
9.70
6.47
5.39
4.41
2.94
2.06
1.90
1.43
1.29
1.08
20.60
10.30
6.87
5.72
4.68
3.12
2.19
2.02
1.51
1.37
1.14
10
15
18
22
33
47
51
68
75
90
TIMING CONTROL—TIMER
The TIMER pin is an analog pin that determines the maximum
on-time when the FET is in linear current limit, and controls
the PWM duty cycle for pulsed load capacitor charging. A
capacitor should be attached to this pin. When the FET is in
current limit, a 19 µA current source charges the external
capacitor. If the FET is still in current limit when the TIMER
capacitor reaches 2.5 V, the GATE driver is turned off and a
1 µA discharge current sink is turned on. The GATE remains
low until the TIMER capacitor is reduced to 0.5 V. At this point,
the GATE pin is turned on again. If the FET goes back into
current limit, the TIMER recharging starts again.
1.26
1.15
0.96
SOFT START (SS PIN)
The SS pin is used to determine the inrush current profile.
A capacitor should be attached to this pin. Whenever the FET
is requested to turn on, the SS pin is held at ground until the
SENSE pin reaches a few mV. A current source is then turned
on, which linearly ramps the capacitor up to 2.5 V. The
reference voltage for the GATE linear control amplifier is
derived from the soft start voltage, such that the inrush linear
current limit is defined as
The PWM duty cycle is set at 6% default level by the size of
these two current sources. Adding a resistor from TIMER to VEE
decreases the duty cycle. Adding a resistor from TIMER to VIN
increases the duty cycle.
In addition, a current proportional to the current into the
DRAIN pin is added to the charging current. The additional
current varies linearly with DRAIN voltage. This reduces the
maximum on-time and the percentage PWM duty cycle when
there is a large voltage across the FET.
ILIMIT = VSOFT _ START /20× RSENSE
Overdriving the SS Pin
The SS pin can be overdriven externally from 0.360 V to 1.95 V
to offset the current limit control loop threshold from 18 mV to
100 mV. This allows different current limits to be selected at
different points of operation without using multiple sense
resistors. The current limit voltage is clamped at 100 mV
maximum.
Rev. B | Page 15 of 24
ADM1073
Data Sheet
shutdown function is triggered by a low pulse of at least 5 µs at
the pin. This pin has an internal pull-up of approximately 6 µA,
allowing it to be driven by an open collector pull-down output
or a push-pull output. The input threshold is 1.5 V.
DRAIN
Analog input fed by a resistor connected to the drain of the
FET. This pin is clamped to go no higher than 4 V with respect
to VEE. Below this level, the voltage on the pin is monitored so
PWRGD
that, if it falls below 2 V, the
output can be set. Above
SHDN
the 4 V level, the current into the pin is detected and used to
modulate the maximum on-time for the linear FET driver. This
is done by summing a proportion of the drain input current
with the charging current for the TIMER timing capacitor,
thereby reducing the allowable on-time.
Level-triggered input. Allows the user to command a shutdown
of the hot swap function. When this input is set low, the GATE
output is switched to VEE to turn the FET off. This pin has an
internal pull-up of approximately 6 µA, allowing it to be driven
by an open collector pull-down output or a push-pull output.
The input threshold is 1.5 V.
PWRGD
UNDERVOLTAGE/OVERVOLTAGE DETECTION
Output to indicate when the load capacitor is fully charged.
This is an open collector output with internal pull-up to VIN.
The ADM1073 incorporates dual pin undervoltage and
overvoltage detection, with a programmable operating voltage
window. When the voltage on the UV pin falls below the UV
falling threshold or the voltage on the OV pin rises above the
OV rising threshold, a fault signal is generated that disables the
linear current regulator and results in the GATE pin being
pulled low. The voltage fault signal is time filtered so that faults
of a duration less than the UV glitch filter time (0.6 ms) and OV
glitch filter time (5 µs) do not force the gate drive low. The filter
operates only on the faulting edge, that is, on a high-to-low
transition on the undervoltage monitor and on a low-to-high
transition on the overvoltage monitor.
PWRGD
When a normal startup is initiated, the
output is
latched low when the DRAIN pin falls below 2 V. The latch is
reset, if either the input supply goes out of range or a current
limit time-out event occurs. The second of these cases ensures
that, if a voltage step of greater than 2 V is presented at the
PWRGD
input, the
flag does not go high while the load
capacitor is being charged up to the additional voltage.
LATCHED
Output to indicate when the device has completed the maxi-
mum number (7) of PWM cycles. This is an open collector
output with an internal current source pull-up. If this PWM
time-out event occurs, the GATE pin is latched low and the
–48V RTN
V
LATCHED
IN
output is set low. This condition can then be reset
by either a power cycling event or a low signal to either the
SHDN RESTART
OVERVOLTAGE
DETECTOR
input or the
LATCHED
input. By connecting the
SHDN
1.93V
signal directly to
be put into a continuous PWM mode. By connecting the
LATCHED RESTART
, the device can effectively
R1
R2
R3
R4
OV
UV
SPLYGD
signal directly to
, the device can
effectively be put into autoretry mode, with a 5-second cooling
period.
868mV
UNDERVOLTAGE
DETECTOR
SPLYGD
FET DRIVE
ENABLE
ADM1073
Output to indicate when the input supply is within the pro-
grammed voltage window. This is an open collector output with
an internal pull-up current source. For very large capacitive
loads where multiple FETs and controllers are required to meet
the inrush requirements, this output can be used to drive
directly into the UV pin of a second controller. This allows the
second FET to start 1 ms after the first one, with the added
advantage that the input supply UV detection is done on one
–48V IN
Figure 33. Undervoltage and Overvoltage Circuitry
(Standard 4-Resistor Configuration)
The operating voltage window is determined by selecting the
resistor ratios R1/R2 and R3/R4. These resistor networks form
two resistor dividers that generate the voltages at the UV and
OV pins, which are proportional to the supply voltage. By
choosing these ratios carefully, the user can program the
ADM1073 to apply the supply voltage to the load only when it is
within specific thresholds. Note that 1% tolerance resistors
should always be used to maintain the accuracy of the pro-
grammed thresholds.
controller only. The
output is asserted only when the
SPLYGD
ADM1073 is not in reset mode.
RESTART
Edge-triggered input. Allows the user to remotely command a
5-second shutdown and restart of the hot swap function,
effectively simulating a board removal and replacement. The
Rev. B | Page 16 of 24
Data Sheet
ADM1073
UV (Undervoltage)
In this manner, the user can program the value of the voltage
hysteresis by varying the parallel impedance of the resistor
divider. The OV comparator has an internal 5 µs time delay.
The voltage on the UV pin is compared to an internal 0.868 V
reference. For the implementation in Figure 33, the undervolt-
age level is then set as
If the voltage on UV or OV goes out of range (below 0.868 V on
UV or above 1.93V on OV), GATE is pulled low. If the supply
subsequently reenters the operating voltage window, the
ADM1073 restores the GATE drive.
VUV = 0.868 × (R1 + R2)/R2
If the UV pin voltage is less than 0.868 V and the comparator
trips, an internal 5 µA current sink is turned on. This pulls the
UV voltage down by
Hysteresis must be considered when reentering the operating
window, that is, VUV must increase above
V
UVHYST(PIN) = 5 µA × R1 × R2/(R1 + R2)
at the UV pin, or by
UVHYST(SUPPLY) = 5 µA × R1
0.868 V + VUVHYST(SUPPLY)
when recovering from an undervoltage fault, and VOV must
drop below
V
at the supply.
1.93 V − VOVHYST(SUPPLY)
In this manner, the user can program the value of the voltage
hysteresis by varying the parallel impedance of the resistor
divider. The UV comparator has an internal 0.6 ms time delay
to prevent nuisance shutdowns under noisy supply conditions.
when recovering from an overvoltage fault for GATE to be
restored.
Alternative UV and OV Configurations
A 2-resistor or a 3-resistor implementation can also be used to
set the UV and OV levels (see Figure 34 and Figure 35).
OV (Overvoltage)
The voltage on the UV pin is compared to an internal 1.93 V
reference. For the implementation in Figure 33, the overvoltage
level is then set as
–48V RTN
V
OV = 1.93 × (R3 + R4)/R4
R1
OV
UV
If the OV pin voltage exceeds 1.93 V and the comparator trips,
an internal 5 µA current source is turned on. This pulls the OV
voltage up by
ADM1073
R2
–48V IN
V
OVHYST(PIN) = 5 µA × R3 × R4/(R3 + R4)
at the OV pin, or by
OVHYST(SUPPLY) = 5 µA × R3
at the supply.
Figure 34. 2-Resistor UV/OV Implementation
V
–48V RTN
R1
OV
ADM1073
R2
UV
R3
–48V IN
Figure 35. 3-Resistor UV/OV Implementation
Rev. B | Page 17 of 24
ADM1073
Data Sheet
FUNCTIONALITY AND TIMING
LIVE INSERTION
The timing waveforms associated with the live insertion of a
plug-in board using the ADM1073 are shown in Figure 36. The
long connector pins are the first to make connection, and the
GND − VEE potential climbs to 48 V. As this voltage is applied,
the voltage at the VIN pin ramps to a constant 12.3 V and is held
at this level with the shunt resistor and external resistor
combination at the VIN pin. In this case, the connection pins are
staggered so that the R1/R2 and R3/R4 resistor dividers are the
last to connect to the backplane. This means that VUV and VOV
begin to ramp after the other pins connect. Note that staggered
connector pins are optional, because an internal time filter is
included on the UV pin.
Figure 37. Typical Startup Sequence
PWRGD
SPLYGD
)
(Ch1 = GATE; Ch2 = SENSE; Ch3 =
; Ch4 =
When VUV crosses the undervoltage rising threshold, it is now
inside the operating voltage window and the −48 V supply must
OVERVOLTAGE AND UNDERVOLTAGE FAULTS
SPLYGD
be applied to the load. The
output is asserted and after
a time delay, tPOR, the ADM1073 begins to ramp up the gate
drive. When the voltage on the SENSE pin reaches 100 mV (the
analog current limit level), the gate drive is held constant. When
the board capacitance is fully charged, the sense voltage begins
to drop below the analog current limit voltage and the gate
voltage is free to ramp up further. The gate voltage eventually
The waveforms for an overvoltage glitch are shown in Figure 38.
When VOV glitches above the overvoltage threshold of 1.93 V, an
overvoltage condition is detected and the GATE voltage is
pulled low. VOV begins to drop back toward the operating
voltage window, and the GATE drive is restored when the
overvoltage falling threshold (1.93 V minus preset OV
hysteresis level) is reached. Figure 38 illustrates the ADM1073’s
reactions to an overvoltage condition.
PWRGD
climbs to its maximum value of 12.3 V and the
output
is asserted. Figure 37 shows some typical startup waveforms.
–48V RTN – VEE
V
LKO
V
IN
V
UVR
V
UV
tPOR
GATE
SENSE
V
OUT
Figure 38. Timing Waveforms Associated with an Overvoltage Fault
PWRGD
SPLYGD
(Ch1 = GATE; Ch2 = OV; Ch3 =
; Ch 4 =
)
SPLYGD
PWRGD
Figure 36. Timing Waveforms Associated with a Live Insertion Event
Rev. B | Page 18 of 24
Data Sheet
ADM1073
An undervoltage glitch is dealt with in a similar way. When VUV
falls below the undervoltage threshold of 0.868 V, the GATE
voltage is pulled low. VUV begins to rise back toward the
operating voltage window, and the GATE drive is restored when
the undervoltage rising threshold (0.868 V plus preset UV
hysteresis level) is reached. Figure 39 illustrates the ADM1073’s
operation in an undervoltage situation.
Figure 41. Soft Start Profile with a 1.5 nF Capacitor
(Ch1 = GATE; Ch2 = SENSE)
Figure 39. Timing Waveforms Associated with an Undervoltage Fault
PWRGD
SPLYGD
(Ch1 = GATE; Ch2 = UV; Ch3 =
; Ch4 =
)
SOFT START
The ADM1073 offers a variable soft start feature. The value of
the capacitor on the SS pin sets the ramp rate of the inrush
current profile at startup. Figure 40 to Figure 42 show different
inrush current ramp rates for three SS capacitors.
Figure 42. Soft Start Profile with an 8.2 nF Capacitor
(Ch1 = GATE; Ch2 = SENSE)
Figure 40. Soft Start Profile with a 0.1 nF Capacitor
(Ch1 = GATE; Ch2 = SENSE)
Rev. B | Page 19 of 24
ADM1073
Data Sheet
CURRENT FAULTS
Some timing waveforms associated with overcurrent faults are
shown in the following figures. Figure 43 shows how a perma-
SPLYGD
nent current fault is dealt with after startup.
going low
indicates when the supply voltage is good. Because the output is
shorted, the sense voltage immediately rises through the 90 mV
circuit breaker threshold, and the fault timer is started. The
linear current control loop then goes into regulation at VSENSE
=
100 mV, accurately limiting the load current at the preset level.
The limited consecutive retry scheme PWMs the GATE pin
seven times. When the seventh retry occurs, the permanent
fault is deemed permanent and the part latches off. The
LATCHED
output asserts at this time. Power must now be
Figure 44. Timing Waveforms Associated with a Temporary Current Fault
Followed by a Permanent Current Fault
cycled to restart the device. This can be achieved via a manual
card reseating event (which cycles the power) or with an
(Ch1 = GATE; Ch2 = SENSE)
Figure 45 shows the behavior of the TIMER pin during a retry
cycle. Different current sources are switched in during the
on-time (TIMER ramping up) and off-times (TIMER ramping
down). This can be seen in the varying ramp-up and ramp-
down rates of TIMER below. The default ratio of tON to tOFF is
6%. This ratio can be reduced with a resistor from TIMER to
RESTART SHDN
external
or
signal.
V
EE or increased with a resistor from TIMER to VIN. The total
retry period can be extended or reduced by changing the value
of the TIMER capacitor.
Figure 43. Timing Waveforms Associated with a Current Fault at Startup,
Using Limited Consecutive Retry (Ch1 = GATE; Ch2 = SENSE;
SPLYGD
LATCHED
Ch3 =
; Ch4 =
)
LATCHED
Note that the
output can also be tied back to the
RESTART
input, giving an infinite retry during current fault
with a 5-second cool-down period after every seven retries. The
waveforms for this event are similar to those in Figure 43, but
repeats every five seconds.
Figure 45. Timing Waveforms during a Retry Cycle for CTIMER = 0.82 nF
(Ch1 = GATE; Ch2 = SENSE; Ch3 = TIMER)
Figure 44 shows the behavior of ADM1073 when a temporary
current fault occurs followed by a permanent current fault.
When the first overcurrent fault occurs, the first 97.5 mV spike
on the SENSE line can be seen. The ADM1073 retries a number
of times, and during the fifth tOFF time this current fault corrects
itself. After this time period, a no-fault condition is detected
and the limited consecutive counter is reset. GATE is reasserted.
When the overcurrent fault returns permanently, the limited
consecutive retry counter detects seven consecutive faults and
the part latches off. In this way, the ADM1073 prevents
nuisance shutdowns caused by transient shorts of a
programmable duration (typically ~0.6 s, set via TIMER, as
follows), but provides latched shutdown protection from
permanently shorted loads.
Rev. B | Page 20 of 24
Data Sheet
ADM1073
LOGIC INPUTS
KELVIN SENSE RESISTOR CONNECTION
SHDN
When using a low-value sense resistor for high current
measurement, the problem of parasitic series resistance can
arise. The lead resistance can be a substantial fraction of the
rated resistance, making the total resistance a function of lead
length. This problem can be avoided by using a Kelvin sense
connection. This type of connection separates the current path
through the resistor and the voltage drop across the resistor.
Figure 48 shows the correct way to connect the sense resistor
between the SENSE and VEE pins of the ADM1073.
Figure 46 shows assertion of the level-triggered
signal
for 150 ms, causing the ADM1073 to shut down for this
duration.
SENSE RESISTOR
CURRENT
FLOW FROM
LOAD
CURRENT
FLOW TO –48V
BACKPLANE
KELVIN SENSE TRACES
Figure 46. Timing Waveforms Associated with a RESET Event
SHDN
PWRGD
SPLYGD
; Ch4 = )
(Ch1 = GATE; Ch2 =
; Ch3 =
RESTART
Figure 47 shows the assertion of the edge-triggered
SENSE
V
EE
signal, causing the ADM1073 to shut down for approximately
five seconds before restarting automatically.
ADM1073
Figure 48. Kelvin Sensing with the ADM1073
RESTART
; Ch4 =
Figure 47. Timing Waveforms Associated with a
RESTART PWRGD
Event
SPLYGD
(Ch1 = GATE; Ch2 =
; Ch3 =
)
Rev. B | Page 21 of 24
ADM1073
Data Sheet
OUTLINE DIMENSIONS
5.10
5.00
4.90
14
8
7
4.50
4.40
4.30
6.40
BSC
1
PIN 1
0.65 BSC
1.05
1.00
0.80
1.20
MAX
0.20
0.09
0.75
0.60
0.45
8°
0°
0.15
0.05
COPLANARITY
0.10
SEATING
PLANE
0.30
0.19
COMPLIANT TO JEDEC STANDARDS MO-153-AB-1
Figure 49. 14-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-14)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
ADM1073ARUZ
ADM1073ARUZ-REEL
ADM1073ARUZ-REEL7
EVAL-ADM1073MEBZ
Temperature Range
Package Description
14-Lead TSSOP
14-Lead TSSOP
14-Lead TSSOP
Micro Evaluation Board
Package Option
RU-14
RU-14
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
RU-14
1 Z = RoHS Compliant Part.
Rev. B | Page 22 of 24
Data Sheet
NOTES
ADM1073
Rev. B | Page 23 of 24
ADM1073
NOTES
Data Sheet
©2004–2013 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04488–0–7/13(B)
Rev. B | Page 24 of 24
相关型号：
©2020 ICPDF网 联系我们和版权申明