HMC1023LP5ETR [ADI]
72 MHz Dual Programmable Low Pass Filter;
| 型号： | HMC1023LP5ETR |
| 厂家： | 
ADI |
| 描述： | 72 MHz Dual Programmable Low Pass Filter 电信 电信集成电路 |
| 文件： | 总35页 (文件大小：2051K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HMC1023LP5E
v01.0113
72 MHz DUAL PROGRAMMABLE
LOW PASS FILTER WITH DRIVER
Typical Applications
Features
The HMC1023LP5E is ideal for:
Low Noise Figure: 10 dB
High linearity:
• Baseband filtering before or after data converters
for point-to-point fixed wireless and cellular
infrastructure transceivers
In-Band Output IP3 > +30 dBm
In-Band Output IP2 > +60 dBm
Pre-programmed and/or Programmable Bandwidth:
5 MHz to 72 MHz. (Please see HMC1023LP5E
Ordering Information)
• Software defined radio applications
• Anti-aliasing and reconstruction filters
• Test and measurement equipment
• ADC driver applications
Exceptional 3 dB Bandwidth Accuracy: 2.5%
Programmable Gain: 0 or 10 dB
Integrated ADC Driver Amplifier
6th order Butterworth Magnitude & Phase Response
Automatic Filter Calibration
Externally Controlled Common Mode Output Level
Filter Bypass Option
Pin & Register Compatible to HMC900LP5E
Read/Write Serial Port Interface (SPI)
32 Lead 5x5 mm SMT Package 25 mm2
Functional Diagram
General Description
The HMC1023LP5E is a 6th order, programmable
bandwidth, fully calibrated, dual low pass filter. It
features programmable 0 or 10 dB gain and supports
arbitrary bandwidths from 5 MHz to 72 MHz. When
calibrated, the bandwidth is accurate to +/-2.5%. Built-
in filter bypass option enables wider bandwidths while
maintaining programmed gain and common mode
control settings.
Integrated ADC driver, programmable input
impedance, and adjustable output common mode
voltage from 0.9 V to 3 V with 2 Vppd signal, or lower
than 0.9 V common mode with lower signal swing
enables simple interface while achieving maximum
performance. Programmable bias settings enable
performance/power dissipation trade-off optimized for
each application.
Filter calibration is accomplished with any reference
clock rate from 20 to 80 MHz. One time programmable
(OTP) memory offers unsurpassed flexibility allowing
the user “set and forget” parameters like gain and
bandwidth setting.
Housed in a compact 5x5 mm SMT QFN package, the
HMC1023LP5E is pin and register compatible to the
existing HMC900LP5E programmable bandwidth Low
Pass Filter. It requires minimal external components
and provides a low cost alternative to more complicated
switched discrete filter architectures.
The 6th order Butterworth transfer function delivers
superior stop band rejection while maintaining both a
flat passband and minimal group delay variation.
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
For price, delivery, and to place orders: Analog Devices, Inc.,
responsibilityisassumedby AnalogDevicesfor itsuse, norforanyinfringementsofpatentsor other
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
Phone: 781-329-4700 • Order online at www.analog.com
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are thepropertyoftheir respectiveowners.
1
Application Support: Phone: 1-800-ANALOG-D
HMC1023* PRODUCT PAGE QUICK LINKS
Last Content Update: 02/23/2017
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DESIGN RESOURCES
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EVALUATION KITS
• Quality And Reliability
• HMC1023LP5 Evaluation Board
• Symbols and Footprints
DOCUMENTATION
Data Sheet
DISCUSSIONS
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• HMC1023 Data Sheet
SAMPLE AND BUY
REFERENCE MATERIALS
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Quality Documentation
TECHNICAL SUPPORT
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number.
• Semiconductor Qualification Test Report: BiCMOS-A (QTR:
2013-00235)
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HMC1023LP5E
v01.0113
72 MHz DUAL PROGRAMMABLE
LOW PASS FILTER WITH DRIVER
Table 1. Electrical Specifications
TA = +25°C, VDDI, VDDQ, VDDCAL, VDDBG, DVDD = 5V +/-5%, GND = 0V, 400 Ω load unless otherwise stated.
Parameter
Conditions
Min.
Typ.
Max.
Units
Analog Performance
min gain setting
max gain setting
0
10
dB
dB
Passband Gain [1]
[1]
5
72
MHz
MHz
%
3 dB corner frequency (fc)
Programmable to any frequency in this range
Bypass mode
75
100
2.5
uncalibrated
20
3.5
3 dB corner frequency variation
calibrated
%
3 dB corner frequency variation vs temperature
Max passband gain error[2]
over -40°C to +85°C
vs ideal 6th order LPF H(s)
at 0.1 dB BW (~0.73 fc)
at 0.5 dB BW (~0.83 fc)
at 1.0 dB BW (~ 0.89 fc)
at 3.0 dB BW (at fc)
min gain, fc = 5 MHz
min gain, fc = 28 MHz
max gain fc = 5 MHz
max gain, fc = 28 MHz
min gain, fc = 5 MHz
max gain, fc = 5 MHz
min gain fc = 28 MHz
max gain, fc = 28 MHz
min gain
0.03
0.5
% / °C
dB
0.250
0.350
0.400
0.400
Max passband group delay variation
(group delay * 3 dB frequency fc )
e.g. for 1.0 dB BW of 40 MHz (fc ~ 44.9 MHz):
max group delay variation = 0.400/ 44.9 MHz = 8.9 ns
22
22
25
25
8
nV/rtHz
nV/rtHz
nV/rtHz
nV/rtHz
nV/rtHz
nV/rtHz
nV/rtHz
nV/rtHz
dB
Output Noise (f = 1 MHz)
Output noise (f > 10*fc)
8
8
8
25
17
19
12
Noise Figure (100 Ω source)
Noise Figure (1 kΩ source)
max gain
dB
min gain
dB
max gain
dB
half scale tones at 0.8fc and
0.6fc
Input referred Passband IM3
Input referred Out of Band IM3
Input referred Out of Band IM3
Output IP3 (inband)
fc = 20 MHz
fc = 72 MHz[2]
-60
-50
dBc
dBc
half scale tones at 1.2fc and
1.6fc. IM3 product at 0.8fc
fc = 20 MHz
-60
-50
dBc
dBc
fc = 72 MHz [2]
half scale tones at 2fc and 3fc.
IM3 product at 0.5fc
fc = 20 MHz
-50
-45
dBc
dBc
fc = 72 MHz [2]
half scale tones at 0.8fc and
0.6fc
fc = 20 MHz
25
17
30
20
dBm
dBm
fc = 72 MHz
half scale tones at 1.2fc and
1.6fc. IM3 product at 0.8fc
fc = 20 MHz
Output IP3 (out of band)
Output IP3 (out of band)
Output IP2 (inband)
25
17
30
20
dBm
dBm
fc = 72 MHz [2]
half scale tones at 2fc and 3fc.
IM3 product at fc
fc = 20 MHz
25
17
30
20
dBm
dBm
fc = 72 MHz[2]
half scale tones at 0.8fc and
0.6fc IM2 product at 0.2fc
fc = 20 MHz
55
55
60
60
dBm
dBm
fc = 72 MHz [2]
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
For price, delivery, and to place orders: Analog Devices, Inc.,
responsibilityisassumedby AnalogDevicesfor itsuse, norforanyinfringementsofpatentsor other
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
Phone: 781-329-4700 • Order online at www.analog.com
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are thepropertyoftheir respectiveowners.
2
Application Support: Phone: 1-800-ANALOG-D
HMC1023LP5E
v01.0113
72 MHz DUAL PROGRAMMABLE
LOW PASS FILTER WITH DRIVER
Electrical Specifications, TA = +25°C (Continued)
Parameter
Conditions
Min.
60
Typ.
65
Max.
Units
dBm
half scale tones at 1.2fc and
1.6fc. IM2 product at 0.4fc
Output IP2 (out of band)[2]
complex signal measured at
0.8fc vs -0.8fc
Sideband Suppression (Uncalibrated)
35
45
dB
I/Q Channel Balance
magnitude
phase
dB
o
0.04
0.5
I/Q Channel Isolation
60
80
dB
Analog I/O
1000 /
400 / 100
Differential Input Impedance
Programmable
Ω
min gain
max gain
min gain
max gain
2
Vppd
Vppd
Vppd
Vppd
V
Full Scale Differential Input
(400 Ω Differential Load)
0.613
0.5
Full Scale Differential Input
(100 Ω Differential Load)
0.156
4
Input Common Mode Voltage Range
Full Scale Differential Output
1
400 Ω Differential Load
100 Ω Differential Load
2
Vppd
Full Scale Differential Output
Output Voltage Range
0.5
Vdd-0.5
3
Vppd
V
0.5
0.9
Output Common Mode Voltage Range
Digital I/O
V
Use doubler mode for clocks
between 20 MHz and 40 MHz
CALCK Frequency
20
40
40
80
MHz
CALCK Duty Cycle
SCLK Frequency
50
20
60
30
%
MHz
V
Digital Input Low Level (VIL)
Digital Input High Level (VIH)
Digital Output Low Level (VOL)
Digital Output High Level (VOH)
Power Supply
0.4
1.5
V
0.4
V
Vdd - 0.4
4.75
Analog & Digital Supplies
Dependent on Bias
5
5.25
V
Supply Current
240
mA
Power on Reset
250
us
[1] The attenuation of the filter transfer function can be calculated directly at any frequency f as: attenuation = 10*log10(1+(f/f0)^(2*6)), where f0
is the 3 dB bandwidth or corner frequency for the filter. Similarly, for a given maximum attenuation and 3 dB bandwidth, f0, the frequency
at which the attenuation is achieved can be calculated as: f=(10^(attenuation/10) -1)^(1/(2*6)) * f0. Note that for a 6th order Butterworth filter the
1 dB bandwidth is at ~89% of the filter bandwidth and 0.5 dB bandwidth is at 84% of the filter bandwidth.
[2] Specified distortion is measured with opamp_bias (Reg 02h[1:0]) settings recommended in Table 9. .
Table 2. Test Conditions
Unless otherwise specified, the following test conditions were used
Parameter
Condition
Temperature
+25 °C
Reg 06h Setting
150
Gain Setting
0 dB
bias settings (opamp_bias Reg 02h[1:0]/ drvr_bias Reg 02h[3:2])
00/10
Input Signal Level
Input/Output Common Mode Level
Output Load
2 Vppd
2V
200 Ω / Output
Analog: +5V, Digital +5V
Supply
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
For price, delivery, and to place orders: Analog Devices, Inc.,
responsibilityisassumedby AnalogDevicesfor itsuse, norforanyinfringementsofpatentsor other
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
Phone: 781-329-4700 • Order online at www.analog.com
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are thepropertyoftheir respectiveowners.
3
Application Support: Phone: 1-800-ANALOG-D
HMC1023LP5E
v01.0113
72 MHz DUAL PROGRAMMABLE
LOW PASS FILTER WITH DRIVER
Figure 1. Filter Attenuation
[1]
(all Bandwidths)
Figure 2. Filter Passband Gain Response
20
0.3
0.2
0.1
0
0
5 MHz
-20
72 MHz
-40
-60
-0.1
-0.2
5 MHz
-0.3
72 MHz
-80
-0.4
-0.5
-100
0.1
1
10
100
1000
0.1
1
10
100
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
5 MHz
28 MHz
5 MHz
28 MHz
40 MHz
50 MHz
72 MHz
7 MHz
40 MHz
50 MHz
72 MHz
Bypass
7 MHz
10 MHz
14 MHz
20 MHz
10 MHz
14 MHz
20 MHz
Figure 4. Filter 3 dB Cutoff vs
[1]
Figure 3. Filter Attenuation, 10dB Gain
Temperature, 10 MHz Bandwidth
20
5
0
5 MHz
-20
0
72 MHz
-40
-3 dB
-60
-80
-5
-100
0.1
-10
1
10
100
1000
5
6
7
8
9
10
20
FREQUENCY (MHz)
FREQUENCY (MHz)
5 MHz
7 MHz
10 MHz
14 MHz
20 MHz
28 MHz
40 MHz
50 MHz
72 MHz
Bypass
-40 C
25 C
85 C
Figure 5. Noise Figure, 100 Ω Source
Figure 6. Noise Figure, 1 kΩ Source
[2]
[2]
Impedance, 1 kΩ Impedance Selected
Impedance, 1 kΩ Impedance Selected
24
26
24
22
20
0 dB Gain
0 dB Gain
20
16
18
10 dB Gain
16
12
10 dB Gain
14
12
8
5
7
10
14
20
28
40
50
72
5
7
10
14
20
28
40
50
72
FILTER BANDWIDTH (MHz)
FILTER BANDWIDTH (MHz)
-40 C
+25 C
+85 C
[1] Degrated stop-band rejection at frequencies > 100 MHz caused by the test fixture.
[2] 1 kΩ input impedance into the HMC1023LP5E selected by writing Reg 02h[10]=0 and Reg 01h[9] = 0.
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
For price, delivery, and to place orders: Analog Devices, Inc.,
responsibilityisassumedby AnalogDevicesfor itsuse, norforanyinfringementsofpatentsor other
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
Phone: 781-329-4700 • Order online at www.analog.com
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are thepropertyoftheir respectiveowners.
4
Application Support: Phone: 1-800-ANALOG-D
HMC1023LP5E
v01.0113
72 MHz DUAL PROGRAMMABLE
LOW PASS FILTER WITH DRIVER
Figure 7. Noise Figure, 1 kΩ Source
Impedance, 100 Ω Impedance Selected
30
[3]
Figure 8. Filter Output Noise
100
28
0 dB Gain
26
72 MHz
24
22
10 dB Gain
10
20
18
5 MHz
5
7
10
14
20
28
40
50
72
0.001
0.01
0.1
1
10
100
FREQUENCY (MHz)
FILTER BANDWIDTH (MHz)
+25 C
5 MHz
7 MHz
28 MHz
40 MHz
50 MHz
72 MHz
-40 C
+85 C
10 MHz
14 MHz
20 MHz
Figure 9. Uncalibrated
Figure 10. UncalibratedSidebandRejection,
Sideband Rejection, 0 dB Gain
10 dB Gain
60
60
55
50
45
40
55
50
45
40
Internal Input Impedance Setting
35
Internal Input Impedance Setting
35
30
30
0
1
2
3
4
5
6
7
8
0
1
2
3
4
5
6
7
8
FILTER BANDWIDTH (MHz)
FILTER BANDWIDTH (MHz)
1000 W 400 W
100 W
1000 W 400 W
100 W
Figure 11. Arbitrary Bandwidth Setting 3
Figure 12. Output IP3,
[5]
[6]
dB Cutoff Frequency Error
72 MHz Bandwidth Setting, 0 dB Gain
4
50
Opamp Bias = 01
3
2
Opamp Bias = 00
Opamp Bias = 10
40
30
20
10
0
1
0
-1
-2
-3
-4
0
10
20
30
40
50
60
70
80
0
10
20
30
40
50
60
70
FREQUENCY (MHz)
ARBITRARY FILTER BANDWIDTH (MHz)
Reg02h[1:0] = 00
Reg02h[1:0] = 01
Reg02h[1:0] = 10
[3] 100 Ω source impedance used, and input impedanceo of HMC1023LP5E set to 1 kΩ
[4] 100 Ω input impedance into the HMC1023LP5E selected by writing Reg 02h[10]=1.
[5] Used recommended OpAmp bias settings (Reg 02h[1:0]) in Table 9.
[6] OIP3 and OIP2 measured from 100 Ω differential source into 400 Ω differential load. Used recommended OpAmp bias settings (Reg 02h[1:0])
in Table 9. OIP3 and OIP2 measurements can be translated from dBm into dBVrms as follows: IPx [dBVrms] = IPx [dBm] -4 dB.
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
For price, delivery, and to place orders: Analog Devices, Inc.,
responsibilityisassumedby AnalogDevicesfor itsuse, norforanyinfringementsofpatentsor other
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
Phone: 781-329-4700 • Order online at www.analog.com
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
5
Application Support: Phone: 1-800-ANALOG-D
Trademarks and registered trademarks are thepropertyoftheir respectiveowners.
HMC1023LP5E
v01.0113
72 MHz DUAL PROGRAMMABLE
LOW PASS FILTER WITH DRIVER
Figure 13. Output IP2,
Figure 14. Output IP3,
Filter Bypass Enabled, 0 dB Gain
[7]
[7]
72 MHz Bandwidth Setting, 0 dB Gain
90
50
40
30
20
10
0
80
70
60
50
40
0
10
20
30
40
50
60
70
0
10
20
30
40
50
60
70
80
90
FREQUENCY (MHz)
FREQUENCY (MHz)
Reg02h[1:0] =00
Reg02h[1:0] = 01
Reg02h[1:0] = 10
Reg02h[1:0] = 00
Reg02h[1:0] = 01
Reg02h[1:0] = 10
Figure 16. Output IP3,
Figure 15. Output IP2,
[7]
[7]
Filter Bypass Enabled, 10 dB Gain
Filter Bypass Mode Enabled, 0 dB Gain
90
50
80
70
60
50
40
40
30
20
10
0
0
10
20
30
40
50
60
70
80
90
0
10
20
30
40
50
60
70
80
90
FREQUENCY (MHz)
FREQUENCY (MHz)
Reg02h[1:0] = 00
Reg02h[1:0] = 01
Reg02h[1:0] = 10
Reg02h[1:0] = 00
Reg02h[1:0] = 01
Reg02h[1:0] = 10
Figure 18. Output IP3 vs Output Common
Mode Voltage, 30 MHz Input
Figure 17. Output IP2, Filter Bypass
Enabled, 10 dB Gain
[8]
[7]
90
80
70
60
50
40
50
40
30
20
10
0
0
10
20
30
40
50
60
70
80
90
0
1
2
3
4
5
FREQUENCY (MHz)
COMMON MODE VOLTAGE (V)
Reg02h[1:0] = 00
Reg02h[1:0] = 01
Reg02h[1:0] = 10
Reg02h[1:0] = 00
Reg02h[1:0] = 01
Reg02h[1:0] = 10
[7] OIP3 and OIP2 measured from 100 Ω differential source into 400 Ω differential load. Used recommended OpAmp bias settings (Reg 02h[1:0])
in Table 9. OIP3 and OIP2 measurements can be translated from dBm into dBVrms as follows: IPx [dBVrms] = IPx [dBm] -4 dB.
[8] 72 MHz Filter Bandwidth Selected. OIP3 and OIP2 measured from 100 Ω differential source into 400 Ω differential load. OIP3 and OIP2
measurements can be translated from dBm into dBVrms as follows: IPx [dBVrms] = IPx [dBm] -4 dB.
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
For price, delivery, and to place orders: Analog Devices, Inc.,
responsibilityisassumedby AnalogDevicesfor itsuse, norforanyinfringementsofpatentsor other
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
Phone: 781-329-4700 • Order online at www.analog.com
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
6
Application Support: Phone: 1-800-ANALOG-D
Trademarks and registered trademarks are thepropertyoftheir respectiveowners.
HMC1023LP5E
v01.0113
72 MHz DUAL PROGRAMMABLE
LOW PASS FILTER WITH DRIVER
Figure 19. Output IP2 vs Output Common
Mode Voltage, 30 MHz Input
Figure 20. Output IP3 vs Output Common
Mode Voltage, 50 MHz Input
[9]
[9]
80
70
60
50
40
30
50
40
30
20
10
0
0
1
2
3
4
5
0
1
2
3
4
5
COMMON MODE VOLTAGE (V)
COMMON MODE VOLTAGE (V)
Reg02h[1:0] = 00
Reg02h[1:0] = 01
Reg02h[1:0] = 10
Reg02h[1:0] = 00
Reg02h[1:0] = 01
Reg02h[1:0] = 10
Figure 22. Output IP3 vs Output Common
Mode Voltage, 70 MHz Input
Figure 21. Output IP2 vs Output Common
Mode Voltage, 50 MHz Input
[9]
[9]
50
40
30
20
10
0
80
70
60
50
40
30
0
1
2
3
4
5
0
1
2
3
4
5
COMMON MODE VOLTAGE (V)
COMMON MODE VOLTAGE (V)
Reg02h[1:0] = 00
Reg02h[1:0] = 01
Reg02h[1:0] = 10
Reg02h[1:0] = 00
Reg02h[1:0] = 01
Reg02h[1:0] = 10
Figure 23. OutputIP2vsOutputCommonMode
Voltage, 70 MHz Input
Figure 24. In-band Output IP3 & Output IP2
[9]
[10]
vs Filter Bandwidth & Impedance
80
70
60
50
40
30
80
90
70
80
OUTPUT IP2
Internal Input
Impedance Setting
60
70
50
60
40
50
30
40
OUTPUT IP3
20
30
5
7
10
14
20
28
40
50
72
0
1
2
3
4
5
FILTER BANDWIDTH (MHz)
COMMON MODE VOLTAGE (V)
1000 W
400 W
100 W
Reg02h[1:0] = 00
Reg02h[1:0] = 01
Reg02h[1:0] = 10
[9] 72 MHz Filter Bandwidth selected. OIP3 and OIP2 measured from 100 Ω differential source into 400 Ω differential load. OIP3 and OIP2
measurements can be translated from dBm into dBVrms as follows: IPx [dBVrms] = IPx [dBm] -4 dB
[10] OIP3 and OIP2 measured from 100 Ω differential source into 400 Ω differential load. Used recommended OpAmp bias settings (Reg 02h[1:0])
in Table 9. OIP3 and OIP2 measurements can be translated from dBm into dBVrms as follows: IPx [dBVrms] = IPx [dBm] -4 dB.
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
For price, delivery, and to place orders: Analog Devices, Inc.,
responsibilityisassumedby AnalogDevicesfor itsuse, norforanyinfringementsofpatentsor other
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
Phone: 781-329-4700 • Order online at www.analog.com
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
7
Application Support: Phone: 1-800-ANALOG-D
Trademarks and registered trademarks are thepropertyoftheir respectiveowners.
HMC1023LP5E
v01.0113
72 MHz DUAL PROGRAMMABLE
LOW PASS FILTER WITH DRIVER
Figure 25. In-bandOutputIP3&OutputIP2
Figure 26. 5 MHz Bandwidth Filter
Magnitude and Group Delay
[11]
vs Bandwidth & Temperature
80
5
90
150
70
60
50
40
30
20
OUTPUT IP2
80
70
60
50
40
30
Gain
0
75
-5
0
Group Delay
-10
-75
OUTPUT IP3
10
-15
0.1
-150
5
7
14
20
28
40
50
72
1
10
FILTER BANDWIDTH (MHz)
FREQUENCY (MHz)
-40 C
+25 C
+85 C
Figure 27. 72 MHz Bandwidth Filter
Figure 28. HMC1023LP5E Filter I/Q
Magnitude and Group Delay
Channel Isolation
20
5
20
20
0
-20
0
Gain
S21
0
-5
10
0
-20
-40
-60
-80
-100
-40
-60
Group Delay
-10
-15
-10
-20
ISOLATION
-80
-100
1
10
100
1
10
FREQUENCY (MHz)
100
FREQUENCY (MHz)
72 MHz Bandwidth
Filter Bypassed
Figure 30. Output Impedance
200
Figure 29. Input Impedance
1000
Reg02h[1:0] = 10
150
800
Reg02h[1:0] = 01
Internal Input Impedance Setting
600
100
Reg02h[1:0] = 00
50
0
400
200
0
72 MHz Bandwidth Setting
Filter Bypassed
-50
-100
1
10
100
1000
1
10
100
FREQUENCY (MHz)
1000
FREQUENCY (MHz)
1000 W
400 W
100 W
[11] OIP3 and OIP2 measured from 100 Ω differential source into 400 Ω differential load. Used recommended OpAmp bias settings (Reg 02h[1:0])
in Table 9. OIP3 and OIP2 measurements can be translated from dBm into dBVrms as follows: IPx [dBVrms] = IPx [dBm] -4 dB
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Table 3. Absolute Maximum Ratings
Stresses above those listed under Absolute Maximum Ratings may
cause permanent damage to the device. This is a stress rating only;
functional operation of the device at these or any other conditions
above those indicated in the operational section of this specification
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Nominal 5V Supply to GND
VDDCAL, VDDI, VDDQ, VDDBG,
DVDD
-0.3 to 5.5 V
-0.3 to 5.5 V
-0.3 to 5.5 V
Common Mode Inputs Pins
(CMI, CMQ)
Input and Output Pins
IIP, IIN, IQP, IQN, OIP, OIN, OQP,
OQN
ELECTROSTATIC SENSITIVE DEVICE
OBSERVE HANDLING PRECAUTIONS
Digital Pins
SEN, SDI, SCK, SDO, CALCK
SDO min load impedance
-0.3 to 5.5 V
1 kΩ
Operating Ambient Temperature
Range
-40 to +85 °C
Storage Temperature
-65 to + 150 °C
150 °C
Maximum Junction Temperature
Thermal Resistance (Ѳ
(junction to ground paddle)
)
JC
10 °C/W
Reflow Soldering
Peak Temperature
Time at Peak Temperature
260 °C
40 µs
ESD Sensitivity (HBM)
1 kV Class 1C
Table 4. Recommended Operating Conditions
Parameter
Condition
Min.
Typ.
Max.
Units
Temperature
Junction Temperature
125
85
°C
°C
Ambient Temperature
Supply Voltage
-40
VDDCAL, VDDI, VDDQ, VDDBG,DVDD
4.75
5
5.25
V
[1] Layout design guidelines set out in Qualification Test Report are strongly recommended.
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Outline Drawing
NOTES:
[1] PACKAGE BODY MATERIAL: LOW STRESS INJECTION MOLDED PLASTIC
SILICA AND SILICON IMPREGNATED.
[2] LEAD AND GROUND PADDLE MATERIAL: COPPER ALLOY.
[3] LEAD AND GROUND PADDLE PLATING: 100% MATTE TIN.
[4] DIMENSIONS ARE IN INCHES [MILLIMETERS].
[5] LEAD SPACING TOLERANCE IS NON-CUMULATIVE.
[6] PAD BURR LENGTH SHALL BE 0.15mm MAX. PAD BURR HEIGHT SHALL
BE 0.25m MAX.
[7] PACKAGE WARP SHALL NOT EXCEED 0.05mm
[8] ALL GROUND LEADS AND GROUND PADDLE MUST BE SOLDERED TO
PCB RF GOUND.
[9] REFER TO HITTITE APPLICATION NOTE FOR SUGGESTED PCB LAND
PATTERN.
Table 5. Package Information
Part Number
Package Body Material
Lead Finish
MSL Rating [1]
MSL1
Package Marking [2]
H1023
XXXX
HMC1023LP5E
RoHS-compliant Low Stress Injection Molded Plastic
100% matte Sn
[1] Max peak reflow temperature of 260 °C
[2] 4-Digit lot number XXXX
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Table 6. Pin Descriptions
Pin Number
Function
Description
Interface Schematic
The pins are not connected internally; however, all data
shown herein was measured with these pins connected to
RF/DC ground externally.
1, 3, 8 - 10,
17, 24, 25, 32
N/C
Quadrature (Q) Channel 5V Supply.
Must be locally decoupled to GND
2, 4
VDDQ
CMQ
5
Quadrature (Q) channel output common mode level
Quadrature (Q) channel positive and negative differential
outputs
6, 7
OQP, OQN
11
CALCK
Calibration clock input
12, 14, 15
SCK, SDI, SEN
SPI Data clock, data input and enable respectively.
13
16
SDO
SPI Data Output
DVDD
Digital 5V Supply. Must be locally decoupled to GND.
Inphase (I) channel negative and positive differential
outputs respectively
18, 19
OIN, OIP
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Table 6. Pin Descriptions (Continued)
Pin Number
Function
Description
Interface Schematic
20
CMI
Inphase (I) channel output common mode level
Inphase (I) Channel 5V Supply. Must be locally decoupled
to GND
21, 23
22
VDDi
VDDCAL
Calibration 5V Supply. Must be locally decoupled to GND
Inphase (I) channel positive and negative differential
inputs respectively
26, 27
IIP, IIN
28
VDDBG
Bias 5V Supply. Must be locally decoupled to GND.
1.2V Bandgap output (testing only)
29
VBG
Quadrature (Q) channel negative and positive differential
inputs respectively
30, 31
IQN, IQP
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Evaluation PCB
The circuit board used in the application should use RF circuit design techniques. Signal lines should have 50
Ohms impedance while the package ground leads and exposed paddle should be connected directly to the
ground plane similar to that shown. A sufficient number of via holes should be used to connect the top and
bottom ground planes. The evaluation circuit board shown is available from Hittite upon request.
Table 7. Evaluation Order Information
Item
Contents
Part Number
HMC1023LP5E Evaluation PCB
USB Interface Board
6’ USB A Male to USB B Female Cable
Evaluation Kit
EKIT01-HMC1023LP5E
CD ROM (Contains User Manual, Evaluation PCB Schematic, Evaluation Software)
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Evaluation PCB Schematic
To view Evaluation PCB Schematic please visit www.hittite.com and choose HMC1023LP5E from the “Search by
Part Number” pull down menu to view the product splash page.
Evaluation Setup
Figure 31. Characterization Setup Block Diagram
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HMC1023LP5E Usage Information
The HMC1023LP5E addresses different filter applications such as fixed frequency or variable bandwidth
implementations dependent on the part selected (see HMC1023LP5E Ordering Information) and the control
provided to the HMC1023LP5E. These modes provide the user with different filter options depending on the system
implementation.
An overview of these trade-offs are shown below.
Table 8. HMC1023LP5E Modes of Operation
Unprogrammed
HMC1023LP5E-00000 HMC1023LP5E-BBBGL Req’d
Pre-programmed
SPI
CALCK
Req’d
Function
Comments
Fixed Bandwidth Filter
Yes
Yes
Default Bandwidth
and Gain as defined Gain as defined by
by register defaults. pre-programming at
Bandwidth and
Default Bandwidth and Gain
setting after Power On Reset
(POR)
Pre-programmed gain and bandwidth
are defined when ordering the part. See
HMC1023LP5E Ordering Information.
No
No
(5 MHz /0dB gain)
factory.
Typical Corner Frequency Ac-
curacy at Default Bandwidth
Accuracy is with respect to bandwidth
after POR.
+/- 20 %
+/- 2.5 %
Full control over HMC1023LP5E requires
access via the digital serial port (SPI).
Variable Bandwidth Filter
Yes
Yes
Default Bandwidth
and Gain as defined Gain as defined by
by register defaults. pre-programming at
Bandwidth and
Default Bandwidth and Gain
setting after Power On Reset
(POR)
Pre-programmed gain and bandwidth
are defined when ordering the part. See
HMC1023LP5E Ordering Information.
(5 MHz /0dB gain)
factory.
Yes
No
Typical Corner Frequency Ac-
curacy at Default Bandwidth
Accuracy is with respect to bandwidth
after POR.
+/- 20 %
+/- 2.5 %
Accuracy is with respect to the desired
bandwidth.
See “Filter Bandwidth Setting” for informa-
tion regarding changing the bandwidth
after when calibration is not possible.
Typical Corner Frequency
Accuracy at all other Band-
widths
+/- 20 %
+/- 5.0 %
Full control over HMC1023LP5E requires
access via the digital serial port (SPI).
Filter calibration requires valid calibration
clock (via CALCK pin). See “RC Calibra-
tion Circuit”
Variable Bandwidth Filter
(with ability to execute User
Calibration to calibrate filter
bandwidth)
Yes
Yes
Default Bandwidth
and Gain as defined Gain as defined by
by register defaults. pre-programming at
Bandwidth and
Default Bandwidth and Gain
setting after Power On Reset
(POR)
Pre-programmed gain and bandwidth
are defined when ordering the part. See
“HMC1023LP5E Ordering Information 20”.
(5 MHz /0dB gain)
factory.
Typical Corner Frequency
Accuracy after POR (before
User Calibration)
Accuracy is with respect to bandwidth
after POR.
+/- 20 %
+/- 2.5 %
Accuracy is with respect to calibrated
bandwidth.
User Calibration requires access to the
HMC1023LP5E via the digital serial port
(SPI) and requires a valid calibration clock
(via CALCK pin).
Yes
Yes
Typical Corner Frequency Ac-
curacy after User Calibration
at calibrated bandwidth
+/- 2.5 %
+/- 2.5 %
Accuracy is with respect to the desired
bandwidth.
User Calibration requires access to the
HMC1023LP5E via the digital serial port
(SPI) and requires a valid calibration clock
(via pin CALCK).
See “Filter Bandwidth Setting” for informa-
tion regarding changing the bandwidth
after calibration when further calibration is
not possible.
Typical Corner Frequency Ac-
curacy after User Calibration
at non calibrated bandwidths
+/- 5.0 %
+/- 5.0 %
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HMC1023LP5E Application Information
Accurate, arbitrary, user defined bandwidths, programmable gain, and flexible programmable IO interface provide
the HMC1023LP5E with unmatched flexibility. This flexibility together with market leading performance, in terms of
linearity, Noise Figure, and bandwidth accuracy enable a universal solution capable of supporting numerous radio
standards, frequencies, and/or bandwidths with a single hardware platform.
The HMC1023LP5E is relevant in both transmitter and receiver applications (Figure 32 and Figure 33). In transmitter
applications the HMC1023LP5E serves as an anti-aliasing filter that rejects Digital-to-Analog Converter aliases and
ensures the desired transmitted spectral mask. In receiver applications the HMC1023LP5E serves as an Analog-to-
Digital converter driver, an anti-aliasing filter, and a blocker rejection filter all in one.
In both transmitter and receiver applications, excellent 6th order butterworth filter response with virtually no pass-band
ripple and exceptional +/-2.5% bandwidth accuracy enables simple modem designs that need not utilize complex
adaptive equalization schemes to compensate for filter ripple and group delay variation.
In such applications, together with Hittite’s Wideband PLLVCOs, the HMC1023LP5E enables truly wideband multi-
standard multi-carrier hardware platforms, software configurable to the demands of each particular application.
Compared to discrete filters, the HMC1023LP5E saves valuable board area and cost. Typically higher order discrete
filters are required to achieve comparable rejection as the HMC1023LP5E due to the inherent error tolerances in the
value of each individual component. In addition, discrete filters are fixed in bandwidth, typically requiring multiple
band specific hardware versions that tends to increase the cost relative to supporting only one hardware version for
all bands supported by the HMC1023LP5E.
The HMC1023LP5E overcomes the matching problem that discrete filters present with respect to baseband signal
processing. The matched dual filter paths provide excellent gain and phase balance between the two channels
eliminating the image problem which results from poor matching.
Figure 32. Typical Receive Path Block Diagram showing HMC1023LP5E
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Figure 33. Typical Transmit Path Block DiagramHMC1023LP5E Ordering Information
Input Interface
Input stage features a programmable input impedance (100 Ω / 400 Ω / 1 kΩ differential, or 50 Ω / 200 Ω / 500 Ω
single-ended) that is configured via Reg 01h[9] and Reg 02h[10]. Programmable impedance enables a configurable
interface, tailored to the requirements of the component driving the HMC1023LP5E. It enables maximum Noise Figure
(NF) performance regardless of the device driving the HMC1023LP5E. NF of the HMC1023LP5E with various input
impedance settings is provided in Figure 5, Figure 6 and Figure 7. Actual input impedance over frequency is shown
in Figure 29.
Wide input common mode voltage range further simplifies input interface. The HMC1023LP5E does not require any
configuration for input common mode voltage as long as the part is operated within the specifications outlined in Table
1.
The HMC1023LP5E does not require any specific impedance at the input. Input interface should be designed
according to the demands of the device driving the HMC1023LP5E, while programmable input impedance of the
HMC1023LP5E permits optimal matching and/or NF performance. Both ac-coupled and dc-coupled interfaces are
supported at the input.
Output Interface
Output common mode voltage of the HMC1023LP5E is set via CMI and CMQ pins for the in-phase and quadrature
outputs respectively. Wide output common mode voltage range simplifies interface with numerous devices. The
HMC1023LP5E‘s 0.9 V to 3 V output common mode voltage range is specified with a 2 Vppd output signal swing.
Lower common mode output voltage is supported with lower signal swing. The key requirement is that the signal
swing in combination with common mode voltage does not go below 0.5 V single-ended. Hence, as an example a
0.7 V output common mode voltage level is supported with 0.8 Vppd signal swing. Figure 18 to Figure 23 show the
effect of output common mode voltage on linearity performance (Output IP2 & Output IP3) of the HMC1023LP5E.
The plots indicate that even for a large output signal swing of 2 Vppd, the HMC1023LP5E typically maintains high
linearity performance below 0.9 V nominal output common mode limit. Figure 34 shows measured output common
mode voltage as a function of input common mode setting on CMI & CMQ pins. The plot is generated with 2 Vppd
output signal and shows that output common mode voltage follows the settings on CMI & CMQ pins well beyond the
rated 0.9 V to 3 V.
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5
4
3
2
1
0
0
1
2
3
4
5
COMMON MODE SETTING CMI & CMQ PIN (V)
Figure 34. Output vs. Input Common Mode Voltage
Output impedance of the HMC1023LP5E is nominally 10 Ω single-ended or 20 Ω differential. The HMC1023LP5E
does not require any special impedance matching at the output. The output of the HMC1023LP5E is an OpAmp driver
capable of driving small and large loads alike. Output interface of the HMC1023LP5E should be designed according
to the demands of the device the HMC1023LP5E is driving.
Linearity, Bandwidth Accuracy, and Current Consumption
As shown in Figure 25, the HMC1023LP5E is a high linearity device, typically exhibiting in excess of 30 dBm Output
IP3, and over 60 dBm Output IP2 throughout the operating range of the part. To maintain maximum performance
as measured by linearity (Output IP2 and Output IP3) and bandwidth accuracy it is recommended to use OpAmp
bias settings (Reg 02h[1:0]) outlined in Table 9. Table 9 shows that higher OpAmp bias setting, and thereby higher
current consumption is required to maintain maximum linearity performance as well as bandwidth accuracy ( < 2.5%
bandwidth error) at bandwidth settings ≥ 10 MHz. Figure 12 to Figure 23 show the effect of OpAmp bias setting (Reg
02h[1:0]) on linearity (OIP2 and OIP3) performance of the HMC1023LP5E.
Table 9. HMC1023LP5E Bias Table
Recommended
Coarse
Bandwidth
Setting
OpAmp Bias
Setting For Best
Performance
Reg 02h[1:0]
HMC1023LP5E
Typical Current
Coarse Bandwidth (MHz)
Consumption (mA)
(Reg 02h[9:6])
5
0000
0001
0010
0011
0100
0101
0110
0111
1000
00
00
00
01
01
01
01
01
10
172
172
172
227
227
227
227
227
260
7
10
14
20
28
40
50
72
Figure 12 to Figure 23 show that the higher OpAmp bias setting typically increases linearity OIP3 & OIP2 by 5 to 10 dB
at high bandwidth setting. However, they also show that the HMC1023LP5E maintains excellent linearity performance
(~60 dBm OIP2 & ~30 dBm OIP3), even at minimum OpAmp bias setting (Reg 02h[1:0] = 0).
Figure 35 shows typical calibrated filter bandwidth error (accuracy) vs OpAmp bias setting (Reg 02h[1:0]). It shows
that higher OpAmp bias is required at filter bandwidth settings ≥ 10 MHz in order to achieve ≤ +/-2.5 % bandwidth
accuracy. However it also shows that excellent bandwidth accuracy (≤ +/-5.5 %) is achievable at all filter bandwidth
settings with even the lowest OpAmp bias setting (Reg 02h[1:0]).
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6
5
4
3
Reg02[1:0] = 00
2
Reg02[1:0] = 01
1
0
Reg02[1:0] = 10
-1
-2
0
10
20
30
40
50
60
70
80
FILTER BANDWIDTH SETTING (MHz)
Figure 35. Calibrated HMC1023LP5E Bandwidth Error vs. OpAmp Bias (Reg 02h[1:0])
Hence for applications in which current consumption is an important performance criteria it is possible to reduce the
HMC1023LP5E current consumption by ~90 mA or ~450 mW at a cost of ~5 dB lower linearity performance and lower,
but still excellent bandwidth accuracy performance of ≤ +/-5.5 %.
Non-Volatile One Time Programmable (OTP) Memory
The HMC1023LP5E includes OTP (One Time Programmable) memory that enables the user to program the default
configuration of the HMC1023LP5E on start-up. The programmable settings are shown in Reg 0Ah they include:
•
•
•
•
Bandwidth
Filter bypass enable
Gain
Input impedance (100 Ω or 1kΩ differential), 400 Ω differential is also available but can only be set via SPI
interface.
•
•
OpAmp bias
Driver bias
Once the OTP memory is programmed, by default on power-up, the HMC1023LP5E enters the state programmed in
OTP memory. However, even after the OTP memory is programmed HMC1023LP5E retains full functionality, and can
be re-configured to any other state via Serial Port Interface. Therefore the configuration burned in OTP memory is only
a default configuration of the HMC1023LP5E on power up, which can be changed to any user defined configuration
after power-up using the SPI.
Detailed instructions on programming the OTP memory are provided in “One Time Programmable Memory (OTP)”
section.
Filter Programming & Calibration
Detailed description of filter bandwidth programming is provided in “Filter Bandwidth Setting” section. To achieve
the rated accuracy, each HMC1023LP5E device requires calibration at least once. Once calibrated, the settings are
always valid for that particular HMC1023LP5E.
Filter calibration requires an input clock. More information about calibration clock and calibration procedure is provided
in “RC Calibration Circuit” section. The calibration clock is only required during calibration. It is not required for the
operation of the HMC1023LP5E.
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v01.0113
72 MHz DUAL PROGRAMMABLE
LOW PASS FILTER WITH DRIVER
HMC1023LP5E Ordering Information
The HMC1023LP5E is available as product that is either un-programmed or pre-programmed. Programming is
available to a variety of filter bandwidths (defined in this context as the 3dB bandwidth).
Other options available for pre-programmed product include the single path gain and bias state as described below.
Gain and bias settings are described in Reg 02h.
When placing an order for the HMC1023LP5E please observe the following guidelines.
1. To order the un-programmed standard part please place order using the part number HMC1023LP5E-000000.
2. To order a pre-programmed HMC1023LP5E please determine the part number as described below and then
contact Hittite Sales at sales@hittite.com or call (978) 250-3343.
2.1 Minimum quantity order for the pre-programmed HMC1023LP5E-BBBGLL is 500 pieces.
3. Pre-Programmed part number description: HMC1023LP5E-BBBGL.
3.1 ‘BBB’ represents a three digit number from the Table 10 that represents the desired bandwidth setting
(3 dB bandwidth) from 5 MHz to 72 MHz (for example BBB = 050 specifies a 5 MHz corner frequency).
3.2 ‘G’ represents the gain setting of either 0 dB (G = 0) or 10 dB (G = 1).
3.3 ‘LL’ represents the OpAmp bias setting of the HMC1023LP5E. For more information please see “Linearity,
Bandwidth Accuracy, and Current Consumption” section.
For example, to order the HMC1023LP5E pre-programmed for 72 MHz 3 dB frequency, 10 dB gain, and standard low
‘00’ OpAmp bias setting please specify part number HMC1023LP5E-720100.
Table 10. Custom Part Frequency Options
BBB frequency for custom part (actual frequency is BBB x 0.1 MHz)
050
052
053
069
070
071
093
095
098
128
131
134
171
175
179
229
235
240
307
315
322
411
422
432
554
565
576
709
720
054
056
057
058
060
061
063
064
066
068
073
075
076
078
080
082
084
086
088
091
100
102
105
108
110
113
116
119
121
124
137
140
141
144
148
151
155
159
163
167
180
184
188
193
198
203
208
213
218
224
246
253
259
265
272
278
280
285
292
300
330
338
347
355
364
373
382
392
400
401
443
454
465
476
488
500
510
521
532
543
587
598
609
621
632
643
654
665
676
687
For additional information or inquiries please contact Hittite Apps Support at apps@hittite.com.
[1] The Output IP2 and Output IP3 for the two linearity settings are shown in Figure 13 and Figure 14. High linearity setting improves linearity for
bandwidths greater than 30 MHz at the cost of increased current consumption (additional 25 mA).
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
For price, delivery, and to place orders: Analog Devices, Inc.,
responsibilityisassumedby AnalogDevicesfor itsuse, norforanyinfringementsofpatentsor other
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
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HMC1023LP5E
v01.0113
72 MHz DUAL PROGRAMMABLE
LOW PASS FILTER WITH DRIVER
Theory of Operation
The HMC1023LP5E consists of the following functional blocks
1. Input Gain Stage
2. 6th Order Butterworth LPF
3. Output Driver
4. RC Calibration Circuit
5. Bias Circuit
6. One Time Programmable Memory
7. Serial Port interface
8. Built in Self Test (RC-BIST)
Input Gain Stage
The HMC1023LP5E input stage consists of a programmable 0 or 10 dB gain stage which in turn drives the 6th order
LPF. A block diagram showing input impedance of the I channel is presented below, Q channel is similar.
Figure 36. Input Stage Block Diagram
6th Order Low Pass Filter (LPF)
The LPF allows for coarse bandwidth tuning by varying the capacitive elements in the filter, while the fine bandwidth
tuning is accomplished by varying the resistors. Note that all Op-Amps in the LPF are class AB for minimum power
consumption in the filter while maintaining excellent distortion characteristics even in large signal swing conditions.
The attenuation due to the LPF can be calculated for any frequency, f, from the standard Butterworth transfer function
for a 6th order filter. Specifically the attenuation of the filter, in dB, can be calculated as:
attenuation = 10*log10(1+(f/fc)(2*6)
)
where fc is the 3 dB bandwidth or corner frequency for the filter.
Note that for a 6th order Butterworth filter the 1 dB bandwidth is 90% of fc, and the 0.3 dB bandwidth is 80% of fc.
Filter Bandwidth Setting
The 3 dB bandwidth of the HMC1023LP5E is programmable anywhere within the range from 5 MHz to 72 MHz. When
calibrated, filter bandwidth is accurate to within +/-2.5% of the programmed bandwidth, if not calibrated it is accurate
to within +/-20% of the programmed bandwidth.
The calibration of HMC1023LP5E is required to be executed only once for each individual HMC1023LP5E. Once
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
For price, delivery, and to place orders: Analog Devices, Inc.,
responsibilityisassumedby AnalogDevicesfor itsuse, norforanyinfringementsofpatentsor other
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
Phone: 781-329-4700 • Order online at www.analog.com
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HMC1023LP5E
v01.0113
72 MHz DUAL PROGRAMMABLE
LOW PASS FILTER WITH DRIVER
executed, if the calibration settings are remembered, they are always valid for a specific HMC1023LP5E.
Please note that best bandwidth accuracy is achieved when the HMC1023LP5E is calibrated at its typical operating
temperature. Programmed bandwidth varies 0.03 %/ºC.
Filter Bandwidth Configuration
The HMC1023LP5E bandwidths are configured using Coarse Bandwidth Settings in Reg 02h[9:6], and Fine Bandwidth
Settings in Reg 03h[3:0]. Coarse Bandwidth Settings select from a choice of coarse bandwidth options in Table 11,
and the Fine Bandwidth Settings further refine the selected coarse bandwidth settings according to Table 12.
In all cases, once the Reg 02h[9:6] and/or Reg 03h[3:0] have been programmed it is required to set Reg 01h[4]=1 in
order to instruct the HMC1023LP5E to use provided settings.
After calculating the settings for a given device they can be stored permanently in the non volatile memory (See “One
Time Programmable Memory (OTP)” for more information).
Uncalibrated Bandwidth Configuration
When not calibrated, the coarse bandwidth is selected via Reg 02h[9:6] according to the desired coarse bandwidth
setting in Table 11.
Example: to select bandwidth of 14 MHz simply write Reg 02h[9:6] = ‘0011’b, then write Reg 01h[4]=1 to instruct the
HMC1023LP5E to use provided settings.
If desired, it is possible to tune to an arbitrary bandwidth choice not provided in Table 11. In that case nearest coarse
bandwidth is selected via Reg 02h[9:6] according to Table 11, and the bandwidth is further refined via Reg 03h[3:0]
according to Table 12, where
Reg 03h[3:0] = fWANTED / fBW_norm_coarse_typ
,
where fBW_norm_coarse_typ corresponds to the selected typical coarse bandwidth setting in Table 11, programmed via Reg
02h[9:6].
Example: to select the bandwidth of 13 MHz, select the closest typical value in Table 11, and program Reg 02h[9:6]
accordingly (ie. Reg 02h[9:6] = ‘0011’b), then Reg 03h[3:0] = fWANTED / fBW_norm_coarse_typ = 13 MHz/14 MHz = 0.9286.
Hence from Table 12, Reg 03h[3:0] = ‘0100’. Finally, write Reg 01h[4]=1 to instruct the HMC1023LP5E to use provided
settings.
In all cases, when uncalibrated the bandwidth is accurate to within +/-20% of the programmed bandwidth.
Calibrated Bandwidth Configuration
The calibration of HMC1023LP5E is required to be executed only once for each individual HMC1023LP5E. Once
executed, if the calibration settings are remembered, they are always valid for that specific HMC1023LP5E. Detailed
instructions of how to calibrate the HMC1023LP5E are available in RC Calibration Circuit section.
When calibrated the programmed bandwidth is accurate to +/-2.5%. The HMC1023LP5E calibrated bandwidth can be
programmed in two ways, Automatic or Manual.
The automatic calibration supports only Coarse Bandwidth Settings in Table 11, whereas the Manual calibration
supports arbitrary bandwidths from 5 MHz to 72 MHz. In both cases the bandwidth is accurate to within +/-2.5%.
Calibrated Automatic Bandwidth Configuration
In Automatic bandwidth setting the user simply selects from a choice of Coarse Bandwidths in Table 11 via Reg
02h[9:6], and the HMC1023LP5E automatically programs Reg 03h[3:0] during calibration so that the selected
bandwidth is accurate to within +/-2.5%.
Example: to select bandwidth of 14 MHz simply write Reg 02h[9:6] = ‘0011’b, then write Reg 01h[4]=1 to instruct the
HMC1023LP5E to use provided settings.
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
For price, delivery, and to place orders: Analog Devices, Inc.,
responsibilityisassumedby AnalogDevicesfor itsuse, norforanyinfringementsofpatentsor other
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
Phone: 781-329-4700 • Order online at www.analog.com
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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HMC1023LP5E
v01.0113
72 MHz DUAL PROGRAMMABLE
LOW PASS FILTER WITH DRIVER
Calibrated Manual Bandwidth Configuration
Manual bandwidth setting enables arbitrary user defined bandwidths between 5 MHz and 72 MHz accurate to within
+/-2.5%. The coarse bandwidth is selected from Table 11 via Reg 02h[9:6], and that bandwidth is further refined using
selections in Table 12 via Reg 03h[3:0].
Initially the calibration result is read from Reg 09h[23:0]. Then required Coarse Bandwidth selection is calculated as
follows:
f
BW_norm_coarse = fWANTED * (Reg 09h[23:0] + 153600)/10370000
(EQ 1)
where fWANTED is the desired arbitrary bandwidth. The Coarse Bandwidth nearest to calculated fBW_norm_coarse is selected
from Table 11 and written to Reg 02h[9:6].
To calculate the Fine Bandwidth Setting fine_tune_ratio is calculated as shown in (EQ 2):
fine_tune_ratio = fBW_norm_coarse / fBW_norm_coarse_typ
(EQ 2)
where the fBW_norm_coarse is given in (EQ 1), and fBW_norm_coarse_typ is the nearest corresponding bandwidth in Table 11. Then
Fine Bandwidth Setting is selected from a nearest column in Table 12 that corresponds to the calculated fine_tune_
ratio and programmed to Reg 03h[3:0].
Example: to select the bandwidth of 13 MHz, initially read Reg 09h[23:0] (in this example Reg 09h[23:0] = 10470000).
Then according to (EQ 1), fBW_norm_coarse = 13 MHz * (10470000 + 153600)/10370000 = 13.318 MHz. Select the closest
typical value in Table 11 to 13.318 MHz and program Reg 02h[9:6] accordingly (ie. Reg 02h[9:6] = ‘0011’b), then Reg
03h[3:0] = fWANTED / fBW_norm_coarse_typ = 13.317917 MHz/14 MHz = 0.95128. Hence from Table 12, Reg 03h[3:0] = ‘0101’.
Finally, write Reg 01h[4]=1 to instruct the HMC1023LP5E to use provided settings.
Please note that the HMC1023LP5E Evaluation Software distributed with HMC1023LP5E Evaluation Kits implements
this Calibrated Arbitrary Bandwidth algorithm.
Table 11. Normalized Bandwidth Look up Table
fBW_norm_coarse
coarse_bandwidth_code[3:0]
min
typ
max
(MHz)
(MHz)
(MHz)
0000
0001
0010
0011
0100
0101
0110
0111
1000
3.948
5.527
5
6.050
8.470
7
7.896
10
14
20
28
40
50
72
12.100
16.940
24.200
33.880
48.400
60.500
87.120
11.054
15.792
22.109
31.584
39.480
56.851
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
For price, delivery, and to place orders: Analog Devices, Inc.,
responsibilityisassumedby AnalogDevicesfor itsuse, norforanyinfringementsofpatentsor other
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
rights of third parties that may result from its use. Specifications subject to change without notice. No
Phone: 781-329-4700 • Order online at www.analog.com
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are thepropertyoftheir respectiveowners.
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HMC1023LP5E
v01.0113
72 MHz DUAL PROGRAMMABLE
LOW PASS FILTER WITH DRIVER
Table 12. Calibration Code Look up Table
fine_tune_ratio
fine_bandwidth_code [3:0]
min
typ
max
(MHz/MHz)
(MHz/MHz)
(MHz/MHz)
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
0.790
0.818
0.846
0.878
0.909
0.943
0.976
1.012
1.048
1.078
1.116
1.155
0.803
0.832
0.862
0.893
0.926
0.959
0.994
1.030
1.063
1.097
1.136
1.183
0.818
0.846
0.878
0.909
0.943
0.976
1.012
1.048
1.078
1.116
1.155
1.210
To reprogram the HMC1023LP5E to any other bandwidth simply repeat the steps above.
Filter Bandwidth Setting After Calibration
In cases where ctune is unknown but the calibrated and programmed bandwidth is known, it is possible to estimate
the value of ctune based on the values of Coarse Bandwidth Code and Fine Bandwidth Code and the corresponding
values in Table 11 and Table 12.
For example, if the 3 dB bandwidth for the HMC1023LP5E was factory pre-programmed to a customer defined
requirement of 34 MHz and Reg 02h[9:6] = “0110” (Coarse Bandwidth Code) and Reg 03h[3:0] = “0010” (Fine
Bandwidth Code), as determined from Reg 0Ah for a pre-programmed part or from Reg 02h & Reg 03h for a non
programmed part, then ctune can be estimated as follows:
1. Lookup the nominal coarse bandwidth and fine bandwidth frequencies.
a. From Table 11 the nominal coarse frequency is 40 MHz
b. From Table 12 the nominal fine normalized frequency is 0.862 MHz/ MHz or simply 0.862
2. Estimate ctune as:
ctune=(40 MHz * 0.862 )/ 34 MHz = 1.0141
This value of ctune can now be used to calculate any arbitrary filter frequency as described above.
RC Calibration Circuit
The RC Calibration block uses a known user supplied clock to measure an on chip RC time constant. This measurement
is representative of the uncorrected corner frequency error for a given bandwidth for the HMC1023LP5E.
Calibration is normally done at room temperature. Refer to “Table 1. Electrical Specifications” for further details on the
variation of the 3 dB cutoff point with temperature. Typically programmed bandwidth varies 0.03 %/ºC.
With this information, the HMC1023LP5E can correctly fine tune the LPF by adjusting the resistors in the LPF to center
the corner frequency to the desired bandwidth.
To calibrate the HMC1023LP5E proceeds as follows:
1. Apply a clock signal of frequency between 20 MHz and 100 MHz on the CALCK pin (pin 11) of the
HMC1023LP5E. The clock signal only needs to be applied during the calibration procedure and is not
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responsibilityisassumedby AnalogDevicesfor itsuse, norforanyinfringementsofpatentsor other
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
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Phone: 781-329-4700 • Order online at www.analog.com
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HMC1023LP5E
v01.0113
72 MHz DUAL PROGRAMMABLE
LOW PASS FILTER WITH DRIVER
required at other time. Please note that an integrated clock doubler must be enabled for clock frequencies
less than 40 MHz. To enable the clock doubler simply write Reg 01h[5] = 1.
2. Write the applied clock signal period to Reg 05h[14:0] in picoseconds.
3. Enable the RC calibration circuit by writing Reg 01h[1] = 1.
4. Write Reg 06h[8:0] = 152d = 96h.
5. Write Reg 04h = 0 to initialize the calibration cycle.
The HMC1023LP5E indicates that the calibration is in process when Reg 08h [4]=1. When Reg 08h [4]=0 calibration
has finished. When complete, the calibration Fine Bandwidth Value can be retrieved from Reg 08h[3:0] Once calibrated
the HMC1023LP5E automatically writes the calibrated fine Fine Bandwidth values to Reg 03h[3:0] (ie. Reg 03h[3:0] =
Reg 08h[3:0]) as explained in Calibrated Automatic Bandwidth Configuration section. If desired, the calibration results
can be overridden via Reg 03h [3:0], as explained in Calibrated Manual Bandwidth Configuration section.
Output Driver
The HMC1023LP5E output driver consists of a differential class AB driver which is designed to drive typical ADC
loads directly or can drive up to 200 Ω in parallel with 50 pF to AC ground per differential output. Note that the output
common mode of the driver is controlled directly via the CMI/CMQ pin and can be set as per “Table 1. Electrical
Specifications”. Also note, that driver loading does not impact filter transfer responses.
A block diagram showing output connections is presented below.
Figure 37. Output Driver Block Diagram
Bias Circuit
A band gap reference circuit generates the reference currents used by the different sections. The bias circuit is
enabled or disabled as required with the I or Q channel as appropriate.
One Time Programmable Memory (OTP)
The HMC1023LP5E features one time programmable memory which can be programmed by the end user or ordered
from the factory precalibrated.
The OTP memory is programmed via the standard 4 wire serial port (SPI) as follows:
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HMC1023LP5E
v01.0113
72 MHz DUAL PROGRAMMABLE
LOW PASS FILTER WITH DRIVER
1. enable OTP write mode (see Reg 0Bh bit 0 enables OTP programming).
2. read the status of the OTP active flag (see Reg 08h, bit 5 is the OTP active flag). The Write Pulse Status (OTP
active flag) must be 0 to allow the OTP to be programmed.
3. write the OTP bit address to be set (Reg 0Ch). This address is a 4 bit number representing the address of the
bit to be programmed. Note that when programming a bit we change its state from 0 to 1 and this operation
cannot be reversed. OTP bit addresses can be found in Reg 08h.
4. start the OTP Write operation. Write any data to the OTP strobe register (Reg 0Dh).
5. read the status of the OTP active flag (Reg 08h, bit 5 is the OTP active flag). If bit 5 is set then the Write pulse
is still high. Repeat until bit 5 is 0 which indicates that the write pulse is finished.
6. Repeat steps 3 to 5 to program the remaining desired bits.
Note that bit 13 OTP_prg_flag must be set by the user to use OTP values.
7. When completed, disable OTP write mode (Reg 0Bh).
Power on Reset and Soft Reset
The HMC1023LP5E has a built in Power On Reset and also a serial port accessible Soft Reset. Power On Reset is
accomplished when power is cycled to the HMC1023LP5E, while Soft Reset is accomplished via the SPI by writing
Reg 00h[5] = 1 followed by writing Reg 00h[5] = 0. All chip registers will be reset to default states approximately 250us
after power up.
Serial Port Interface
The HMC1023LP5E features a four wire SPI. Four wires (SEN,SCK,SDI,SDO) are necessary to implement a SPI
Read/Write functionality, while a Write only functionality can be implemented with 3 wires (SEN,SCK,SDI). The
HMC1023LP5E SPI features a 3-bit Chip_ID that enables operation of up to 8 devices on the same SPI bus. Chip_ID
of HMC1023LP5E is set to ‘101’b.
Please note that every SPI operation is both a Read and a Write. Data is written to the HMC1023LP5E on the SDI line,
and read from the HMC1023LP5E on the SDO line every Read/Write cycle, as shown in Figure 38. Every SPI write
the HMC1023LP5E returns the data contained in the register whose address is specified in Reg 00h[4:0] prior to the
Write/Read cycle.
Hence to read from a particular HMC1023LP5E register, it is necessary to initially write the address of that register to
Register 0 (ie. Reg 00h[4:0] = REG_ADDR, where REG_ADDR is the address of the register to be read on the next
Read/Write cycle). The desired register will be read on the next (2nd) Write/Read cycle. If nothing additional is desired
to be written to the HMC1023LP5E on the 2nd Write/Read cycle, simply rewrite Reg 00h[4:0] = REG_ADDR on the
second Read/Write cycle to conclude the register read.
In summary, the Read cycle uses indirect addressing where Reg 00h contains the pointer to the address of the
register to be Read. Note that in any SPI cycle the Write data is stored in the register at the end of the cycle when SEN
goes high. This means that the address pointer (Reg 00h[4:0]) must be set prior to the Read/Write cycle in which the
desired data is read.
Typical serial port operation can be run with SCK at speeds up to 30 MHz.
Serial Port WRITE Operation
The host changes the data on the falling edge of SCK and the HMC1023LP5E reads the data on the rising edge.
A typical WRITE cycle is shown in Figure 38. It is 32 clock cycles long.
1. The host sets Serial Port Enable (SEN) low and places the MSB of the data on Serial Data Input (SDI)
followed by a rising edge on SCK.
2. HMC1023LP5E reads SDI (MSB first) on the 1st rising edge of SCK after SEN.
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HMC1023LP5E
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3. HMC1023LP5E registers the data bits, D23:D0, on the next 23 rising edges of SCK (total of 24 data bits).
4. Host places the 5 register address bits, A4:A0, on the next 5 falling edges of SCK (MSB to LSB) while the
HMC1023LP5E reads the address bits on the corresponding rising edge of SCK.
5. Host places the 3 chip address bits, CA2:CA0=[101], on the next 3 falling edges of SCK (MSB to LSB). Note
the HMC1023LP5E chip address is fixed as “5d” or “101b”.
6. SEN goes from low to high after the 32nd rising edge of SCK. This completes the WRITE cycle.
7. HMC1023LP5E also exports data back on the Serial Data Out (SDO) line. For details see the section on
READ operation.
Serial Port READ Operation
The Read data is available on SDO line. This line itself is tri-stated when the device is not being addressed. However
when the device is active and has been addressed by the SPI, the HMC1023LP5E controls the SDO line and exports
data on this line during the next SPI cycle.
HMC1023LP5E changes the data to the host on the rising edge of SCK and the host reads the data from HMC1023LP5E
on the falling edge.
A typical READ cycle is shown in Figure 38. Read cycle is 32 clock cycles long. To specifically read a register, the
address of that register must be written to dedicated Reg 00h. This requires two full cycles, one to write the
required address, and a 2nd to retrieve the data. A read cycle can then be initiated as follows;
1. The host sets SEN line low, followed by a rising edge SCK.
2. HMC1023LP5E reads SDI (MSB first) on the 1st rising edge of SCK after SEN is set low.
3. HMC1023LP5E registers the data bits in the next 23 rising edges of SCK (total of 24 data bits). The LSBs of
the data bits represent the address of the register that is intended to be read.
4. Host places the 5 register address bits on the next 5 falling edges of SCK (MSB to LSB) while the
HMC1023LP5E reads the address bits on the corresponding rising edge of SCK. For a read operation this
is “00000”b.
5. Host places the 3 chip address bits <101> on the next 3 falling edges of SCK (MSB to LSB). Note the
HMC1023LP5E chip address is fixed as “5d” or “101b”.
6. SEN goes from low to high after the 32th rising edge of SCK. This completes the first portion of the READ
cycle, in which the address of the register to be read on the next Read/Write cycle is written to Reg 00h.
7. The host sets SEN line low, followed by a rising edge SCK.
8. HMC1023LP5E places the 24 data bits, 5 address bits, and 3 Chip_ID bits, on the SDO, on each rising edge
of the SCK, commencing with the first rising edge beginning with MSB.
9. The host sets SEN line high after reading the 32 bits from the SDO output. The 32 bits consists of 24 data
bits, 5 address bits, and the 3 chip id bits.
10. This completes the READ cycle.
Note that the second Read/Write cycle is also both a Read and a Write. Hence if it is not desired to write
anything new to the HMC1023LP5E on the second Read/Write cycle simply rewrite the same data to Reg
00h that was written on the previous cycle.
Serial Port Bus Operation with Multiple Devices
The SPI bus architecture supports multiple devices on the same SPI bus. Each HMC1023LP5E on the bus requires
a dedicated SEN line to enable the appropriate device.
The SDO line is normally driven by the HMC1023LP5E during and after an SPI read/write which is addressed directly
to the HMC1023LP5E (chip address = 5d or ‘101’b). A write to the HMC1023LP5E where chip address is set to any
value other than 5d or ‘101’b is required in order to ensure that the SDO pin remains tri-stated by the HMC1023LP5E
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For price, delivery, and to place orders: Analog Devices, Inc.,
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after accessing the HMC1023LP5E. Such a write will not result in any change in the HMC1023LP5E configuration
because of the incorrect chip address.
Figure 38. SPI Timing Diagram
Table 13. Main SPI Timing Characteristics
DVDD = 5V 5%, GND = 0V
Parameter
Conditions
Min
8
Typ
Max
Units
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
t
t
t
t
t
t
t
t
SDI to SCK Setup Time
SDI to SCK Hold Time
1
2
3
4
5
6
7
8
8
SCK High Duration [
10
10
20
20
8
a]
SCK Low Duration
SEN Low Duration
SEN High Duration
SCK to SEN [
b]
SCK to SDO Out[c]
8
a. The SPI is relative insensitive to the duty cycle of SCK.
b. SEN must rise after the 32nd falling edge of SCK but before the next rising SCK edge. If SCK is shared amongst several devices this
timing must be respected.
c. Typical load to SDO 10pF, max 20pF
Built In Self Test (RC-BIST)
The HMC1023LP5E RC Calibration state machine features built in self test (RC-BIST) to facilitate improved device
testing.
The RC-BIST can be exercised as follows:
1. Apply reset to the chip via a power cycle (hard reset) or via the SPI (soft reset). Soft reset is accomplished by
writing Reg 00h = 20h, followed by writing Reg 00h = 0h.
2. Setup the RCCAL input parameters if desired. Note that the RC-BIST will work with the default settings from
power up however test coverage will improve if the following SPI registers are also accessed:
a. program the RC clock period (Reg 05h).
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v01.0113
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b. program the measurement adjustment setting (Reg 06h).
c. program the threshold adjustment settings.
3. enable BIST mode (Reg 0Eh).
4. start the BIST by writing any data to the BIST strobe register (Reg 04h). Note that the BIST will take 2^18
260k clock cycles to complete.
~
5. read the result of the BIST test. Read the value in the BIST Out register (Reg 0F). Bit 16 is the busy flag and
will be set when the BIST is still running. When this bit is reset then the BIST output value in bits 15:0 are
valid.
Note that the value of the BIST output must be compared to the expected result depending on values
programmed into the registers in step 2.
The BIST procedure can be repeated as desired to ensure adequate test coverage for the RC Calibration engine. The
suggested register settings to maximize test coverage with BIST is provided below.
Table 14. Test Conditions
Register Settings
Expected Result
Reg 05h[14:0]=65, Reg 06h[8:0]=255, Reg10h[4:0] to eg1Ah[4:0]=0d or 0h
Reg 05h[14:0]=32702, Reg 06h[8:0]=36, Reg10h[4:0] to Reg1Ah[4:0]=31d or 1Fh
Reg 05h[14:0]=10922, Reg 06h[8:0]=170, Reg10h[4:0] to Reg1Ah[4:0]=10d or Ah
Reg 05h[14:0]=21845, Reg06h[8:0]=853, Reg10h[4:0] to Reg1Ah[4:0]=21d or 15h
Reg 0Fh[15:0]=36092, Reg 09h[23:0]=14942167
Reg 0Fh[15:0]=55027, Reg 09h[23:0]=14143649
Reg 0Fh[15:0]=28618, Reg 09h[23:0]=8907563
Reg oFg[15:0]=16368, Reg 09h[23:0]=3396981
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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
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Register Map
Table 15. Reg 00h - Chip_ID (Read Only)
Bit
Name
Width Default
Description
[23:0]
Chip_ID
24 D7780 HMC1023LP5E Chip_ID.
Table 16. Reg 00h - Read Address (Write Only)
Bit
Name
Width Default
Description
[4:0]
Register Read Address
5
1
1
-
-
-
Address of the register to be read on the next read/write cycle.
Soft Reset.
1: Soft reset. It is recommended to set this bit to 0 after soft reset event (ie. after
writing Reg 00h[5] = 1)
0: No change
[5]
Soft Reset
[23:6]
Not Defined
Don’t Care.
Table 17. Reg 01h - Enable
Bit
[0]
[1]
[2]
[3]
[4]
Name
Width Default
Description
Default use stored OTP values (only if OTP is programmed)
Enable RC Calibration circuit
OTP_DontUse
1
1
1
1
1
0
0
1
1
0
cal_enable
filter_I_enable
filter_Q_enable
force_cal_code
Enable I channel gain stage, filter, and driver
Enable Q channel gain stage, filter, and driver
Force calibration setting to use SPI values (Reg 03h - Calibration)
0-- Doubler Disabled. RC Calibration clock
40 MHz<RC calibration clock<80 MHz
[5]
doubler_enable
reserved
1
3
0
1 -- Doubler Enabled. RC Calibration clock
20 MHz<RC calibration clock<40 MHz
Note: calibration clock duty cycle must be within 50% +/- 10%
[8:6]
000
Sets the I and Q channel input impedances together with Reg 01h[9].
Reg 02h[10] Reg 01h[9] impedance
0
0
1
0
1
x
1000 Ω (default)
400 Ω
100 Ω
[9]
LSB_Zinput_select
unused
1
0
(Reg 02h[10] and One Time Programmable memory Reg 0Ah[15] select between
100 Ω and 1000/400 Ω)
[23:10]
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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
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Table 18. Reg 02h - Settings
Bit
Name
Width Default
Description
Opamp bias setting.
00 -- min bias
[1:0]
opamp_bias[1:0]
2
2
01
10
11 -- max bias
opamp_bias[1:0]=01 standard bias (characterized value)
opamp_bias[1:0]=10 high linearity bias
Driver bias setting.
00 -- min bias
11 -- max bias
[3:2]
drvr_bias[1:0]
drvr_bias[1:0]=10 standard bias (characterized value)
VGA gain setting.
0: 0dB VGA gain
1: 10dB VGA gain
[4]
[5]
gain_10dB
1
1
0
0
Filter bypass setting.
0: Filter bypass disabled
1: Filter bypass enabled
bypass_filter
Sets filter coarse tuning range
0000 - 5 MHz
0001 - 7 MHz
0010 - 10 MHz
0011 - 14 MHz
0100 - 20 MHz
0101 - 28 MHz
0110 - 40 MHz
[9:6]
coarse_bandwidth_code[3:0]
4
0000
0111 - 50 MHz
1000 - 72 MHz
Sets the I and Q channel input impedances together with Reg 01h[9].
Reg 02h[10] Reg 01h[9] impedance
0
0
1
0
1
x
1000 Ω (default)
400 Ω
100 Ω
[10]
MSB_Zinput_select
unused
1
0
(Reg 02h[10] and One Time Programmable memory Reg 0Ah[15] select between
100 Ω and 1000/400 Ω)
[23:11]
Table 19. Reg 03h - Calibration
Bit
Name
fine_bandwidth_code[3:0]
unused
Width Default
Description
fine bandwidth setting override bits
(register 01 bit 4, force_cal_code, must be set).
0000 - Minimum frequency
0001
0010
0011
0100
0101
0110
0111
[3:0]
4
0000
1000
1001
1010
1011 - Maximum frequency
[23:4]
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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
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Table 20. Reg 04h - Calibration/RC-BIST Strobe
Calibration strobe register is used only to initialize a calibration cycle. Writing any value to this register serves to
request a new calibration cycle.
Note that this register is also used to start the Built In Self Test (RC-BIST) mode and this is used to test the
fault coverage of the RC calibration engine.
Bit
Name
Width Default
Description
[23:0]
Request calibration
1
0
Writing to any bit in this register starts a calibration cycle.
Table 21. Reg 05h - Clk Period
Bit
Name
clock_period[14:0]
unused
Width Default
Description
Sets the clock period for the RC calibration circuit. Clock period entered is in
[14:0]
[23:15]
15
0000h pico seconds.
i.e. 1/40 MHz clock =25000ps= 110000110101000b=61A8h
Table 22. Reg 06h - Measure Adjust
Correction value used to adjust RC Calibration result. Value is in 1.024ns increments.
Bit
Name
Width Default
Description
Correction value to ADD to counter output before counter is decoded for
calibration setting.
Number is in 2’s complement format.
[8:0]
[23:9]
meas_adj[8:0]
9
000h
Note this applies to all settings universally.
unused
Table 23. Reg 07h Unused
Table 24. Reg 08h - Calibration Status (read only)
Bit
Name
Width Default
Description
fine_bandwidth_setting (must run a calibration cycle to get valid data)
Valid states are 0000 to 1011 (see Table 3. Reg 03h - Calibration)
[3:0]
fine_bandwidth_code[3:0]
4
0000
[4]
[5]
cal_busy
1
1
Calibration active flag
OTP write active flag
OPT _write_busy
unused
[23:6]
Table 25. Reg 09h - Calibration Count (read-only)
Bit
Name
Width Default
Description
[23:0]
count_read[23:0]
24
Output of calibration counter in pico seconds (unadjusted)
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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
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Table 26. Reg 0Ah - OTP Values (read-only)
Bit
Name
Width Default
Description
OTP_fine_bandwidth_
code[3:0]
Non volatile fine_bandwidth_code[3:0]. Definition is same as per “Reg 03h -
Calibration”
[3:0]
4
OTP_course_bandwidth_
code[2:0]
[6:4]
3
Non volatile version of SPI values found in Reg 02h[6:8]
[7]
[8]
OTP_Gain_10dB
1
1
2
2
OTP_bypass_filter
OTP_opamp_bias[1:0]
OTP_drvr_bias[1:0]
Non volatile version of SPI values found in “Reg 02h - Settings”
[10:9]
[12:11]
This flag must be set if the OTP values are to be used and must be set by the
[13]
OTP_prg_flag
1
1
user.
If not set, this flag overrides bit 0 of Reg 01h.
[14]
[15]
OTP_Coarse_Bandwidth[3]
OTP__Zinput_select
unused
Non volatile version of SPI values found in Reg 02h[9]
Non volatile version of SPI value found in Reg 02h[10]
[23:16]
Table 27. Reg 0Bh - OTP Write Enable
Bit
Name
EFR_Write_enable
unused
Width Default
Description
[0]
1
0
Enables OTP Programming
[23:1]
Table 28. Reg 0Ch - OTP Write
OTP address register is used in programming of OTP.
Bit
Name
OTP Address
unused
Width Default
Description
[3:0]
4
0
Address of OTP bit to be set
[23:4]
Table 29. Reg 0Dh - OTP Write Pulse
OTP strobe register is used in programming of OTP.
Bit
Name
Width Default
Description
[23:0]
reserved
1
0
reserved
Table 30. Reg 0Eh - RC-BIST Enable
Bit
Name
enable_RCBIST_mode
unused
Width Default
Description
[0]
1
0
RC-BIST mode enable
[23:1]
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responsibilityisassumedby AnalogDevicesfor itsuse, norforanyinfringementsofpatentsor other
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
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Table 31. Reg 0Fh - RC-BIST Out
Bit
Name
Width Default
Description
[15:0]
crc_BIST[15:0]
16
1
0
0
RC-BIST CRC check result
RC-BIST busy flag. Indicates that BIST cycle is not completed and data crc_
BIST[15:0] is invalid
[16]
crc_RC-BIST_busy_flag
unused
[23:17]
Table 32. Reg 10h to Reg1A - Window Threshold
OTP strobe register is used in programming of OTP.
Bit
Name
Width Default
Description
[23:0]
reserved
reserved
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