HMC1132PM5ETR [ADI]
HMC1132PM5ETR;
| 型号： | HMC1132PM5ETR |
| 厂家： | 
ADI |
| 描述： | HMC1132PM5ETR 射频 微波 |
| 文件： | 总17页 (文件大小：363K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
27 GHz to 32 GHz,
GaAs, pHEMT, MMIC Power Amplifier
Data Sheet
HMC1132PM5E
FEATURES
FUNCTIONAL BLOCK DIAGRAM
PSAT: 29.5 dBm
High output IP3: 37 dBm
High gain: 24 dB (typical) at 29 GHz to 32 GHz
DC supply: 5 V at 650 mA
50 Ω matched input/output
32-lead, 5 mm × 5 mm LFCSP package: 25 mm2
GND
NIC
NIC
1
2
3
4
5
6
7
8
24 GND
23 NIC
HMC1132PM5E
22
NIC
21 GND
GND
RFIN
GND
NIC
20
19
RFOUT
GND
APPLICATIONS
18 NIC
17 GND
GND
Point to point radios
Point to multipoint radios
Very small aperture terminals (VSATs) and satellite
communication (SATCOM)
Military and space
PACKAGE
BASE
NIC = NOT INTERNALLY CONNECTED.
Figure 1.
GENERAL DESCRIPTION
The HMC1132PM5E is a four-stage, gallium arsenide (GaAs)
pseudomorphic high electron mobility transistor (pHEMT),
monolithic microwave integrated circuit (MMIC) power
amplifier. The device operates from 27 GHz to 32 GHz,
providing 24 dB of gain and 29.5 dBm of saturated output
power from a 5 V power supply.
multipoint radio systems. The amplifier configuration and high
gain make the HMC1132PM5E an ideal candidate for last stage
signal amplification before the antenna.
The HMC1132PM5E amplifier input/outputs (I/Os) are
internally matched to 50 Ω. The device is housed in a RoHS
compliant, premolded cavity, 5 mm × 5 mm LFCSP package,
making the device compatible with high volume surface-mount
technology (SMT) assembly equipment.
The HMC1132PM5E exhibits excellent linearity with high
output third-order intercept (IP3) of 37 dBm, and it is
optimized for high capacity, point to point and point to
Rev. 0
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Tel: 781.329.4700
Technical Support
©2018 Analog Devices, Inc. All rights reserved.
www.analog.com
HMC1132PM5E
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Interface Schematics .....................................................................5
Typical Performance Characteristics ..............................................6
Theory of Operation ...................................................................... 13
Applications Information.............................................................. 14
Application Circuit..................................................................... 14
Evaluation Board ............................................................................ 15
Bill of Materials........................................................................... 15
Evaluation Board Schematic ..................................................... 16
Outline Dimensions....................................................................... 17
Ordering Guide .......................................................................... 17
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Electrical Specifications............................................................... 3
Absolute Maximum Ratings............................................................ 4
Thermal Resistance ...................................................................... 4
ESD Caution.................................................................................. 4
Pin Configuration and Function Descriptions............................. 5
REVISION HISTORY
9/2018—Revision 0: Initial Version
Rev. 0 | Page 2 of 17
Data Sheet
HMC1132PM5E
SPECIFICATIONS
ELECTRICAL SPECIFICATIONS
TA = 25°C, VDD1 = VDD2 = 5 V, quiescent current (IDDQ) = 650 mA, and frequency range = 27 GHz to 29 GHz, unless otherwise noted.
Table 1.
Parameter
Symbol Min Typ
Max Unit
Test Conditions/Comments
FREQUENCY RANGE
27
29
GHz
dB
GAIN
19
22
Gain Variation over Temperature
0.028
dB/°C
RETURN LOSS
Input
Output
7
9
dB
dB
POWER
Output Power for 1 dB Compression P1dB
26.5 28.5
29.5
dBm
dBm
dBm
Saturated Output Power
PSAT
IP3
OUTPUT THIRD-ORDER INTERCEPT
37
Measurement taken at 5 V, 650 mA, output power (POUT
per tone = 20 dBm
)
NOISE FIGURE
NF
7
dB
V
SUPPLY VOLTAGE
VDD
IDDQ
4
6
QUIESCENT SUPPLY CURRENT
500
750
mA
Adjust the gate bias voltage (VGG) from −2 V up to 0 V to
achieve desired quiescent current (IDDQ
)
TA = 25°C, VDD1 = VDD2 = 5 V, quiescent current (IDDQ) = 650 mA, and frequency range = 29 GHz to 32 GHz, unless otherwise noted.
Table 2.
Parameter
Symbol Min Typ
Max Unit
Test Conditions/Comments
FREQUENCY RANGE
29
32
GHz
dB
GAIN
21
24
Gain Variation over Temperature
0.034
dB/°C
RETURN LOSS
Input
Output
11
14
dB
dB
POWER
Output Power for 1 dB Compression P1dB
27
29
29.5
37
dBm
dBm
dBm
dB
Saturated Output Power
OUTPUT THIRD-ORDER INTERCEPT
NOISE FIGURE
PSAT
IP3
NF
Measurement taken at 5 V, 650 mA, POUT per tone = 20 dBm
Adjust the gate bias voltage (VGG) from −2 V up to 0 V to
5.5
SUPPLY VOLTAGE
VDD
IDDQ
4
6
V
QUIESCENT SUPPLY CURRENT
500
750
mA
achieve desired quiescent current (IDDQ
)
Rev. 0 | Page 3 of 17
HMC1132PM5E
Data Sheet
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 3.
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Careful attention to
PCB thermal design is required.
Parameter
Rating
Drain Bias Voltage (VDDx
Gate Voltage (VGG)
Radio Frequency Input Power (RFIN)1
Continuous Power Dissipation (PDISS),
TBASE2 = 85°C (Derate 57.47 mW/°C
Above 85°C)
Output Load Voltage Standing Wave
Ratio (VSWR)
Storage Temperature Range
Operating Temperature Range
Peak Reflow Temperature, Moisture
Sensitivity Level 3 (MSL3)3
)
6.5 V
−2.5 V to +0.5 V
18 dBm
θJC is the junction to case thermal resistance.
5.17 W
Table 4. Thermal Resistance
Package
CG-32-21
θJC
Unit
7:1
17.4
°C/W
1 Thermal resistance (θJC) was determined by simulation under the following
conditions: the heat transfer is due solely to thermal conduction from the
channel, through the ground paddle, to the PCB, and the ground paddle is
held constant at the operating temperature of 85°C.
−65°C to +150°C
−55°C to +85°C
260°C
Electrostatic Discharge (ESD) Sensitivity
Human Body Model (HBM)
ESD CAUTION
Class 0B, passed
150 V
Junction Temperature to Maintain
1 Million Hour Mean Time to Failure
(MTTF)
175°C
Nominal Junction Temperature
(TBASE2 = 85°C, VDDx = 5 V)
141.55°C
1 Maximum input power is limited to 18 dBm or thermal limits constrained by
maximum power dissipation (see Figure 31), whichever is lower.
2 TBASE is the actual temperature on the package base.
3 See the Ordering Guide for additional information.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Rev. 0 | Page 4 of 17
Data Sheet
HMC1132PM5E
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
GND
NIC
NIC
1
2
3
4
5
6
7
8
24 GND
23 NIC
22
NIC
HMC1132PM5E
21 GND
GND
RFIN
GND
NIC
TOP VIEW
20
19
RFOUT
GND
(Not to Scale)
18 NIC
17 GND
GND
NOTES
1. NIC = NOT INTERNALLY CONNECTED.
2. THE EXPOSED PAD. EXPOSED PAD MUST
BE CONNECTED TO RF AND DC GROUND.
Figure 2. Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
Mnemonic Description
1, 4, 6, 8, 9, 16, 17, 19, GND
21, 24, 25, 32
Ground. These pins and the exposed pad must be connected to RF and dc ground.
2, 3, 7, 10, 11, 13, 14,
18, 22, 23, 26 to 30
NIC
Not Internally Connected. These pins are not connected internally. However, all data was measured
with these pins connected to RF and dc ground externally.
5
RFIN
RF Input. This pin is dc-coupled and matched to 50 Ω. See Figure 4 for the RFIN interface schematic.
12, 15
VDD1, VDD2
Drain Bias Voltage. External 100 pF, 10 nF, and 4.7 μF bypass capacitors are required. See Figure 5 for
the VDD1 and VDD2 interface schematic.
20
31
RFOUT
VGG
RF Output. This pin is ac-coupled and matched to 50 Ω. See Figure 6 for the RFOUT interface
schematic.
Gate Control for Amplifier. Adjust VGG to achieve the recommended bias current. External 100 pF,
10 nF, and 4.7 μF bypass capacitors are required. See Figure 7 for the VGG interface schematic.
EPAD
Exposed Pad. The exposed pad must be connected to RF and dc ground.
INTERFACE SCHEMATICS
GND
RFOUT
Figure 3. GND Interface
Figure 6. RFOUT Interface
RFIN
V
GG
Figure 7. VGG Interface
Figure 4. RFIN Interface
V
,V
DD1 DD2
Figure 5. VDD1 and VDD2 Interface
Rev. 0 | Page 5 of 17
HMC1132PM5E
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
30
28
26
24
22
20
18
16
14
12
10
20
S22
S21
S11
10
0
+85°C
+25°C
–40°C
–10
–20
25
27
29
31
33
35
25
27
29
31
33
35
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 8. Response (Gain and Return Loss) vs. Frequency, VDDx = 5 V,
IDDQ = 650 mA
Figure 11. Gain vs. Frequency for Various Temperatures, VDDx = 5 V,
IDDQ = 650 mA
28
28
26
24
22
20
18
500mA
550mA
26
600mA
650mA
700mA
24
750mA
22
20
18
16
14
12
10
16
6V
14
12
10
5V
4V
25
27
29
31
33
35
25
27
29
31
33
35
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 12. Gain vs. Frequency for Various Quiescent Currents (IDDQ), VDDx = 5 V
Figure 9. Gain vs. Frequency for Various Drain Bias Voltages (VDDx),
IDDQ = 650 mA
0
0
–5
–5
–10
–10
+85°C
+25°C
–40°C
6V
5V
4V
–15
–15
–20
25
–20
25
27
29
31
33
35
27
29
31
33
35
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 13. Input Return Loss vs. Frequency for Various Drain Bias Voltages
(VDDx), IDDQ = 650 mA
Figure 10. Input Return Loss vs. Frequency for Various Temperatures,
DDx = 5 V, IDDQ = 650 mA
V
Rev. 0 | Page 6 of 17
Data Sheet
HMC1132PM5E
0
0
–5
+85°C
+25°C
–40°C
–5
–10
–15
–10
–15
–20
500mA
550mA
600mA
650mA
700mA
750mA
–20
25
27
29
31
33
35
25
27
29
31
33
35
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 14. Input Return Loss vs. Frequency for Various Quiescent Currents
(IDDQ), VDDx = 5 V
Figure 17. Output Return Loss vs. Frequency for Various Temperatures,
VDDx = 5 V, IDDQ = 650 mA
0
0
500mA
550mA
600mA
650mA
700mA
6V
5V
4V
750mA
–5
–5
–10
–15
–20
–10
–15
–20
25
27
29
31
33
35
25
27
29
31
33
35
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 15. Output Return Loss vs. Frequency for Various Drain Bias Voltages
(VDDx), IDDQ = 650 mA
Figure 18. Output Return Loss vs. Frequency for Various Quiescent Currents
(IDDQ), VDDx = 5 V
0
10
8
+85°C
+25°C
–15
–40°C
–30
6
–45
–60
–75
–90
4
+85°C
+25°C
2
–40°C
0
25
25
27
29
31
33
35
27
29
31
33
35
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 16. Reverse Isolation vs. Frequency for Various Temperatures,
DDx = 5 V, IDDQ = 650 mA
Figure 19. Noise Figure vs. Frequency for Various Temperatures, VDDx = 5 V,
DDQ = 650 mA
V
I
Rev. 0 | Page 7 of 17
HMC1132PM5E
Data Sheet
32
30
28
26
24
32
30
28
26
24
22
20
+85°C
+25°C
–40°C
6V
5V
4V
22
20
25
27
29
31
33
35
25
27
29
31
33
35
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 20. P1dB vs. Frequency for Various Temperatures, VDDx = 5 V,
IDDQ = 650 mA
Figure 23. P1dB vs. Frequency for Various Drain Bias Voltages (VDDx),
IDDQ = 650 mA
32
32
30
28
26
500mA
550mA
600mA
30
650mA
700mA
750mA
28
26
24
22
20
+85°C
24
+25°C
–40°C
22
20
25
27
29
31
33
35
25
27
29
31
33
35
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 21. P1dB vs. Frequency for Various Quiescent Currents (IDDQ), VDDx = 5 V
Figure 24. PSAT vs. Frequency for Various Temperatures, VDDx = 5 V,
IDDQ = 650 mA
32
30
28
26
24
32
30
28
26
24
6V
5V
4V
500mA
550mA
600mA
22
22
650mA
700mA
750mA
20
25
20
27
29
31
33
35
25
27
29
31
33
35
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 22. PSAT vs. Frequency for Various Drain Bias Voltages (VDDx),
DDQ = 650 mA
Figure 25. PSAT vs. Frequency for Various Quiescent Currents (IDDQ),
VDDx = 5 V
I
Rev. 0 | Page 8 of 17
Data Sheet
HMC1132PM5E
30
25
20
15
10
5
30
25
20
15
10
5
+85°C
+25°C
–40°C
6V
5V
4V
0
25
0
25
27
29
31
33
35
27
29
31
33
35
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 26. Power Added Efficiency (PAE) vs. Frequency for Various Temperatures,
DDx = 5 V, IDDQ = 650 mA, PAE Measured at PSAT
Figure 29. PAE vs. vs. Frequency for Various Drain Bias Voltages (VDDx),
DDQ = 650 mA, PAE Measured at PSAT
V
I
30
25
20
15
10
5
35
30
25
20
15
10
5
880
840
800
760
720
680
640
600
500mA
550mA
600mA
650mA
700mA
750mA
P
GAIN
PAE
OUT
I
DD
0
0
25
27
29
31
33
35
–10 –8 –6 –4 –2
0
2
4
6
8
10 12 14
FREQUENCY (GHz)
INPUT POWER (dBm)
Figure 27. PAE vs. Frequency for Various Quiescent Currents (IDDQ),
VDDx = 5 V, PAE Measured at PSAT
Figure 30. Output Power (POUT), Gain, Power Added Efficiency (PAE),
Drain Current (IDD) vs. Input Power, 27 GHz, VDDx = 5 V, IDDQ = 650 mA
35
30
25
20
15
10
5
880
840
800
760
720
680
640
600
35
30
25
20
15
10
5
880
840
800
760
720
680
640
600
P
GAIN
PAE
P
OUT
GAIN
PAE
OUT
I
I
DD
DD
0
0
–10 –8 –6 –4 –2
0
2
4
6
8
10 12 14
–10 –8 –6 –4 –2
0
2
4
6
8
10 12 14
INPUT POWER (dBm)
INPUT POWER (dBm)
Figure 28. Output Power (POUT), Gain, Power Added Efficiency (PAE), and
Drain Current (IDD) vs. Input Power, 29.5 GHz, VDDx = 5 V, IDDQ = 650 mA
Figure 31. Output Power (POUT), Gain, Power Added Efficiency (PAE), Drain
Current (IDD) vs. Input Power, 32 GHz, VDDx = 5 V, IDDQ = 650 mA
Rev. 0 | Page 9 of 17
HMC1132PM5E
Data Sheet
35
35
30
25
20
15
30
25
20
15
GAIN
P1dB
GAIN
P1dB
P
P
SAT
SAT
4.0
4.5
5.0
(V)
5.5
6.0
4.0
4.5
5.0
V (V)
DDx
5.5
6.0
V
DDx
Figure 32. Gain, P1dB, and PSAT vs. VDDx, 27 GHz, IDDQ = 650 mA
Figure 35. Gain, P1dB, and PSAT vs. VDDX, 29.5 GHz, IDDQ = 650 mA
35
35
GAIN
P1dB
P
SAT
30
25
20
15
30
25
20
15
GAIN
P1dB
P
SAT
4.0
4.5
5.0
(V)
5.5
6.0
500
550
600
650
(mA)
700
750
V
I
DDQ
DDx
Figure 33. Gain, P1dB, and PSAT vs. VDDx, 32 GHz, IDDQ = 650 mA
Figure 36. Gain, P1dB, and PSAT vs. IDDQ, 27 GHz, VDDx = 5 V
35
35
30
25
20
15
GAIN
P1dB
GAIN
P1dB
P
P
SAT
SAT
30
25
20
15
500
550
600
650
(mA)
700
750
500
550
600
650
(mA)
700
750
I
I
DDQ
DDQ
Figure 34. Gain, P1dB, and PSAT vs. IDDQ, 29.5 GHz, VDDx = 5 V
Figure 37. Gain, P1dB, and PSAT vs. IDDQ, 32 GHz, VDDx = 5 V
Rev. 0 | Page 10 of 17
Data Sheet
HMC1132PM5E
5.5
5.0
4.5
4.0
3.5
3.0
2.5
40
35
30
25
20
MAXIMUM P
DISS
32GHz
2.0
1.5
1.0
31GHz
30GHz
29GHz
28GHz
27GHz
–40°C
+25°C
+85°C
–10
–6
–2
2
6
10
14
26
27
28
29
30
31
32
33
INPUT POWER (dBm)
FREQUENCY (GHz)
Figure 38. Power Dissipation vs. Input Power at TA = 85°C, VDDx = 5 V,
IDDQ = 650 mA
Figure 41. Output IP3 vs. Frequency for Various Temperatures,
POUT per Tone = 20 dBm, VDDx = 5 V, IDDQ = 650 mA
40
35
30
40
35
30
6V
500m A
550m A
600m A
650m A
25
25
5V
4V
700m A
750m A
20
26
20
26
27
28
29
30
31
32
33
27
28
29
30
31
32
33
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 39. Output IP3 vs. Frequency for Various Supply Voltages (VDDx),
Figure 42. Output IP3 vs. Frequency for Various Quiescent Currents (IDDQ),
VDDx = 5 V
IDDQ = 650 mA
60
50
40
30
20
10
0
60
50
40
30
20
32GHz
31GHz
30GHz
29GHz
28GHz
27GHz
32GHz
31GHz
30GHz
29GHz
10
28GHz
27GHz
0
10
10
12
14
16
18
20
22
24
12
14
16
18
20
22
24
P
PER TONE (dBm)
P
PER TONE (dBm)
OUT
OUT
Figure 40. Third-Order Intermodulation Distortion Relative to Carrier (IM3) vs.
POUT per Tone, VDDx = 4 V, IDDQ = 650 mA
Figure 43. IM3 vs. POUT per Tone, VDDx = 5 V, IDDQ = 650 mA
Rev. 0 | Page 11 of 17
HMC1132PM5E
Data Sheet
60
50
40
30
20
1000
900
800
700
600
500
32GHz
31GHz
30GHz
29GHz
28GHz
27GHz
32GHz
31GHz
30GHz
29GHz
28GHz
27GHz
10
0
–10
–6
–2
2
6
10
14
10
12
14
16
18
20
22
24
INPUT POWER (dBm)
P
PER TONE (dBm)
OUT
Figure 46. Drain Current (IDD) vs. Input Power for Various Frequencies,
VDDx = 5 V, IDDQ = 650 mA
Figure 44. IM3 vs. POUT per Tone, VDDx = 6 V, IDDQ = 650 mA
1500
1300
1100
900
2.0
32GHz
31GHz
30GHz
29GHz
28GHz
27GHz
1.5
1.0
0.5
700
0
500
–0.5
–1.0
–1.5
300
100
–100
–1.8
–1.6
–1.4
–1.2
–1.0
–0.8
–0.6
–10
–6
–2
2
6
10
14
V
(V)
INPUT POWER (dBm)
GG
Figure 45. Gate Current (IGG) vs. Input Power for Various Frequencies,
VDDx = 5 V, IDDQ = 650 mA
Figure 47. Quiescent Current (IDDQ) vs. VGG, VDDx = 5 V, Representative of a
Typical Device
Rev. 0 | Page 12 of 17
Data Sheet
HMC1132PM5E
THEORY OF OPERATION
The architecture of the HMC1132PM5E power amplifier is
shown in Figure 48. The amplifier consists of a cascade of four,
single-stage amplifiers. This approach provides a high P1dB as
well as a high gain that is flat across the operating frequency
range. VDD1 provides drain bias to the first three gain stages,
whereas VDD2 provides drain bias to the fourth gain stage. VGG
provides gate bias to all four gain stages, allowing control of the
quiescent current. RFIN and RFOUT provide dc paths to GND
as a way of increasing the overall ESD robustness of the device.
V
V
DD2
DD1
RFIN
RFOUT
V
GG
Figure 48. Architecture and Simplified Block Diagram
Rev. 0 | Page 13 of 17
HMC1132PM5E
Data Sheet
APPLICATIONS INFORMATION
The HMC1132PM5E is a GaAs, pHEMT, MMIC power
amplifier. Capacitive bypassing is required for VDD1, VDD2, and
The following bias sequence is recommended during power-down:
1. Turn off the RF signal.
VGG (see Figure 49). The drain bias voltage must be applied to
2. Decrease the gate bias voltage to −2 V to achieve an IDDQ
=
both VDD1 and VDD2, and the gate bias voltage must be applied to
VGG. Although the RFIN and RFOUT ports ac couple the signal,
dc paths to GND are provided to increase the ESD robustness of
the device. External dc blocking of RFIN and/or RFOUT is
desirable when appreciable levels of dc are present.
0 mA (approximately).
3. Decrease the drain bias voltages to 0 V.
4. Increase the gate bias voltage to 0 V.
The VDDx = 5 V and IDDQ = 650 mA bias conditions are the
operating points recommended to optimize the overall
performance of the device. Unless otherwise noted, the data
shown was obtained using the recommended bias conditions.
Operation of the HMC1132PM5E at different bias conditions
may provide performance that differs from what is shown in the
Typical Performance Characteristics section. Biasing the
HMC1132PM5E for a higher drain current typically results in
higher P1dB, PSAT, and gain, though at the expense of increased
power consumption.
All measurements for this device were taken using the typical
application circuit shown in Figure 49, configured as shown on
the evaluation PCB (see Figure 50).
The following bias sequence is recommended during power-up:
1. Connect the evaluation board to ground.
2. Set the gate bias voltage to −2 V.
3. Set the drain bias voltages to 5 V.
4. Increase the gate bias voltage to achieve a quiescent IDDQ
=
650 mA.
5. Apply the RF signal.
APPLICATION CIRCUIT
Figure 49 shows the typical application circuit.
V
GG
C30
4.7µF
C20
10nF
C10
100pF
1
2
3
4
5
6
7
8
24
HMC1132PM5E
23
22
21
20
19
18
17
J1
RFIN
J2
RFOUT
V
DD1
C23
4.7µF
C13
10nF
C3
100pF
V
DD2
C25
4.7µF
C15
10nF
C5
100pF
Figure 49. Typical Application Circuit
Rev. 0 | Page 14 of 17
Data Sheet
HMC1132PM5E
EVALUATION BOARD
The HMC1132PM5E evaluation board is a 2-layer board
fabricated using Rogers 4350 and best practices suited for high
frequency RF design. The RF input and RF output traces have a
50 Ω characteristic impedance. The circuit board is attached to
a heat sink. Components are mounted using SN63 solder,
allowing rework of the surface-mount components without
compromising attachment of the PCB to a heat sink.
During operation, to control the temperature of the
HMC1132PM5E, attach the evaluation board to a temperature
controlled plate. For the proper bias sequence, see the
Applications Information section.
The evaluation board schematic is shown in Figure 51. A fully
populated and tested evaluation board (see Figure 50) is
available from Analog Devices, Inc., upon request.
The evaluation board and populated components are designed
to operate over the ambient temperature range of −40°C to +85°C.
Figure 50. Evaluation PCB
BILL OF MATERIALS
Table 6. Bill of Materials for Evaluation PCB EV1HMC1132PM5
Item
Description
J1, J2
J3, J4
Connector, SRI K connector. SRI Part Number 25-146-1000-92.
DC pins.
J5, J6
Connector, SRI K connector. Not populated.
100 pF capacitors, 0402 package.
10 nF capacitors, 0402 package.
4.7 μF capacitors, Case A package.
HMC1132PM5E amplifier.
C3, C5, C10
C13, C15, C20
C23, C25, C30
U1
Heat Sink
PCB
Used for thermal transfer from the HMC1132PM5E amplifier.
08_047754 evaluation board. Circuit board material: Rogers 4350.
Rev. 0 | Page 15 of 17
HMC1132PM5E
Data Sheet
EVALUATION BOARD SCHEMATIC
VG1
C30
4.7µF
C20
10nF
C10
100pF
+
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
GND
NIC
GND
NIC
NIC
NIC
U1
GND
RFIN
GND
NIC
GND
RFOUT
GND
NIC
J1
J2
HMC1132PM5E
RFIN
RFOUT
K_SRI-NS
K_SRI-NS
GND
GND
VD3
VD7
+
+
C23
4.7µF
C13
10nF
C3
100pF
C25
4.7µF
C5
100pF
C15
10nF
J3
J4
VD7
VD5
VD3
VD1
VG2
VG1
10
9
10
9
7
5
3
1
VD2
VD4
VD6
VD8
8
7
5
3
1
8
6
4
2
6
4
2
87759-1050
87759-1050
THRUCAL
J5
J6
K_SRI-NS
DEPOP
K_SRI-NS
DEPOP
NIC = NOT INTERNALLY CONNECTED.
Figure 51. Evaluation Board Schematic
Rev. 0 | Page 16 of 17
Data Sheet
HMC1132PM5E
OUTLINE DIMENSIONS
DETAIL A
(JEDEC 95)
5.10
5.00 SQ
4.90
0.30
0.25
0.20
PIN 1
INDICATOR
PIN 1
INDICATOR AREA OPTIONS
(SEE DETAIL A)
25
24
32
1
0.50
BSC
3.20
3.10 SQ
3.00
EXPOSED
PAD
17
16
8
9
0.45
0.40
0.35
TOP VIEW
SIDE VIEW
BOTTOM VIEW
3.50 REF
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
1.35
1.25
1.15
0.60 REF
0.40
0.050 MAX
0.035 NOM
SECTION OF THIS DATA SHEET.
COPLANARITY
SEATING
PLANE
0.08
0.203 REF
Figure 52. 32-Lead Lead Frame Chip Scale Package, Premolded Cavity [LFCSP_CAV]
5 mm × 5 mm Body and 1.25 mm Package Height
(CG-32-2)
Dimensions shown in millimeters
ORDERING GUIDE
Package
Option
Model1, 2
Temperature
−40°C to +85°C
MSL Rating3 Description4
HMC1132PM5E
MSL3
MSL3
32-Lead Lead Frame Chip Scale Package, Premolded Cavity [LFCSP_CAV]
32-Lead Lead Frame Chip Scale Package, Premolded Cavity [LFCSP_CAV]
Evaluation Board
CG-32-2
CG-32-2
HMC1132PM5ETR −40°C to +85°C
EV1HMC1132PM5
1 All models are RoHS compliant parts.
2 When ordering the evaluation board only, reference the model number, EV1HMC1132PM5.
3 See the Absolute Maximum Ratings section for additional information.
4 The lead finish of the HMC1132PM5E and the HMC1132PM5ETR is nickel palladium gold (NiPdAu).
©2018 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D17225-0-9/18(0)
Rev. 0 | Page 17 of 17
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