HMC7043_技术文档

High Performance, 3.2 GHz, 14-Output

Fanout Buffer

Data Sheet

HMC7043

The HMC7043 is designed to meet the requirements of multicarrier

GSM and LTE base station designs, and offers a wide range of

clock management and distribution features to simplify baseband

FEATURES

JEDEC JESD204B support

Low additive jitter: <15 fs rms at 2457.6 MHz (12 kHz to 20 MHz)

Very low noise floor: −155.2 dBc/Hz at 983.04 MHz

Up to 14 LVDS, LVPECL, or CML type device clocks (DCLKs)

Maximum CLKOUTx/CLKOUTx and SCLKOUTx/SCLKOUTx

frequency of 3200 MHz

JESD204B-compatible system reference (SYSREF) pulses

25 ps analog and ½ clock input cycle digital delay

independently programmable on each of 14 clock

output channels

and radio card clock tree designs.

The HMC7043 provides 14 low noise and configurable outputs

to offer flexibility in interfacing with many different components in

a base transceiver station (BTS) system, such as data converters,

local oscillators, transmit/receive modules, field programmable

gate arrays (FPGAs), and digital front-end ASICs. The HMC7043

can generate up to seven DCLK and SYSREF clock pairs per the

JESD204B interface requirements.

SPI-programmable adjustable noise floor vs. power consumption

SYSREF valid interrupt to simplify JESD204B synchronization

Supports deterministic synchronization of multiple

HMC7043 devices

RFSYNCIN pin or SPI-controlled SYNC trigger for output

synchronization of JESD204B

GPIO alarm/status indicator to determine system health

Clock input to support up to 6 GHz

48-lead, 7 mm × 7 mm LFCSP package

The system designer can generate a lower number of DCLK and

SYSREF pairs, and configure the remaining output signal paths

for independent phase and frequency. Both the DCLK and SYSREF

clock outputs can be configured to support different signaling

standards, including CML, LVDS, LVPECL, and LVCMOS, and

different bias conditions to adjust for varying board insertion losses.

One of the unique features of the HMC7043 is the independent

flexible phase management of each of the 14 channels. All

14 channels feature both frequency and phase adjustment. The

outputs can also be programmed for 50 Ω or 100 Ω internal and

external termination options.

APPLICATIONS

JESD204B clock generation

Cellular infrastructure (multicarrier GSM, LTE, W-CDMA)

Data converter clocking

Phase array reference distribution

Microwave baseband cards

The HMC7043 device features an RF SYNC feature that synchro-

nizes multiple HMC7043 devices deterministically, that is, ensures

that all clock outputs start with the same edge. This operation is

achieved by rephrasing the nested HMC7043 or SYSREF control

unit/divider, deterministically, and then restarting the output

dividers with this new phase.

GENERAL DESCRIPTION

The HMC7043 is a high performance clock buffer for the

The HMC7043 is offered in a 48-lead, 7 mm × 7 mm LFCSP

package with an exposed pad connected to ground.

distribution of ultralow phase noise references for high speed data

converters with either parallel or serial (JESD204B type) interfaces.

FUNCTIONAL BLOCK DIAGRAM

CLKOUT0

SCLKOUT1

CLKIN/

CLKIN

÷

CLKOUT12

SCLKOUT13

RFSYNCIN/

RFSYNCIN

SYSREF

CONTROL

SPI

CONTROL

INTERFACE

14-CLOCK

DISTRIBUTION

SDATA

SLEN SCLK

Figure 1.

Rev. B

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HMC7043* Product Page Quick Links

Last Content Update: 11/01/2016

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Data Sheet

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Buffer Data Sheet

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HMC7043

Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

Terminology.................................................................................... 14

Theory of Operation ...................................................................... 15

Detailed Block Diagram ............................................................ 16

Clock Input Network ................................................................. 16

Clock Output Network .............................................................. 17

Typical Programming Sequence............................................... 23

Power Supply Considerations................................................... 24

Serial Control Port ......................................................................... 27

Serial Port Interface (SPI) Control........................................... 27

Control Registers............................................................................ 28

Control Register Map ................................................................ 28

Control Register Map Bit Descriptions ................................... 33

Applications Information .............................................................. 41

Evaluation PCB And Schematic............................................... 41

Outline Dimensions....................................................................... 43

Ordering Guide .......................................................................... 43

Applications....................................................................................... 1

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Conditions..................................................................................... 3

Supply Current.............................................................................. 3

Digital Input/Output (I/O) Electrical Specifications............... 4

Clock Input Path Specifications.................................................. 4

Additive Jitter and Phase Noise Characteristics....................... 5

Clock Output Distribution Specifications................................. 5

Clock Output Driver Characteristics......................................... 6

Absolute Maximum Ratings............................................................ 8

ESD Caution.................................................................................. 8

Pin Configuration and Function Descriptions............................. 9

Typical Performance Characteristics ........................................... 11

Typical Application Circuits.......................................................... 13

REVISION HISTORY

7/2016—Rev. A to Rev. B

Changes to Table 1............................................................................ 3

5/2016—Rev. 0 to Rev. A

Changes to Table 3 ............................................................................. 4

Change to Maximum Operating Frequency Parameter, Table 7..... 7

Added Figure 6, Renumbered Sequentially ................................ 11

Change to Synchronization FSM/Pulse Generator

Timing Section................................................................................. 21

Changes to Table 20........................................................................ 28

Change to Table 22 ......................................................................... 33

Changes to Table 28........................................................................ 34

Changes to Table 29........................................................................ 35

Change to Table 31 ......................................................................... 36

Change to Table 38 ......................................................................... 37

Changes to Table 41........................................................................ 39

12/2015—Revision 0: Initial Version

Rev. B | Page 2 of 43

Data Sheet

HMC7043

SPECIFICATIONS

V_CC= 3.3 V ꢀ5% ꢁad T_A= 2ꢀ°C% ualess otherwise aoted. Miaimum ꢁad mꢁximum vꢁlues ꢁre givea over the full V_CCꢁad T_A(−40°C to

+8ꢀ°C) vꢁriꢁtioa% ꢁs listed ia Tꢁble 1.

CONDITIONS

Table 1.

Parameter¹

Min

Typ Max

Unit Test Conditions/Comments

SUPPLY VOLTAGE, V_CC

VCC1_CLKDIST

VCC2_OUT

3.135 3.3

3.465

V

3.3 V 5ꢀ, ꢁsuuly voltage for CLK diꢁtribstion

3.3 V 5ꢀ, ꢁsuuly voltage for Ostust Channel 2 and

Ostust Channel 3

VCC3_OUT

3.135 3.3

3.465

V

3.3 V 5ꢀ, ꢁsuuly voltage for Ostust Channel 4, Ostust

Channel 5, Ostust Channel 6 and Ostust Channel 7

VCC4_CLKIN

VCC5_SYSREF

VCC6_OUT

3.135 3.3

3.465

V

3.3 V 5ꢀ, ꢁsuuly voltage for the clock inust uath

3.3 V 5ꢀ, ꢁsuuly voltage for the common SYSREF divider

3.3 V 5ꢀ, ꢁsuuly voltage for Ostust Channel 8, Ostust

Channel 9, Ostust Channel 10, and Ostust Channel 11

VCC7_OUT

3.135 3.3

3.465

V

3.3 V 5ꢀ, ꢁsuuly voltage for Ostust Channel 0, Ostust

Channel 1, Ostust Channel 12, and Ostust Channel 13

TEMPERATURE

Ambient Temueratsre Range, T_A

−40

+25 +85

°C

¹Maximsm valseꢁ are gsaranteed by deꢁign and characterization.

SUPPLY CURRENT

For detꢁiled test coaditioas% see Tꢁble 17 ꢁad Tꢁble 18.

Table 2

Parameter^{1, 2}

Min Typ

Max Unit Test Conditions/Comments

CURRENT CONSUMPTION³

VCC1_CLKDIST

VCC2_OUT⁴

87

90

52

125

250

500

mA

Tyuical valse iꢁ given at T_A= 25°C with two LVDS clockꢁ at divide by 8

Tyuical valse iꢁ given at 25°C with two LVDS high uerformance clockꢁ,

fsndamental freqsency of the clock inust (f_O), two SYSREF clockꢁ (off)

VCC3_OUT⁴

VCC4_CLKIN

16

25

mA

Tyuical valse iꢁ given at T_A= 25°C with RF ꢁynchronization (RFSYNC) inust

bsffer off

VCC5_SYSREF

VCC6_OUT⁴

23

90

35

500

mA

Tyuical valse iꢁ given at T_A= 25°C with internal RF SYNC uath off

Tyuical valse iꢁ given at 25°C with two LVDS high uerformance clockꢁ at

divide by 2, two SYSREF clockꢁ (off)

Tyuical valse iꢁ given at 25°C with two LVDS clockꢁ at divide by 8, two SYSREF

clockꢁ (off)

VCC7_OUT⁴

100

458

500

mA

Total Csrrent

¹Maximsm valseꢁ are gsaranteed by deꢁign and characterization.

²Csrrentꢁ inclsde LVDS termination csrrentꢁ.

³Maximsm valseꢁ are for all circsitꢁ enabled in their worꢁt caꢁe uower conꢁsmution mode, PVT variationꢁ, and accosnting for ueak csrrent draw dsring temuorary

ꢁynchronization eventꢁ.

⁴Tyuical ꢁuecification auulieꢁ to a normal sꢁage urofile (Profile 1 in Table 17) bst very low dsty cycle csrrentꢁ (ꢁync eventꢁ) and ꢁome outional featsreꢁ are diꢁabled.

Thiꢁ ꢁuecification aꢁꢁsmeꢁ ostust configsrationꢁ aꢁ deꢁcribed in the teꢁt conditionꢁ/commentꢁ colsmn.

Rev. B | Page 3 of 43

HMC7043

Data Sheet

DIGITAL INPUT/OUTPUT (I/O) ELECTRICAL SPECIFICATIONS

Table 3.

Parameter

Min

Typ

Max

Unit Test Conditions/Comments

DIGITAL INPUT SIGNALS (RESET, SLEN, SCLK)

Safe Input Voltage Range

Input Load

−0.1

+3.6

V

pF

0.3

Input Voltage

Input Logic High

Input Logic Low

SPI Bus Frequency

1.2

0

V_CC

0.5

10

V

MHz

DIGITAL BIDIRECTIONAL SIGNALS

CONFIGURED AS INPUTS (SDATA, GPIO)

Safe Input Voltage Range

Input Capacitance

Input Resistance

−0.1

+3.6

V

pF

GΩ

0.4

50

Input Voltage

Input Logic High

Input Logic Low

1.22

0

V_CC

0.24

V

Input Hysteresis

0.2

2

V

Occurs around 0.85 V

Does not include t_DGPO

GPIO ALARM MUXING/DELAY

Delay from Internal Alarm/Signal to

General-Purpose Output (GPO) Driver

ns

DIGITAL BIDIRECTIONAL SIGNALS

CONFIFURED AS OUTPUTS (SDATA, GPIO)

CMOS Mode

Logic 1 Level

Logic 0 Level

1.6

1.9

0

2.2

0.1

V

Output Drive Resistance (R_DRIVE

Output Driver Delay (t_DGPO

)

50

Ω

ns

)

1.5 + 42 × C_LOAD

Approximately 1.5 ns + 0.69 × R_DRIVE× C_LOAD

(C_LOADin nF)

Maximum Supported DC Current¹

Open-Drain Mode

Logic 1 Level

0.6

mA

V

External 1 kΩ pull-up resistor

3.6 V maximum permitted; specifications set by

external supply

3.6

Logic 0 Level

Pull-Down Impedance

Maximum Supported Sink Current¹

0.13

60

0.28

V

Ω

mA

Against a 1 kΩ external pull-up resistor to 3.3 V

5

¹Guaranteed by design and characterization for long-term reliability.

CLOCK INPUT PATH SPECIFICATIONS

Table 4.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

CLK INPUT (CLKIN) CHARACTERISTICS

Recommended Input Power, AC-Coupled

Differential

−6

−10

+8

+6

dBm

dB

Single-Ended¹

Noise floor degrade by 3 dB at f_CLKIN= 2400 MHz

When terminated with 100 Ω differential

Return Loss

−12

Clock Input Frequency (f_CLKIN

)

200

3200 MHz

Fundamental mode; if <1 GHz, set the low frequency

clock input path enable bit (Register 0x0064, Bit 0)

200

0.4

6000 MHz

Using clock input ÷ 2

Common-Mode Range

2.4

V

¹Guaranteed by design and characterization.

Rev. B | Page 4 of 43

Data Sheet

HMC7043

ADDITIVE JITTER AND PHASE NOISE CHARACTERISTICS

Table 5.

Parameter¹

Min Typ

Max

Unit

Test Conditions/Comments

ADDITIVE JITTER

RMS Additive Jitter

HMC7044 used as a clock source (see Figure 3)

Clock output frequency (f_CLKOUT) = 983.04 MHz, BW = 12 kHz to 20 MHz,

clock input slew rate ≥ 8 ns

<30

<15

fs rms

f_CLKOUT= 2457.6 MHz, BW = 12 kHz to 20 MHz, clock input slew rate ≥ 4 ns

CLOCK OUTPUT PHASE NOISE

HMC830 used as a clock source and configured to produce 983.04 MHz

at the output (see Figure 4), input slew rate > 1 V/ns

Absolute Phase Noise

Offset = 1 MHz

Offset = 10 MHz

Offset = 20 MHz

−144.3

−154.8

−155.2

dBc/Hz

f_CLKOUT= 983.04 MHz, f_CLKOUT= 983.04 MHz, divide by 1 at the output

f_CLKOUT= 983.04 MHz, f_CLKOUT= 2949.12 MHz, divide by 3 at the output

f_CLKOUT= 983.04 MHz, f_CLKOUT= 983.04 MHz, divide by 1 at the output

¹Guaranteed by design and characterization.

CLOCK OUTPUT DISTRIBUTION SPECIFICATIONS

Table 6.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

CLOCK OUTPUT SKEW

CLKOUTx/CLKOUTx to SCLKOUTx/SCLKOUTx Skew

Within One Clock Output Pair

Any CLKOUTx/CLKOUTx to Any SCLKOUTx/SCLKOUTx

15

|ps|

ps

Same pair, same type termination and

configuration

30

Any pair, same type termination and

configuration

PROPAGATION DELAY CLKIN to CLKOUTx and SCLKOUTx¹770

CLOCK OUTPUT DIVIDER CHARACTERISTICS

820

870

f_CLKIN= 983.04 MHz, all V_CCset to 3.3 V

12-Bit Divider Range

1

4094

1, 3, 5, and all even numbers up to 4094

SYSREF CLOCK OUTPUT DIVIDER CHARACTERISTICS

12-Bit Divider Range

1

1, 3, 5, and all even numbers up to 4094;

pulse generator behavior is only

supported for divide ratios ≥ 32

CLOCK OUTPUT ANALOG FINE DELAY

Analog Fine Delay

Adjustment Range¹

Resolution

135

0

670

17

ps

MHz

24 delay steps, f_CLKOUT= 983.04 MHz

f_CLKOUT= 983.04 MHz (2949.12 MHz/3)

25

1600

Maximum Analog Fine Delay Frequency

CLOCK OUTPUT COARSE DELAY (FLIP FLOP BASED)

Coarse Delay Adjustment Range

Coarse Delay Resolution

Maximum Frequency Coarse Delay

CLOCK OUTPUT COARSE DELAY (SLIP BASED)

Coarse Delay

½ CLKIN period 17 delay steps

ps

MHz

169.54

1500

f_CLKIN= 2949.12 MHz

Adjustment Range

Resolution

Maximum Frequency Coarse Delay

1 to ∞

339.08

1600

CLKIN period

ps

MHz

f_CLKIN= 2949.12 MHz

¹Guaranteed by design and characterization.

Rev. B | Page 5 of 43

HMC7043

Data Sheet

CLOCK OUTPUT DRIVER CHARACTERISTICS

Table 7.

Parameter

Min Typ

Max Unit

Test Conditions/Comments

CML MODE (LOW POWER)

−3 dB Bandwidth

Output Rise Time

R_L= 100 Ω, 9.6 mA

1950

175

145

185

145

MHz

ps

Differential output voltage = 980 mV p-p diff

f_CLKOUT= 245.76 MHz, 20% to 80%

f_CLKOUT= 983.04 MHz, 20% to 80%

f_CLKOUT= 245.76 MHz, 20% to 80%

f_CLKOUT= 983.04 MHz, 20% to 80%

f_CLKOUT= 1075 MHz (2150 MHz/2)

f_CLKOUT= 245.76 MHz (2949.12 MHz/12)

f_CLKOUT= 983.04 MHz (2949.12 MHz/3)

f_CLKOUT= 245.76 MHz (2949.12 MHz/12)

R_L= 100 Ω, 14.5 mA

Differential output voltage = 1470 mV p-p diff

f_CLKOUT= 245.76 MHz, 20% to 80%

f_CLKOUT= 983.04 MHz, 20% to 80%

f_CLKOUT= 245.76 MHz, 20% to 80%

f_CLKOUT= 983.04 MHz, 20% to 80%

f_CLKOUT= 1075 MHz (2150 MHz/2)

f_CLKOUT= 245.76 MHz (2949.12 MHz/12)

f_CLKOUT= 983.04 MHz (2949.12 MHz/3)

Output Fall Time

Output Duty Cycle¹

Differential Output Voltage Magnitude

47.5 50

52.5

%

1390

1360

V_CC− 1.05

mV p-p diff

V

Common-Mode Output Voltage

CML MODE (HIGH POWER)

−3 dB Bandwidth

1500

250

165

255

170

MHz

ps

%

Output Rise Time

Output Fall Time

Output Duty Cycle¹

Differential Output Voltage Magnitude

47.5 50

52.5

2000

1800

mV p-p diff

Differential Output

Voltage Magnitude

Power

Common-Mode Output Voltage

LVPECL MODE

590

−3.6

V_CC− 1.6

mV p-p diff

dBm diff

V

f_CLKOUT= 3200 MHz

f_CLKOUT= 245.76 MHz (2949.12 MHz/12)

R_L= 150 Ω, 4.8 mA

−3 dB Bandwidth

Output Rise Time

2400

135

130

135

130

MHz

ps

%

Differential output voltage = 1240 mV p-p diff

f_CLKOUT= 245.76 MHz, 20% to 80%

f_CLKOUT= 983.04 MHz, 20% to 80%

f_CLKOUT= 245.76 MHz, 20% to 80%

f_CLKOUT= 983.04 MHz, 20% to 80%

f_CLKOUT= 1075 MHz (2150 MHz/2)

f_CLKOUT= 245.76 MHz (2949.12 MHz/12)

f_CLKOUT= 983.04 MHz (2949.12 MHz/3)

Output Fall Time

Output Duty Cycle¹

Differential Output Voltage Magnitude

47.5 50

52.5

1760

1850

mV p-p diff

Differential Output

Voltage Magnitude

Power

Common-Mode Output Voltage

LVDS MODE (LOW POWER)

Maximum Operating Frequency

Output Rise Time

930

0.3

V_CC− 1.3

mV p-p diff

dBm diff

V

f_CLKOUT= 3200 MHz

f_CLKOUT= 245.76 MHz (2949.12 MHz/12)

1.75 mA

Differential output voltage = 320 mV p-p diff

f_CLKOUT= 245.76 MHz, 20% to 80%

f_CLKOUT= 983.04 MHz, 20% to 80%

f_CLKOUT= 245.76 MHz, 20% to 80%

f_CLKOUT= 983.04 MHz, 20% to 80%

f_CLKOUT= 1075 MHz (2150 MHz/2)

f_CLKOUT= 245.76 MHz (2949.12 MHz/12)

1700

135

100

135

95

MHz

ps

%

Output Fall Time

Output Duty Cycle¹

Differential Output Voltage Magnitude

Common-Mode Output Voltage

47.5 50

52.5

390

1.1

mV p-p diff

V

Rev. B | Page 6 of 43

Data Sheet

HMC7043

Parameter

Min Typ

Max Unit

Test Conditions/Comments

LVDS MODE (HIGH POWER)

Maximum Operating Frequency

Output Rise Time

3.5 mA

1700

145

105

145

100

MHz

ps

Differential output voltage = 600 mV p-p diff

f_CLKOUT= 245.76 MHz, 20% to 80%

f_CLKOUT= 983.04 MHz, 20% to 80%

f_CLKOUT= 245.76 MHz, 20% to 80%

f_CLKOUT= 983.04 MHz, 20% to 80%

f_CLKOUT= 1075 MHz (2150 MHz/2)

f_CLKOUT= 245.76 MHz (2949.12 MHz/12)

f_CLKOUT= 983.04 MHz (2949.12 MHz/3)

f_CLKOUT= 245.76 MHz (2949.12 MHz/12)

Output Fall Time

Output Duty Cycle¹

Differential Output Voltage Magnitude

47.5 50

750

52.5

%

mV p-p diff

V

730

1.1

Common-Mode Output Voltage

CMOS MODE

Maximum Operating Frequency

Output Rise Time

600

425

MHz

ps

Single-ended output voltage = 940 mV p-p diff

f_CLKOUT= 245.76 MHz, 20% to 80%

Output Fall Time

Output Duty Cycle¹

420

47.5 50

ps

%

f_CLKOUT= 245.76 MHz, 20% to 80%

f_CLKOUT= 1075 MHz (2150 MHz/2)

52.5

Output Voltage

High

V_CC

V_CC− 0.5

0.07

0.5

V

Load current = 1 mA

Load current = 10 mA

Load current = 1 mA

Load current = 10 mA

Low

¹Guaranteed by design and characterization.

Rev. B | Page 7 of 43

HMC7043

Data Sheet

ABSOLUTE MAXIMUM RATINGS

Table 8.

Stresses at or above those listed under Absolute Maximum

Ratings may cause permanent damage to the product. This is a

stress rating only; functional operation of the product at these

or any other conditions above those indicated in the operational

section of this specification is not implied. Operation beyond

the maximum operating conditions for extended periods may

affect product reliability.

Parameter

Rating

VCC1, VCC2, VCC3, VCC4, VCC5, VCC6, VCC7 to −0.3 V to +3.6 V

Ground

Maximum Junction Temperature

Thermal Resistance (Channel to Ground Pad)

Storage Temperature Range

Operating Temperature Range

Peak Reflow Temperature

125°C

7°C/W

−65°C to +125°C

−40°C to +85°C

260°C

ESD CAUTION

ESD Sensitivity Level

Human Body Model (HBM)

Charged Device Model (CDM)¹

Class 1C

Class 4

¹Per JESD22-C101-F (CDM) standard.

Rev. B | Page 8 of 43

Data Sheet

HMC7043

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

1

2

36 SCLKOUT9

SCLKOUT9

CLKOUT0

35

3

4

5

6

7

8

9

10

11

12

SCLKOUT1

RESET

BGAPBYP1

LDOBYP2

34 GPIO

33 SDATA

32

SCLK

HMC7043

31 SLEN

TOP VIEW

VCC5_SYSREF

RFSYNCIN

30

29

(Not to Scale)

VCC1_CLKDIST

SCLKOUT3

CLKOUT2

28 RFSYNCIN

27 VCC4_CLKIN

26

CLKIN

CLKOUT2

25 CLKIN

NOTES

1. RSV = RESERVED PIN AND MUST BE TIED TO GROUND.

2. CONNECT THE EXPOSED PAD TO A HIGH QUALITY RF/DC GROUND.

Figure 2.

Table 9. Pin Function Descriptions

Pin No. Mnemonic

Type¹Description

1

2

3

4

5

6

CLKOUT0

SCLKOUT1

RESET

O

I

True Clock Output Channel 0. Default DCLK profile.

Complementary Clock Output Channel 0. Default DCLK profile.

True Clock Output Channel 1. Default SYSREF profile.

Complementary Clock Output Channel 1. Default SYSREF profile.

Device Reset Input. Active high. For normal operation, set RESET to 0.

Band Gap Bypass Capacitor Connection. Connect a 4.7 µF capacitor to ground. This pin affects all

internally regulated supplies.

BGAPBYP1

7

LDOBYP2

LDO Bypass 2. Connect a 4.7 µF capacitor to ground. The internal digital supply is 1.8 V. This pin is the

LDO bypass for the SYSREF section.

8

9

10

11

12

13

VCC1_CLKDIST

SCLKOUT3

CLKOUT2

P

3.3 V Supply for CLK Distribution.

O

P

True Clock Output Channel 3. Default SYSREF profile.

Complementary Clock Output Channel 3. Default SYSREF profile.

True Clock Output Channel 2. Default DCLK profile.

Complementary Clock Output Channel 2. Default DCLK profile.

CLKOUT2

VCC2_OUT

Power Supply for Clock Group 1 (Southwest)—Channel 2 and Channel 3. See the Clock Grouping,

Skew, and Crosstalk section.

14

15

16

17

18

19

RSV

R

Reserved Pin. This pin must be tied to ground.

SCLKOUT5

CLKOUT4

VCC3_OUT

O

P

True Clock Output Channel 5. Default SYSREF profile.

Complementary Clock Output Channel 5. Default SYSREF profile.

True Clock Output Channel 4. Default DCLK profile.

Complementary Clock Output Channel 4. Default DCLK profile.

Power Supply for Clock Group 2 (South)—Channel 4, Channel 5, Channel 6, and Channel 7. See the

Clock Grouping, Skew, and Crosstalk section.

20

21

22

23

24

25

26

CLKOUT6

SCLKOUT7

RSV

O

R

I

True Clock Output Channel 6. Default DCLK profile.

Complementary Clock Output Channel 6. Default DCLK profile.

True Clock Output Channel 7. Default SYSREF profile.

Complementary Clock Output Channel 7. Default SYSREF profile.

Reserved Pin. This pin must be tied to ground.

Complementary Clock Input.

CLKIN

I

True Clock Input.

Rev. B | Page 9 of 43

HMC7043

Data Sheet

Pin No. Mnemonic

Type¹Description

27

28

29

30

31

32

33

34

35

36

37

38

39

VCC4_CLKIN

RFSYNCIN

VCC5_SYSREF

SLEN

SCLK

SDATA

GPIO

SCLKOUT9

CLKOUT8

VCC6_OUT

P

I

Power Supply for the Clock Input Path.

True RF Synchronization Input with Deterministic Delay.

Complementary RF Synchronization Input with Deterministic Delay.

Power Supply for Common SYSREF Divider.

SPI Latch Enable.

SPI Clock.

SPI Data.

Programmable General-Purpose Input/Output.

True Clock Output Channel 9. Default SYSREF profile.

Complementary Clock Output Channel 9. Default SYSREF profile.

True Clock Output Channel 8. Default DCLK profile.

Complementary Clock Output Channel 8. Default DCLK profile.

P

I/O

O

P

Power Supply for Clock Group 3 (North)—Channel 8, Channel 9, Channel 10, and Channel 11. See the

Clock Grouping, Skew, and Crosstalk section.

40

41

42

43

44

45

46

47

48

CLKOUT10

SCLKOUT11

SCLKOUT13

CLKOUT12

VCC7_OUT

O

P

True Clock Output Channel 10. Default DCLK profile.

Complementary Clock Output Channel 10. Default DCLK profile.

True Clock Output Channel 11. Default SYSREF profile.

Complementary Clock Output Channel 11. Default SYSREF profile.

True Clock Output Channel 13. Default SYSREF profile.

Complementary Clock Output Channel 13. Default SYSREF profile.

True Clock Output Channel 12. Default DCLK profile.

Complementary Clock Output Channel 12. Default DCLK profile.

Power Supply for Clock Group 0 (Northwest)—Channel 0, Channel 1, Channel 12, and Channel 13. See

the Clock Grouping, Skew, and Crosstalk section.

EP

Exposed Pad. Connect the exposed pad to a high quality RF/dc ground.

¹O is output, I is input, P is power, R is reserved, and I/O is input/output.

Rev. B | Page 10 of 43

Data Sheet

HMC7043

TYPICAL PERFORMANCE CHARACTERISTICS

–100

2.25

2.10

1.95

1.80

1.65

1.50

1.35

1.20

1.05

0.90

0.75

0.60

0.45

0.30

0.15

0

HMC7043 OUTPUT:

HMC7044-CLOCK SOURCE

HMC7043

LVPECL

AT FUNDEMENTAL MODE

1MHz, –140.30 dBc/Hz

5MHz, –151.02 dBc/Hz

10MHz, –151.77 dBc/Hz

20MHz, –151.97 dBc/Hz

RMS JITTER = 77.01fs

CML100 HIGH

CML100 LOW

LVDS HIGH

–110

–120

–130

–140

–150

–160

HMC7044 AS CLOCK SOURCE:

OUTPUT FREQ = 983.04MHz

OUTPUT POWER = 3.7dBm

1MHz, –140.56dBc/Hz

5MHz, –153.26dBc/Hz

10MHz, –154.28dBc/Hz

20MHz, –154.85dBc/Hz

RMS JITTER (12kHz TO 20MHz): 73.74fs

1

10

100

1000

10000

1.0

1.5

2.0

2.5

3.0

3.5

FREQUENCY OFFSET (kHz)

FREQUENCY (GHz)

Figure 3. Additive Jjitter at 983.04 MHz at Output

Figure 6.Differential Output Voltage vs. Frequency over Various Modes

–100

–110

–120

–130

–140

–150

–160

–170

2.00

HMC830-CLOCK SOURCE HMC830 AS CLOCK SOURCE:

–40°C

+25°C

HMC7043

OUTPUT FREQ = 983.04MHz

OUTPUT POWER = 4dBm

1MHz, –144.49dBc/Hz

+85°C

1.75

1.5

5MHz, –158.38dBc/Hz

10MHz,–162.61dBc/Hz

20MHz, –164.29dBc/Hz

1.25

1.00

0.75

0.5

HMC7043 OUTPUT:

AT FUNDEMENTAL MODE

1MHz, –144.31 dBc/Hz

5MHz, –153.46 dBc/Hz

10MHz, –154.78 dBc/Hz

20MHz, –155.18 dBc/Hz

0.25

0

1

10

100

1000

10000

100M

1G

3G

FREQUENCY OFFSET (kHz)

FREQUENCY (Hz)

Figure 7. LVPECL Differential Output Power vs. Frequency over Various

Temperatures

Figure 4. Absolute Phase Noise Measured at 983.04 MHz at Output

3.5

0.4

0.3

LVPECL

CML100 HIGH

CML100 LOW

3.0

LVDS HIGH

CMOS (NOT IN

DIFFERENTIAL MODE)

0.2

2.5

0.1

2.0

1.5

1.0

0.5

0

–0.1

–0.2

–0.3

–0.4

100M

1G

3.2G

0

0.4

0.8

1.2

TIME (ns)

1.6

2.0

FREQUENCY (Hz)

CLKOUT0

Figure 8. Differential CLKOUT0/

at 2457 MHz, LVPECL

Figure 5. Differential Output Power vs. Frequency over Various Modes

Rev. B | Page 11 of 43

HMC7043

Data Sheet

1.0

0.6

0.4

2.5

2.0

1.5

1.0

0.5

0

0.8

0.6

0.4

0.2

0

–0.2

–0.4

–0.6

–0.8

–1.0

–0.2

–0.4

–0.6

CLKOUT0

CLKOUT2

VALID PHASE ALARM

–0.5

715

0

1

2

3

4

5

6

7

8

9

10

695

700

705

710

TIME (ns)

CLKOUT0

Figure 9. Differential CLKOUT0/

Voltage at 614.4 MHz, LVPECL

Figure 12. Output Channel Synchronization After Rephase

0.6

2.5

2.0

1.5

1.0

0.5

0

30

CLKOUT0

CLKOUT2

VALID PHASE ALARM

0.4

0.2

25

20

15

10

0

–0.2

–0.4

–0.6

–40°C

+25°C

+85°C

–0.5

0

200

400

600

TIME (ns)

800

1000

DELAY STEP

Figure 10. Output Channel Synchronization Before and After Rephase

Figure 13. Analog Delay Step Size vs. Delay Step over Temperature,

LVPECL at 983.04 MHz

800

0.6

0.4

2.5

2.0

1.5

1.0

0.5

0

–40°C

+27°C

CLKOUT0

CLKOUT2

700

+85°C

600

VALID PHASE ALARM

500

400

300

200

100

0

0.2

0

–0.2

–0.4

–0.6

–100

FUND:FUNDAMENTAL MODE AT 2949.12MHz

DIS: ANALOG DELAY IS DISABLED AT 983.04MHz

–200

–0.5

350

0

2

4

6

8

10 12 14 16 18 20 22 24 26 28 30

330

335

340

345

DELAY STEP

TIME (ns)

Figure 11. Output Channel Synchronization Before Rephase

Figure 14. Analog Delay vs. Delay Setting over Temperature, LVPECL at

983.04 MHz

Rev. B | Page 12 of 43

Data Sheet

HMC7043

TYPICAL APPLICATION CIRCUITS

HMC7043

0.1µF

HMC7043

HIGH

IMPEDANCE

INPUT

LVDS

OUTPUT

DOWNSTREAM

DEVICE

100Ω IMPEDANCE

100Ω

OUTPUT

DEVICE

INPUT

0.1µF

Figure 15. AC-Coupled LVDS Output Driver

Figure 19. DC-Coupled LVDS Output Driver

VCC

HMC7043

100Ω

LVPECL-

COMPATIBLE

OUTPUT

DOWNSTREAM

DEVICE

(LVPECL)

0.1µF

HMC7043

HIGH

IMPEDANCE

INPUT

DOWNSTREAM

DEVICE

100Ω

50Ω

CML

OUTPUT

0.1µF

50Ω

GND

Figure 16. AC-Coupled CML (Configured High-Z) Output Driver

Figure 20. DC-Coupled LVPECL Output Driver

0.1µF

HMC7043

DOWNSTREAM

DEVICE

100Ω

(CML)

HIGH

IMPEDANCE

INPUT

DOWNSTREAM

VCC

100Ω

DEVICE

100Ω

CML

OUTPUT

0.1µF

CML

OUTPUT

Figure 17. AC-Coupled CML (Internal) Output Driver

Figure 21. DC-Coupled CML (Internal) Output Driver

0.1µF

HMC7043

3.3V

DRIVER

0.1µF

SELF BIASED

REF, VCXO

INPUTS

0.1µF

Figure 22. CLKIN, RFSYNCIN Input Single-Ended Mode

CLKIN

Figure 18. CLKIN/

, RFSYNCIN Input Differential Mode

Rev. B | Page 13 of 43

HMC7043

Data Sheet

TERMINOLOGY

Phase Jitter and Phase Noise

wave, the time jitter is a displacement of the edges from their

ideal (regular) times of occurrence. In both cases, the variations in

timing from the ideal are the time jitter. Because these variations

are random in nature, the time jitter is specified in seconds root

mean square (rms) or 1 sigma of the Gaussian distribution.

An ideal sine wave has a continuous and even progression of

phase with time from 0° to 360° for each cycle. Actual signals,

however, display a certain amount of variation from ideal phase

progression over time. This phenomenon is phase jitter. Although

many causes can contribute to phase jitter, one major cause is

random noise, which is characterized statistically as being

Gaussian (normal) in distribution.

Time jitter that occurs on a sampling clock for a DAC or an

ADC decreases the signal-to-noise ratio (SNR) and dynamic

range of the converter. A sampling clock with the lowest possible

jitter provides the highest performance from a given converter.

This phase jitter leads to the energy of the sine wave in the

frequency domain spreading out, producing a continuous power

spectrum. This power spectrum is usually reported as a series of

values whose units are dBc/Hz at a given offset in frequency from

the sine wave (carrier). The value is a ratio (expressed in decibels)

of the power contained within a 1 Hz bandwidth with respect to

the power at the carrier frequency. For each measurement, the

offset from the carrier frequency is also given.

Additive Phase Noise

Additive phase noise is the amount of phase noise that is

attributable to the device or subsystem being measured.

The phase noise of any external oscillators or clock sources is

subtracted, which makes it possible to predict the degree to

which the device impacts the total system phase noise when

used in conjunction with the various oscillators and clock

sources, each of which contributes a phase noise to the total. In

many cases, the phase noise of one element dominates the

system phase noise. When there are multiple contributors to

phase noise, the total is the square root of the sum of squares of

the individual contributors.

It is meaningful to integrate the total power contained within some

interval of offset frequencies (for example, 10 kHz to 10 MHz).

This is the integrated phase noise over that frequency offset

interval and can be readily related to the time jitter due to the

phase noise within that offset frequency interval.

Phase noise has a detrimental effect on the performance of analog-

to-digital converters (ADCs), digital-to-analog converters (DACs),

and RF mixers. It lowers the achievable dynamic range of the

converters and mixers, although they are affected in somewhat

different ways.

Additive Time Jitter

Additive time jitter is the amount of time jitter that is attributable to

the device or subsystem being measured. The time jitter of any

external oscillators or clock sources is subtracted, which makes

it possible to predict the degree to which the device impacts the

total system time jitter when used in conjunction with the various

oscillators and clock sources, each of which contributes a time

jitter to the total. In many cases, the time jitter of the external

oscillators and clock sources dominates the system time jitter.

Time Jitter

Phase noise is a frequency domain phenomenon. In the time

domain, the same effect is exhibited as time jitter. When observing

a sine wave, the time of successive zero crossings varies. In a square

Rev. B | Page 14 of 43

Data Sheet

HMC7043

THEORY OF OPERATION

The HMC7043 is a high performance, clock distribution IC

designed for extending the number of clock signals across the

system with minimal noise contribution. The device can be

used for distributing the noise sensitive reference clocks for high

speed data converters with either parallel or serial (JESD204B)

interfaces, FPGAs, and local oscillators. The HMC7043 is

designed to meet the requirements of demanding base station

designs, and offers a wide range of clock management and

distribution features to simplify baseband and radio card clock

tree designs. The device provides 14 low noise and configurable

outputs to offer flexibility in distributing clocks while applying

frequency division, phase adjustment, cycle slip, and external

signal synchronization options.

The HMC7043 provides output clock signals of up to 3.2 GHz,

while having the flexibility to support input reference frequencies of

up to 6 GHz when the internal clock division blocks are turned on.

The higher frequency support enables higher bandwidth RF

designs, and allows for distribution of low noise RF phase-locked

loop (PLL) voltage controlled oscillator (VCO) outputs as well

as other critical clocks across the system.

One of the key challenges in JESD204B system design is ensuring

the synchronization of data converter frame alignment across

the system, from the FPGA or digital front end (DFE) to ADCs

and DACs through a large clock tree that may comprise multiple

clock generation and distribution ICs.

There are two input paths on the HMC7043; one is for the clock

signal that is distributed, and the other may be used as an external

synchronization signal. In typical JESD204B systems, serial data

converter interfaces, there may be a need to ensure that all clock

signals that are sent to the data converters have phases which are

controlled by an FPGA. By virtue of the RF SYNC input, the

device ensures that output signals have a deterministic phase

alignment to this synchronization input. The RF SYNC input

can also implement multiple device clock trees by nesting more

than one HMC7043 to generate an even larger clock distribution

network, while still maintaining phase alignment across the

clock tree.

The HMC7043 generates up to seven DCLK and SYSREF clock

pairs per the JESD204B interface requirements. The system

designer can generate a lower number of DCLK and SYSREF

pairs, and configure the remaining output signal paths as

DCLKs, additional SYSREFs, or other reference clocks with

independent phase and frequency adjustment. Frequency

adjustment can be accomplished by selecting the appropriate

output divider values.

One of the unique features of the HMC7043 is the independent

flexible phase management of each of the 14 channels. Using a

combination of divider slip based, digital (coarse) and analog

(fine) delay adjustments, each channel can be programmed to

have a different phase offset. The phase adjustment capability

allows the designer to offset board flight time delay variations,

match data converter sample windows, and meet JESD204B

synchronization challenges. The output signal path design of

the HMC7043 is implemented to ensure both linear phase

adjustment steps and minimal noise perturbation when phase

adjustment circuits are turned on.

Offering excellent crosstalk, frequency isolation, and spurious

performance, the device generates independent frequencies in

both single-ended and differential formats including LVPECL,

LVDS, CML, and CMOS, and different bias conditions to

offset varying board insertion losses. The outputs can also be

programmed for ac or dc coupling and 50 Ω or 100 Ω internal

and external termination options.

The HMC7043 is programmed via a 3-wire serial port interface

(SPI). The HMC7043 is offered in a 48-lead, 7 mm × 7 mm,

LFCSP package with the exposed pad to ground.

Rev. B | Page 15 of 43

HMC7043

Data Sheet

DETAILED BLOCK DIAGRAM

CLK DISTRIBUTION PATH

SYSREF TIMER

CLKIN

DIVIDER

÷1, ÷2

COARSE

CYCLE

SLIP/

DIVIDER

(1 TO 4094)

DIGITAL

DELAY

SYNC

CLKOUT0

ANALOG

DELAY

RFSYNCIN

MUX

FUNDAMENTAL MODE

GPI

SPI

SYNC/PULSOR

CONTROL

COARSE

DIGITAL

DELAY

CYCLE

SLIP/

SYNC

DIVIDER

(1 TO 4094)

SCLKOUT1

ANALOG

DELAY

FUNDAMENTAL MODE

TO LEAF DIVIDERS

CYCLE

COARSE

DIGITAL

DELAY

COARSE

CYCLE

SLIP/

SYNC

DIVIDER

(1 TO 4094)

DIVIDER

(1 TO 4094)

DIGITAL

DELAY

SLIP/

SYNC

CLKOUT2

ANALOG

DELAY

ANALOG

DELAY

CLKOUT8

MUX

FUNDAMENTAL MODE

COARSE

DIVIDER

COARSE

DIGITAL

DELAY

CYCLE

SLIP/

SYNC

CYCLE

SLIP/

SYNC

DIVIDER

(1 TO 4094)

DIGITAL

(1 TO 4094)

SCLKOUT3

SCLKOUT9

DELAY

ANALOG

DELAY

ANALOG

DELAY

FUNDAMENTAL MODE

COARSE

DIVIDER

COARSE

DIGITAL

DELAY

CYCLE

SLIP/

SYNC

CYCLE

SLIP/

SYNC

DIVIDER

(1 TO 4094)

DIGITAL

(1 TO 4094)

DELAY

CLKOUT4

ANALOG

DELAY

ANALOG

DELAY

CLKOUT10

MUX

FUNDAMENTAL MODE

COARSE

DIVIDER

COARSE

DIGITAL

DELAY

CYCLE

SLIP/

SYNC

CYCLE

SLIP/

SYNC

DIVIDER

(1 TO 4094)

DIGITAL

(1 TO 4094)

SCLKOUT5

SCLKOUT11

DELAY

ANALOG

DELAY

ANALOG

DELAY

FUNDAMENTAL MODE

COARSE

DIVIDER

COARSE

DIGITAL

DELAY

CYCLE

SLIP/

SYNC

CYCLE

SLIP/

SYNC

DIVIDER

(1 TO 4094)

DIGITAL

(1 TO 4094)

DELAY

CLKOUT6

ANALOG

DELAY

ANALOG

DELAY

CLKOUT12

MUX

FUNDAMENTAL MODE

COARSE

DIVIDER

COARSE

DIGITAL

DELAY

CYCLE

SLIP/

SYNC

CYCLE

SLIP/

SYNC

DIVIDER

(1 TO 4094)

DIGITAL

(1 TO 4094)

SCLKOUT13

SCLKOUT7

DELAY

ANALOG

DELAY

ANALOG

DELAY

FUNDAMENTAL MODE

DEVICE

LDOs

SPI

ALARM GENERATION

GPIO

CONTROL

BGABYP1 LDOBYP2

SDATA SCLK SLEN

RESET

Figure 23. Detailed Block Diagram

CLOCK INPUT NETWORK

2.8V

50Ω,

100Ω,

1kΩ

Input Termination Network—Common for All Input Buffers

4kΩ

The two clock and RFSYNC input buffers share similar architecture

and control features. The input termination network is configurable

to 100 Ω, 200 Ω, and 2 kΩ differentially. It is typically ac-coupled

on the board, and uses the on-chip resistive divider to set the

internal common-mode voltage, V_CM, to 2.1 V.

5kΩ

1pF

50Ω,

100Ω,

1kΩ

50Ω

Figure 24. On-Chip Termination Network for Clock and RFSYNC Buffers

By closing the 50 Ω termination switch (see Figure 24), the network

also can serve as the termination system for an LVPECL driver.

Although the input termination network for the two clock and

RFSYNC input buffers is identical, the buffer behind the

network is different.

Recommendations for Normal Use

For both buffer types, unless there are extenuating circumstances

in the application, use 100 Ω differential termination resistors

to control reflections, to use the on-chip dc bias network to set

the common mode level, and to externally ac couple the input

signals in. Do not use a receiver side dc termination of the

LVPECL signal.

Rev. B | Page 16 of 43

Data Sheet

HMC7043

Single-Ended Operation

•

Fine phase control of synchronization channels with

respect to the DCLK channel

The buffers can support a single-ended signal with slightly reduced

input sensitivity and bandwidth. If driving any of the buffers

single-ended, ac couple the unused leg of the buffer to ground

at the input of the die.

•

Frequency coverage to satisfy typical clock rates in systems

Skew between SYSREF and DCLK channels that is much

less than a DCLK period

•

Spur and crosstalk performance that does not impact

system budgets

Maximum Signal Swing Considerations

The internal supplies to these input buffers are supplied directly

from 3.3 V. The ESD network and parasitic diodes can generally

shunt away excess power and protect the internal circuits

(withstanding reference powers above 13 dBm). Nevertheless,

to protect from latch-up concerns, the signals on the reference

inputs must not exceed the 3.3 V internal supply. For a 2.1 V

common mode, 50 Ω single-ended source, this allows ~1200 mV

of amplitude, or 11 dBm maximum reference power.

The HMC7043 output network supports the following recom-

mended features, which are sometimes critical in user applications:

•

Deterministic synchronization of the output channels with

respect to an external signal (RFSYNC), which allows

multichip synchronization and clean expansion to larger

systems

Pulse generator behavior to temporarily generate a

synchronization pulse stream at a user request

The flexibility to define unused JESD204B SYSREF and

DCLK channels for other purposes

Glitchless phase control of signals relative to each other

50% duty cycle clocks with odd division ratios

Multimode output buffers with a variety of swings and

termination options

Skew between all channels is much less than a DCLK period

Adjustable performance vs. power consumption for less

sensitive clock channels

•

CLOCK OUTPUT NETWORK

The HMC7043 is a high performance clock buffer, is appropriate

for JESD204B data converters, and much of the uniqueness of a

JESD204B clock generation chip relates to the array of output

channels. In this device, the output network requirements include

•

A large number of device clock (DCLK) and synchronization

(SYSREF) channels

Very good phase noise floor of the DCLK channels that can

be connected to critical data converter sample clock inputs

Deterministic phase alignment between all output channels

•

relative to one another

SYSREF INPUT NETWORK

RF

SYNC

D Q

RESET

SYSREF TIMER

CLKIN PATH

PULSE GENERATOR REQUEST (FROM SPI OR GPI PIN)

SYNC REQUEST (FROM SPI OR GPI PIN)

SYNC/PULSE GENERATOR

CONTROL

SYNC_FSM_STATE

OUTPUT CHANNEL ×14

LEAF CONTROLLER

DIGITAL

DELAY AND

RETIME

CLOCK

GATING

DIVIDER

Figure 25. Clock Output Network Simplified Diagram

Rev. B | Page 17 of 43

HMC7043

Data Sheet

Each of the 14 output channels are logically identical. The only

distinction between the SYSREF and DCLK channels is in the

SPI configuration, and in how they are used. Each channel

contains independent dividers, phase adjustment, and analog

delay circuits. This combination provides the ultimate flexibility,

cleanly accommodating nonJESD204B devices in the system.

To support divider synchronization, arbitrary phase slips, and

pulse generator modes, the following blocks are included:

•

A clock gating stage pauses the clock for synchronization

or slip operations

•

An output channel leaf (×14) controller that manages slip,

synchronization, and pulse generators with information

from the SYSREF finite state machine (FSM)

In addition to the 14 output channel dividers, an internal SYSREF

timer continually operates, and the synchronization of the output

channel dividers occurs deterministically with respect to this

timer, which the user can rephased deterministically by the user

through GPI or SPI or deterministically by using the RFSYNCIN/

Each channel has an array of control signals. Some of the

controls are described in Table 10.

System wide broadcast signals can be triggered from the SPI or

general-purpose input (GPI) port to issue a SYNC command

(to align dividers to the system internal SYSREF timer), issue a

pulse generator stream, (temporarily exporting SYSREF signals to

receivers), or to cause the dividers to slip a number of clock

input cycles to adjust their phases.

RFSYNCIN

differential pins.

The pulse generator functionality of the JESD204B standard

involves temporarily generating SYSREF output pulses, with

appropriate phasing, to downstream devices. The centralized

SYSREF timer and the associated SYNC/pulse generator control

manage the process of enabling the intended SYSREF channels,

phasing them, and then disabling them for signal integrity and

power saving advantages.

Individual dividers can be made sensitive to these events by

adjusting their slip enable, SYNC enable, and Start-Up Mode[1:0]

configuration, as described in Table 11.

When output buffers are configured in CMOS mode and phase

alignment is required among the outputs, additional multislip

delays must be issued for Channel 0, Channel 3, Channel 5,

Channel 6, Channel 9, Channel 10, and Channel 13. The value

of the delay must be as large as half of the selected divider ratio.

Note that this requirement of having additional multislip delays

is not needed when the channels are used in LVPECL, CML, or

LVDS mode.

Basic Output Divider Channel

Each of the 14 output channels are logically identical, and support

divide ratios from 1 to 4094. The supported odd divide ratios

(1, 3, or 5) have 50.0% duty cycle. The only distinction between

a SYSREF channel and a device clock channel is in the SPI

configuration and the typical usage of a given channel.

For basic functionality and phase control, each output path

consists of the following:

If a channel is configured to behave as a pulse generator, to

temporarily power up and power down according to the GPI

and SPI pulse generator commands; additional controls define the

behavior outside of the pulse generator chain (see Table 12).

•

Divider—generates the logic signal of the appropriate

frequency and phase

Digital phase adjust—adjusts the phase of each channel in

increments of ½ clock input cycles

Retimer—a low noise flip flop to retime the channel,

removing any accumulated jitter

Each divider has an additional phase offset register that adjusts

the start phase or influences the behavior of slip events sent via

the SPI (see Table 13).

•

Analog fine delay—provides a number of ~25 ps delay steps

Selection mux—selects the fundamental, divider, analog

delay, or an alternate path

Table 14 outlines the typical configuration combinations for a

DCLK channel relative to a SYSREF synchronization channel.

Note that other combinations are possible. Synchronization of

downstream devices can be managed manually, or by using the

pulse generator functionality of the HMC7043. See the Typical

Programming Sequence section for more information about the

differences between the two methods.

•

Multimode output buffer—low noise LVDS, CML, CMOS,

or LVPECL

The digital phase adjuster and retimer launch on either clock

phase of the clock input, depending on the digital phase adjust

setpoint (Coarse Digital Delay[4:0]).

Rev. B | Page 18 of 43

Data Sheet

HMC7043

Table 10. Basic Divider Controls

Bit Name

Description

Channel Enable

Channel enable. If set to 0, the channel is disabled. If set to 1, the channel can be enabled depending on the

settings of the Start-Up Mode[1:0], Seven Pairs of 14-Channel Outputs Enable[6:0], and sleep mode bits.

12-Bit Channel Divider[11:0] Divide ratio.12-bit divide ratio, split across two words (MSB and LSB). Set to 0 if not using the channel divider

(Output Mux Selection[1:0] = 2 or 3)

High Performance Mode

Coarse Digital Delay[4:0]

Fine Analog Delay[4:0]

High performance mode. Adjusts the divider and buffer bias to improve swing/phase noise slightly at the expense of

power. The performance advantage is about 1 dB, and the current penalty depends on whether the divider is enabled.

Digital delay. Adjusts the phase of the divider signal by up to 17 ½ cycles of the clock input. This circuit is

practically noiseless; however, note that a low amount of additional current is consumed.

Analog delay. Adjusts the delay of the divider signal in increments of ~25 ps. Set Output Mux Selection[1:0] = 1

to expose this channel. Exposing this channel causes phase noise degradation of up to 12 dB; therefore, do not use

on noise sensitive DCLK channels.

Output Mux Selection[1:0]

Output mux selection. 00 = divider channel, 01 = analog delay, 10 = other channel of pair, 11 = input clock.

Fundamental mode can be generated with the divider (12-Bit Channel Divider[11:0] = 1), or via Output Mux

Selection[1:0] = 10 and 12-Bit Channel Divider[11:0] = 0. Because the divider path consumes power and degrades

phase noise slightly, the fundamental mux path is recommended, but at a cost of a deterministic skew vs. a path

that is divider-based. Such skew can be compensated for with delay (digital and analog) on the divider-based

path.

Force Mute[1]

Force mute. If 1, and the channel enable is true (channel enable = 1) and Force Mute[0] = 0, the signal just

before the output buffer is asynchronously forced to Logic 0. To see the effect of this, the output buffer must

be enabled, which is dependent on the dynamic driver enable and Start-Up Mode[1:0] controls.

Table 11. Channel Features

Bit Name

Description

Slip Enable

Slip enable. A channel processes slip requests broadcast from the SPI or GPI (or, if multislip enable = 1, initiated

following a recognized SYNC or pulse generator startup).

SYNC Enable

SYNC enable. A channel processes synchronization events broadcast from the SPI or GPI or due to SYNC/RF SYNC (via

the SYSREF FSM) to reset the phase. This signal can be safely toggled on and off to adjust SYNC sensitivity without

risking the state of the divider.

Start-Up Mode[1:0]

00 = asynchronous (normal mode). The divider starts with uncontrolled phase. It is rephased by SYNC events if SYNC

enable = 1.

11 = dynamic (pulse generator mode). The divider monitors pulse generator events broadcast from the SYSREF

controller. It is powered up just before a pulse generator chain, rephased at the start, and powered down after the

pulse generator chain. This mode is only supported for divide ratios > 31.

Table 12. Pulse Generator Mode Behavior Options

Bit Name Description

Dynamic Driver Enable Dynamic output buffer enable (pulse generator mode only).

0 = the output buffer is simply enabled/disabled with the main channel enable.

1 = the output buffer enable is controlled together with the channel divider, which allows it to dynamically power

down outside pulse generator events.

Force Mute[0]

Idle at Logic 0 (pulse generator mode only).

1 = if the buffer remains on outside of the pulse generator chain, drive to Logic 0.

0 = if the buffer remains on outside of the pulse generator chain, allow the outputs to float naturally to

approximately V_CM

.

Rev. B | Page 19 of 43

HMC7043

Data Sheet

Table 13. Multislip Configuration

Bit Name

Description

Multislip Enable

Allow multislip. This bit determines whether the 12-Bit Multislip Digital Delay[11:0] parameter is used

for multislip operations. Note that a multislip operation is automatically started following a SYNC or

pulse generator initiation if multislip enable = 1.

12-Bit Multislip Digital Delay[11:0] Multislip amount. If multislip enable = 1, any slip events (caused by GPI, SPI, SYNC, or pulse generator

events) repeat the number of times set by 12-Bit Multislip Digital Delay[11:0] to adjust the phase by the

multislip amount × clock input cycles. A value of 0 is not supported if multislip enable = 1. Note that

phase slips are free from a noise and current perspective, that is, no additional power is needed and

with no noise degradation, but they take some time to occur. Each slip operation takes a number of

nanoseconds to complete, and thus the phases do not necessarily stabilize immediately. An alarm is

available for the user to indicate when all phase operations are complete.

Table 14. Typical Configuration Combinations

Bit Name

DCLK

Pulse Generator SYSREF

Manual SYSREF

Big

NonJESD204B

Any

Normal

12-Bit Channel Divider[11:0]

Start-Up Mode-Bit

Fine Analog Delay[4:0]

Coarse Digital Delay[4:0]

Slip Enable

Multislip Enable

High Performance Mode

Sync Enable

Small

Normal

Off

Optional

On

Big

Pulse generator

Normal

Optional

Off

On

Don’t care

Optional

Off

On

Off

Optional

Don’t care

Dynamic Driver Enable

Force Mute[1:0]

Don’t care

On

Synchronization FSM/Pulse Generator Timing

Figure 27 shows the start-up behavior of an example divider

that is configured as a pulse generator, with a period matching

the internal SYSREF period.

Figure 25 show a block diagram of the interface of the SYNC/

pulse generator control to the divider channels and the internal

SYSREF timer.

The startup of the pulse stream occurs a fixed number of clock

input cycles after the FSM transitions to the start phase. Disabling

the pulse generator stream where the logic path is forced to zero

comes from a combinational path directly from the FSM.

The SYSREF timer counts in periods defined by SYSREF

Timer[11:0], a 12-bit setting from the SPI. The SYSREF

timer sequences the enable, reset, and startup, and disables

the downstream dividers in the event of sync or pulse generator

requests. Program the SYSREF timer count to a submultiple of

the lowest output frequency in the clock network, and never

faster than 4 MHz. To synchronize the divider channels, it is

recommended, though not required, that the SYSREF Timer[11:0]

bits be set to a related frequency that is either a factor or

multiple of other frequencies on the IC.

Because the divider has the option for nearly arbitrary phase

adjustment, the stop condition can arrive when the pulse stream

is a Logic 1 and create a runt pulse.

For phase offsets of zero to (50% − 8) clock input cycles, and at

clock input frequencies <3 GHz, this condition is met naturally

within the design. For clock input frequencies >3 GHz, it is

recommended to use digital delay or slip offsets to increase the

natural phase offset and avoid the stress conditions.

The pulse generator is defined with respect to the periods of

this SYSREF timer, not with respect to the output period. This

behavior of the pulse generator leads to a timing constraint that

must be considered to prevent any runt pulses from affecting

the pulse generator stream.

The situation is avoided by never applying phase offset more

than (50% − 8) clock input cycles to an output channel

configured as a pulse generator.

Rev. B | Page 20 of 43

Data Sheet

HMC7043

RF_SYNC

RESET

NOTIFY CHANNEL FSM

WHAT TYPE OF EVENT

IS COMING

PULSE

GENERATOR

SETUP

SYNC

SETUP

POWER DIVIDERS/SYNC BLOCKS,

PAUSE BLOCKS, RESET LATCHES

CLEAR

REMOVE LATCH RESET,

PREPARE TO START CLOCKS

WAIT

SYNC

REQUEST

START CLOCKS,

STARTUP

WITH CLEAN TIMING,

SMALL PIPELINE DELAY

PULSE

GENERATOR

TIMEOUT?

WAIT UNTIL THE NUMBER OF

PULSE GENERATOR CYCLES

EXPIRES

DONE

REMOVE POWER

PULSE

GENERATOR

REQUEST

Figure 26. Synchronization FSM Flowchart

FSM STATE

STARTUP

PULSE GENERATOR = 2

DONE

DIVIDER CHANNEL

IF MUTE SIGNAL ARRIVES QUICKLY

RELATIVE TO SIGNAL TRAIN,

NO RUNT PULSE

FIXED NUMBER OF CLOCK INPUT CYCLES

FROM STATE CHANGE TO STARTUP, AND

ANY INTENTIONAL DIGITAL/ANALOG OFFSET

FSM STATE

STARTUP

PULSE GENERATOR = 2

DONE

DIVIDER CHANNEL

IF CONTROL IS TOO LATE

RELATIVE TO SIGNAL TRAIN,

THERE IS A RUNT PULSE

Figure 27. Start-Up Behavior of an Example Divider Configured as a Pulse Generator

Rev. B | Page 21 of 43

HMC7043

Data Sheet

Clock Grouping, Skew, and Crosstalk

Table 15. Supply Pin Clock Grouping by Location

Although the output channels are logically independent, for

physical reasons, they are first grouped into pairs, called clock

groups. Each clock group shares a reference, an input buffer,

and a SYNC retime flip flop originating from the clock

distribution network.

Supply Pin

Location

Clock Group

Channel

VCC2_OUT

Southwest

1

2

3

VCC3_OUT

VCC6_OUT

VCC7_OUT

South

2

3

4

5

6

0

4

5

6

7

The second level of grouping is according to the supply pin. Clock

Group 1 (Channel 2 and Channel 3) is on an independent supply,

and the other supply pins are each responsible for two clock groups.

Northeast

Northwest

8

9

As the output channels are more tightly coupled (by sharing a

clock group or by sharing a supply pin), the skew is minimized.

However, the isolation between those channels suffers.

10

11

12

13

0

Table 15 shows the clock grouping by location, and Table 16

show the typical skew and isolation that can be expected and how

it scales with distance between output channels.

1

Isolation improves as either the aggressor or the affected

frequencies decrease. Nevertheless, for particularly important

clock channels where spurious tones must be minimized, carefully

consider their frequency and channel configurations to isolate

continuously running frequencies onto different supply domains.

Channels configured as pulse generators are normally not an

issue, because they are disabled during normal operation.

Table 16. Typical Skew and Isolation vs. Distance

Typical

Skew (ps)

1 GHz Isolation,

Differential (dB)

Distance

Distant Supply Group

Closest Neighbor on

20

15

90 to 100

70

Different Supply Group

Shared Supply

Same Clock Group

10

60

45

Rev. B | Page 22 of 43

Data Sheet

HMC7043

Output Buffer Details

NORTHWEST

NORTHEAST

CLKOUT0

SCLKOUT9

SCLKOUT1

GPIO

SPI

RESET

VCC5_

SYSREF

BGAPBYP1

LDOBYP2

RFSYNCIN

VCC1_

CLKDIST

VCC4_

CLKIN

SCLKOUT3

CLKIN

CLKOUT2

SOUTHWEST

SOUTH

Figure 28. Clock Grouping

Figure 28 shows the clock groups by supply pin location on the

package. With appropriate supply pin bypassing, the spurious

noise of the outputs is improved.

the user to identify quickly that the desired SYSREF and device

clock states are presented at the outputs of the HMC7043.

The user has the flexibility to assign the SYSREF valid interrupt to

a GPO pin or to use a software flag, set via Register 0x007D, Bit 2,

which the user may poll as necessary. The flag notifies the user

when the system is configured and operating in the desired

state, or conversely when it is not ready.

Table 15 describes how the supply pins of each of the 14 clock

channels are connected within the seven clock groups. Clock

channels that are closest to each other have the best channel to

channel skew performance, but they also have the lowest isolation

from each other. Select critical signals that require high isolation

from each other from groups with distant supply pin locations.

An example of the expected isolation and channel to channel

skew performance of the HMC7043 at 1 GHz is provided in

Table 16.

TYPICAL PROGRAMMING SEQUENCE

To initialize the HMC7043 to an operational state, use the

following programming procedure:

1. Connect the HMC7043 to the rated power supplies. No

specific power supply sequencing is necessary.

2. Release the hardware reset by switching from Logic 1 to

Logic 0 when all supplies are stable.

SYSREF Valid Interrupt

One of the challenges in a JESD204B system is to control and

minimize the latency from the primary system controller IC,

typically an ASIC or FPGA, to the data converters. To estimate

the correct amount of latency in the system, the designer must

know the time required for a master clock generator like the

HMC7043 to provide the correct output phases at each output

channel after receiving the synchronization request. Typically, a

period of time is required on the device to implement the

change requests on the outputs due to internal state machine

cycles, data transfers, and any propagation delays. The SYSREF

valid interrupt is a function to notify the user that the correct

output settings and phase relationships are established, allowing

3. Load the configuration updates (provided by Analog

Devices, Inc.) to specific registers (see Table 40).

4. Program the SYSREF timer. Set the divide ratio (a submultiple

of the lower output channel frequency). Set the pulse

generator mode configuration, for example, selecting the

level sensitivity option and the number of pulses desired.

5. Program the output channels. Set the output buffer modes

(for example, LVPECL, CML, and LVDS). Set the divide

ratio, channel start-up mode, coarse/analog delays, and

performance modes.

6. Ensure the clock input signal are provided to CLKIN.

Rev. B | Page 23 of 43

HMC7043

Data Sheet

7. Issue a software restart to reset the system and initiate

calibration. Toggle the restart dividers/FSMs bit to 1 and

then back to 0.

8. Send a sync request via the SPI (set the reseed request bit)

to align the divider phases and send any initial pulse

generator stream.

9. Wait six SYSREF periods (6 × SYSREF Timer[11:0]) to

allow the outputs to phase appropriately (~3 μs in typical

configurations).

To resynchronize one or more of the JESD204B slaves, use the

following procedure:

1. Set the channel enable and SYNC enable bit of the SYSREF

channel of interest.

2. To prevent an output channel from responding to a sync

request, disable the SYNC enable mask of each channel so

that it continues to run normally without a phase adjustment.

3. Issue a reseed request to phase the SYSREF channel

properly with respect to the DCLK.

10. Confirm that the outputs have all reached their phases by

checking that the clock outputs phases status bit = 1.

11. At this time, initialize any other devices in the system.

Configure the slave JESD204B devices in the system to

operate with the SYSREF signal outputs from the HMC7043.

The SYSREF channels from the HMC7043 can be on either

asynchronously or dynamically, and may temporarily turn

on for a pulse generator stream.

12. Slave JESD204B devices in the system must be configured

to monitor the input SYSREF signal exported from the

HMC7043. At this point, SYSREF channels from the

HMC7043 can either be on asynchronously (running) or on

dynamically (temporarily turn on for a pulse generator train).

13. When all JESD204B slaves are powered and ready, send a

pulse generator request to send out a pulse generator chain on

any SYSREF channels programmed for pulse generator mode.

4. Enable the JESD204B slave sensitivity to the SYSREF channel.

5. If the SYSREF channel is in pulse generator mode, wait at

least 20 SYSREF periods from Step 3, and issue a pulse

generator request.

POWER SUPPLY CONSIDERATIONS

The output buffers are susceptible to supply with a certain

extent. The output buffers are also susceptible to supply noise,

but to a lesser extent. A noise tone of −60 dBV at a 40 MHz

offset results in a −90 dBc tone at the output of the buffers in

CML mode and −85 dBc in LVPECL mode. This result is a

relatively flat frequency response, and these numbers are

measured differentially. Phase noise/spurs caused by supply

noise on the output buffers do not scale with output frequency.

Table 17 lists the supply network of the HMC7043 by pin, showing

the relevant functional blocks. Three different usage profiles are

defined for the network, not including the output channel

supplies, which are accounted for separately.

The system is initialized.

For power savings and the reduction of the cross coupling of

frequencies on the HMC7043, shut down the SYSREF channels.

The values listed under Profile 0 to Profile 2 in Table 17 and

Table 18 are the typical currents of that block or feature. If a

number is not listed in a profile column, a typical profile does

not exist for that block or feature, but the user can mix and

match features outside of the profile list, and can determine

what the power consumption is going to be given the current

listings per feature.

1. Program each JESD204B slave to ignore the SYSREF input

channel.

2. On the HMC7043, disable the individual channel enable bits

of each SYSREF channel.

Rev. B | Page 24 of 43

Data Sheet

HMC7043

Table 17. Supply Network of the HMC7043 by Pin for VCC1_CLKDIST, VCC4_CLKIN, and VCC5_SYSREF

Profile¹

Circuit Block

Comment

Typical Current (mA)

0

1

2

VCC1_CLKDIST

Regulator to 1.8 V, Bypassed on LDOBYP2

SYSREF Timer

2

1

2

1

2

GPO Driver in High Speed Mode²

Clock Input Distribution Network

Minimum possible value

Minimum possible value³

84

8

84

87

16

34

36

16

Sync Retiming Network

Subtotal for VCC1_CLKDIST

VCC4_CLKIN

10

16

7

CLKIN/CLKIN Buffer

Extra current for divide by 2

CLKIN/CLKIN Path

RFSYNCIN/RFSYNCIN⁴Retimer

RFSYNCIN/RFSYNCIN Buffer

Subtotal or VCC4_CLKIN

3

9

0

16

VCC5_SYSREF

SYSREF Input Network

SYSREF Counter Base

11

12

4

11

12

SYSREF Counter, SYNC Network

Subtotal for VCC5_SYSREF

Subtotal (Without Output Paths)

27

0

23

0

10

126

52

¹Profile 0 is sleep mode; Profile 1 is power-up defaults, SYSREF timer running and RFSYNC buffer is disabled; Profile2 is only one clock output enabled, SYSREF timer is

not running and RFSYNC buffer is disabled.

²The current is highly dependent on rate of input/output and load of input/output traces. For heavily loaded traces, it is recommended to use a series resistance of

~100 Ωto minimize the IR drop on the internal regulator during transitions.

³A temporary current only.

⁴Transient current in synchronization mode, can be temporarily enabled when using external synchronization.

Rev. B | Page 25 of 43

HMC7043

Data Sheet

Table 18. Supply Network of the HMC7043 by Pin for the Clock Output Network

Profile¹

Per Output Channel

Comment

Typical Current (mA)

0

1

2

3

4

Digital Regulator and Other Sources

2.5

0.5

2.5 2.5

2.5

Buffer

LVPECL

CML100

High Power

Low Power

Including term currents

43

43 43

43

31

24

LVDS

High Power

At 307 MHz

10

Low Power

8

CMOS

At 100 MHz, both sections

25

Included²

Channel Mux

Different Power Modes Deleted

2

3

Digital Delay

Off

Setpoint > 1

Included²

3

Analog Delay

Off

Included²

0

Minimum Setting

Maximum Setting

Glitchless mode enabled

Not using divider path

9

Divider Logic

0

Included²

0

÷1

÷2

÷3

÷4

÷5

÷6

÷8

÷16

27

24

31

28

30

26

28

29

4

29

÷32

÷2044

SYNC Logic³

Slip Logic³

Subtotal

29

89

4

2.5

48 87

13

¹Profile 0 is sleep mode; Profile 1 is fundamental mode; Profile 2 is SYSREF channel matched to fundamental mode; Profile 3 is LVDS—high power signal source from

other channel; and Profile 4 is worst case configuration for power consumption of a channel.

²The base current consumption of the circuit (for example, mux) is included in the buffer typical current.

³Currents only occur temporarily during a synchronization event.

Rev. B | Page 26 of 43

Data Sheet

HMC7043

SERIAL CONTROL PORT

Typical Write Cycle

SERIAL PORT INTERFACE (SPI) CONTROL

A typical write cycle is shown in Figure 30 and occurs as follows:

The HMC7043 can be controlled via the SPI using 24-bit

registers and three pins: serial port enable (SLEN) serial data

input/output (SDATA), and serial clock (SCLK).

1. The master (host) asserts both SLEN and SDATA to

indicate a read, followed by a rising edge SCLK. The slave

(HMC7043) reads SDIO on the first rising edge of SCLK

after SLEN. Setting SDATA low initiates a write.

2. The host places the 2-bit multibyte field to be written to

low (0) on the next two falling edges of SCLK. The

HMC7043 registers the 2-bit multibyte field on the next

two rising edges of SCLK.

The 24-bit register, shown in Table 19, consists of the following:

•

1-bit read/write command

2-bit multibyte field (W1, W0)

13-bit address field (A12 to A0)

8-bit data field (D7 to D0)

3. The host places the13-bit address field (A12 to A0), MSB

first, on SDATA on the next 13 falling edges of SCLK. The

HMC7043 registers the 13-bit address field (MSB first) on

SDIO over the next 13 rising edges of SCLK.

4. The host places the 8-bit data (D7 to D0) MSB first on the

next eight falling edges of SCLK. The HMC7043 register

the 8-bit data (D7 to D0) MSB first on the next eight rising

edges of SCLK.

Table 19. SPI Bit Map

MSB

LSB

Bit 23

Bit 22

Bit 21

Bits[20:8]

Bits[7:0]

D7 to D0

R/W

W1

W0

A12 to A0

Typical Read Cycle

A typical read cycle is shown in Figure 29 and occurs as follows:

5. The final rising edge of SCLK performs the internal data

transfer into the register file, updating the configuration of

the device.

1. The master (host) asserts both SLEN and SDATA to

indicate a read, followed by a rising edge SCLK. The slave

(HMC7043) reads SDATA on the first rising edge of SCLK

after SLEN. Setting SDATA high initiates a read.

6. Deassertion of SLEN completes the register write cycle.

2. The host places the 2-bit multibyte field to be written to

low (0) on the next two falling edges of SCLK. The

HMC7043 registers the 2-bit multibyte field on the next

two rising edges of SCLK.

3. The host places the 13-bit address field (A12 to A0) MSB

first on SDATA on the next 13 falling edges of SCLK. The

HMC7043 registers the 13-bit address field (MSB first) on

SDATA over the next 13 rising edges of SCLK.

4. The host registers the 8-bit data on the next eight rising

edges of SCLK. The HMC7043 places 8-bit data (D7 to D0)

MSB first on the next eight falling edges of SCLK.

5. Deassertion of SLEN completes the register read cycle.

1

2

3

4

5

16

17

18

24

SCLK

X

READ W1

W0

A12 A11

A0

D7

D6

D0

SDATA

SLEN

Figure 29. SPI Timing Diagram, Read Operation

1

2

3

4

5

24

16

17

18

SCLK

WRITE

X

W1

W0

A12 A11

A0

D7

D6

D0

SDATA

SLEN

Figure 30. SPI Timing Diagram, Write Operation

Rev. B | Page 27 of 43

HMC7043

Data Sheet

CONTROL REGISTERS

CONTROL REGISTER MAP

Table 20. Control Register Map

Default

Value

Address

(Hex)

Register Name

Bit 7 (MSB)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0 (LSB)

(Hex)

Global Control

0x0000

Global soft reset

control

Reserved

Soft reset

0x00

0x0001

Global request

and mode

control

Reseed

request

High performance Reserved

distribution path

Reserved Mute output Pulse

drivers

Restart

generator dividers/

Sleep mode

request

FSMs

0x0002

0x0003

Reserved

Multislip Reserved

request

0x00

0x34

Global enable

control

Reserved

RF

Reserved

SYSREF

timer

enable

Reserved Reserved

reseeder

enable

0x0004

0x0005

Reserved

Seven Pairs of 14-Channel Outputs Enable[6:0]

Reserved

0x7F

0x0F

Global mode

and enable

control

0x0006

Global clear

alarms

Reserved

Clear alarms

0x00

0x0007

Global

miscellaneous

control

Reserved

Reserved (scratchpad)

Reserved

0x00

0x0008

0x0009

Input Buffer

0x000A

CLKIN0

CLKIN0/

input buffer

control

Reserved

Input Buffer Mode[3:0]

Buffer enable

0x07

0x000B

CLKIN1

CLKIN1/

Reserved

input buffer

control

GPIO/SDATA Control

0x0046

0x0050

GPI control

Reserved

GPI Selection [2:0]

GPO Selection[4:0]

GPI enable

GPO enable

0x00

0x37

GPO control

Reserved

GPO

mode

0x0054

SDATA control

Reserved

SDATA

mode

SDATA enable 0x03

SYSREF/SYNC

0x005A

Pulse generator

control

Reserved

Pulse Generator Mode Selection[2:0]

0x00

0x04

0x005B

SYNC control

SYNC

retime

Reserved SYNC invert

polarity

0x005C

0x005D

SYSREF timer

control

SYSREF Timer[7:0] (LSB)

0x00

0x01

Reserved

SYSREF Timer[11:8](MSB)

Clock Distribution Network

0x0064

Clock input

control

Reserved

Divide

by 2 on

clock

Low

frequency

clock input

0x00

input

0x0065

Analog delay

common

control

Reserved

Analog delay

low power

mode

0x00

Alarm Masks Register

0x0071 Alarm mask

control

Reserved

Sync

request

mask

Reserved

Clock

SYSREF

sync

status

mask

Reserved

0x10

outputs

phase

status

mask

Product ID Registers

0x0078

0x0079

0x007A

Product ID

Product ID Value[7:0] (LSB)

Product ID Value[15:8] (Mid)

Product ID Value[23:16] (MSB)

Rev. B | Page 28 of 43

Data Sheet

HMC7043

Default

Value

(Hex)

Address

(Hex)

Register Name

Bit 7 (MSB)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0 (LSB)

Alarm Readback Status Registers

0x007B

Readback

register

Reserved

Sync

Alarm signal

Reserved

0x007D

Alarm readback

Reserved

Clock

SYSREF

sync

status

request

status

outputs

phases

status

0x007F

Alarm readback

Reserved

SYSREF Status Register

0x0091

SYSREF status

register

Reserved

Channel

outputs

FSM busy

SYSREF FSM State[3:0]

0x00

Other Controls

0x0098

0x0099

0x009D

0x009E

0x009F

0x00A0

0x00A2

0x00A3

0x00A4

0x00AD

0x00B5

0x00B6

0x00B7

0x00B8

Reserved

0x00

0xAA

0x55

0x56

0x03

0x00

Reserved

Clock Distribution

0x00C8

Channel

Output 0

control

High

performance

mode

SYNC enable

Slip enable Reserved

Start-Up Mode[1:0]

Multislip Channel

enable enable

0xF3

0x00C9

0x00CA

0x00CB

0x00CC

0x00CD

0x00CE

0x00CF

0x00D0

12-Bit Channel Divider[7:0] (LSB)

12-Bit Channel Divider[11:8] (MSB)

0x04

0x00

Reserved

Fine Analog Delay[4:0]

Coarse Digital Delay[4:0]

12-Bit Multislip Digital Delay[7:0] (LSB)

12-Bit Multislip Digital Delay[11:8] (MSB)

Reserved

Dynamic

Output Mux Selection[1:0] 0x00

Idle at Zero[1:0]

Driver Mode[1:0]

Reserved

Driver Impedance[1:0]

0x01

driver

enable

0x00D2

Channel

Output 1

control

High

performance

mode

SYNC enable

Slip enable Reserved

Start-Up Mode[1:0]

Multislip Channel

0xFD

enable

0x00D3

0x00D4

0x00D5

0x00D6

0x00D7

0x00D8

0x00D9

0x00DA

12-Bit Channel Divider[7:0] (LSB)

12-Bit Channel Divider[11:8] (MSB)

0x00

0x01

0x00

Reserved

Fine Analog Delay[4:0]

Coarse Digital Delay[4:0]

12-Bit Multislip Digital Delay[7:0] (LSB)

Reserved

12-Bit Multislip Digital Delay[11:8] (MSB)

Reserved

Output Mux Selection[1:0] 0x00

Driver Impedance[1:0] 0x30

Idle at Zero[1:0]

Dynamic

Driver Mode[1:0]

Reserved

driver

enable

Rev. B | Page 29 of 43

HMC7043

Data Sheet

Default

Value

(Hex)

Address

(Hex)

Register Name

Bit 7 (MSB)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0 (LSB)

0x00DC

Channel

Output 2

control

High

performance

mode

SYNC enable

Slip enable Reserved

Start-Up Mode[1:0]

Multislip Channel

0xF3

enable

0x00DD

0x00DE

0x00DF

0x00E0

0x00E1

0x00E2

0x00E3

0x00E4

12-Bit Channel Divider[7:0] (LSB)

12-Bit Channel Divider[11:8] (MSB)

0x08

0x00

0x0

Reserved

Fine Analog Delay[4:0]

Coarse Digital Delay[4:0]

12-Bit Multislip Digital Delay[7:0] (LSB)

0x00

Reserved

12-Bit Multislip Digital Delay[11:8] (MSB)

Reserved

Output Mux Selection[1:0] 0x00

Idle at Zero[1:0]

Dynamic

Driver Mode[1:0]

Reserved

Driver Impedance[1:0]

0x01

driver

enable

0x00E6

Channel

Output 3

control

High

performance

mode

SYNC enable

Slip enable Reserved

Start-Up Mode[1:0]

Multislip Channel

0xFD

enable

0x00E7

0x00E8

0x00E9

0x00EA

0x00EB

0x00EC

0x00ED

0x00EE

12-Bit Channel Divider[7:0] (LSB)

12-Bit Channel Divider[11:8] (MSB)

0x00

0x01

0x00

Reserved

Fine Analog Delay[4:0]

Coarse Digital Delay[4:0]

12-Bit Multislip Digital Delay[7:0] (LSB)

Reserved

12-Bit Multislip Digital Delay[11:8] (MSB)

Reserved

Output Mux Selection[1:0] 0x00

Idle at Zero[1:0]

Dynamic

Driver Mode[1:0]

Reserved

Driver Impedance[1:0]

0x30

driver

enable

0x00F0

Channel

Output 4

control

High

performance

mode

SYNC enable

Slip enable Reserved

Start-Up Mode[1:0]

Multislip Channel

0xF3

enable

0x00F1

0x00F2

0x00F3

0x00F4

0x00F5

0x00F6

0x00F7

0x00F8

12-Bit Channel Divider[7:0] (LSB)

12-Bit Channel Divider[11:8] (MSB)

0x02

0x00

Reserved

Fine Analog Delay[4:0]

Coarse Digital Delay[4:0]

12-Bit Multislip Digital Delay[7:0] (LSB)

Reserved

12-Bit Multislip Digital Delay[11:8] (MSB)

Reserved

Output Mux Selection[1:0] 0x00

Idle at Zero[1:0]

Dynamic

Driver Mode[1:0]

Reserved

Driver Impedance[1:0]

0x01

driver

enable

0x00FA

Channel

Output 5

control

High

performance

mode

SYNC enable

Slip enable Reserved

Start-Up Mode[1:0]

Multislip Channel

0xFD

enable

0x00FB

0x00FC

0x00FD

0x00FE

0x00FF

0x0100

0x0101

0x0102

12-Bit Channel Divider[7:0] (LSB)

12-Bit Channel Divider[11:8] (MSB)

0x00

0x01

0x00

Reserved

Fine Analog Delay[4:0]

Coarse Digital Delay[4:0]

12-Bit Multislip Digital Delay[7:0] (LSB)

Reserved

12-Bit Multislip Digital Delay[11:8] (MSB)

Reserved

Output Mux Selection[1:0] 0x00

Driver Impedance[1:0] 0x30

Idle at Zero[1:0]

Dynamic

Driver Mode[1:0]

Reserved

driver

enable

Rev. B | Page 30 of 43

Data Sheet

HMC7043

Default

Value

(Hex)

Address

(Hex)

Register Name

Bit 7 (MSB)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0 (LSB)

0x0104

Channel

Output 6

control

High

performance

mode

SYNC enable

Slip enable Reserved

Start-Up Mode[1:0]

Multislip Channel

0xF3

enable

0x0105

0x0106

0x0107

0x0108

0x0109

0x010A

0x010B

0x010C

12-Bit Channel Divider[7:0] (LSB)

12-Bit Channel Divider[11:8] (MSB)

0x02

0x00

Reserved

Fine Analog Delay[4:0]

Coarse Digital Delay[4:0]

12-Bit Multislip Digital Delay[7:0] (LSB)

Reserved

12-Bit Multislip Digital Delay[11:8] (MSB)

Reserved

Output Mux Selection[1:0] 0x00

Idle at Zero[1:0]

Dynamic

Driver Mode[1:0]

Reserved

Driver Impedance[1:0]

0x01

driver

enable

0x010E

Channel

Output 7

control

High

performance

mode

SYNC enable

Slip enable Reserved

Start-Up Mode[1:0]

Multislip Channel

0xFD

enable

0x010F

0x0110

0x0111

0x0112

0x0113

0x0114

0x0115

0x0116

12-Bit Channel Divider[7:0] (LSB)

12-Bit Channel Divider[11:8] (MSB)

0x00

0x01

0x00

Reserved

Fine Analog Delay[4:0]

Coarse Digital Delay[4:0]

12-Bit Multislip Digital Delay[7:0] (LSB)

Reserved

12-Bit Multislip Digital Delay[11:8] (MSB)

Reserved

Output Mux Selection[1:0] 0x00

Idle at Zero[1:0]

Dynamic

Driver Mode[1:0]

Reserved

Driver Impedance[1:0]

0x30

driver

enable

0x0118

Channel

Output 8

control

High

performance

mode

SYNC enable

Slip enable Reserved

Start-Up Mode[1:0]

Multislip Channel

0xF3

enable

0x0119

0x011A

0x011B

0x011C

0x011D

0x011E

0x011F

0x0120

12-Bit Channel Divider[7:0] (LSB)

12-Bit Channel Divider[11:8] (MSB)

0x02

0x00

Reserved

Fine Analog Delay[4:0]

Coarse Digital Delay[4:0]

12-Bit Multislip Digital Delay[7:0] (LSB)

Reserved

12-Bit Multislip Digital Delay[11:8] (MSB)

Reserved

Output Mux Selection[1:0] 0x00

Idle at Zero[1:0]

Dynamic

Driver Mode[1:0]

Reserved

Driver Impedance[1:0]

0x01

driver

enable

0x0122

Channel

Output 9

control

High

performance

mode

SYNC enable

Slip enable Reserved

Start-Up Mode[1:0]

Multislip Channel

0xFD

enable

0x0123

0x0124

0x0125

0x0126

0x0127

0x0128

0x0129

0x012A

12-Bit Channel Divider[7:0] (LSB)

12-Bit Channel Divider[11:8] (MSB)

0x00

0x01

0x00

Reserved

Fine Analog Delay[4:0]

Coarse Digital Delay[4:0]

12-Bit Multislip Digital Delay[7:0] (LSB)

Reserved

12-Bit Multislip Digital Delay[11:8] (MSB)

Reserved

Output Mux Selection[1:0] 0x00

Driver Impedance[1:0] 0x30

Idle at Zero[1:0]

Dynamic

Driver Mode[1:0]

Reserved

driver

enable

Rev. B | Page 31 of 43

HMC7043

Data Sheet

Default

Value

(Hex)

Address

(Hex)

Register Name

Bit 7 (MSB)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0 (LSB)

0x012C

Channel

Output 10

control

High

performance

mode

SYNC enable

Slip enable Reserved

Start-Up Mode[1:0]

Multislip Channel

0xF3

enable

0x012D

0x012E

0x012F

0x0130

0x0131

0x0132

0x0133

0x0134

12-Bit Channel Divider[7:0] (LSB)

12-Bit Channel Divider[11:8] (MSB)

0x02

0x00

Reserved

Fine Analog Delay[4:0]

Coarse Digital Delay[4:0]

12-Bit Multislip Digital Delay[7:0] (LSB)

Reserved

12-Bit Multislip Digital Delay[11:8] (MSB)

Reserved

Output Mux Selection[1:0] 0x00

Idle at Zero[1:0]

Dynamic

Driver Mode[1:0]

Reserved

Driver Impedance[1:0]

0x01

driver

enable

0x0136

Channel

Output 11

control

High

performance

mode

SYNC enable

Slip enable Reserved

Start-Up Mode[1:0]

Multislip Channel

0xFD

enable

0x0137

0x0138

0x0139

0x013A

0x013B

0x013C

0x013D

0x013E

12-Bit Channel Divider[7:0] (LSB)

12-Bit Channel Divider[11:8] (MSB)

0x00

0x01

0x00

Reserved

Fine Analog Delay[4:0]

Coarse Digital Delay[4:0]

12-Bit Multislip Digital Delay[7:0] (LSB)

Reserved

12-Bit Multislip Digital Delay[11:8] (MSB)

Reserved

Output Mux Selection[1:0] 0x00

Idle at Zero[1:0]

Dynamic

Driver Mode[1:0]

Reserved

Driver Impedance[1:0]

0x30

driver

enable

0x0140

Channel

Output 12

control

High

performance

mode

SYNC enable

Slip enable Reserved

Start-Up Mode[1:0]

Multislip Channel

0xF3

enable

0x0141

0x0142

0x0143

0x0144

0x0145

0x0146

0x0147

0x0148

12-Bit Channel Divider[7:0] (LSB)

12-Bit Channel Divider[11:8] (MSB)

0x10

0x00

Reserved

Fine Analog Delay[4:0]

Coarse Digital Delay[4:0]

12-Bit Multi-Slip Digital Delay[7:0] (LSB)

Reserved

12-Bit Multislip Digital Delay[11:8] (MSB)

Reserved

Output Mux Selection[1:0] 0x00

Idle at Zero[1:0]

Dynamic

Driver Mode[1:0]

Reserved

Driver Impedance[1:0]

0x01

driver

enable

0x014A

Channel

Output 13

control

High

performance

mode

SYNC enable

Slip enable Reserved

Start-Up Mode [1:0]

Multislip Channel

0xFD

enable

0x014B

0x014C

0x014D

0x014E

0x014F

0x0150

0x0151

0x0152

12-Bit Channel Divider[7:0] (LSB)

12-Bit Channel Divider[11:8] (MSB)

0x00

0x01

0x00

Reserved

Fine Analog Delay[4:0]

Coarse Digital Delay[4:0]

12-Bit Multislip Digital Delay[7:0] (LSB)

Reserved

12-Bit Multislip Digital Delay[11:8] (MSB)

Reserved

Output Mux Selection[1:0] 0x00

Driver Impedance[1:0] 0x30

Idle at Zero[1:0]

Dynamic

Driver Mode[1:0]

Reserved

driver

enable

Rev. B | Page 32 of 43

Data Sheet

HMC7043

CONTROL REGISTER MAP BIT DESCRIPTIONS

Global Control (Register 0x0000 to Register 0x0009)

Table 21. Global Soft Reset Control

Address

Bits Bit Name

Settings

Description

Access

0x0000

[7:1] Reserved

Reserved

RW

0

Soft reset

Resets all registers, dividers, and FSMs to default values

Table 22. Global Request and Mode Control

Address Bits

Bit Name

Settings Description

Access

0x0001

7

Reseed request

Requests the centralized resync timer and FSM to reseed any of the output

dividers that are programmed to pay attention to sync events. This signal is

rising edge sensitive, and is only acknowledged if the resync FSM has

completed all events (has finished any previous pulse generator and/or

sync events, and is in the done state (SYSREF FSM State[3:0] = 0010).

RW

6

High performance

distribution path

High performance distribution path select. The clock distribution path

has two modes.

0

1

Power priority.

Noise priority. Provides the option for better noise floors on the divided

output signals.

5

Reserved

Reserved.

4

Reserved

Reserved.

3

Mute output drivers

Pulse generator request

Restart dividers/FSMs

Sleep mode

Mutes the output drivers (dividers still run in the background).

Asks for a pulse stream (see the Typical Programming Sequence section).

Resets all dividers and FSMs. Does not affect configuration registers.

Forces shutdown. Output network, and I/O buffers are disabled.

Reserved.

2

1

0

0x0002

[7:2]

1

Reserved

RW

Multislip request

Requests a slip or multislip event from all divider channels that are

sensitive to slip or multislip commands. The dividers are rising edge

sensitive and take some time to process the request, after which the

phase synchronization alarm is asserted.

0

Reserved

Reserved.

Table 23. Global Enable Control

Address

Bits

[7:6]

5

Bit Name

Settings

Description

Access

0x0003

Reserved

RW

RF reseeder enable

Reserved

Enable RF reseed for SYSREF

Reserved

[4:3]

2

SYSREF timer enable

Reserved

Enable internal SYSREF time reference

Reserved

1

0

Reserved

0x0004

7

Reserved

RW

[6:0]

Seven Pairs of 14-Channel Outputs Enable[6:0]

[0]

[1]

[2]

[3]

[4]

[5]

[6]

Enable Channel 0 and 1

Enable Channel 2 and 3

Enable Channel 4 and 5

Enable Channel 6 and 7

Enable Channel 8 and 9

Enable Channel 10 and 11

Enable Channel 12 and 13

Table 24. Global Mode and Enable Control

Address Bits Bit Name

0x0005 [7:0] Reserved

Settings Description

Access

Reserved

RW

Rev. B | Page 33 of 43

HMC7043

Data Sheet

Table 25. Global Clear Alarms

Address Bits Bit Name

Settings Description

Access

0x0006

[7:1] Reserved

Clear alarms

Reserved

Clear latched alarms

RW

0

Table 26. Global Miscellaneous Control

Address Bits Bit Name

Settings

Description

Reserved.

Access

0x0007

0x0008

[7:0] Reserved

[7:0] Reserved (scratchpad)

RW

Reserved. The user can write/read to this register to confirm input/outputs RW

to the HMC7043. This register does not affect device operation.

0x0009

[7:0] Reserved

Reserved.

RW

Input Buffer (Register 0x000A to Register 0x000B)

CLKIN

RFSYNCIN

Input Buffer Control

Table 27. CLKIN/

Address

and RFSYNCIN/

Bits Bit Name

Settings Description

Access

0x000A, 0x000B

[7:5] Reserved

Reserved

RW

[4:1] Input Buffer Mode[3:0]

Input buffer control

[0]

[1]

[2]

[3]

Enable internal 100 Ω termination

Enable ac coupling input mode

Enable LVPECL input mode

High-Z input enable

0

Buffer enable

Enable input buffer

GPIO/SDATA Control (Register 0x0046 to Register 0x0054)

Table 28. GPI Control

Address Bits Bit Name

Settings Description

Access

0x0046

[7:4] Reserved

Reserved

RW

[3:1] GPI Selection[2:0]

Select the GPI functionality, Bits[2:0]

Reserved

Put the chip into sleep mode

Issue a mute

Issue a pulse generator request

Issue a reseed request

Issue a restart request

Reserved

Issue a slip request

Reserved

Reserved.

Reserved

Reserved.

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

0

GPI enable

GPI function enable. Before changing the function of the pin, disable it first,

and then reenable it after the function change.¹

¹Note that it is possible to have a GPIO delete pin configured as both an output and an input.

Rev. B | Page 34 of 43

Data Sheet

HMC7043

Table 29. GPO Control

Address

Bits Bit Name

Reserved

[6:2] GPO Selection[4:0]

Settings Description

Access

0x0050

7

Reserved

RW

Select the GPO functionality, Bits[4:0]

Alarm signal

SDATA from SPI communication

00000

00001

00010

00011

00100

00101

00110

00111

01000

01001

01010

01011

01100

01101

01110

01111

10000

10001

10010

10011

10100

10101

10110

10111

11000

11001

11010

11011

11100

11101

11110

11111

SYSREF sync status has not synchronized since reset

Clock outputs phase status

Sync request status signal

Channel outputs FSM busy

SYSREF FSM State 0

SYSREF FSM State 1

SYSREF FSM State 2

SYSREF FSM State 3

Force Logic 1 to GPO

Force Logic 0 to GPO

Reserved

Pulse generator request status signal

Reserved

1

0

GPO mode

GPO enable

Selects the mode of GPO driver

Open-drain mode

CMOS mode

0

1

GPO driver enable

Table 30. SDATA Control

Address

Bits

[7:2]

1

Bit Name

Reserved

Settings

Description

Access

0x0054

Reserved

RW

SDATA mode

Selects the mode of SDATA driver

Open-drain mode

CMOS mode

0

1

0

SDATA enable

SDATA driver enable

Rev. B | Page 35 of 43

HMC7043

Data Sheet

SYSREF/SYNC (Register 0x005A to Register 0x005D)

Table 31. Pulse Generator Control

Address Bits

Bit Name

Settings Description

Access

0x005A

[7:3] Reserved

Reserved.

RW

[2:0] Pulse Generator

Mode

SYSREF output enable with pulse generator.

000

Level sensitive. When the GPI is configured to issue a pulse generator

Selection[2:0]

request (GPI Selection[2:0] = 100), or a pulse generator request is issued

through the SPI or as a SYNC pin-based pulse generator, run the pulse

generator. Otherwise, stop the pulse generator.

001

010

011

100

101

110

111

1 pulse.

2 pulses.

4 pulses.

8 pulses.

16 pulses.

Continuous mode (50% duty cycle).

Table 32. SYNC Control

Address Bits Bit Name

Settings Description

Access

0x005B

[7:3] Reserved

Reserved

RW

2

SYNC retime

0

1

Bypass the retime (non-deterministic SYNC event condition)

Retime the external SYNC (deterministic SYNC event condition)

1

0

Reserved

SYNC polarity

SYNC polarity (must be 0 if not using CLKIN/CLKIN as the input)

0

1

Positive

Negative

Table 33. SYSREF Timer Control

Address Bits Bit Name

Settings Description

Access

0x005C

[7:0] SYSREF Timer[7:0]

(LSB)

12-bit SYSREF timer setpoint LSB. This sets the internal beat frequency of

the master timer, which controls synchronization and pulse generator

events. Set the 12-bit timer to a submultiple of the lowest output SYSREF

frequency, and program it to be no faster than 4 MHz.

RW

0x005D

[7:4] Reserved

Reserved.

RW

[3:0] SYSREF Timer[11:8]

(MSB)

12-bit SYSREF timer setpoint MSB.

Clock Distribution Network (Register 0x0064 to Register 0x0065)

Table 34. Clock Input Control

Address

Bits

Bit Name

Settings

Description

Access

0x0064

[7:2] Reserved

Reserved

RW

1

0

Divide by 2 on clock input

Low frequency clock input

Use divide by 2 on clock input path

Changes bias to Class A for low frequency clock input

Table 35. Analog Delay Common Control

Address Bits Bit Name

0x0065 [7:1] Reserved

Analog delay low

power mode

Settings Description

Access

Reserved.

RW

0

Analog delay is low power mode. Can save power for low settings of analog

delay, but is not glitchless between setpoints.

Rev. B | Page 36 of 43

Data Sheet

HMC7043

Alarm Masks Register (Register 0x0071)

Table 36. Alarm Mask Control Register

Address Bits Bit Name

Settings Description

Access

0x0071

[7:5] Reserved

Reserved

RW

4

3

2

Sync request mask

Reserved

Clock outputs phase status

mask

If set, allow sync request signals to generate an alarm signal

Reserved

If set, allow clock output phases status signal to generate an alarm

signal

1

0

SYSREF sync status mask

Reserved

If set, allow SYSREF sync status signal to generate an alarm signal

Reserved

Product ID Registers (Register 0x0078 to 0x007A)

Table 37. Product ID Registers

Address

0x0078

0x0079

0x007A

Bits

[7:0]

Bit Name

Settings

Description

Access

Product ID Value[7:0] (LSB)

Product ID Value[15:8] (Mid)

Product ID Value[23:16] (MSB)

24-bit product ID value low

24-bit product ID value mid

24-bit product ID value high

R

Alarm Readback Status Registers (Register 0x007B to 0x007F)

Table 38. Alarm Readback Status Registers

Address Bits Bit Name

Settings Description

Access

0x007B

0x007D

[7:1] Reserved

Reserved.

R

0

Alarm signal

Readback alarm status from SPI.

Reserved.

[7:5] Reserved

R

4

3

2

Sync request status

Unsynchronized.

Reserved.

Reserved

Clock outputs phases

status

SYSREF alarm.

0

1

SYSREF of the HMC7043 is not valid; that is, the phase output is not stable.

SYSREF of the HMC7043 is valid; that is, the phase output is stable.

SYSREF SYNC status alarm.

1

SYSREF sync status

0

1

The HMC7043 has been synchronized with an external sync pulse or a

sync request from the SPI.

The HMC7043 never synchronized with an external sync pulse or a sync

request from the SPI.

0

Reserved

Reserved.

0x007F

[7:0] Reserved

R

Rev. B | Page 37 of 43

HMC7043

Data Sheet

SYSREF Status Register (Register 0x0091)

Table 39. SYSREF Status

Address Bits Bit Name

0x0091 [7:5] Reserved

Channel outputs

FSM busy

Settings Description

Access

Reserved.

R

4

One of clock outputs FSM requested clock, and it is running.

[3:0] SYSREF FSM

State[3:0]

Indicates the current step of the SYSREF reseed process. Note that the three

different progressions are caused by different trigger events (reseed, pulse

generator, reserved).

0000 Reset.

0010 Done.

0100 Get ready.

0101 Get ready.

0110 Get ready.

1010 Running (pulse generator).

1011 Start.

1100 Power up.

1101 Power up.

1110 Power up.

1111 Clear reset.

Bias Settings (Register 0x0096 to Register 0x00B8)

For optimum performance of the chip, Register 0x0098 to Register 0x00B8 must be programmed to a different value than their default value.

Table 40. Reserved Registers

Address

0x0098

0x0099

0x009D

0x009E

0x009F

0x00A0

0x00A2

0x00A3

0x00A4

0x00AD

0x00B5

0x00B6

0x00B7

0x00B8

Bits

Bit Name

Settings

Description

Access

RW

[7:0] Reserved

Reserved

Clock output driver low power setting (set to 0x4D instead of default value)

Clock output driver high power setting (set to 0xDF instead of default value)

Reserved

Rev. B | Page 38 of 43

Data Sheet

HMC7043

Clock Distribution (Register 0x00C8 to Register 0x0152)

The bit descriptions in Table 41 apply to all 14 channels.

Table 41. Channel 0 to Channel 13 Control

Address

Bits

Bit Name

Settings¹Description

High performance mode. Adjusts the divider and buffer

bias to improve swing/phase noise at the expense of

Access

0x00C8, 0x00D2, 0x00DC,

0x00E6, 0x00F0, 0x00FA,

0x0104, 0x010E, 0x0118,

0x0122, 0x012C, 0x0136,

0x0140, 0x014A

7

High performance

mode

RW

power.

6

5

SYNC enable

Slip enable

Susceptible to SYNC event. The channel can process a

SYNC event to reset the phase.

Susceptible to slip event. The channel can process a slip

request from SPI or GPI. Note that if slip enable is true,

but multislip is off, a channel slips by 1 clock input cycle

on an explicit slip request broadcast from the SPI/GPI.

4

Reserved

Reserved.

[3:2]

Start-Up

Mode[1:0]

Configures the channel to normal mode with

asynchronous startup, or to a pulse generator mode with

dynamic start-up. Note that this must be set to

asynchronous mode if the channel is unused.

00

01

10

11

Asynchronous.

Reserved.

Dynamic.

1

Multislip enable

Channel enable

Allow multislip operation (default = 0 for SYSREF, 1 for

DCLK).

Do not engage automatic multislip on channel startup.

Multislip events after SYNC or pulse generator request, if

the slip enable bit = 1.

0

1

0

Channel enable. If this bit is 0, channel is disabled.

0x00C9, 0x00D3, 0x00DD,

0x00E7, 0x00F1, 0x00FB,

0x0105, 0x010F, 0x0119,

0x0123, 0x012D, 0x0137,

0x0141, 0x014B

[7:0]

12-Bit Channel

Divider[7:0] (LSB)

12-bit channel divider setpoint LSB. The divider supports

even divide ratios from 2 to 4094. The supported odd

divide ratios are 1, 3, and 5. All even and odd divide ratios

have 50.0% duty cycle.

RW

0x00CA, 0x00D4, 0x00DE,

0x00E8, 0x00F2, 0x00FC,

0x0106, 0x0110, 0x011A,

0x0124, 0x012E, 0x0138,

0x0142, 0x014C

[7:4]

[3:0]

Reserved

Reserved.

12-Bit Channel

Divider[11:8]

(MSB)

12-bit channel divider setpoint MSB.

0x00CB, 0x00D5, 0x00DF,

0x00E9, 0x00F3, 0x00FD,

0x0107, 0x0111, 0x011B,

0x0125, 0x012F, 0x0139,

0x0143, 0x014D

[7:5]

[4:0]

Reserved

Reserved.

Fine Analog

Delay[4:0]

24 fine delay steps. Step size = 25 ps. Values bigger than

23 has no effect on analog delay.

0x00CC, 0x00D6, 0x00E0,

0x00EA, 0x00F4, 0x00FE,

0x0108, 0x0112, 0x011C,

0x0126, 0x0130, 0x013A,

0x0144, 0x014E

[7:5]

[4:0]

Reserved

Reserved.

Coarse Digital

Delay[4:0]

17 coarse delay steps. Step size = ½ input clock cycle. This

flip flop (FF)-based digital delay does not increase noise

level at the expense of power. Values bigger than 17 have

no effect on coarse delay.

0x00CD, 0x00D7, 0x00E1,

0x00EB, 0x00F5, 0x00FF,

0x0109, 0x0113, 0x011D,

0x0127, 0x0131, 0x013B,

0x0145, 0x014F

[7:0]

12-Bit Multislip

Digital Delay[7:0]

(LSB)

12-bit multislip digital delay amount LSB. Step size =

(delay amount: MSB + LSB) × input clock cycles. If

multislip enable bit = 1, any slip events (caused by GPI,

SPI, SYNC, or pulse generator events) repeat the number

of times set by 12-Bit Multislip Digital Delay[11:0] to

adjust the phase by step size.

RW

Rev. B | Page 39 of 43

HMC7043

Data Sheet

Address

Bits

[7:4]

[3:0]

Bit Name

Settings¹Description

Access

0x00CE, 0x00D8, 0x00E2,

0x00EC, 0x00F6, 0x0100,

0x010A, 0x0114, 0x011E,

0x0128, 0x0132, 0x013C,

0x0146, 0x0150

Reserved

Reserved.

RW

12-Bit Multislip

Digital Delay[11:8]

(MSB)

12-bit multislip digital delay amount MSB.

0x00CF, 0x00D9, 0x00E3,

0x00ED, 0x00F7, 0x0101,

0x010B, 0x0115, 0x011F,

0x0129, 0x0133, 0x013D,

0x0147, 0x0151

[7:2]

[1:0]

Reserved

Reserved.

RW

Output Mux

Selection[1:0]

Channel output mux selection.

Channel divider output.

Analog delay output.

00

01

10

11

Other channel of the clock group pair.

Input clock (fundamental). Fundamental can also be

generated with 12-bit channel divider ratio = 1.

0x00D0, 0x00DA, 0x00E4,

0x00EE, 0x00F8, 0x0102,

0x010C, 0x0116, 0x0120,

0x012A, 0x0134, 0x013E,

0x0148, 0x0152

[7:6]

Idle at Zero[1:0]

Idle at Logic 0 selection (pulse generator mode only).

Force to Logic 0 or VCM.

RW

00

01

10

11

Normal mode (selection for DCLK).

Reserved.

Force to Logic 0.

Force outputs to float, goes naturally to VCM.

Dynamic driver enable (pulse generator mode only).

Driver is enabled/disabled with channel enable bit.

Driver is dynamically disabled with pulse generator events.

Output driver mode selection.

CML mode.

LVPECL mode.

LVDS mode.

CMOS mode.

5

Dynamic driver

enable

0

1

[4:3]

Driver Mode[1:0]

00

01

10

11

2

Reserved

Reserved.

[1:0]

Driver

Impedance[1:0]

Output driver impedance selection for CML mode.

Internal resistor disable.

Internal 100 Ω resistor enable per output pin.

Reserved.

00

01

10

11

Internal 50 Ω resistor enable per output pin.

¹X means don’t care.

Rev. B | Page 40 of 43

Data Sheet

HMC7043

APPLICATIONS INFORMATION

60 TO 150

SECONDS

RAMP UP

3°C/SECOND MAX

EVALUATION PCB AND SCHEMATIC

260 – 5/0°C

For the circuit board in this application, use RF circuit design

techniques. Ensure that signal lines have 50 Ω impedance.

Connect the package ground leads and exposed paddle directly

to the ground plane similar to that shown in Figure 32 and

Figure 33. Use a sufficient number of via holes to connect the

top and bottom ground planes. The evaluation circuit board is

available from Analog Devices, Inc., upon request.

217°C

150°C TO 200°C

RAMP DOWN

6°C/SECOND MAX

TIME (Second)

60 TO 180

SECONDS

20 TO 40

SECONDS

480 SECONDS MAX

The typical Pb-free reflow solder profile shown in Figure 31 is

based on JEDEC J-STD-20C.

Figure 31. Pb-Free Reflow Solder Profile

Figure 32. Evaluation PCB Layout, Top Side

Rev. B | Page 41 of 43

HMC7043

Data Sheet

Figure 33. Evaluation PCB Layout, Bottom Side

Rev. B | Page 42 of 43

Data Sheet

HMC7043

OUTLINE DIMENSIONS

7.10

7.00 SQ

6.90

0.31

0.25

0.19

PIN 1

INDICATOR

PIN 1

INDICATOR

37

48

36

1

0.50

BSC

5.66

5.60 SQ

5.54

EXPOSED

PAD

25

12

13

24

0.45

0.40

0.35

0.20 MIN

TOP VIEW

BOTTOM VIEW

5.50 REF

0.90

0.85

0.80

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

0.05 MAX

0.02 NOM

COPLANARITY

0.08

SECTION OF THIS DATA SHEET.

SEATING

PLANE

0.20 REF

Figure 34. 48-Lead Lead Frame Chip Scale Package [LFCSP]

7 mm × 7 mm Body and 0.85 mm Package Height

(HCP-48-1)

Dimensions shown in millimeters

NOTE 1

4.10

NOTE 6

2.10

2.00

1.90

12.10

12.00

11.90

4.00

3.90

1.85

1.75

1.65

0.35

0.30

0.25

A

Ø 1.5 ~ 1.6

7.60

7.50

7.40

NOTE 6

16.30

16.00

15.70

7.35

7.25

7.15

NOTE 4

1.20

1.10

1.00

TOP VIEW

A

Ø 1.5 MIN

7.35

7.25

DETAIL A

NOTE 5

DIRECTION OF FEED

7.15

SECTION A-A

NOTE 4

0.25

NOTES:

1. 10 SPROCKET HOLE PITCH CUMUL ATIVE TOLERANCE ± 0.20

2. CAMBER IN COMPLIANCE WITH EIA 481

3. MATERIAL: CONDUCTIVE BLACK PO LYSTYRENE

4. MEASURED ON A PLANE 0.30 mm ABOVE THE BOTTOM OF

THE POCKET

R 0.25

DETAIL A

5. MEASURED FROM A PLANE ON THE INSIDE BOTTOM OF

THE POCKET TO THE TOP SURFACE OF THE CARRIER

6. POCKET POSITION RELATIVE TO SPROCKET HOLE MEASURED

AS TRUE POSITION OF POCKET, NOT POCKET HOLE

Figure 35. LFCSP Tape and Reel Outline Dimensions

Dimensions shown in millimeters

ORDERING GUIDE

Model¹

Temperature Range Lead Finish

MSL Rating²Package Description

Package Option

Branding³

7043

HMC7043LP7FE

−40^oC to +85°C

NiPdAu

MSL-3

48-Lead Lead Frame Chip HCP-48-1

Scale Package [LFCSP]

XXXX

7043

XXXX

HMC7043LP7FETR −40^oC to +85°C

NiPdAu

MSL-3

48-Lead Lead Frame Chip HCP-48-1

Scale Package [LFCSP]

EK1HMC7043LP7F −40°C to +85°C

¹E = RoHS Compliant Part.

Evaluation Kit

²The maximum peak reflow temperature is 260°C for the HMC7043LP7FE.

³Four-digit lot number represented by XXXX.

registered trademarks are the property of their respective owners.

D13114-0-7/16(B)

Rev. B | Page 43 of 43


型号：	HMC7043
厂家：	ADI
描述：	JEDEC JESD204B support
文件：	总44页 (文件大小：919K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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