HMC8100 [ADI]
High linearity: supports modulations to 1024 QAM;
| 型号： | HMC8100 |
| 厂家： | 
ADI |
| 描述： | High linearity: supports modulations to 1024 QAM |
| 文件： | 总28页 (文件大小：706K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Intermediate Frequency Receiver,
800 MHz to 4000 MHz
HMC8100LP6JE
Data Sheet
FEATURES
GENERAL DESCRIPTION
High linearity: supports modulations to 1024 QAM
Rx IF range: 80 MHz to 200 MHz
Rx RF range: 800 MHz to 4000 MHz
Rx power control: 80 dB
SPI programmable bandpass filters
SPI controlled interface
The HMC8100LP6JE is a highly integrated intermediate
frequency (IF) receiver chip that converts radio frequency (RF)
input signals ranging from 800 MHz to 4000 MHz down to a
single-ended intermediate frequency (IF) signal of 140 MHz at its
output.
The IF receiver chip is housed in a compact 6 mm × 6 mm
LFCSP package and supports complex modulations up to
1024 QAM. The HMC8100LP6JE device includes two variable
gain amplifiers (VGAs), three power detectors, a programmable
automatic gain control (AGC) block, and selected integrated
band-pass filters with 14 MHz, 28 MHz, 56 MHz, and 112 MHz
bandwidth. The HMC8100LP6JE also supports baseband IQ
interfaces after the mixer so that the chips can be used in the
full outdoor units (ODU) configuration. The HMC8100LP6JE
supports all standard microwave frequency bands from 6 GHz
to 42 GHz.
40-lead, 6 mm × 6 mm LFCSP package
APPLICATIONS
Point to point communications
Satellite communications
Wireless microwave backhaul systems
FUNCTIONAL BLOCK DIAGRAM
HMC8100
DVDD
AMP2_P
1
2
3
4
5
6
7
8
9
30 VDD5V
SPI
OTP
29 IRM_I_N
AMP2_N
28 IRM_I_P
FILTER
VCC_FILTER
FILTER2P
VCC_AMP3
GND1
27 VCC_IRM
26 VCC_VGA1_BALUN
25 VCC_VGA1
14MHz
28MHz
56MHz
112MHz
FILTER1P
24
23
AGC
VCC_AMP1
VCC_BB
GND2
22 AMP1
21 GND
VGA_EXT_CAP 10
PACKAGE
BASE
GND
Figure 1.
Rev. A
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Last Content Update: 11/01/2016
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HMC8100LP6JE
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Typical Performance Characteristics..............................................9
External AGC Configuration.......................................................9
Internal AGC Configuration..................................................... 16
Theory of Operation ...................................................................... 18
Register Array Assignments and Serial Interface................... 18
Register Descriptions..................................................................... 20
Register Array Assignments...................................................... 20
Applications Information.............................................................. 24
Schematic/Typical Application Circuit.................................... 24
Evaluation Printed Circuit Board (PCB) ................................ 25
Outline Dimensions....................................................................... 27
Ordering Guide .......................................................................... 27
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Electrical Characteristics: 800 MHz to 1800 MHz RF
Frequency Range .......................................................................... 3
Electrical Characteristics: 1800 MHz to 2800 MHz RF
Frequency Range .......................................................................... 3
Electrical Characteristics: 2800 MHz to 4000 MHz RF
Frequency Range .......................................................................... 4
Absolute Maximum Ratings............................................................ 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Descriptions............................. 7
REVISION HISTORY
5/2016—v00.0416 to Rev. A
This Hittite Microwave Products data sheet has been reformatted
to meet the styles and standards of Analog Devices, Inc.
Updated Format..................................................................Universal
Added Pin Configuration Diagram, Renumbered
Sequentially ....................................................................................... 7
Added Ordering Guide.................................................................. 22
04/2016—v00.0416: Initial Version
Rev. A | Page 2 of 27
Data Sheet
HMC8100LP6JE
SPECIFICATIONS
TA = 25°C, IF frequency = 140 MHz, local oscillator (LO) input signal level = 0 dBm, RF input signal level = −80 dBm per tone, filter
bandwidth = 56 MHz, IF gain limit (decimal) = 7, sideband select = lower sideband, AGC select = external AGC, unless otherwise noted,
see the Typical Performance Characteristics section.
ELECTRICAL CHARACTERISTICS: 800 MHz TO 1800 MHz RF FREQUENCY RANGE
Table 1.
Parameter
Min
Typ
Max
Unit
OPERATING CONDITIONS
LO Frequency Range
IF Frequency Range
RF INPUT INTERFACE
Input Impedance
600
80
2000
200
MHz
MHz
50
10
Ω
dB
Return Loss
IF OUTPUT INTERFACE
Input Impedance
Return Loss
50
13
Ω
dB
8
2
LO INPUT INTERFACE
Input Impedance
Return Loss
50
9
Ω
dB
DYNAMIC PERFORMANCE
Power Conversion Gain
RF VGA Dynamic Range
IF VGA Dynamic Range
Image Rejection
Noise Figure at PIN (One Tone)
Output Third-Order Intercept (OIP3)
Output 1 dB Compression Point (OP1dB)
LO Leakage at the IF Input
LO Leakage at the RF Input
RF Leakage at the IF Output
POWER SUPPLY
81
40
86
52
49
36
5
16
11
−48
−75
−68
dB
dB
dB
dBc
dB
dBm
dBm
dBm
dBm
dBm
30
8
11
7
−26
−70
−60
Supply Voltage
VCCX
VCC − VGA1
3.3
3.3
V
V
Supply Current
VCCX
VCC − VGA1
600
11
mA
μA
1 VCC – VGA = VC_VGA_IF + VC_VGA_RF can be adjusted from 3.3 V (minimum ATTEN) to 0 V (maximum ATTEN) to control the IF and RF VGA in external AGC mode.
ELECTRICAL CHARACTERISTICS: 1800 MHz TO 2800 MHz RF FREQUENCY RANGE
Table 2.
Parameter
Min
Typ
Max
Unit
OPERATING CONDITIONS
LO Frequency Range
IF Frequency Range
RF INPUT INTERFACE
Input Impedance
Return Loss
1600
80
3000
200
MHz
MHz
50
12
Ω
dB
Rev. A | Page 3 of 27
HMC8100LP6JE
Data Sheet
Parameter
IF OUTPUT INTERFACE
Input Impedance
Min
8
Typ
Max
Unit
50
13
Ω
dB
Return Loss
LO INPUT INTERFACE
Input Impedance
Return Loss
50
15
Ω
dB
7
DYNAMIC PERFORMANCE
Power Conversion Gain
RF VGA Dynamic Range
IF VGA Dynamic Range
Image Rejection
Noise Figure at PIN (One Tone)
Output Third-Order Intercept (OIP3)
Output 1 dB Compression Point (OP1dB)
LO Leakage at the IF Input
LO Leakage at the RF Input
RF Leakage at the IF Output
POWER SUPPLY
77
40
40
30
85
47
49
36
5
18
11
−55
−73
−73
dB
dB
dB
dBc
dB
dBm
dBm
dBm
dBm
dBm
7
11
7
−45
−66
−65
Supply Voltage
VCCX
VCC − VGA1
3.3
3.3
V
V
Supply Current
VCCX
VCC − VGA1
600
11
mA
μA
1 VCC – VGA = VC_VGA_IF + VC_VGA_RF can be adjusted from 3.3 V (minimum ATTEN) to 0 V (maximum ATTEN) to control the IF and RF VGA in external AGC mode.
ELECTRICAL CHARACTERISTICS: 2800 MHz TO 4000 MHz RF FREQUENCY RANGE
Table 3.
Parameter
Min
Typ
Max
Unit
OPERATING CONDITIONS
LO Frequency Range
IF Frequency Range
RF INPUT INTERFACE
Input Impedance
2600
80
4200
200
MHz
MHz
50
13
Ω
dB
Return Loss
IF OUTPUT INTERFACE
Input Impedance
Return Loss
50
13
Ω
dB
8
7
LO INPUT INTERFACE
Input Impedance
Return Loss
50
14
Ω
dB
DYNAMIC PERFORMANCE
Power Conversion Gain
RF VGA Dynamic Range
IF VGA Dynamic Range
Image Rejection
72
35
82
47
49
38
5
dB
dB
dB
dBc
dB
30
12
Noise Figure at PIN (One Tone)
Output Third-Order Intercept (OIP3)
8
22
dBm
Rev. A | Page 4 of 27
Data Sheet
HMC8100LP6JE
Parameter
Min
7
Typ
12
−65
−66
−72
Max
Unit
dBm
dBm
dBm
dBm
Output 1 dB Compression Point (OP1dB)
LO Leakage at the IF Input
LO Leakage at the RF Input
RF Leakage at the IF Output
POWER SUPPLY
−48
−62
−65
Supply Voltage
VCCX
VCC − VGA1
3.3
3.3
V
V
Supply Current
VCCX
VCC − VGA1
600
11
mA
μA
1 VCC – VGA = VC_VGA_IF + VC_VGA_RF can be adjusted from 3.3 V (minimum ATTEN) to 0 V (maximum ATTEN) to control the IF and RF VGA in external AGC mode.
Rev. A | Page 5 of 27
HMC8100LP6JE
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 4.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Parameter
RF Input
LO Input
VCCX
Rating
10 dBm
10 dBm
−0.5 V to +5.5 V
−0.3 V to +3.6 V
150°C
Maximum Junction Temperature to
Maintain 1 Million Hour MTTF
ESD CAUTION
Thermal Resistance (RTH), Junction to
Ground Paddle
10.5°C/W
Temperature
Operating
Storage
Maximum Peak Reflow Temperature
(MSL3)
−40°C to +85°C
−65°C to +150°C
260°C
ESD Sensitivity (Human Body Model)
2000 V (Class 2)
Rev. A | Page 6 of 27
Data Sheet
HMC8100LP6JE
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
DVDD
AMP2_P
AMP2_N
1
2
3
4
5
6
7
8
9
30 VDD5V
29 IRM_I_N
28 IRM_I_P
27 VCC_IRM
26 VCC_VGA1_BALUN
25 VCC_VGA1
24 FILTER1P
23 VCC_AMP1
22 AMP1
21 GND
VCC_FILTER
FILTER2P
VCC_AMP3
GND1
VCC_BB
GND2
VGA_EXT_CAP 10
HMC8100
TOP VIEW
(Not to Scale)
NOTES
1. EXPOSED PAD. CONNECT THE EXPOSED PAD TO A LOW
IMPEDANCE THERMAL AND ELECTRICAL GROUND PLANE.
Figure 2. Pin Configuration
Table 5. Pin Function Descriptions
Pin No. Mnemonic Description
1
2
DVDD
AMPT2_P
SPI Digital Power Supply. See Figure 52 for the required components.
Second Differential Amplifier Output (Positive).
3
AMP2_N
Second Differential Amplifier Output (Negative).
4
5
VCC_FILTER
FILTER2P
Power Supply for the Filter. See Figure 52 for the required components.
Input of the Third External Filter Amplifier.
6
VCC_AMP3
GND1, GND2, GND3
VCC_BB
VGA_EXT_CAP
RX_OUT
VCC_VGA3
AUX_OUT
PD3_IN
PD3_OUT/RSSI
VC_VGA_IF/CAP−
VC_VGA_RF/CAP+
VCC_PD1
PD1_OUT
RFIN
AMP1
VCC_AMP1
FILTER1P
VCC_VGA1
VCC_VGA1_BALUN
VCC_IRM
Power Supply for the Third External Filter Amplifier. See Figure 52 for the required components.
Ground Connect.
Power Supply for the Baseband Blocks. See Figure 52 for the required components.
External Capacitor for VGA3. See Figure 52 for the required components.
Receiver Output.
Power Supply for VGA3. See Figure 52 for the required components.
Receiver Auxiliary Output.
Receive AGC Loop Input.
7, 9, 21
8
10
11
12
13
14
15
16
17
18
19
20
22
23
24
25
26
27
28
29
30
31
Third Power Detector Output.
Control Voltage of IFVGA/AGC Integrator Capacitor. See Figure 52 for the required components.
Control Voltage of RFVGA/AGC Integrator Capacitor. See Figure 52 for the required components.
Power Supply for the First Power Detector. See Figure 52 for the required components.
First Power Detector Output.
Radio Frequency Input. This pin is matched to 50 Ω.
Single-Ended Output of Amplifier 1.
Power Supply for AMP1. See Figure 52 for the required components.
RFVGA Input.
Power Supply for the RFVGA. See Figure 52 for the required components.
Power Supply for RFVGA Balun. See Figure 52 for the required components.
Power Supply for the Image Reject Mixer. See Figure 52 for the required components.
Positive In-Phase IF Output for the Image Reject Mixer.
Negative In-Phase IF Output for the Image Reject Mixer.
5 V Supply for Overtemperature (OTP) Burning. See Figure 52 for the required components.
Positive Quadrature IF Output for the Image Reject Mixer.
Rev. A | Page 7 of 27
IRM_I_P
IRM_I_N
VDD5V
IRM_Q_P
HMC8100LP6JE
Data Sheet
32
33
34
35
36
37
38
39
40
IRM_Q_N
LOP
LON
SEN
SCLK
SDI
SDO
RST
REF_CLK_P
EPAD
Negative Quadrature IF Output for the Image Reject Mixer.
Local Oscillator Input (Positive). This pin is ac-coupled and matched to 50 Ω.
Local Oscillator Input (Negative). This pin is ac-coupled and matched to 50 Ω.
SPI Serial Enable.
SPI Clock Digital Input.
SPI Serial Data Input.
SPI Serial Data Output.
SPI Reset.
Filter Calibration Clock.
Exposed Pad. Connect the exposed pad to a low impedance thermal and electrical ground plane.
Rev. A | Page 8 of 27
Data Sheet
HMC8100LP6JE
TYPICAL PERFORMANCE CHARACTERISTICS
EXTERNAL AGC CONFIGURATION
Lower sideband selected, maximum gain.
90
90
85
80
75
70
65
60
85
80
75
70
14MHz
28MHz
65
+85°C
+25°C
–40°C
56MHz
112MHz
EXT
60
0.8
0.8
1.2
1.6
2.0
2.4
2.8
3.2
3.6
4.0
1.2
1.6
2.0
2.4
2.8
3.2
3.6
4.0
RF FREQUENCY (GHz)
RF FREQUENCY (GHz)
Figure 3. Conversion Gain vs. RF Frequency
over Internal and External Filters
Figure 6. Conversion Gain vs. RF Frequency over Temperature, 56 MHz Filter
90
90
85
80
75
70
85
80
75
70
65
60
–4dBm
–2dBm
0dBm
+2dBm
+4dBm
3.63V
3.30V
2.97V
65
60
0.8
1.2
1.6
2.0
2.4
2.8
3.2
3.6
4.0
0.8
1.2
1.6
2.0
2.4
2.8
3.2
3.6
4.0
RF FREQUENCY (GHz)
RF FREQUENCY (GHz)
Figure 7. Conversion Gain vs. RF Frequency at Various VCCx, 56 MHz Filter
Figure 4. Conversion Gain vs. RF Frequency at Various Local
Oscillator (LO) Powers, 56 MHz Filter
45
45
+85°C
+25°C
–40°C
+85°C
+25°C
–40°C
35
35
25
15
25
15
5
5
–5
–5
–15
–25
–15
–25
3.3 3.0 2.7 2.4 2.1 1.8 1.5 1.2 0.9 0.6 0.3
VC_VGA_RF (V)
0
3.3 3.0 2.7 2.4 2.1 1.8 1.5 1.2 0.9 0.6 0.3
0
VC_VGA_RF (V)
Figure 5. Conversion Gain vs. VC_VGA_RF at RF = 1 GHz, 56 MHz Filter
(RF Input Power = −40 dBm, VC_VGA_IF = 0 V)
Figure 8. Conversion Gain vs. VC_VGA_RF at RF = 2 GHz, 56 MHz Filter
(RF Input Power = −40 dBm, VC_VGA_IF = 0 V)
Rev. A | Page 9 of 27
HMC8100LP6JE
Data Sheet
Lower sideband selected, maximum gain.
45
90
80
70
60
50
40
30
20
+85°C
+25°C
–40°C
+85°C
+25°C
–40°C
35
25
15
5
–5
–15
–25
3.3 3.0 2.7 2.4 2.1 1.8 1.5 1.2 0.9 0.6 0.3
VC_VGA_RF (V)
0
3.3 3.0 2.7 2.4 2.1 1.8 1.5 1.2 0.9 0.6 0.3
VC_VGA_IF (V)
0
Figure 9. Conversion Gain vs. VC_VGA_RF at RF = 4 GHz, 56 MHz Filter
(RF Input Power = −40 dBm, VC_VGA_IF = 0 V)
Figure 12. Conversion Gain vs. VC_VGA_IF at RF = 1 GHz, 56 MHz Filter
(VC_VGA_RF = 3.3 V)
90
90
+85°C
+25°C
–40°C
+85°C
+25°C
–40°C
80
80
70
60
50
40
30
20
70
60
50
40
30
20
3.3 3.0 2.7 2.4 2.1 1.8 1.5 1.2 0.9 0.6 0.3
VC_VGA_IF (V)
0
3.3 3.0 2.7 2.4 2.1 1.8 1.5 1.2 0.9 0.6 0.3
VC_VGA_IF (V)
0
Figure 10. Conversion Gain vs. VC_VGA_IF at RF = 2 GHz, 56 MHz Filter
(VC_VGA_RF = 3.3 V)
Figure 13. Conversion Gain vs. VC_VGA_IF at RF = 4 GHz, 56 MHz Filter,
(VC_VGA_RF = 3.3 V)
10
10
14MHz
+85°C
9
8
7
6
5
4
3
2
1
0
9
28MHz
56MHz
112MHz
+25°C
–40°C
8
7
6
5
4
3
2
1
0
0.8
1.2
1.6
2.0
2.4
2.8
3.2
3.6
4.0
0.8
1.2
1.6
2.0
2.4
2.8
3.2
3.6
4.0
RF FREQUENCY (GHz)
RF FREQUENCY (GHz)
Figure 11. Noise Figure vs. RF Frequency over Internal Filters
Figure 14. Noise Figure vs. RF Frequency over Temperature, 56 MHz Filter
Rev. A | Page 10 of 27
Data Sheet
HMC8100LP6JE
Lower sideband selected, maximum gain.
10
10
9
8
7
6
5
4
3
2
1
0
–4dBm
–2dBm
0dBm
+2dBm
+4dBm
3.63V
3.30V
2.97V
9
8
7
6
5
4
3
2
1
0
0.8
1.2
1.6
2.0
2.4
2.8
3.2
3.6
4.0
0.8
1.2
1.6
2.0
2.4
2.8
3.2
3.6
4.0
RF FREQUENCY (GHz)
RF FREQUENCY (GHz)
Figure 15. Noise Figure vs. RF Frequency at Various LO Powers, 56 MHz Filter
Figure 18. Noise Figure vs. RF Frequency at Various VCCx, 56 MHz Filter
50
45
40
35
30
25
20
15
50
45
40
35
30
25
20
15
10
10
14MHz
+85°C
28MHz
+25°C
56MHz
112MHz
5
5
–40°C
0
0.8
0
0.8
1.2
1.6
2.0
2.4
2.8
3.2
3.6
4.0
1.2
1.6
2.0
2.4
2.8
3.2
3.6
4.0
RF FREQUENCY (GHz)
RF FREQUENCY (GHz)
Figure 16. Image Rejection vs. RF Frequency over Internal Filters
Figure 19. Image Rejection vs. RF Frequency over Temperature, 56 MHz Filter
50
45
40
35
30
25
20
50
45
40
35
30
25
20
15
15
–4dBm
–2dBm
0dBm
10
10
3.63V
3.30V
2.97V
+2dBm
+4dBm
5
5
0
0.8
0
0.8
1.2
1.6
2.0
2.4
2.8
3.2
3.6
4.0
1.2
1.6
2.0
2.4
2.8
3.2
3.6
4.0
RF FREQUENCY (GHz)
RF FREQUENCY (GHz)
Figure 17. Image Rejection vs. RF Frequency at Various LO Powers,
56 MHz Filter
Figure 20. Image vs. RF Frequency at Various VCCx, 56 MHz Filter
Rev. A | Page 11 of 27
HMC8100LP6JE
Data Sheet
Lower sideband selected, maximum gain.
32
32
28
24
20
16
12
8
14MHz
28MHz
+85°C
+25°C
–40°C
28
56MHz
112MHz
24
20
16
12
8
4
4
0
0.8
0
0.8
1.2
1.6
2.0
2.4
2.8
3.2
3.6
4.0
1.2
1.6
2.0
2.4
2.8
3.2
3.6
4.0
RF FREQUENCY (GHz)
RF FREQUENCY (GHz)
Figure 21. Output IP3 vs. RF Frequency over Internal Filters
Figure 24. Output IP3 vs. RF Frequency over Temperature, 56 MHz Filter
32
32
3.63V
3.30V
2.97V
–4dBm
–2dBm
0dBm
+2dBm
+4dBm
28
24
20
16
12
8
28
24
20
16
12
8
4
4
0
0.8
0
0.8
1.2
1.6
2.0
2.4
2.8
3.2
3.6
4.0
1.2
1.6
2.0
2.4
2.8
3.2
3.6
4.0
RF FREQUENCY (GHz)
RF FREQUENCY (GHz)
Figure 22. Output IP3 vs. RF Frequency at Various LO Powers, 56 MHz Filter
Figure 25. Output IP3 vs. RF Frequency at Various VCCx, 56 MHz Filter
0
0
+85°C
+25°C
–40°C
+85°C
+25°C
–40°C
–5
–5
–10
–15
–20
–25
–30
–10
–15
–20
–25
–30
–35
–35
0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0 4.4 4.8
0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0 4.4 4.8
RF FREQUENCY (GHz)
LO FREQUENCY (GHz)
Figure 23. RF Return Loss vs. RF Frequency over Temperature (Optimize RF
Return Loss by Adjusting Capacitor C12, see Figure 52)
Figure 26. LO Return Loss vs. LO Frequency over Temperature
Rev. A | Page 12 of 27
Data Sheet
HMC8100LP6JE
Lower sideband selected, maximum gain.
0
0
–10
–20
–30
–40
–50
–60
–70
–80
+85°C
+25°C
–40°C
LO TO RF LEAKAGE
LO TO IF LEAKAGE
–5
–10
–15
–20
–25
–30
–35
0
0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50
IF FREQUENCY (GHz)
0.8
1.2
1.6
2.0
2.4
2.8
3.2
3.6
4.0
4.4
LO FREQUENCY (GHz)
Figure 30. LO Leakage vs. LO Frequency at RF and IF Ports with 56 MHz Filter
Figure 27. IF Return Loss vs. IF Frequency over Temperature
0
0
LO TO (AMP2_P + AMP2_N) LEAKAGE
–10
RF TO IF LEAKAGE
RF TO (AMP2_P + AMP2_N) LEAKAGE
–10
–20
–30
–40
–50
–60
–70
–80
–20
–30
–40
–50
–60
–70
–80
0.8
1.2
1.6
2.0
2.4
2.8
3.2
3.6
4.0
0.8
1.2
1.6
2.0
2.4
2.8
3.2
3.6
4.0
LO FREQUENCY (GHz)
RF FREQUENCY (GHz)
Figure 31. LO Leakage vs. LO Frequency at (AMP2_P + AMP2_N) Pins
Figure 28. RF Leakage vs. RF Frequency at IF Port with 56 MHz Filter and at
(AMP2_P + AMP2_N) Pins
20
20
+85°C
+25°C
–40°C
+85°C
+25°C
–40°C
10
10
0
–10
–20
–30
–40
0
–10
–20
–30
–40
–50
–50
0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50
0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50
IF FREQUENCY (GHz)
IF FREQUENCY (GHz)
Figure 32. 28 MHz Internal Filter Response vs. IF Frequency at RF = 1 GHz
(RF Input Power = −30 dBm, Adjusted VC_VGA_IF and VC_VGA_RF to
Achieve 10 dB of Gain)
Figure 29. 14 MHz Internal Filter Response vs. IF Frequency at RF = 1 GHz
(RF Input Power = −30 dBm, Adjusted VC_VGA_IF and VC_VGA_RF to
Achieve 10 dB of Gain)
Rev. A | Page 13 of 27
HMC8100LP6JE
Data Sheet
Lower sideband selected, maximum gain.
20
20
10
+85°C
+25°C
–40°C
+85°C
+25°C
–40°C
10
0
0
–10
–20
–30
–40
–50
–10
–20
–30
–40
–50
0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50
0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50
IF FREQUENCY (GHz)
IF FREQUENCY (GHz)
Figure 33. 56 MHz Internal Filter Response vs. IF Frequency at RF = 1 GHz
(RF Input Power = −30 dBm, Adjusted VC_VGA_IF and VC_VGA_RF to
Achieve 10 dB of Gain)
Figure 36. 112 MHz Internal Filter Response vs. IF Frequency at RF = 1 GHz
2.0
2.0
+85°C
+85°C
1.9
1.9
+25°C
+25°C
–40°C
1.8
–40°C
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
–45 –40 –35 –30 –25 –20 –15 –10 –5
0
5
10
–50 –45 –40 –35 –30 –25 –20 –15 –10 –5
0
5
10
IF OUTPUT POWER (dBm)
IF OUTPUT POWER (dBm)
Figure 34. PD3 Output Voltage vs. IF Power Output at RF = 1 GHz,
56 MHz Filter
Figure 37. PD3 Output Voltage vs. IF Power Output at RF = 2 GHz,
56 MHz Filter
2.0
15
14
13
12
11
10
9
+85°C
+25°C
1.9
–40°C
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
8
7
+85°C
+25°C
6
–40°C
5
0.8
–55 –50 –45 –40 –35 –30 –25 –20 –15 –10 –5
0
5
1.2
1.6
2.0
2.4
2.8
3.2
3.6
4.0
IF OUTPUT POWER (dBm)
RF FREQUENCY (GHz)
Figure 35. PD3 Output Voltage vs. IF Power Output at RF = 4 GHz,
56 MHz Filter
Figure 38. Output P1dB vs. RF Frequency over Temperature, 56 MHz Filter
Rev. A | Page 14 of 27
Data Sheet
HMC8100LP6JE
Lower sideband selected, maximum gain.
15
14
13
12
11
10
9
8
7
6
5
4
5
6
7
0.8
1.2
1.6
2.0
2.4
2.8
3.2
3.6
4.0
RF FREQUENCY (GHz)
Figure 39. Output P1dB vs. RF Frequency over IF Gain Limit, 56 MHz Filter
Rev. A | Page 15 of 27
HMC8100LP6JE
Data Sheet
INTERNAL AGC CONFIGURATION
POUT = −9 dBm per tone, lower sideband, and 56 MHz filter selected.
80
80
70
60
50
40
30
20
10
0
70
60
50
40
30
20
+85°C
+25°C
–40°C
+85°C
+25°C
–40°C
10
0
–70 –65 –60 –55 –50 –45 –40 –35 –30 –25 –20 –15 –10 –5
0
–70 –65 –60 –55 –50 –45 –40 –35 –30 –25 –20 –15 –10 –5
0
INPUT POWER (dBm)
INPUT POWER (dBm)
Figure 40. IM3 vs. Input Power over Temperature, RF = 1 GHz
Figure 43. IM3 vs. Input Power over Temperature, RF = 2 GHz
80
70
60
50
40
30
70
+85°C
+25°C
–40°C
60
50
40
30
20
10
0
20
+85°C
+25°C
–40°C
10
0
–70 –65 –60 –55 –50 –45 –40 –35 –30 –25 –20 –15 –10 –5
INPUT POWER (dBm)
0
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
INPUT POWER (dBm)
Figure 41. IM3 vs. Input Power over Temperature, RF = 4 GHz
Figure 44. Noise Figure vs. Input Power over Temperature, RF = 1 GHz
70
70
+85°C
+25°C
–40°C
+85°C
+25°C
–40°C
60
50
40
30
20
10
0
60
50
40
30
20
10
0
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
INPUT POWER (dBm)
INPUT POWER (dBm)
Figure 42. Noise Figure vs. Input Power over Temperature, RF = 2 GHz
Figure 45. Noise Figure vs. Input Power over Temperature, RF = 4 GHz
Rev. A | Page 16 of 27
Data Sheet
HMC8100LP6JE
POUT = −9 dBm per tone, lower sideband, and 56 MHz filter selected.
–4
–4
–6
+85°C
+25°C
–40°C
+85°C
+25°C
–40°C
–6
–8
–8
–10
–12
–14
–16
–18
–10
–12
–14
–16
–18
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
INPUT POWER (dBm)
INPUT POWER (dBm)
Figure 46. Output Power vs. Input Power over Temperature, RF = 1 GHz
Figure 48. Output Power vs. Input Power over Temperature, RF = 2 GHz
–4
+85°C
+25°C
–40°C
–6
–8
–10
–12
–14
–16
–18
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
INPUT POWER (dBm)
Figure 47. Output Power vs. Input Power over Temperature, RF = 4 GHz
Rev. A | Page 17 of 27
HMC8100LP6JE
Data Sheet
THEORY OF OPERATION
The HMC8100LP6JE is a highly integrated intermediate
frequency (IF) receiver chip that converts radio frequency (RF)
to a single-ended IF signal at its output. The internal active gain
circuit (AGC) of the HMC8100LP6JE is able to actively level the
output power at the IF output via SPI control. The gain control of
the HMC8100LP6JE can be controlled externally as an alternative
option via the VC_VGA_RF and VC_VGA_IF pins with
voltages ranging from 3.3 V (minimum attenuation) to 0 V
(maximum attenuation).
REGISTER ARRAY ASSIGNMENTS AND SERIAL
INTERFACE
The register arrays for the HMC8100LP6JE are organized into
nine registers of 16 bits. Using the serial interface, the arrays are
written or read one row at a time, as shown in Figure 50 and
Figure 51. Figure 50 shows the sequence of signals on the enable
(SEN), CLK, and data (SDI) lines to write one 16-bit array of data
to a single register. The enable line goes low, the first of 24 data
bits is placed on the data line, and the data is sampled on the
rising edge of the clock. The data line should remain stable for
at least 2 ns after the rising edge of CLK. The device supports a
serial interface running up to 10 MHz, the interface is 3.3 V
CMOS logic.
The HMC8100LP6JE utilizes an input low noise amplifier
(LNA) cascaded with a variable gain amplifier (VGA), which
can either be controlled by the internal AGC or external
voltages, that feeds the RF signals to an image reject mixer. The
local oscillator port can either be driven single ended through
LON or differentially through the combination of LON and
LOP.
A write operation requires 24 data bits and 24 clock pulses, as
shown in Figure 50. The 24 data bits contain the 3-bit chip
address, followed by the 5-bit register array number, and finally
the 16-bit register data. After the 24th clock pulses of the write
operation, the enable line returns high to load the register array
on the IC.
The radio frequency is then converted to intermediate
frequencies, which can either feed off chip via baseband
differential outputs or feed on chip into a programmable band-
pass filter. It is recommended during IF mode operation that
the baseband outputs be unconnected. The programmable
band-pass filter on chip has four programmable bandwidths
(14 MHz, 28 MHz, 56MHz, and 112 MHz). The programmable
band-pass filter has the capability to adjust the center frequency.
A read operation requires 24 data bits and 48 clock pulses, as
shown in Figure 51. For every register read operation, a write
to Register 7 is required first. The data written should contain
the 3-bit chip address, followed by the 5-bit register number
for Register 7, and finally the 5-bit number of the register to
be read. The remaining 11 bits should be logic zeroes. When
the read operation is initiated, the data is available on the
data output (SDO) pin.
From the factory, a filter calibration is conducted and the center
frequency of the filter is set to 140 MHz. This calibration can be
recalled via SPI control or the customer can adjust the center
frequency, but the calibration value must be stored off chip (see
the Register Array Assignments section). An external filter
option can be utilized to allow the customer to select other filter
bandwidths/responses that are not available on chip. The
external filter path coming from the image reject mixer feeds
into an amplifier that has differential outputs. The output of the
external filter can be fed back into the chip, which is then
connected to another amplifier.
Read Example
If reading Register 2, the following 24 bits should be written to
initiate the read operation.
00000000000 00010 00111 110
ZERO BITS (11 BITS)
REGISTER 7 ADDRESS (5 BITS)
REGISTER TO BE READ (5 BITS)
CHIP ADDRESS (3 BITS)
Figure 49. Sample Bits to Initiate Read
A VGA follows immediately after the band-pass filter. Control
the IF VGA either by the AGC or external voltages. The output
of the variable gain amplifier is the output of the device.
Rev. A | Page 18 of 27
Data Sheet
HMC8100LP6JE
24 CLOCK CYCLES
SEN
CLK
1
24
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SDI
REGISTER
ADDRESS
CHIP
ADDRESS
WRITE DATA
Figure 50. Timing Diagram, SPI Register Write
24 CLOCK CYCLES
24 CLOCK CYCLES
SEN
CLK
1
24
1
24
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23
SDI
0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SDO
CHIP
ADDRESS
READ
REGISTER
REG 7
ALL ZEROS
ADDRESS ADDRESS
READ DATA
Figure 51. Timing Diagram, SPI Register Read
Rev. A | Page 19 of 27
HMC8100LP6JE
Data Sheet
REGISTER DESCRIPTIONS
REGISTER ARRAY ASSIGNMENTS
In the Access columns (Table 6 through Table 14), R means read, W means write, and R/W means read/write.
Enable Bits
Table 6. Enable Register, (Address 0x01)
Bit No.
Bit Name
Description
Reset
Access
15
PD2_EN
Power Detector 2 enable
0 = disable
0x1
R/W
1 = enable
14
13
Factory diagnostics
PD3_AMP1_EN
Logic 0 for normal operation
Auxiliary output (Pin 13) enable
0 = disable
0x0
0x1
R/W
R/W
1 = enable
12
11
Reserved
AMP1_EN
Logic 1 for normal operation
LNA enable
0x1
0x1
R/W
R/W
0 = disable
1 = enable
10
9
RF_VGA_EN
IRM_EN
RF VGA enable
0 = disable
1 = enable
0x1
0x1
0x1
0x1
R/W
R/W
R/W
R/W
R/W
Image reject mixer enable
0 = disable
1 = enable
8
FIL2_EN
Filter 2 enable
0 = disable
1 = enable
7
IF_VGA_EN
Filter 2 enable
0 = disable
1 = enable
6
5
Factory diagnostics
PD1_EN
Logic 0 for normal operation
Power Detector 1 enable
0 = disable
0x0
0x1
1 = enable
4
3
2
1
0
PD3_EN
Power Detector 3 enable
0 = disable
1 = enable
0x1
0x1
0x1
0x1
0x0
R/W
R/W
R/W
R/W
R/W
AGC_EN
Available gain control (AGC) enable
0 = enable
1 = disable
AMP3_PDWN
AMP2_PDWN
IQ_BUF_EN
Amplifier 3 power-down
0 = enable
1 = disable
Amplifier 2 power-down
0 = enable
1 = disable
IQ buffer enable
0 = disable
1 = enable
Rev. A | Page 20 of 27
Data Sheet
HMC8100LP6JE
Image Reject and Band-Pass Filter Bits
Table 7. Image Reject and Band-Pass Filter Register, (Address 0x02)
Bit No.
Bit Name
Description
Reset
Access
15
IRM_IS
Image sideband select
0 = lower sideband
0x1
R/W
1 = upper sideband
[14:13]
FIL2_SEL
Internal band-pass filter select
00 = 14 MHz
01 = 28 MHz
10 = 56 MHz
11 = 112 MHz
0x2
R/W
R/W
12
SEL_EXT_FIL
Select external filter
0x0
0 = internal
1 = external
11
10
Reserved
Not used
0x0
0x1
R/W
R/W
FIL2_CAL_OVR
Override on-chip calibration and use 8-bit word from SPI
0 = use on-chip calibration word
1 = use FIL2_FREQ_SET word from SPI
Enable filter center frequency calibration
0 = disable
9
FIL2_CAL_EN
0x0
R/W
1 = enable (transition from 0 to 1)
Not used
8
Reserved
0x1
R/W
R/W
[7:0]
FIL2_FREQ_SET
Internal band-pass filter center frequency setting
0x85
Band-Pass Filter Bits: OTP and SPI
Table 8. Band-Pass Filter Register, (Address 0x03)
Bit No.
[15:12]
11
Bit Name
Reserved
Description
Reset
0x8
Access
R/W
Logic 1000 for normal operation
Override SPI FIL2_FRQ_SET and use 8-bit word from OTP
0 = select OTP setting
FIL_OPT_MUX_SEL
0x0
R/W
1 = select SPI setting
[10:0]
Reserved
Logic 110 1001 1111 for normal operation
0x69F
R/W
AGC
Table 9. AGC Register, (Address 0x04)
Bit No.
Bit Name
Description
Reset
Access
[15:12]
AGC_SELECT
Active gain control (AGC) select
0x3 = internal AGC mode
0xC = external AGC mode
Active gain control external capacitor select
0 = no external capacitor
1 = external capacitor
0x3
R/W
11
AGC_EXT_CAP_SEL
0x0
R/W
Rev. A | Page 21 of 27
HMC8100LP6JE
Data Sheet
Bit No.
Bit Name
Description
Reset
Access
[10:8]
AGC_BW
AGC bandwidth
000 = 17 Hz
0x4
R/W
001 = 22 Hz
010 = 33 Hz
011 = 67 Hz
100 = 83 Hz
101 = 111 Hz (recommended setting)
110 = 167 Hz
111 = 333 Hz
[7:6]
[5:0]
VGA3_GAIN
POUT_CTRL
VGA 3 attentuation
00 = 0 dB (recommended setting)
01 = 5 dB
10 = 10 dB
11 = 15 dB
0x0
R/W
R/W
Power output control
0x0 = −54 dBm
0x1 = −53 dBm
0x2 = …
0x30
0x3E = +8 dBm
0x3F = +9 dBm
Active Gain Control: IF Gain Limit Bits
Table 10. AGC Register, (Address 0x05)
Bit No.
[15:12]
[11:9]
Bit Name
Reserved
Description
Not used
Reset
0xA
Access
R/W
IF_GAIN_LIMIT
IF gain limit
0x4
R/W
000 = 0 dB
001 = 6 dB
010 = 12 dB
011 = 18 dB
100 = 24 dB
101 = 30 dB
110 = 36 dB
111 = 42 dB
[8:0]
Reserved
Logic 1 0000 0100 for normal operation
0x104
R/W
Band-Pass Filter Bits: Calibration and 8-Bit Word Frequency
Table 11. Band-Pass Filter Register, (Address 0x06)
Bit No.
[15:10]
9
Bit Name
Reserved
Description
Not used
Reset
0x0
Access
R
R
R
R
FIL2_CAL_OVFL
FIL2_VCAL_END
FL2_FC_CAL
FIL2 calibration overflow signal
FIL2 calibration end signal
FIL2 8-bit word frequency setting, read only
0x1
8
0x1
[7:0]
0x85
Rev. A | Page 22 of 27
Data Sheet
HMC8100LP6JE
AGC: Blocker Power Detector Bits
Table 12. AGC Register, (Address 0x12)
Bit No.
[15:8]
Bit Name
Reserved
Description
Not used
Reset
0xF0
0x0
Access
R/W
7
6
Reserved
Not used
R/W
AGC_BLOCKER_MODE_EN
AGC blocker mode enable
0x01
R/W
0 = off
1 = on
[5:3]
AGC_BLOCKER_PD2_REF
AGC blocker power detector reference level
0x3
R/W
000 = −4 dBm
001 = −2 dBm
010 = 0 dBm
011 = 2 dBm
100 = 4 dBm
101 = 6 dBm
110 = 8 dBm
111 = 10 dBm
[2:0]
AGC_BLOCKER_PD2_LOOP_BW
AGC blocker power detector loop bandwidth control
000 = 17 Hz
0x4
R/W
001 = 22 Hz
010 = 33 Hz
011 = 67 Hz
100 = 83 Hz
101 = 111 Hz
110 = 167 Hz
111 = 333 Hz
Phase I Bits
Table 13. Phase I Register, (Address 0x14)
Bit No.
[15:12]
[11:9]
[8:0]
Bit Name
Reserved
Description
Not used
Reset
0xF
Access
R/W
Reserved
Not used
0x0
R/W
I_PHASE_ADJ
I phase adjust
0x0
R/W
Phase Q Bits
Table 14. Phase Q Register, (Address 0x15)
Bit No.
[15:12]
[11:9]
[8:0]
Bit Name
Reserved
Description
Not used
Reset
0xF
Access
R/W
Reserved
Not used
0x0
R/W
Q_PHASE_ADJ
Q phase adjust
0x0
R/W
Rev. A | Page 23 of 27
HMC8100LP6JE
Data Sheet
APPLICATIONS INFORMATION
During operation at P1dB, the IF gain limit of the
HMC8100LP6JE, as described in the Register Array
Assignments and Serial Interface section, needs to be limited by
the radio frequency (RF), as listed in Table 15. There is a
recommended IF gain limit setting and maximum allowed IF
gain limit setting that is to be used.
SCHEMATIC/TYPICAL APPLICATION CIRCUIT
Table 15. Recommended IF Gain Limit Settings by RF
Frequency
RF Frequency
(GHz)
Maximum
Setting
Recommended
Setting
0.8 to 1.8
1.8 to 2.8
2.8 to 4.0
5
6
7
4
5
6
Rev. A | Page 24 of 27
Data Sheet
HMC8100LP6JE
EVALUATION PRINTED CIRCUIT BOARD (PCB)
3 1
3 2
3 3
3 4
3 5
3 6
3 7
3 8
3 9
4 0
2 0
1 9
1 8
1 7
1 6
1 5
1 4
1 3
1 2
1 1
Figure 52. PCB Schematic/Typical Applications Circuit
Rev. A | Page 25 of 27
HMC8100LP6JE
Data Sheet
Figure 53. Evaluation PCB
Rev. A | Page 26 of 27
Data Sheet
HMC8100LP6JE
OUTLINE DIMENSIONS
DETAIL A
(JEDEC 95)
0.30
0.25
0.20
6.10
6.00 SQ
5.90
0.004
BSC
PIN 1
PIN 1
INDICATOR
0.011
SQ
NS
INDIC ATOR AREA OPTIO
(SEE DETAIL A)
31
40
30
1
0.50
BSC
4.60
4.50 SQ
4.40
EXPOSED
PAD
21
10
20
11
0.45
0.40
0.35
TOP VIEW
SIDE VIEW
BOTTOM VIEW
0.20 MIN
0.95
0.90
0.85
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.05 MAX
0.02 NOM
COPLANARITY
0.08
SECTION OF THIS DATA SHEET.
SEATING
PLANE
0.203 REF
COMPLIANT TO JEDEC STANDARDS MO-220-VJJD-5.
Figure 54. 40-Lead Lead Frame Chip Scale Package [LFCSP]
6 mm × 6 mm Body and 0.90 mm Package Height
(CP-40-22)
Dimensions shown in millimeters
ORDERING GUIDE
Temperature
Range
MSL
Package
Option
Package
Marking4
Model1, 2
Rating3
Package Description
40-Lead Lead Frame Chip Scale Package
H8100
XXXX
HMC8100LP6JE
−40°C to +85°C
MSL3
CP-40-22
EK1HMC8100LP6J
[LFCSP] Evaluation Kit
1 HMC8100LP6JE is a RoHS compliant part.
2 The HMC8100LP6JE lead finish is NiPdAu.
3 See the Absolute Maximum Ratings section.
4 XXXX is the 4-digit lot number.
©2016 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D13867-0-5/16(A)
Rev. A | Page 27 of 27
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