HMC8402-SX [ADI]
Low Noise Amplifier;
| 型号： | HMC8402-SX |
| 厂家： | 
ADI |
| 描述： | Low Noise Amplifier 射频 微波 |
| 文件： | 总15页 (文件大小：361K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
2 GHz to 30 GHz, GaAs, pHEMT, MMIC,
Low Noise Amplifier
Data Sheet
HMC8402
FEATURES
GENERAL DESCRIPTION
Output power for 1 dB compression (P1dB): 21.5 dBm typical
Saturated output power (PSAT): 22 dBm typical
Gain: 13.5 dB typical
Noise figure: 2 dB
Output third order intercept (IP3): 26 dBm typical
Supply voltage: 7 V at 68 mA
The HMC8402 is a gallium arsenide (GaAs), pseudomorphic
high electron mobility transistor (pHEMT), monolithic microwave
integrated circuit (MMIC), low noise amplifier which operates
between 2 GHz and 30 GHz. The amplifier provides 13.5 dB of
gain, 2 dB noise figure, 26 dBm output IP3, and 21.5 dBm of
output power at 1 dB gain compression while requiring 68 mA
from a 7 V supply. The HMC8402 is self biased with only a single
positive supply needed to achieve a drain current IDQ of 68 mA.
50 Ω matched input/output
Die size: 2.7 mm × 1.35 mm × 0.05 mm
The HMC8402 amplifier input/outputs are internally matched to
50 Ω facilitating integration into multichip modules (MCMs). All
data is taken with the chip connected via two 0.025 mm (1 mil)
wire bonds of minimal length 0.31 mm (12 mils).
APPLICATIONS
Test instrumentation
Microwave radios and very small aperture terminals (VSATs)
Military and space
Telecommunications infrastructure
Fiber optics
FUNCTIONAL BLOCK DIAGRAM
3
HMC8402
4
RFOUT
V
2
GG
2
1
RFIN
Figure 1.
Rev. C
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HMC8402
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Interface Schematics .....................................................................6
Typical Performance Characteristics ..............................................7
Theory of Operation ...................................................................... 12
Applications Information.............................................................. 13
Biasing Procedures..................................................................... 13
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
2 GHz to 18 GHz Frequency Range........................................... 3
18 GHz to 26 GHz Frequency Range......................................... 3
26 GHz to 30 GHz Frequency Range......................................... 4
Absolute Maximum Ratings............................................................ 5
ESD Caution.................................................................................. 5
Pin Configuration and Function Descriptions............................. 6
Mounting and Bonding Techniques for Millimeterwave GaAs
MMICs......................................................................................... 13
Typical Application Circuit....................................................... 14
Assembly Diagram ..................................................................... 14
Outline Dimensions....................................................................... 15
Ordering Guide .......................................................................... 15
REVISION HISTORY
4/2018—Rev. B to Rev. A
Updated Outline Dimensions ....................................................... 15
Changes to Ordering Guide .......................................................... 15
10/2017—Rev. A to Rev. B
Changes to Figure 1.......................................................................... 1
Changes to Table 5, Figure 3, and Figure 6 ................................... 6
Added Figure 34; Renumbered Sequentially .............................. 11
10/2016—Rev. 0 to Rev. A
Change to Table 4 ............................................................................. 5
Changes to Figure 8.......................................................................... 7
Updated Outline Dimensions ....................................................... 15
7/2016—Revision 0: Initial Version
Rev. C | Page 2 of 15
Data Sheet
HMC8402
SPECIFICATIONS
2 GHz TO 18 GHz FREQUENCY RANGE
TA = 25°C, VDD = 7 V, IDQ = 74 mA.
Table 1.
Parameter
Symbol
Test Conditions/Comments
Min
Typ
Max
Unit
GHz
dB
FREQUENCY RANGE
GAIN
Gain Variation Over Temperature
RETURN LOSS
2
18
11.5 13.5
0.005
dB/°C
Input
Output
10
12
dB
dB
OUTPUT
Output Power for 1 dB Compression
Saturated Output Power
Output Third Order Intercept
NOISE FIGURE
P1dB
PSAT
IP3
19
45
21
22
26
2.5
dBm
dBm
dBm
dB
Measurement taken at POUT/tone = 0 dBm
Nominal voltage (VDD) = 7 V
NF
5
SUPPLY CURRENT
Total Supply Current
Total Supply Current vs. VDD
VDD = 5 V
IDQ
IDQ
68
85
mA
62
65
68
72
7
mA
mA
mA
mA
V
VDD = 6 V
VDD = 7 V
VDD = 8 V
SUPPLY VOLTAGE
VDD
5
8
18 GHz TO 26 GHz FREQUENCY RANGE
TA = 25°C, VDD = 7 V, IDQ = 74 mA.
Table 2.
Parameter
Symbol
Test Conditions/Comments
Min
Typ
Max
Unit
GHz
dB
FREQUENCY RANGE
GAIN
Gain Variation Over Temperature
RETURN LOSS
18
26
11.5 13.5
0.006
dB/°C
Input
Output
17
14
dB
dB
OUTPUT
Output Power for 1 dB Compression
Saturated Output Power
Output Third Order Intercept
NOISE FIGURE
P1dB
PSAT
IP3
17
45
20
21
24
2.5
dBm
dBm
dBm
dB
Measurement taken at POUT/tone = 0 dBm
Nominal voltage (VDD) = 7 V
NF
4
SUPPLY CURRENT
Total Supply Current
Total Supply Current vs. VDD
VDD = 5 V
IDQ
IDQ
68
85
mA
62
65
68
72
7
mA
mA
mA
mA
V
VDD = 6 V
VDD = 7 V
VDD = 8 V
SUPPLY VOLTAGE
VDD
5
8
Rev. C | Page 3 of 15
HMC8402
Data Sheet
26 GHz TO 30 GHz FREQUENCY RANGE
TA = 25°C, VDD = 7 V, IDQ = 74 mA.
Table 3.
Parameter
Symbol
Test Conditions/Comments
Min
26
Typ
Max
Unit
GHz
dB
FREQUENCY RANGE
GAIN
30
11
13
Gain Variation Over Temperature
RETURN LOSS
0.009
dB/°C
Input
Output
10
10
dB
dB
OUTPUT
Output Power for 1 dB Compression
Saturated Output Power
Output Third Order Intercept
NOISE FIGURE
P1dB
PSAT
IP3
15
45
19
20.5
23
dBm
dBm
dBm
dB
Measurement taken at POUT/tone = 0 dBm
Nominal voltage (VDD) = 7 V
NF
3.0
4.5
85
SUPPLY CURRENT
Total Supply Current
Total Supply Current vs. VDD
VDD = 5 V
IDQ
IDQ
68
mA
62
65
68
72
7
mA
mA
mA
mA
V
VDD = 6 V
VDD = 7 V
VDD = 8 V
SUPPLY VOLTAGE
VDD
5
8
Rev. C | Page 4 of 15
Data Sheet
HMC8402
ABSOLUTE MAXIMUM RATINGS
Stresses at or above those listed under Absolute Maximum
Table 4.
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Parameter
Rating
Drain Bias Voltage (VDD
)
10 V
Gate Bias Voltage (VGG2)
RF Input Power (RFIN)
Channel Temperature
Continuous Power Dissipation (PDISS),
TA = 85°C (Derate 17.2 mW/°C Above 85°C)
−2.6 V to +3.6 V
20 dBm
175°C
1.55 W
Thermal Resistance, θJC (Channel to
Bottom Die)
58°C/W
ESD CAUTION
Storage Temperature Range
Operating Temperature Range
ESD Sensitivity, Human Body Model (HBM)
−65°C to +150°C
−55°C to +85°C
Class 1A (250 V)
Rev. C | Page 5 of 15
HMC8402
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
HMC8402
3
4
2
1
ADI2014
Figure 2. Pad Configuration
Table 5. Pad Function Descriptions
Pad No.
Mnemonic
Description
1
RFIN
Radio Frequency (RF) Input. This pad is ac-coupled and matched to 50 Ω, and has a large value resistor to
GND for ESD protection. See Figure 3 for the interface schematic.
2
3
4
VGG
2
Gain Control. This pad is dc-coupled and is used to accomplish gain control by bringing this voltage
lower and becoming more negative. See Figure 4 for the interface schematic.
Power Supply Voltage for the Amplifier. Connect a dc bias to provide drain current (IDQ). See Figure 5 for
the interface schematic.
RF Output. This pad is ac-coupled and matched to 50 Ω, and has a large value resistor to GND for ESD
protection. See Figure 6 for the interface schematic.
VDD
RFOUT
Die Bottom GND
Die bottom must be connected to RF/dc ground. See Figure 7 for the interface schematic.
INTERFACE SCHEMATICS
V
DD
RFIN
Figure 5. VDD Interface Schematic
Figure 3. RFIN Interface Schematic
RFOUT
V
2
GG
Figure 6. RFOUT Interface Schematic
GND
Figure 4. VGG2 Interface Schematic
Figure 7. GND Interface Schematic
Rev. C | Page 6 of 15
Data Sheet
HMC8402
TYPICAL PERFORMANCE CHARACTERISTICS
20
16
15
14
13
12
11
10
9
+85°C
+25°C
–55°C
15
10
INPUT RETURN LOSS
5
0
GAIN
OUTPUT RETURN LOSS
–5
–10
–15
–20
–25
–30
8
7
6
2
6
10
14
18
22
26
30
0
4
8
12
16
20
24
28
32
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 8. Response Gain and Return Loss vs. Frequency
Figure 11. Gain vs. Frequency at Various Temperatures
0
–2
0
–2
+85°C
+25°C
–55°C
+85°C
+25°C
–55°C
–4
–4
–6
–6
–8
–8
–10
–12
–14
–16
–18
–20
–10
–12
–14
–16
–18
–20
2
6
10
14
18
22
26
30
2
6
10
14
18
22
26
30
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 12. Output Return Loss vs. Frequency at Various Temperatures
Figure 9. Input Return Loss vs. Frequency at Various Temperatures
6
6
+85°C
+25°C
–55°C
5
5V
6V
7V
5
8V
4
3
2
1
0
4
3
2
1
0
0
5
10
15
20
25
30
0
5
10
15
20
25
30
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 10. Noise Figure vs. Frequency at Various Temperatures
Figure 13. Noise Figure vs. Frequency at Various Supply Voltages
Rev. C | Page 7 of 15
HMC8402
Data Sheet
26
24
22
20
18
16
14
26
24
22
20
18
16
14
12
+85°C
+25°C
–55°C
+85°C
+25°C
–55°C
12
2
6
10
14
18
22
26
30
30
30
2
6
10
14
18
22
26
30
30
8
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 14. P1dB vs. Frequency at Various Temperatures
Figure 17. PSAT vs. Frequency at Various Temperatures
26
24
22
20
18
16
14
12
26
24
22
20
18
16
14
12
5V
5V
6V
7V
8V
6V
7V
8V
2
6
10
14
18
22
26
2
6
10
14
18
22
26
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 15. P1dB vs. Frequency at Various Supply Voltages
Figure 18. PSAT vs. Frequency at Various Supply Voltages
60
55
50
45
40
35
30
25
20
32
+85°C
+25°C
–55°C
30
28
26
24
22
20
18
16
14
4GHz
6GHz
10GHz
16GHz
20GHz
24GHz
26GHz
0
1
2
3
4
5
6
7
2
6
10
14
18
22
26
P
/TONE (dBm)
FREQUENCY (GHz)
OUT
Figure 16. Output IP3 vs. Frequency for Various Temperatures at
POUT = 0 dBm/Tone
Figure 19. Output Third Order Intermodulation (IM3) vs. POUT/Tone for
Various Frequencies at VDD = 6 V
Rev. C | Page 8 of 15
Data Sheet
HMC8402
60
55
50
45
40
35
30
25
20
60
55
50
45
40
35
4GHz
4GHz
6GHz
6GHz
30
25
20
10GHz
16GHz
20GHz
24GHz
26GHz
10GHz
16GHz
20GHz
24GHz
26GHz
0
1
2
3
4
5
6
7
8
0
1
2
3
4
5
6
7
8
P
/TONE (dBm)
P
/TONE (dBm)
OUT
OUT
Figure 23. Output (IM3) vs. POUT/Tone for Various Frequencies at VDD = 8 V
Figure 20. Output (IM3) vs. POUT/Tone for Various Frequencies at VDD = 7 V
25
20
15
10
5
160
140
120
100
80
0
+85°C
+25°C
–55°C
–10
–20
–30
–40
–50
–60
–70
–80
P
OUT
GAIN
PAE
I
DD
0
–10
60
–8
–6
–4
–2
0
2
4
6
8
10
12
2
6
10
14
18
22
26
30
INPUT POWER (dBm)
FREQUENCY (GHz)
Figure 24. Power Compression at 16 GHz
Figure 21. Reverse Isolation vs. Frequency at Various Temperatures
16
1.2
1.1
1.0
0.9
0.8
5V
6V
7V
8V
15
14
13
12
11
10
9
0.7
4GHz
6GHz
0.6
0.5
10GHz
16GHz
8
20GHz
7
24GHz
26GHz
6
0.4
–10
0
5
10
15
20
25
30
–8
–6
–4
–2
0
2
4
6
8
10
12
FREQUENCY (GHz)
INPUT POWER (dBm)
Figure 25. Gain vs. Frequency at Various Supply Voltages
Figure 22. Power Dissipation vs. Input Power at Various Frequencies, TA = 85°C
Rev. C | Page 9 of 15
HMC8402
Data Sheet
0
0
–2
5V
6V
7V
8V
–2.6V
–2.4V
–2.2V
–2.0V
–1.8V
–1.6V
–1.4V
–0.8V
0V
–2
+1.0V
+1.4V
+2.6V
–4
–4
–6
–6
–8
–8
–10
–12
–14
–16
–18
–20
–10
–12
–14
–16
–18
–20
0
5
10
15
20
25
30
0
5
10
15
20
25
30
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 26. Input Return Loss vs. Frequency at Various Supply Voltages
Figure 29. Input Return Loss vs. Frequency at Various VGG2 Voltages
0
0
5V
–2.6V
–2.4V
–2.2V
–2.0V
–1.8V
–1.6V
–1.4V
–0.8V
0V
–2
–4
6V
7V
8V
–2
–4
+1.0V
+1.4V
+2.6V
–6
–6
–8
–8
–10
–12
–14
–16
–18
–20
–10
–12
–14
–16
–18
–20
0
5
10
15
20
25
30
0
5
10
15
20
25
30
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 30. Output Return Loss vs. Frequency at Various VGG2 Voltages
Figure 27. Output Return Loss vs. Frequency at Various Supply Voltages
15
10
5
20
15
10
5
0
0
–5
–10
–15
–5
–10
–20
–25
–30
–2.6V
–2.4V
–2.2V
–2.0V
–1.8V
–1.6V
–1.4V
–0.8V
0V
+1.0V
+1.4V
+2.6V
–15
2.6 2.2 1.8 1.4 1.0 0.6 0.2 –0.2 –0.6 –1.0 –1.4 –1.8 –2.2 –2.6
0
5
10
15
20
25
30
V
2 (V)
FREQUENCY (GHz)
GG
Figure 31. Gain vs. VGG
2
Figure 28. Gain vs. Frequency at Various VGG2 Voltages
Rev. C | Page 10 of 15
Data Sheet
HMC8402
30
25
20
15
10
5
30
25
20
15
10
5
–1.8V
–1.4V
–1.0V
–0.6V
–0.4V
–0.2V
0V
+0.8V
+1.4V
+2.0V
+2.6V
+0.4V
–2.4V
–2.0V
–1.8V
–1.6V
–1.4V
–1.2V
–1.0V
–0.6V
0V
+1.0V
+2.0V
+2.6V
0
0
2
6
10
14
18
22
26
30
2
6
10
14
18
22
26
30
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 35. P1dB vs. Frequency at Various VGG2 Voltages
Figure 32. Output IP3 vs. Frequency at Various VGG2 Voltages
30
25
20
15
10
5
26
24
22
20
18
16
14
12
10
–1.8V
–1.4V
–1.0V
–0.6V
–0.4V
–0.2V
0V
+0.8V
+1.4V
+2.0V
+2.6V
+0.4V
0
2.6 2.2 1.8 1.4 1.0 0.6 0.2 –0.2 –0.6 –1.0 –1.4 –1.8 –2.2 –2.6
2
6
10
14
18
22
26
30
V
2 (V)
FREQUENCY (GHz)
GG
Figure 36. PSAT vs Frequency at Various VGG2 Voltages
Figure 33. Output IP3 vs. VGG2 at 16 GHz
36
34
32
30
28
26
24
22
20
18
16
14
12
10
0 dBm/TONE
2 dBm/TONE
4 dBm/TONE
6 dBm/TONE
8 dBm/TONE
2
4
6
8
10
12
14
16
18
20
22
24
FREQUENCY (GHz)
Figure 34. OIP2 vs. Frequency for Various POUT/Tone Levels
Rev. C | Page 11 of 15
HMC8402
Data Sheet
THEORY OF OPERATION
The HMC8402 is a GaAs, pHEMT, MMIC low noise amplifier.
Its basic architecture is that of a single supply biased cascode
distributed amplifier with an integrated RF choke for the drain.
The cascode distributed architecture uses a fundamental cell
consisting of a stack of two field effect transistors (FETs) with the
source of the upper FET connected to the drain of the lower FET.
The fundamental cell is then duplicated several times, with an
RFIN transmission line interconnecting the gates of the lower
FETs and an RFOUT transmission line interconnecting the
drains of the upper FETs.
Though the gate bias voltages of the upper FETs are set internally
by a resistive voltage divider tapped off of VDD, the VGG2 pad is
provided to allow the user an optional means of changing the
gate bias of the upper FETs. Adjustment of the VGG2 voltage
across the range of −2 V to +2.6 V changes the gate bias of the
upper FETs, thus affecting gain changes of approximately 6 dB,
depending on frequency. Increasing the voltage applied to VGG2
increases the gain, whereas decreasing the voltage decreases the
gain. For the nominal VDD = 7.0 V, the resulting VGG2 open-
circuit voltage is approximately 3.18 V.
Additional circuit design techniques are used around each cell
to optimize the overall bandwidth and noise figure. The major
benefit of this architecture is that a low noise figure is maintained
across a bandwidth far greater than what a single instance of the
fundamental cell provides. A simplified schematic of this
architecture is shown in Figure 37.
V
DD
T-LINE
RFOUT
V
2
GG
T-LINE
RFIN
ACG ACG
Figure 37. Architecture and Simplified Schematic
Rev. C | Page 12 of 15
Data Sheet
HMC8402
APPLICATIONS INFORMATION
To minimize bond wire length, place microstrip substrates as
close to the die as possible. Typical die to substrate spacing is
0.076 mm to 0.152 mm (3 mil to 6 mil).
BIASING PROCEDURES
Capacitive bypassing is required for VDD, as shown in the typical
application circuit in Figure 39. Gain control is possible through
Handling Precautions
the application of a dc voltage to VGG2. If gain control is used, VGG
2
must be bypassed by 100 pF, 0.01 µF, and 4.7 µF capacitors. If gain
control is not used, VGG2 can be either left open or capacitively
bypassed as described.
To avoid permanent damage, adhere to the following precautions:
•
All bare die ship in either waffle or gel-based ESD protective
containers, sealed in an ESD protective bag. After the sealed
ESD protective bag is opened, store all die in a dry nitrogen
environment.
The recommended bias sequence during power-up is as follows:
1. Set VDD to 7 V (this results in an IDQ near its specified
typical value).
2. If the gain control function is to be used, apply to VGG2 a
voltage within the range of −2 V to +2.6 V until the desired
gain is achieved.
•
Handle the chips in a clean environment. Never use liquid
cleaning systems to clean the chip.
•
•
Follow ESD precautions to protect against ESD strikes.
While bias is applied, suppress instrument and bias supply
transients. To minimize inductive pickup, use shielded
signal and bias cables.
3. Apply the RF input signal.
The recommended bias sequence during power-down is as follows:
•
Handle the chip along the edges with a vacuum collet or
with a sharp pair of bent tweezers. The surface of the chip
may have fragile air bridges and must not be touched with
vacuum collet, tweezers, or fingers.
1. Turn off the RF input signal.
2. Remove the VGG2 voltage or set it to 0 V.
3. Set VDD to 0 V.
Unless otherwise noted, all measurements and data shown were
taken using the typical application circuit (see Figure 39), configured
as shown on the assembly diagram (see Figure 40) and biased
per the conditions in the Specifications section. The bias conditions
shown in the Specifications section are the operating points
recommended to optimize the overall performance. Operation
using other bias conditions may provide performance that differs
from what is shown in this data sheet. To obtain the best
performance while not damaging the device, follow the
recommended biasing sequence outlined in this section.
Mounting
The chip is back metallized and can be die mounted with gold/tin
(AuSn) eutectic preforms or with electrically conductive epoxy.
The mounting surface must be clean and flat.
Eutectic Die Attach
It is best to use an 80% gold/20% tin preform with a work surface
temperature of 255°C and a tool temperature of 265°C. When
hot 90% nitrogen/10% hydrogen gas is applied, maintain tool tip
temperature at 290°C. Do not expose the chip to a temperature
greater than 320°C for more than 20 sec. No more than 3 sec of
scrubbing is required for attachment.
MOUNTING AND BONDING TECHNIQUES FOR
MILLIMETERWAVE GaAs MMICs
Attach the die directly to the ground plane eutectically or with
conductive epoxy. To bring RF to and from the chip, use 50 Ω
microstrip transmission lines on 0.127 mm (5 mil) thick alumina
thin film substrates (see Figure 38).
Epoxy Die Attach
ABLETHERM 2600BT is recommended for die attachment.
Apply a minimum amount of epoxy to the mounting surface so
that a thin epoxy fillet is observed around the perimeter of the
chip after placing it into position. Cure the epoxy per the schedule
provided by the manufacturer.
0.051mm (0.002") THICK GaAs MMIC
WIRE BOND
0.076mm
(0.003")
Wire Bonding
RF bonds made with 0.003 in. × 0.0005 in. gold ribbon are recom-
mended for the RF ports. These bonds must be thermosonically
bonded with a force of 40 g to 60 g. DC bonds of 1 mil (0.025 mm)
diameter, thermosonically bonded, are recommended. Create ball
bonds with a force of 40 g to 50 g and wedge bonds with a force
of 18 g to 22 g. Create all bonds with a nominal stage temperature
of 150°C. Apply a minimum amount of ultrasonic energy to
achieve reliable bonds. Keep all bonds as short as possible, less
than 12 mil (0.31 mm).
RF GROUND PLANE
0.150mm
0.254mm (0.010") THICK ALUMINA
THIN FILM SUBSTRATE
(0.005”) THICK
MOLY TAB
Figure 38. Routing RF Signals
Rev. C | Page 13 of 15
HMC8402
Data Sheet
TYPICAL APPLICATION CIRCUIT
V
DD
4.7µF
4.7µF
0.1µF
0.1µF
100pF
100pF
V
2
2
1
GG
3
4
RFOUT
RFIN
Figure 39. Typical Application Circuit
ASSEMBLY DIAGRAM
+
–
–
+
TO V SUPPLY
DD
0.1µF
ALL BOND WIRES ARE
1mil DIAMETER
0.1µF
3mil NOMINAL GAP
100pF
100pF
50Ω
TRANSMISSION LINE
Figure 40. Assembly Diagram
Rev. C | Page 14 of 15
Data Sheet
HMC8402
OUTLINE DIMENSIONS
2.700
0.05
0.043
0.175
0.080 × 0.080
0.100
(Pad 2 and Pad 3)
3
0.080 × 0.200
0.187
0.721
4
1.363
0.187
0.107
2
0.187
0.543
0.080 × 0.204
1
ADI2014
0.185
0.084
0.0152
0.010
SIDE VIEW
0.010
2.217
0.1300.162
0.084
Figure 41. 4-Pad Bare Die [CHIP]
(C-4-3)
Dimensions shown in millimeter
ORDERING GUIDE
Model1,2
HMC8402
Temperature Range
−55°C to +85°C
Package Description
4-Pad Bare Die [CHIP]
4-Pad Bare Die [CHIP]
Package Option
C-4-3
C-4-3
HMC8402-SX
−55°C to +85°C
1 The HMC8402-SX is a sample order of two devices.
2 The HMC8402 and HMC8402-SX are RoHS compliant parts.
©2016–2018 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D13853-0-4/18(C)
Rev. C | Page 15 of 15
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