HMC8410CHIPS-SX [ADI]
Low noise figure: 1.1 dB typical;
| 型号： | HMC8410CHIPS-SX |
| 厂家： | 
ADI |
| 描述： | Low noise figure: 1.1 dB typical 射频 微波 |
| 文件： | 总16页 (文件大小：399K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
0.01 GHz to 10 GHz, GaAs, pHEMT, MMIC,
Low Noise Amplifier
Data Sheet
HMC8410CHIPS
FEATURES
FUNCTIONAL BLOCK DIAGRAM
Low noise figure: 1.1 dB typical
High gain: 19.5 dB typical
2
RFOUT/V
DD
High output third-order intercept (IP3): 33 dBm typical
Die size: 0.95 mm × 0.61 × 0.102 mm
1
RFIN/V
1
GG
HMC8410CHIPS
APPLICATIONS
Figure 1.
Software defined radios
Electronics warfare
Radar applications
GENERAL DESCRIPTION
The HMC8410CHIPS is a gallium arsenide (GaAs), monolithic
microwave integrated circuit (MMIC), pseudomorphic high
electron mobility transistor (pHEMT), low noise wideband ampli-
fier that operates from 0.01 GHz to 10 GHz. The HMC8410CHIPS
provides a typical gain of 19.5 dB, a 1.1 dB typical noise figure,
and a typical output IP3 of 33 dBm, requiring only 65 mA from
a 5 V supply voltage. The saturated output power (PSAT) of
22.5 dBm enables the low noise amplifier (LNA) to function as a
local oscillator (LO) driver for many of Analog Devices, Inc.,
balanced, I/Q or image rejection mixers.
The HMC8410CHIPS also features inputs/outputs (I/Os) that are
internally matched to 50 Ω, making it ideal for surface-mounted
technology (SMT)-based, high capacity microwave radio
applications.
Rev. 0
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Tel: 781.329.4700
Technical Support
©2016 Analog Devices, Inc. All rights reserved.
www.analog.com
HMC8410CHIPS
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Interface Schematics .....................................................................6
Typical Performance Characteristics ..............................................7
Theory of Operation ...................................................................... 12
Applications Information.............................................................. 13
Recommended Bias Sequencing .............................................. 13
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Electrical Specifications................................................................... 3
0.01 GHz to 3 GHz Frequency Range........................................ 3
3 GHz to 8 GHz Frequency Range............................................. 3
8 GHz to 10 GHz Frequency Range........................................... 4
Absolute Maximum Ratings............................................................ 5
ESD Caution.................................................................................. 5
Pin Configuration and Function Descriptions............................. 6
Mounting and Bonding Techniques for Millimeterwave GaAs
MMICs......................................................................................... 13
Application Circuits ....................................................................... 15
Assembly Diagram ..................................................................... 15
Outline Dimensions....................................................................... 16
Ordering Guide .......................................................................... 16
REVISION HISTORY
10/2016—Revision 0: Initial Version
Rev. 0 | Page 2 of 16
Data Sheet
HMC8410CHIPS
SPECIFICATIONS
0.01 GHz TO 3 GHz FREQUENCY RANGE
TA = 25°C, VDD = 5 V, and IDQ = 65 mA, unless otherwise noted.
Table 1.
Parameter
Symbol
Min
0.01
17.5
Typ
Max
Unit
GHz
dB
dB/°C
dB
Test Conditions/Comments
FREQUENCY RANGE
3
GAIN
19.5
0.01
1.1
Gain Variation Over Temperature
NOISE FIGURE
1.6
RETURN LOSS
Input
Output
15
24
dB
dB
OUTPUT
Output Power for 1 dB Compression
Saturated Output Power
Output Third-Order Intercept
SUPPLY
P1dB
PSAT
IP3
19.0
21.0
22.5
33
dBm
dBm
dBm
Current
Voltage
IDQ
VDD
65
5
80
6
mA
V
Adjust VGG1 to achieve IDQ = 65 mA typical
2
3 GHz TO 8 GHz FREQUENCY RANGE
TA = 25°C, VDD = 5 V, and IDQ = 65 mA, unless otherwise noted.
Table 2.
Parameter
Symbol
Min
3
Typ
Max
Unit
GHz
dB
Test Conditions/Comments
FREQUENCY RANGE
8
GAIN
15.5
18
Gain Variation Over Temperature
0.01
1.4
dB/°C
dB
NOISE FIGURE
1.9
RETURN LOSS
Input
Output
12
12
dB
dB
OUTPUT
Output Power for 1 dB Compression
Saturated Output Power
Output Third-Order Intercept
SUPPLY
P1dB
PSAT
IP3
17.5
20.5
22.5
31.5
dBm
dBm
dBm
Current
Voltage
IDQ
VDD
65
5
80
6
mA
V
Adjust VGG1 to achieve IDQ = 65 mA typical
2
Rev. 0 | Page 3 of 16
HMC8410CHIPS
Data Sheet
8 GHz TO 10 GHz FREQUENCY RANGE
TA = 25°C, VDD = 5 V, and IDQ = 65 mA, unless otherwise noted.
Table 3.
Parameter
Symbol
Min
8
Typ
Max
Unit
GHz
dB
Test Conditions/Comments
FREQUENCY RANGE
10
GAIN
13
16
Gain Variation Over Temperature
0.01
1.7
dB/°C
dB
NOISE FIGURE
2.2
RETURN LOSS
Input
Output
6
10
dB
dB
OUTPUT
Output Power for 1 dB Compression
Saturated Output Power
Output Third-Order Intercept
SUPPLY
P1dB
PSAT
IP3
17.5
19.5
21.5
33
dBm
dBm
dBm
Current
Voltage
IDQ
VDD
65
5
80
6
mA
V
Adjust VGG1 to achieve IDQ = 65 mA typical
2
Rev. 0 | Page 4 of 16
Data Sheet
HMC8410CHIPS
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 4.
θJC is the junction to case thermal resistance, channel to bottom
of die.
Parameter1
Rating
Drain Bias Voltage (VDD
Radio Frequency (RF) Input Power (RFIN)
Continuous Power Dissipation (PDISS), T = 85°C
(Derate 13.23 mW/°C Above 85°C)
)
7 V dc
20 dBm
1.2 W
Table 5. Thermal Resistance
Package Type
θJC
Unit
C-2-3
75.57
°C/W
Channel Temperature
175°C
Storage Temperature Range
Operating Temperature Range
ESD Sensitivity
−65°C to +150°C
−55°C to +85°C
ESD CAUTION
Human Body Model (HBM)
Class 1B passed
500 V
1 When referring to a single function of a multifunction pin in the parameters,
only the portion of the pin name that is relevant to the specification is listed.
For the full pin names of multifunction pins, refer to the Pin Configuration
and Function Descriptions section.
2 See the Ordering Guide section for more information.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Rev. 0 | Page 5 of 16
HMC8410CHIPS
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
HMC8410CHIPS
2
RFOUT/V
DD
TOP VIEW
(Not to Scale)
1
RFIN/V
1
GG
Figure 2. Pad Configuration
Table 6. Pad Function Descriptions
Pin No.
Mnemonic Description
1
RFIN/VGG
1
RF Input (RFIN). This pin is ac-coupled and matched to 50 Ω. See Figure 4 for the interface schematic.
Gate Bias of the Amplifier (VGG1). This pin is ac-coupled and matched to 50 Ω. See Figure 4 for the interface
schematic.
2
RFOUT/VDD RF Output (RFOUT). This pin is ac-coupled and matched to 50 Ω. See Figure 5 for the interface schematic.
Drain Bias for Amplifier (VDD). This pin is ac-coupled and matched to 50 Ω. See Figure 5 for the interface
schematic.
Die Bottom GND
Ground. Die bottom must be connected to RF/dc ground.
INTERFACE SCHEMATICS
RFOUT/V
DD
GND
Figure 5. RFOUT/VDD Interface Schematic
Figure 3. GND Interface Schematic
RFIN/V
1
GG
Figure 4. RFIN/VGG1 Interface Schematic
Rev. 0 | Page 6 of 16
Data Sheet
HMC8410CHIPS
TYPICAL PERFORMANCE CHARACTERISTICS
25
20
15
10
5
22
20
18
16
14
12
10
8
+85°C
+25°C
–55°C
0
–5
–10
–15
–20
S11
S21
S22
–25
–30
0
1
2
3
4
5
6
7
8
9
10
11
0
1
2
3
4
5
6
7
8
9
10
11
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 6. Gain and Return Loss vs. Frequency
Figure 9. Gain vs. Frequency for Various Temperatures
0
–2
0
–5
+85°C
+25°C
–55°C
+85°C
+25°C
–55°C
–4
–10
–15
–20
–25
–30
–35
–6
–8
–10
–12
–14
–16
–18
–20
0
1
2
3
4
5
6
7
8
9
10
11
0
1
2
3
4
5
6
7
8
9
10
11
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 7. Input Return Loss vs. Frequency for Various Temperatures
Figure 10. Output Return Loss vs. Frequency for Various Temperatures
4.0
15
+85°C
+25°C
+85°C
14
+25°C
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
–55°C
–55°C
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
1
2
3
4
5
6
7
8
9
10
11
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 8. Noise Figure vs. Frequency for Various Temperatures
Figure 11. Noise Figure vs. Frequency for Various Temperatures,
10 MHz to 1 GHz
Rev. 0 | Page 7 of 16
HMC8410CHIPS
Data Sheet
25
24
23
22
21
20
19
18
17
16
15
50
45
40
35
30
25
20
15
10
5
+85°C
+25°C
–55°C
+85°C
+25°C
–55°C
0
0
1
2
3
4
5
6
7
8
9
10
11
0
1
2
3
4
5
6
7
8
9
10
11
11
11
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 15. Output IP2 vs. Frequency for Various Temperatures at POUT/Tone =
5 dBm
Figure 12. P1dB vs. Frequency for Various Temperatures
0
25
+85°C
+25°C
24
23
22
21
20
19
18
17
16
15
–55°C
–5
–10
–15
–20
–25
–30
–35
+85°C
+25°C
–55°C
0
1
2
3
4
5
6
7
8
9
10
11
0
1
2
3
4
5
6
7
8
9
10
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 16. Reverse Isolation vs. Frequency for Various Temperatures
Figure 13. PSAT vs. Frequency for Various Temperatures
40
35
30
25
20
15
10
40
35
30
25
20
15
10
5
+85°C
+25°C
–55°C
0dBm
5dBm
10dBm
5
0
0
0
1
2
3
4
5
6
7
8
9
10
0
1
2
3
4
5
6
7
8
9
10
11
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 14. Output IP3 vs. Frequency for Various Temperatures,
Output Power (POUT)/Tone = 5 dBm
Figure 17. Output IP3 vs. Frequency for Various POUT/Tone
Rev. 0 | Page 8 of 16
Data Sheet
HMC8410CHIPS
40
35
30
25
20
15
55
50
45
40
35
30
25
20
15
10
5
P
PAE
GAIN
P1dB
SAT
OUTPUT IP3
SAT
P
10
0
0
0.2
0.4
0.6
0.8
1.0
0
1
2
3
4
5
6
7
8
9
10
11
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 18. Gain, P1dB, PSAT, and Output IP3 vs. Frequency
Figure 21. PSAT and PAE vs. Frequency
40
35
30
25
20
15
10
5
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
P1dB
PAE
1GHz
3GHz
5GHz
7GHz
9GHz
0
–10 –8 –6 –4 –2
0
2
4
6
8
10 12 14
0
1
2
3
4
5
6
7
8
9
10
11
INPUT POWER (dBm)
FREQUENCY (GHz)
Figure 22. Power Dissipation vs. Input Power for Various Frequencies, TA = 85°C
Figure 19. P1dB and Power Added Efficiency (PAE) vs. Frequency
50
100
95
90
85
80
75
70
65
60
55
50
22
5mA
45mA
65mA
70mA
80mA
15mA
25mA
35mA
45
40
35
30
25
20
15
10
5
20
18
16
14
12
10
8
P
OUT
GAIN
PAE
I
DD
0
–10
–5
0
5
10
0
1
2
3
4
5
6
7
8
9
10
11
INPUT POWER (dBm)
FREQUENCY (GHz)
Figure 20. POUT, Gain, PAE, and Supply Current with RF Applied (IDD) vs.
Input Power at 5 GHz
Figure 23. Gain vs. Frequency for Various Supply Currents, VDD = 5 V
Rev. 0 | Page 9 of 16
HMC8410CHIPS
Data Sheet
4.0
40
35
30
25
20
15
10
5
5mA
15mA
25mA
35mA
45mA
65mA
70mA
75mA
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
5mA
15mA
35mA
65mA
75mA
25mA
45mA
70mA
0
0
1
2
3
4
5
6
7
8
9
10
11
0
1
2
3
4
5
6
7
8
9
10
11
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 27. Output IP3 vs. Frequency for Various Supply Currents (IDQ),
OUT/Tone = 5 dBm, VDD = 5 V
Figure 24. Noise Figure vs. Frequency for Various Supply Currents (IDQ),
VDD = 5 V
P
22
20
18
16
14
12
10
8
25
3V
4V
5V
6V
7V
20
5mA
15
15mA
25mA
35mA
45mA
65mA
10
70mA
75mA
80mA
5
0
0
1
2
3
4
5
6
7
8
9
10
11
0
1
2
3
4
5
6
7
8
9
10
11
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 28. Gain vs. Frequency for Various Supply Voltages, IDQ = 65 mA
Figure 25. P1dB vs. Frequency for Various Supply Currents (IDQ), VDD = 5 V
4.0
3V
4V
25
24
23
22
5V
6V
7V
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
21
5mA
15mA
25mA
20
35mA
45mA
65mA
70mA
75mA
80mA
19
18
0
1
2
3
4
5
6
7
8
9
10
11
0
1
2
3
4
5
6
7
8
9
10
11
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 29. Noise Figure vs. Frequency for Various Supply Voltages, IDQ = 65 mA
Figure 26. PSAT vs. Frequency for Various Supply Currents (IDQ), VDD = 5 V
Rev. 0 | Page 10 of 16
Data Sheet
HMC8410CHIPS
25
23
21
19
17
15
13
11
90
80
70
60
50
40
30
20
10
0
3V
4V
5V
6V
7V
0
1
2
3
4
5
6
7
8
9
10
11
–0.90 –0.85 –0.80 –0.75 –0.70 –0.65 –0.60 –0.55 –0.50 –0.45
FREQUENCY (GHz)
V 1 (V)
GG
Figure 33. Supply Current with RF Applied (IDD) vs. VGG1, VDD = 5 V,
Representative of a Typical Device
Figure 30. P1dB vs. Frequency for Various Supply Voltages, IDQ = 65 mA
120
100
80
27
25
23
21
19
17
60
5mA
15mA
40
25mA
35mA
45mA
3V
4V
65mA
20
15
70mA
75mA
80mA
5V
6V
7V
0
–10
13
–5
0
5
10
15
0
2
4
6
8
10
INPUT POWER (dBm)
FREQUENCY (GHz)
Figure 34. Supply Current with RF Applied (IDD) vs. Input Power for
Various Supply Currents (IDQ), VDD = 5 V
Figure 31. PSAT vs. Frequency for Various Supply Voltages, IDQ = 65 mA
20
18
16
14
40
35
30
25
20
15
12
5mA
15mA
25mA
10
35mA
45mA
65mA
10
3V
4V
8
70mA
75mA
80mA
5V
6V
7V
5
6
0
–10
–5
0
5
10
15
0
1
2
3
4
5
6
7
8
9
10
11
INPUT POWER (dBm)
FREQUENCY (GHz)
Figure 35. Gain vs. Input Power for Various Supply Currents (IDQ) at 5 GHz,
DD = 5 V
Figure 32. Output IP3 vs. Frequency for Various Supply Voltages,
POUT/Tone = 5 dBm
V
Rev. 0 | Page 11 of 16
HMC8410CHIPS
Data Sheet
THEORY OF OPERATION
The HMC8410CHIPS is a GaAs, MMIC, pHEMT, low noise
wideband amplifier.
The HMC8410CHIPS has single-ended input and output ports
whose impedances are nominally equal to 50 Ω over the 0.01 GHz
to 10 GHz frequency range. Consequently, it can directly insert
into a 50 Ω system with no required impedance matching
circuitry, which also means that multiple HMC8410CHIPS
amplifiers can be cascaded back to back without the need for
external matching circuitry.
The cascode amplifier uses a fundamental cell of two field effect
transistors (FETs) in series, source to drain. The basic schematic
for the cascode cell is shown in Figure 36, which forms a low
noise amplifier operating from 0.01 GHz to 10 GHz with excellent
noise figure performance.
RFOUT/V
The input and output impedances are sufficiently stable vs.
variations in temperature and supply voltage so that no impedance
matching compensation is required.
DD
To achieve optimal performance from the HMC8410CHIPS and
prevent damage to the device, do not exceed the absolute
maximum ratings.
RFIN/V
1
GG
Figure 36. Basic Schematic for the Cascode Cell
Rev. 0 | Page 12 of 16
Data Sheet
HMC8410CHIPS
APPLICATIONS INFORMATION
Figure 39 shows the basic connections for operating the
HMC8410CHIPS. The data taken herein used wideband bias
tees on the input and output ports to provide both ac coupling and
the necessary supply voltages to the RFIN/VGG1 and RFOUT/VDD
pins. A 5 V dc drain bias is supplied to the amplifier through
the choke inductor connected to the RFOUT/VDD pin, and the
−2 V gate bias voltage is supplied to the RFIN/VGG1 pin through
the choke inductor. The RF signal must be ac-coupled to prevent
disrupting the dc bias applied to RFIN/VGG1 and RFOUT/VDD.
The nonideal characteristics of ac coupling capacitors and
choke inductors (for example, self resonance) can introduce
performance trade-offs that must be considered when using a
single application circuit across a very wide frequency range.
MOUNTING AND BONDING TECHNIQUES FOR
MILLIMETERWAVE GaAs MMICS
Attach the die directly to the ground plane eutectically or with
conductive epoxy (see the Handling Precautions section).
To bring the radio frequency to and from the chip, implementing
50 Ω transmission lines using a microstrip or coplanar waveguide
on 0.127 mm (5 mil) thick alumina, thin film substrates is recom-
mended (see Figure 37). When using 0.254 mm (10 mil) thick
alumina, it is recommended that the die be raised to ensure that
the die and substrate surfaces are coplanar. Raise the die 0.150 mm
(6 mil) to ensure that the surface of the die is coplanar with the
surface of the substrate. To accomplish this, attach the 0.102 mm
(4 mil) thick die to a 0.150 mm (6 mil) thick, molybdenum (Mo)
heat spreader (moly tab), which can then be attached to the
ground plane (see Figure 37 and Figure 38).
RECOMMENDED BIAS SEQUENCING
The recommended bias sequence during power-up is as follows:
1. Connect to GND.
0.102mm (0.004") THICK GaAs MMIC
2. Set RFIN/VGG1 to −2 V.
3. Set RFOUT/VDD to 5 V.
4. Increase RFIN/VGG1 to achieve a typical supply current
(IDQ) = 65 mA.
WIRE BOND
0.076mm
(0.003")
5. Apply the RF signal.
The recommended bias sequence during power-down is as
follows:
RF GROUND PLANE
1. Turn off the RF signal.
2. Decrease RFIN/VGG1 to −2 V to achieve a typical IDQ = 0 mA.
3. Decrease RFOUT/VDD to 0 V.
0.127mm (0.005") THICK ALUMINA
THIN FILM SUBSTRATE
4. Increase RFIN/VGG1 to 0 V.
Figure 37. Die Without the Moly Tab
The bias conditions previously listed (RFOUT/VDD = 5 V and
I
DQ = 65 mA) are the recommended operating conditions to
0.102mm (0.004") THICK GaAs MMIC
achieve optimum performance. The data used in this data sheet
was taken with the recommended bias conditions. When using
the HMC8410CHIPS with different bias conditions, different
performance than that shown in the Typical Performance
Characteristics section may result.
WIRE BOND
0.076mm
(0.003")
Figure 29, Figure 30, and Figure 31 show that increasing the
voltage from 3 V to 7 V typically increases P1dB and PSAT at the
expense of power consumption with minor degradation on
noise figure (NF).
RF GROUND PLANE
0.150mm (0.005") THICK
MOLY TAB
0.254mm (0.010") THICK ALUMINA
THIN FILM SUBSTRATE
Figure 38. Die With the Moly Tab
Place microstrip substrates as close to the die as possible to
minimize bond wire length. Typical die to substrate spacing is
0.076 mm to 0.152 mm (3 mil to 6 mil).
Rev. 0 | Page 13 of 16
HMC8410CHIPS
Data Sheet
Handling Precautions
•
•
Follow ESD precautions to protect against ESD strikes.
While bias is applied, suppress instrument and bias supply
transients. Use shielded signal and bias cables to minimize
inductive pickup.
Handle the chip along the edges with a vacuum collet or
with a sharp pair of bent tweezers. The surface of the chip
may have fragile air bridges and must not be touched with
a vacuum collet, tweezers, or fingers.
To avoid permanent damage, follow these storage, cleanliness,
static sensitivity, transient, and general handling precautions:
•
Place all bare die in either waffle or gel-based ESD
protective containers and then seal the die in an ESD
protective bag for shipment. After the sealed ESD
protective bag is opened, store all die in a dry nitrogen
environment.
•
•
Handle the chips in a clean environment. Do not attempt
to clean the chip using liquid cleaning systems.
Rev. 0 | Page 14 of 16
Data Sheet
HMC8410CHIPS
APPLICATION CIRCUIT
V
1
V
DD
GG
RFIN
1
2
RFOUT
EXTERNAL BIAS TEE
EXTERNAL BIAS TEE
Figure 39. Application Circuit
ASSEMBLY DIAGRAM
3mil NOMINAL GAP
50Ω
TRANSMISSION
LINE
RFOUT/V
DD
RFIN/V
1
GG
Figure 40. Assembly Diagram
Rev. 0 | Page 15 of 16
HMC8410CHIPS
Data Sheet
OUTLINE DIMENSIONS
0.950
0.159
0.630
0.102
ADI 2015
0.162
0.248
0.186
0.610
2
0.162
0.165
1
0.099
SIDE VIEW
TOP VIEW
0.779
0.078
Figure 41. 2-Pad Bare Die [CHIP]
(C-2-3)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Temperature Range
−55°C to +85°C
−55°C to +85°C
Package Description
2-Pad Bare Die [CHIP]
2-Pad Bare Die [CHIP]
Package Option
HMC8410CHIPS
HMC8410CHIPS-SX
C-2-3
C-2-3
1 The HMC8410CHIPS and HMC8410CHIPS-SX are RoHS Compliant Parts.
©2016 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D15093-0-10/16(0)
Rev. 0 | Page 16 of 16
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