IRF7811_技术文档

Synchronous Buck Controller with

Constant On Time and Valley Current Mode

Data Sheet

ADP1878/ADP1879

FEATURES

TYPICAL APPLICATIONS CIRCUIT

V

= 2.95V TO 20V

IN

Power input voltage range: 2.95 V to 20 V

On-board bias regulator

Minimum output voltage: 0.6 V

VIN

C

ADP1878/

ADP1879

0.6 V reference voltage with 1.0% accuracy

Supports all N-channel MOSFET power stages

Available in 300 kHz, 600 kHz, and 1.0 MHz options

No current sense resistor required

Power saving mode (PSM) for light loads (ADP1879 only)

Resistor programmable current limit

Power good with internal pull-up resistor

Externally programmable soft start

Thermal overload protection

C

IN

C2

R

C

COMP

BST

DRVH

SW

C

10kΩ

Q1

BST

V

L

REG

EN

FB

R

V

TOP

OUT

V

OUT

C

Q2

OUT

R

BOT

LOAD

GND

DRVL

C

VREG2

VREG

C

VREG

R

PGD

PGOOD

SS

V

EXT

RES

R

RES

C

SS

PGND

Short-circuit protection

Standalone precision enable input

Integrated bootstrap diode for high-side drive

Starts into a precharged output

Figure 1.

Available in a 14-lead LFCSP_WD package

APPLICATIONS

Telecommunications and networking systems

Mid-to-high end servers

Set-top boxes

DSP core power supplies

conditions. The low-side current sense, current gain scheme and

integration of a boost diode, together with the PSM/forced

pulse-width modulation (PWM) option, reduce the external

device count and improve efficiency.

GENERAL DESCRIPTION

The ADP1878/ADP1879 are versatile current-mode, synchronous

step-down controllers. They provide superior transient response,

optimal stability, and current-limit protection by using a constant

on time, pseudo fixed frequency with a programmable current-limit,

current control scheme. These devices offer optimum performance

at low duty cycles by using a valley, current-mode control architec-

ture allowing the ADP1878/ADP1879 to drive all N-channel power

stages to regulate output voltages to as low as 0.6 V.

The ADP1878/ADP1879 operate over the −40°C to +125°C

junction temperature range and are available in a 14-lead

LFCSP_WD package.

100

V

= 5V (PSM)

IN

95

90

85

80

75

70

65

60

55

50

45

40

35

30

25

The ADP1879 is the power saving mode (PSM) version of the

device and is capable of pulse skipping to maintain output

regulation while achieving improved system efficiency at light

loads (see the ADP1879 Power Saving Mode (PSM) section for

more information).

V

= 16.5V

IN

V

= 13V

IN

V

= 13V (PSM)

IN

Available in three frequency options (300 kHz, 600 kHz, and

1.0 MHz) plus the PSM option, the ADP1878/ADP1879 are well

suited for a wide range of applications that require a single input

power supply range from 2.95 V to 20 V. Low voltage biasing is

supplied via a 5 V internal low dropout regulator (LDO). In

addition, soft start programmability is included to limit input

inrush current from the input supply during startup and to

provide reverse current protection during precharged output

T

= 25°C

A

V

= 1.8V

OUT

f

SW

= 300kHz

V

= 16.5V (PSM)

IN

WÜRTH INDUCTOR:

744325120, L = 1.2µH, DCR = 1.8mꢀ

INFINEON FETs:

BSC042N03MS G (UPPER/LOWER)

10

100

1k

10k

100k

LOAD CURRENT (mA)

Figure 2. ADP1878/ADP1879 Efficiency vs. Load Current (V_OUT= 1.8 V, 300 kHz)

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registeredtrademarks arethe property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

www.analog.com

ADP1878/ADP1879

Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

Pseudo Fixed Frequency............................................................ 22

Power-Good Monitoring........................................................... 23

Applications Information.............................................................. 24

Feedback Resistor Divider ........................................................ 24

Inductor Selection...................................................................... 24

Output Ripple Voltage (ΔV_RR) .................................................. 24

Output Capacitor Selection....................................................... 24

Compensation Network ............................................................ 25

Efficiency Consideration........................................................... 26

Input Capacitor Selection.......................................................... 27

Thermal Considerations............................................................ 27

Design Example.......................................................................... 29

External Component Recommendations.................................... 31

Layout Considerations................................................................... 33

IC Section (Left Side of Evaluation Board)............................. 35

Power Section ............................................................................. 35

Differential Sensing.................................................................... 36

Typical Application Circuits ......................................................... 37

12 A, 300 kHz High Current Application Circuit.................. 37

5.5 V Input, 600 kHz Current Application Circuit................ 37

300 kHz High Current Application Circuit............................ 38

Packaging and Ordering Information ......................................... 39

Outline Dimensions................................................................... 39

Ordering Guide .......................................................................... 40

Applications....................................................................................... 1

Typical Applications Circuit............................................................ 1

General Description......................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Absolute Maximum Ratings ....................................................... 5

Thermal Resistance ...................................................................... 5

ESD Caution.................................................................................. 5

Pin Configuration and Function Descriptions............................. 6

Typical Performance Characteristics ............................................. 7

Theory of Operation ...................................................................... 17

Block Diagram ............................................................................ 17

Startup.......................................................................................... 18

Soft Start ...................................................................................... 18

Precision Enable Circuitry ........................................................ 18

Undervoltage Lockout ............................................................... 18

On-Board Low Dropout (LDO) Regulator............................. 18

Thermal Shutdown..................................................................... 19

Programming Resistor (RES) Detect Circuit.......................... 19

Valley Current-Limit Setting .................................................... 19

Hiccup Mode During Short Circuit......................................... 21

Synchronous Rectifier................................................................ 21

ADP1879 Power Saving Mode (PSM)...................................... 21

Timer Operation......................................................................... 22

REVISION HISTORY

6/12—Rev. 0 to Rev. A

Changes to Table 1.............................................................................3

7/11—Revision 0: Initial Version

Rev. A | Page 2 of 40

Data Sheet

ADP1878/ADP1879

SPECIFICATIONS

All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC). VREG = 5 V,

BST − SW = VREG − V_{RECT_DROP}(see Figure 40 to Figure 42). VIN = 12 V. The specifications are valid for T_J= −40°C to +125°C,

unless otherwise specified.

Table 1.

Parameter

Symbol

Test Conditions/Comments

Min

Typ

Max

Unit

POWER SUPPLY CHARACTERISTICS

High Input Voltage Range

VIN

C_VIN= 22 μF(25 V rating) right at Pin 1 to PGND (Pin 11)

ADP1878ACPZ-0.3-R7/ADP1879ACPZ-0.3-R7 (300 kHz)

ADP1878ACPZ-0.6-R7/ADP1879ACPZ-0.6-R7 (600 kHz)

ADP1878ACPZ-1.0-R7/ADP1879ACPZ-1.0-R7 (1.0 MHz)

FB = 1.5 V, no switching

2.95

3.25

12

1.1

20

V

mA

Quiescent Current

Shutdown Current

I_{Q_REG}

I_{Q_BST}

I_REG,SD

I_BST,SD

UVLO

+

EN < 600 mV

140

225

μA

Undervoltage Lockout

UVLO Hysteresis

Rising VIN (see Figure 35 for temperature variation)

Falling VIN from operational state

2.65

178

V

mV

INTERNAL REGULATOR

CHARACTERISTICS

Do not load VREG externally because it is intended to

bias internal circuitry only

VREG Operational Output Voltage VREG

C_VREG= 4.7 μF to PGND, 0.22 μF to GND, V_IN= 2.95 V to 20 V

ADP1878ACPZ-0.3-R7/ADP1879ACPZ-0.3-R7 (300 kHz)

ADP1878ACPZ-0.6-R7/ADP1879ACPZ-0.6-R7 (600 kHz)

ADP1878ACPZ-1.0-R7/ADP1879ACPZ-1.0-R7 (1.0 MHz)

V_IN= 7 V, 100 mA

2.75

3.05

4.82

4.83

5

5.5

V

VREG Output in Regulation

Load Regulation

4.981 5.16

4.982 5.16

V_IN= 12 V, 100 mA

0 mA to 100 mA, V_IN= 7 V

V

32

34

1.8

2.0

306

229

mV

mA

0 mA to 100 mA, V_IN= 20 V

Line Regulation

V_IN= 7 V to 20 V, 20 mA

V_IN= 7 V to 20 V, 100 mA

VIN to VREG Dropout Voltage

Short VREG to PGND

SOFT START

Soft Start Period Calculation

ERROR AMPLIFER

100 mA out of VREG, V_IN≤ 5 V

V_IN= 20 V

415

320

Connect external capacitor from SS pin to GND,

C_SS= 10 nF/ms

10

nF/ms

FB Regulation Voltage

V_FB

T_J= 25°C

T_J= −40°C to +85°C

T_J= −40°C to +125°C

600

594.2 600

mV

605.8 mV

596

604

Transconductance

FB Input Leakage Current

CURRENT SENSE AMPLIFIER GAIN

Programming Resistor (RES)

Value from RES to PGND

G_m

I_{FB, LEAK}

320

496

1

670

50

μS

nA

FB = 0.6 V, EN = VREG

RES = 47 kΩ 1%

2.7

3

3.3

V/V

RES = 22 kΩ 1%

RES = none

RES = 100 kΩ 1%

5.5

11

22

6

12

24

6.5

13

26

V/V

SWITCHING FREQUENCY

Typical values measured at 50% time points with 0 nF at

DRVH and DRVL; maximum values are guaranteed by

bench evaluation¹

ADP1878ACPZ-0.3-R7/

ADP1879ACPZ-0.3-R7

300

kHz

On Time

Minimum On Time

Minimum Off Time

V_IN= 5 V, V_OUT= 2 V, T_J= 25°C

V_IN= 20 V

84% duty cycle (maximum)

1120 1200 1345 ns

145

340

190

400

ns

Rev. A | Page 3 of 40

ADP1878/ADP1879

Data Sheet

Parameter

Symbol

Test Conditions/Comments

Min

Typ

Max

Unit

ADP1878ACPZ-0.6-R7/

ADP1879ACPZ-0.6-R7

600

kHz

On Time

Minimum On Time

Minimum Off Time

ADP1878ACPZ-1.0-R7/

ADP1879ACPZ-1.0-R7

V_IN= 5 V, V_OUT= 2 V, T_J= 25°C

V_IN= 20 V, V_OUT= 0.8 V

65% duty cycle (maximum)

500

540

82

340

1.0

605

110

400

ns

MHz

On Time

V_IN= 5 V, V_OUT= 2 V, T_J= 25°C

V_IN= 20 V

45% duty cycle (maximum)

285

312

52

340

360

85

400

ns

Minimum On Time

Minimum Off Time

OUTPUT DRIVER CHARACTERISTICS

High-Side Driver

Output Source Resistance

Output Sink Resistance

Rise Time²

I_SOURCE= 1.5 A, 100 ns, positive pulse (0 V to 5 V)

I_SINK= 1.5 A, 100 ns, negative pulse (5 V to 0 V)

BST − SW = 4.4 V, C_IN= 4.3 nF (see Figure 59)

BST − SW = 4.4 V, C_IN= 4.3 nF (see Figure 60)

2.20

0.72

25

3

1

Ω

ns

t_{r, DRVH}

t_{f, DRVH}

Fall Time²

11

Low-Side Driver

Output Source Resistance

Output Sink Resistance

Rise Time²

I_SOURCE= 1.5 A, 100 ns, positive pulse (0 V to 5 V)

I_SINK= 1.5 A, 100 ns, negative pulse (5 V to 0 V)

V_REG= 5.0 V, C_IN= 4.3 nF (see Figure 60)

1.5

0.7

18

2.2

1

Ω

ns

t_r,DRVL

t_f,DRVL

Fall Time²

V_REG= 5.0 V, C_IN= 4.3 nF (see Figure 59)

16

Propagation Delays

DRVL Fall to DRVH Rise²

DRVH Fall to DRVL Rise²

SW Leakage Current

Integrated Rectifier

Channel Impedance

PRECISION ENABLE THRESHOLD

Logic High Level

t_tpdhDRVH

t_tpdhDRVL

I_SWLEAK

BST − SW = 4.4 V (see Figure 59)

BST − SW = 4.4 V (see Figure 60)

BST = 25 V, SW = 20 V, V_REG= 5 V

15.7

16

ns

μA

110

663

I_SINK= 10 mA

22.3

Ω

V_IN= 2.9 V to 20 V, V_REG= 2.75 V to 5.5 V

605

634

31

mV

Enable Hysteresis

COMP VOLTAGE

COMP Clamp Low Voltage

V_COMP(LOW)Tie EN pin to VREG to enable device

(2.75 V ≤ V_REG≤ 5.5 V)

0.47

V

COMP Clamp High Voltage

COMP Zero Current Threshold

THERMAL SHUTDOWN

Thermal Shutdown Threshold

Thermal Shutdown Hysteresis

CURRENT LIMIT

V_COMP(HIGH)(2.75 V ≤ V_REG≤ 5.5 V)

2.55

V

V_{COMP_ZCT}

T_TMSD

(2.75 V ≤ V_REG≤ 5.5 V)

Rising temperature

1.10

155

15

°C

Hiccup Current-Limit Timing

COMP = 2.4 V

6

ms

OVERVOLTAGE AND POWER-

GOOD THRESHOLDS

PGOOD

FB_PGD

FB Power-Good Threshold

FB Power-Good Hysteresis

FB Overvoltage Threshold

FB Overvoltage Hysteresis

PGOOD Low Voltage During Sink

PGOOD Leakage Current

V_FBrising during system power up

542

34

691

35

143

1

566

55

710

55

200

100

mV

nA

FB_OV

V_FBrising during overvoltage event, I_PGOOD= 1 mA

V_PGOOD

I_PGOOD= 1 mA

PGOOD = 5 V

¹The maximum specified values are with the closed loop measured at 10% to 90% time points (see Figure 59 and Figure 60), C_GATE= 4.3 nF, and the high- and low-side

MOSFETs being Infineon BSC042N03MS G.

²Not automatic test equipment (ATE) tested.

Rev. A | Page 4 of 40

Data Sheet

ADP1878/ADP1879

ABSOLUTE MAXIMUM RATINGS

THERMAL RESISTANCE

Table 2.

Parameter

θ_JAis specified for the worst-case conditions, that is, a device

soldered in a circuit board for surface-mount packages.

Rating

VREG to PGND, GND

VIN, EN, PGOOD to PGND

FB, COMP, RES, SS to GND

DRVL to PGND

SW to PGND

BST to SW

BST to PGND

DRVH to SW

PGND to GND

−0.3 V to +6 V

−0.3 V to +28 V

−0.3V to (VREG + 0.3 V)

−2.0 V to +28 V

−0.6 V to (VREG + 0.3 V)

−0.3V to +28 V

−0.3 V to VREG

0.3 V

Boundary Condition

In determining the values given in Table 2 and Table 3, natural

convection is used to transfer heat to a 4-layer evaluation board.

Table 3. Thermal Resistance

Package Type

θ_JA

Unit

θ_JA(14-Lead LFCSP_WD)

4-Layer Board

30

°C/W

PGOOD Input Current

θ_JA(14-Lead LFCSP_WD)

4-Layer Board

35 mA

ESD CAUTION

30°C/W

Operating Junction Temperature Range

Storage Temperature Range

Soldering Conditions

−40°C to +125°C

−65°C to +150°C

JEDEC J-STD-020

Maximum Soldering Lead Temperature 300°C

(10 sec)

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

Absolute maximum ratings apply individually only, not in

combination. Unless otherwise specified, all other voltages are

referenced to PGND.

Rev. A | Page 5 of 40

ADP1878/ADP1879

Data Sheet

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

ADP1878/ADP1879

1

2

3

4

5

6

7

14

13

12

11

10

9

VIN

COMP

EN

BST

SW

DRVH

PGND

DRVL

PGOOD

SS

FB

GND

RES

8

VREG

TOP VIEW

(Not to Scale)

NOTES

1. CONNECT THE EXPOSED PAD TO THE

ANALOG GROUND PIN (GND).

Figure 3. Pin Configuration

Table 4. Pin Function Descriptions

No.

Mnemonic Description

1

VIN

High-Side Input Voltage. Connect VIN to the drain of the high-side MOSFET.

2

COMP

Output of the Error Amplifier. Connect compensation network between this pin and AGND to achieve stability (see

the Compensation Network section).

3

4

5

EN

FB

GND

IC Enable. Connect EN to VREG to enable the IC. When pulled down to AGND externally, EN disables the IC.

Noninverting Input of the Internal Error Amplifier. This is the node where the feedback resistor is connected.

Analog Ground Reference Pin of the IC. Connect all sensitive analog components to this ground plane (see the Layout

Considerations section).

6

7

RES

VREG

Current Sense Gain Resistor (External). Connect a resistor between the RES pin and GND (Pin 5).

Internal Regulator Supply Bias Voltage for the ADP1878/ADP1879 Controller (Includes the Output Gate Drivers).

Connecting a bypass capacitor of 1 μF directly from this pin to PGND and a 0.1 μF capacitor across VREG and GND are

recommended.

8

SS

Soft Start Input. Connect an external capacitor to GND to program the soft start period. There is a capacitance value

of 10 nF for every 1 ms of soft start delay.

9

PGOOD

DRVL

Open-Drain Power-Good Output. PGOOD sinks current when FB is out of regulation or during thermal shutdown.

Connect a 3 kΩ resistor between PGOOD and VREG. Leave PGOOD unconnected if it is not used.

Drive Output for the External Low-Side, N-Channel MOSFET. This pin also serves as the current sense gain setting pin

(see Figure 69).

10

11

12

13

14

PGND

DRVH

SW

Power Ground. Ground for the low-side gate driver and low-side N-channel MOSFET.

Drive Output for the External High-Side N-Channel MOSFET.

Switch Node Connection.

Bootstrap for the High-Side N-Channel MOSFET Gate Drive Circuitry. An internal boot rectifier (diode) is connected

between VREG and BST. A capacitor from BST to SW is required. An external Schottky diode can also be connected

between VREG and BST for increased gate drive capability.

BST

EP

Exposed Pad. Connect the exposed pad to the analog ground pin (GND).

Rev. A | Page 6 of 40

Data Sheet

ADP1878/ADP1879

TYPICAL PERFORMANCE CHARACTERISTICS

100

95

90

100

95

90

85

80

75

70

65

60

55

50

45

40

35

30

25

20

15

10

5

V

= 13V

IN

85

80

75

70

65

60

55

50

45

40

35

30

25

20

15

10

5

V

= 13V (PSM)

IN

V

= 13V (PSM)

IN

V

= 16.5V

IN

V

= 16.5V

IN

V

= 13V

IN

T

V

= 25°C

= 0.8V

= 300kHz

T = 25°C

A

V

= 16.5V (PSM)

A

IN

V

= 0.8V

= 600kHz

OUT

V

= 16.5V

(PSM)

IN

f

SW

WÜRTH INDUCTOR:

744325072, L = 0.72µH, DCR = 1.3mΩ

INFINEON FETs:

BSC042N03MS G (UPPER/LOWER)

WÜRTH INDUCTOR:

744355147, L = 0.47µH, DCR = 0.67mΩ

INFINEON FETs:

BSC042N03MS G (UPPER/LOWER)

0

10

100

1k

10k

100k

10

100

1k

10k

100k

LOAD CURRENT (mA)

Figure 4. Efficiency—300 kHz, V_OUT= 0.8 V

Figure 7. Efficiency—600 kHz, V_OUT= 0.8 V

100

95

90

85

80

75

70

65

60

55

50

45

40

35

30

25

20

15

10

5

100

95

90

85

80

75

70

65

60

55

50

45

40

35

30

25

20

15

10

5

V

= 5V (PSM)

IN

V

= 13V

IN

V

= 13V (PSM)

IN

V

= 16.5V

IN

V

= 13V (PSM)

IN

V

= 13V

IN

V

= 16.5V

IN

V

= 16.5V (PSM)

IN

V

= 16.5V (PSM)

IN

T

V

= 25°C

= 1.8V

= 300kHz

T

= 25°C

A

= 1.8V

= 600kHz

A

V

f

OUT

f

SW

WÜRTH INDUCTOR:

744325120, L = 1.2µH, DCR = 1.8mΩ

INFINEON FETs:

BSC042N03MS G (UPPER/LOWER)

WÜRTH INDUCTOR:

744325072, L = 0.72µH, DCR = 1.3mΩ

INFINEON FETs:

BSC042N03MS G (UPPER/LOWER)

0

10

0

10

100

1k

10k

100

1k

10k

LOAD CURRENT (mA)

Figure 5. Efficiency—300 kHz, V_OUT= 1.8 V

Figure 8. Efficiency—600 kHz, V_OUT= 1.8 V

100

95

90

85

80

75

70

65

60

55

50

45

40

35

30

25

20

15

10

5

100

95

90

85

80

75

70

65

60

55

50

45

40

35

30

25

20

15

10

5

V

= 16.5V (PSM)

V

= 13V (PSM)

IN

V

= 16.5V (PSM)

IN

V

= 13V (PSM)

IN

V

= 13V

IN

V

= 16.5V

IN

V

= 16.5V

IN

V

= 20V (PSM)

IN

V

= 20V

IN

T

V

= 25°C

= 7V

= 300kHz

T = 25°C

A

V

= 5V

= 600kHz

OUT

f

SW

WÜRTH INDUCTOR:

7443551200, L = 2.0µH, DCR = 2.6mΩ

INFINEON FETs:

BSC042N03MS G (UPPER/LOWER)

WÜRTH INDUCTOR:

744318180, L = 1.4µH, DCR = 3.2mΩ

INFINEON FETs:

BSC042N03MS G (UPPER/LOWER)

0

10

0

10

100

1k

LOAD CURRENT (mA)

10k

100

1k

10k

LOAD CURRENT (mA)

Figure 6. Efficiency—300 kHz, V_OUT= 7 V

Figure 9. Efficiency—600 kHz, V_OUT= 5 V

Rev. A | Page 7 of 40

ADP1878/ADP1879

Data Sheet

100

95

90

85

80

75

70

65

60

55

50

45

40

35

30

25

20

15

10

5

0.807

0.806

0.805

0.804

0.803

0.802

0.801

0.800

0.799

0.798

0.797

0.796

0.795

0.794

0.793

0.792

V

= 13V

IN

V

= 13V (PSM)

IN

V

= 16.5V

IN

T

V

= 25°C

A

= 0.8V

OUT

= 1.0MHz

V

= 16.5V (PSM)

IN

f

SW

WÜRTH INDUCTOR:

744303012, L = 0.12µH, DCR = 0.33mΩ

INFINEON FETs:

BSC042N03MS G (UPPER/LOWER)

V

= 13V

V

= 16.5V

IN

+125°C

+25°C

–40°C

+125°C

+25°C

–40°C

0

10

100

1k

10k

100k

0

2000

4000

6000

8000

10,000

LOAD CURRENT (mA)

Figure 10. Efficiency—1.0 MHz, V_OUT= 0.8 V

Figure 13. Output Voltage Accuracy—300 kHz, V_OUT= 0.8 V

1.821

100

95

90

85

80

75

70

65

60

55

50

45

40

35

30

25

20

15

10

5

V

= 13V

IN

1.816

1.811

1.806

1.801

1.796

1.791

1.786

V

= 13V (PSM)

IN

V

= 16.5V

IN

V

= 16.5V (PSM)

IN

T

V

f

= 25°C

A

= 1.8V

OUT

= 1.0MHz

SW

V

= 5.5V

V

= 13V

V

= 16.5V

IN

WÜRTH INDUCTOR:

744303022, L = 0.22µH, DCR = 0.33mΩ

INFINEON FETs:

BSC042N03MS G (UPPER/LOWER)

IN

+125°C

+25°C

–40°C

+125°C

+25°C

–40°C

+125°C

+25°C

–40°C

0

1500 3000 4500 6000 7500 9000 10,500 12,000 13,500 15,000

LOAD CURRENT (mA)

10

100

1k

10k

100k

LOAD CURRENT (mA)

Figure 14. Output Voltage Accuracy—300 kHz, V_OUT= 1.8 V

Figure 11. Efficiency—1.0 MHz, V_OUT= 1.8 V

7.100

100

95

90

85

80

75

70

65

60

55

50

45

40

35

30

25

20

15

10

5

7.095

7.090

7.085

7.080

7.075

7.070

7.065

7.060

7.055

7.050

7.045

7.040

7.035

7.030

7.025

7.020

7.015

7.010

7.005

7.000

V

= 13V (PSM)

IN

V

= 13V

IN

V

= 16.5V (PSM)

IN

V

= 16.5V

IN

T

V

= 25°C

= 5V

= 1.0MHz

A

OUT

f

SW

WÜRTH INDUCTOR:

744355090, L = 0.9µH, DCR = 1.6mΩ

INFINEON FETs:

BSC042N03MS G (UPPER/LOWER)

+125°C

+25°C

–40°C

V

= 13V

= 16.5V

IN

0

1000 2000 3000 4000 5000 6000 7000 8000 9000

LOAD CURRENT (mA)

10

100

1k

LOAD CURRENT (mA)

10k

100k

Figure 15. Output Voltage Accuracy—300 kHz, V_OUT= 7 V

Figure 12. Efficiency—1.0 MHz, V_OUT= 5 V

Rev. A | Page 8 of 40

Data 4heet

ADP1878/ADP1879

0.808

0.806

0.804

0.802

0.800

0.798

0.796

0.794

0.807

0.805

0.803

0.801

0.799

0.797

0.795

0.793

0.791

0.789

0.787

V

= 13V

+125°C

+25°C

–40°C

V

= 16.5V

+125°C

+25°C

–40°C

IN

+125°C

+25°C

–40°C

V

= 13V

= 16.5V

IN

0.792

0

1000 2000 3000 4000 5000 6000 7000 8000 9000 10,000

LOAD CURRENT (mA)

0

2000

4000

6000

8000

10,000

LOAD CURRENT (mA)

Figure 16. Output Voltage Accuracy—600 kHz, V_OUT= 0.8 V

Figure 19. Output Voltage Accuracy—1.0 MHz, V_OUT= 0.8 V

1.820

1.818

1.816

1.814

1.812

1.810

1.808

1.806

1.804

1.802

1.800

1.798

1.796

1.794

1.792

1.790

1.788

1.786

1.784

1.782

1.780

1.778

1.776

1.774

1.772

1.770

1.815

1.810

1.805

1.800

1.795

1.790

V

= 13V

V

= 16.5V

V

= 13V

+125°C

+25°C

–40°C

V

= 16.5V

IN

+125°C

+25°C

–40°C

+125°C

+25°C

–40°C

+125°C

+25°C

–40°C

00

1000 2000 3000 4000 5000 6000 7000 8000 9000 10,000

LOAD CURRENT (mA)

0

1500

3000

4500

6000

7500

9000 10,500 12,000

LOAD CURRENT (mA)

Figure 17. Output Voltage Accuracy—600 kHz, V_OUT= 1.8 V

Figure 20. Output Voltage Accuracy—1.0 MHz, V_OUT= 1.8 V

5.030

5.04

5.03

5.02

5.01

5.00

4.99

4.98

4.97

4.96

4.95

4.94

4.93

5.025

5.020

5.015

5.010

5.005

5.000

4.995

4.990

4.985

4.980

4.975

4.970

V

= 13V

V

= 16.5V

IN

4.92

4.91

4.90

+125°C

+25°C

–40°C

+125°C

+25°C

–40°C

+125°C

+25°C

–40°C

V

= 13V

= 16.5V

= 20V

IN

0

1000 2000 3000 4000 5000 6000 7000 8000 9000 10,000

LOAD CURRENT (mA)

0

800 1600 2400 3200 4000 4800 5600 6400 7200 8000 8800 9600

LOAD CURRENT (mA)

Figure 18. Output Voltage Accuracy—600 kHz, V_OUT= 5 V

Figure 21. Output Voltage Accuracy—1.0 MHz, V_OUT= 5 V

Rev. A | Page 9 of 40

ADP1878/ADP1879

Data 4heet

601.0

900

880

860

840

820

800

780

760

740

720

700

+125°C

+25°C

–40°C

600.5

V

= 5V, V = 20V

IN

REG

600.0

599.5

599.0

598.5

598.0

597.5

597.0

V

= 5V, V = 13V

IN

REG

–40.0

–7.5

25.0

57.5

90.0

122.5

13.0

13.5

14.0

14.5

15.0

(V)

15.5

16.0

16.5

V

TEMPERATURE (°C)

IN

Figure 22. Feedback Voltage vs. Temperature

Figure 25. Switching Frequency vs. High Input Voltage, 1.0 MHz,

V_INRange = 13 V to 16.5 V

280

325

315

305

295

285

275

265

255

V

= 13V

= 20V

= 16.5V

+125°C

+25°C

–40°C

+125°C

+25°C

–40°C

NO LOAD

IN

265

250

235

220

205

190

10.8 11.0 11.2 11.4 11.6 11.8 12.0 12.2 12.4 12.6 12.8 13.0 13.2

0

2000

4000

6000

8000

10,000

V

(V)

LOAD CURRENT (mA)

IN

Figure 26. Frequency vs. Load Current, 300 kHz, V_OUT= 0.8 V

Figure 23. Switching Frequency vs. High Input Voltage, 300 kHz, 10% of 12 V

330

320

310

300

290

280

270

260

250

240

650

V

= 20V

= 13V

= 16.5V

+125°C

+25°C

–40°C

+125°C

+25°C

–40°C

NO LOAD

IN

600

550

500

450

400

13.0 13.4 13.8 14.2 14.6 15.0 15.4 15.8 16.2

0

1500 3000 4500 6000 7500 9000 10,500 12,000 13,500 15,000

LOAD CURRENT (mA)

V

(V)

IN

Figure 27. Frequency vs. Load Current, 300 kHz, V_OUT= 1.8 V

Figure 24. Switching Frequency vs. High Input Voltage, 600 kHz, V_OUT= 1.8 V,

V_INRange = 13 V to 16.5 V

Rev. A | Page 10 of 40

Data 4heet

ADP1878/ADP1879

338

334

330

326

322

318

314

310

306

302

298

740

733

726

719

712

705

698

691

684

677

670

663

656

649

642

635

628

621

V

= 13V

= 16.5V

+125°C

+25°C

–40°C

V

= 13V

= 16.5V

+125°C

+25°C

–40°C

IN

0

800 1600 2400 3200 4000 4800 5600 6400 7200 8000 8800 9600

LOAD CURRENT (mA)

0

800 1600 2400 3200 4000 4800 5600 6400 7200 8000 8800

LOAD CURRENT (mA)

Figure 28. Frequency vs. Load Current, 300 kHz, V_OUT= 7 V

Figure 31. Frequency vs. Load Current, 600 kHz, V_OUT= 5 V

850

775

700

625

550

475

400

+125°C

+25°C

–40°C

540

510

480

450

420

390

360

330

300

V

= 13V

= 16.5V

IN

V

= 13V

= 16.5V

+125°C

+25°C

–40°C

IN

0

1200 2400 3600 4800 6000 7200 8400 9600 10,800 12,000

LOAD CURRENT (mA)

0

2000

4000

6000

8000

10,000

12,000

LOAD CURRENT (mA)

Figure 29. Frequency vs. Load Current, 600 kHz, V_OUT= 0.8 V

Figure 32. Frequency vs. Load Current, V_OUT= 1.0 MHz, 0.8 V

1225

1150

1075

1000

925

675

V

= 13V

= 16.5V

+125°C

+25°C

–40°C

IN

V

= 13V

= 16.5V

IN

655

635

615

595

575

555

535

515

495

850

775

700

+125°C

+25°C

–40°C

625

550

0

1200 2400 3600 4800 6000 7200 8400 9600 10,800 12,000

LOAD CURRENT (mA)

0

1000 2000 3000 4000 5000 6000 7000 8000 9000 10,000

LOAD CURRENT (mA)

Figure 30. Frequency vs. Load Current, 600 kHz, V_OUT= 1.8 V

Figure 33. Frequency vs. Load Current, 1.0 MHz, V_OUT= 1.8 V

Rev. A | Page 11 of 40

ADP1878/ADP1879

Data 4heet

1450

82

80

78

76

74

72

70

68

66

64

62

+125°C

+25°C

–40°C

V

= 13V

= 16.5V

+125°C

+25°C

–40°C

IN

1400

1350

1300

1250

1200

1150

1100

1050

1000

5.5

6.7

7.9

9.1

10.3 11.5 12.7 13.9 15.1 16.3

(V)

0

800 1600 2400 3200 4000 4800 5600 6400 7200 8000

LOAD CURRENT (mA)

V

IN

Figure 34. Frequency vs. Load Current, 1.0 MHz, V_OUT= 5 V

Figure 37. Maximum Duty Cycle vs. High Voltage Input (V_IN)

680

2.658

V

= 2.7V

= 3.6V

= 5.5V

REG

630

580

530

480

430

380

330

280

230

180

2.657

2.656

2.655

2.654

2.653

2.652

2.651

2.650

2.649

–40

–20

0

20

40

60

80

100

120

–40

–20

0

20

40

60

80

100

120

TEMPERATURE (°C)

Figure 35. UVLO vs. Temperature

Figure 38. Minimum Off Time vs. Temperature

680

95

90

85

80

75

70

65

60

55

+125°C

+25°C

–40°C

+125°C

+25°C

–40°C

630

580

530

480

430

380

330

280

230

180

300

400

500

600

700

800

900

1000

2.7

3.1

3.5

3.9

V

4.3

(V)

4.7

5.1

5.5

FREQUENCY (kHz)

REG

Figure 36. Maximum Duty Cycle vs. Frequency

Figure 39. Minimum Off Time vs. V_REG(Low Input Voltage)

Rev. A | Page 12 of 40

Data 4heet

ADP1878/ADP1879

800

80

72

64

56

48

40

32

24

16

8

V

= 2.7V

= 3.6V

= 5.5V

+125°C

+25°C

–40°C

300kHz

1MHz

+125°C

+25°C

–40°C

REG

720

640

560

480

400

320

240

160

80

2.7

3.1

3.5

3.9

V

4.3

(V)

4.7

5.1

5.5

300

400

500

600

700

800

900

1000

FREQUENCY (kHz)

REG

Figure 40. Internal Rectifier Drop vs. Frequency

Figure 43. Low-Side MOSFET Body Diode Conduction Time vs. V_REG

1280

1200

1120

1040

960

880

800

720

640

560

480

400

320

240

160

80

V

= 5.5V

= 13V

= 16.5V

1MHz

T

= 25°C

IN

A

300kHz

OUTPUT VOLTAGE

1

INDUCTOR CURRENT

2

SW NODE

3

LOW SIDE

4

B

CH1 50mV

CH3 10V

CH2 5A Ω M400ns

35.8%

A

CH2

3.90A

W

2.7

3.1

3.5

3.9

V

4.3

4.7

5.1

5.5

B

T

CH4 5V

W

(V)

REG

Figure 44. Power Saving Mode (PSM) Operational Waveform, 100 mA

Figure 41. Internal Boost Rectifier Drop vs. VREG (Low Input Voltage)

Over V_INVariation

720

300kHz

1MHz

+125°C

+25°C

–40°C

OUTPUT VOLTAGE

640

560

480

400

320

240

160

80

1

INDUCTOR CURRENT

2

SW NODE

3

LOW SIDE

4

B

CH1 50mV

CH3 10V

CH2 5A Ω M4.0µs

35.8%

A

CH2

3.90A

W

2.7

3.1

3.5

3.9

V

4.3

4.7

5.1

5.5

B

T

CH4 5V

W

(V)

REG

Figure 42. Internal Boost Rectifier Drop vs. V_REG

Figure 45. PSM Waveform at Light Load, 500 mA

Rev. A | Page 13 of 40

ADP1878/ADP1879

Data Sheet

OUTPUT VOLTAGE

2

4

OUTPUT VOLTAGE

INDUCTOR CURRENT

12A NEGATIVE STEP

SW NODE

1

3

1

3

SW NODE

LOW SIDE

4

B

CH1 5A

CH3 10V

Ω

M400ns

30.6%

A

CH3

2.20V

CH1 10A Ω CH2 200mV

CH3 20V CH4 5V

M20µs

T 48.2%

A

CH1

3.40A

W

B

T

CH4 100mV

W

Figure 46. CCM Operation at Heavy Load, 12 A

(See Figure 95 for Application Circuit)

Figure 49. Negative Step During Heavy Load Transient Behavior—PSM Enabled,

12 A (See Figure 95 Application Circuit)

OUTPUT VOLTAGE

2

4

OUTPUT VOLTAGE

12A STEP

1

2

LOW SIDE

1

3

SW NODE

LOW SIDE

4

3

B

CH1 10A

CH3 20V

Ω

CH2 5V

CH4 200mV

M2ms

15.6%

A

CH1

6.20A

CH1 10A

CH3 20V

Ω

CH2 200mV

CH4 5V

M2ms

A

CH1

3.40A

W

B

T

75.6%

W

Figure 47. Load Transient Step—PSM Enabled, 12 A

(See Figure 95 Application Circuit)

Figure 50. Load Transient Step—Forced PWM at Light Load, 12 A

(See Figure 95 Application Circuit)

OUTPUT VOLTAGE

4

2

12A POSITIVE STEP

SW NODE

1

2

3

LOW SIDE

1

3

SW NODE

LOW SIDE

4

B

CH1 10A Ω CH2 200mV

CH3 20V CH4 5V

M20µs

A

CH1

3.40A

CH1 10A Ω CH2 5V

M20µs

43.8%

A

CH1

6.20A

W

B

T

30.6%

T

W

CH3 20V

CH4 200mV

Figure 48. Positive Step During Heavy Load Transient Behavior—PSM Enabled,

12 A, V_OUT= 1.8 V (See Figure 95 Application Circuit)

Figure 51. Positive Step During Heavy Load Transient Behavior—Forced PWM

at Light Load, 12 A, V_OUT= 1.8 V (See Figure 95 Application Circuit)

Rev. A | Page 14 of 40

Data Sheet

ADP1878/ADP1879

OUTPUT VOLTAGE

2

1

INDUCTOR CURRENT

12A NEGATIVE STEP

2

4

1

SW NODE

LOW SIDE

3

SW NODE

B

LOW

SIDE

3

4

B

CH1 10A Ω CH2 200mV

M10µs

A

CH1

5.60A

CH1 2V

CH2 5A

CH4 5V

Ω

M2ms

32.8%

A

CH1

720mV

W

T

23.8%

T

CH3 20V

CH4 5V

CH3 10V

Figure 52. Negative Step During Heavy Load Transient Behavior—Forced PWM

at Light Load, 12 A (See Figure 95 Application Circuit)

Figure 55. Start-Up Behavior at Heavy Load, 12 A, 300 kHz

(See Figure 95 Application Circuit)

OUTPUT VOLTAGE

1

INDUCTOR CURRENT

2

INDUCTOR CURRENT

LOW SIDE

2

4

SW NODE

3

B

CH1 2V

CH3 10V

CH2 5A

CH4 5V

Ω

M4ms

49.4%

A

CH1

920mV

CH1 2V

CH3 10V

CH2 5A

CH4 5V

Ω

M4ms

41.6%

A

CH1

720mV

W

T

Figure 53. Output Short-Circuit Behavior Leading to Hiccup Mode

Figure 56. Power-Down Waveform During Heavy Load

1

OUTPUT VOLTAGE

1

2

INDUCTOR CURRENT

2

SW NODE

3

4

LOW SIDE

4

B

CH1 5V

CH3 10V

CH2 10A

CH4 5V

Ω

M10µs

36.2%

A

CH2

8.20A

CH1 50mV

CH2 5A

CH4 5V

Ω

M2µs

35.8%

A

CH2

3.90A

W

B

T

CH3 10V

W

Figure 54. Magnified Waveform During Hiccup Mode

Figure 57. Output Voltage Ripple Waveform During PSM Operation

at Light Load, 2 A

Rev. A | Page 15 of 40

ADP1878/ADP1879

Data Sheet

V

= 5.5V

= 3.6V

= 2.7V

REG

T

= 25°C

A

LOW SIDE

570

550

530

510

490

470

450

430

4

HIGH SIDE

SW NODE

3

2

M

HS MINUS

SW

CH2 5V

CH4 2V

M40ns

29.0%

A

CH2

4.20V

–40

–20

0

20

40

60

80

100

120

T

CH3 5V

MATH 2V 40ns

TEMPERATURE (°C)

Figure 61. Transconductance vs. Temperature

Figure 58. Output Drivers and SW Node Waveforms

680

630

580

530

480

430

380

330

T

= 25°C

+125°C

+25°C

–40°C

A

LOW SIDE

16ns (t _,DRVL)

f

4

22ns (

t

)

pdhDRVH

HIGH SIDE

25ns (

t

)

,DRVH

r

SW NODE

3

2

HS MINUS

SW

M

CH2 5V

CH4 2V

M40ns

29.0%

A

CH2

4.20V

2.7

3.0

3.3

3.6

3.9

V

4.2

(V)

4.5

4.8

5.1

5.4

T

CH3 5V

MATH 2V 40ns

REG

Figure 62. Transconductance vs. V_REG

Figure 59. High-Side Driver Rising and Low-Side Falling Edge Waveforms (C_IN=

4.3 nF (High-/Low-Side MOSFET), Q_TOTAL= 27 nC (V_GS= 4.4 V (Q1), V_GS= 5 V (Q3))

1.30

18ns (

t

)

,DRVL

LOW SIDE

r

1.25

1.20

1.15

1.10

1.05

1.00

0.95

0.90

0.85

0.80

0.75

0.70

+125°C

+25°C

–40°C

4

HIGH SIDE

24ns (

t

)

pdh,DRVL

HS MINUS

SW

11ns (t _,DRVH

f

)

SW NODE

3

2

M

T

= 25°C

A

CH2 5V

CH4 2V

M20ns

A

CH2

4.20V

2.7

3.1

3.5

3.9

V

4.3

(V)

4.7

5.1

5.5

T

39.2%

CH3 5V

MATH 2V 20ns

REG

Figure 63. Quiescent Current vs. V_REG

Figure 60. High-Side Driver Falling and Low-Side Rising Edge Waveforms (C_IN=

4.3 nF (High-/Low-Side MOSFET), Q_TOTAL= 27 nC (V_GS= 4.4 V (Q1), V_GS= 5 V (Q3))

Rev. A | Page 16 of 40

Data Sheet

ADP1878/ADP1879

THEORY OF OPERATION

BLOCK DIAGRAM

PGOOD

690mV

FB

600mV

ADP1878/ADP1879

530mV

VREG

t_ONTIMER

VIN

PRECISION

ENABLE

C

EN

TO ENABLE

ALL BLOCKS

THRESHOLD/

HYSTERESIS

I

630mV

SW

INFORMATION

LDO

VREG

R (TRIMMED)

t_ON= 2RC(V

/V

)

OUT IN

REF

SW FILTER

VREG

BST

BIAS BLOCK

AND REFERENCE

STATE

MACHINE

REF_ZERO

TON

I

SS

DRVH

BG_REF

SS

COMP

SS

PSM

300kΩ

IN_PSM

HS_0

LEVEL

HS

IN_SS

HS

SW

SHIFT

IN_HICCUP

SS_REF

SW

LS

COMP

FB

COMP

PWM

8kΩ

VREG

LS_0

IREV

LS

DRVL

ERROR

AMP

800kΩ

PGND

PWM

0.6V

IREV

COMP

CS

AMP

LOWER

COMP

CLAMP

RES DETECT AND

GAIN SET

REF_ZERO

ADC

CS GAIN SET

0.4V

GND

RES

Figure 64. ADP1878/ADP1879 Block Diagram

The ADP1878/ADP1879 are versatile current-mode, synchronous

step-down controllers that provide superior transient response,

optimal stability, and current-limit protection by using a constant

on time, pseudo fixed frequency with a programmable current

sense gain, current control scheme. In addition, these devices offer

optimum performance at low duty cycles by using a valley, current-

mode control architecture. This allows the ADP1878/ADP1879

to drive all N-channel power stages to regulate output voltages

to as low as 0.6 V.

Rev. A | Page 17 of 40

ADP1878/ADP1879

Data Sheet

STARTUP

PRECISION ENABLE CIRCUITRY

Each ADP1878/ADP1879 has an internal regulator (VREG)

for biasing and supplying power for the integrated N-channel

MOSFET drivers. Place a bypass capacitor directly across the

VREG (Pin 7) and PGND (Pin 13) pins. Included in the power-

up sequence is the biasing of the current sense amplifier, the

current sense gain circuit (see the Programming Resistor (RES)

Detect Circuit section), the soft start circuit, and the error

amplifier.

The ADP1878/ADP1879 have precision enable circuitry. The

precision enable threshold is 630 mV including 30 mV of

hysteresis (see Figure 66). Connecting the EN pin to GND

disables the ADP1878/ADP1879, reducing the supply current

of the device to approximately 140 μA.

V

REG

10kΩ

PRECISION

ENABLE COMP.

EN

The current sense blocks provide valley current information

(see the Programming Resistor (RES) Detect Circuit section)

and they are a variable of the compensation equation for loop

stability (see the Compensation Network section). In a process

performed by the RES detect circuit, the valley current informa-

tion is extracted by forcing 0.4 V across the RES and PGND pins

generating current. The current through the RES resistor is used

to set the current sense amplifier gain (see the Programming

Resistor (RES) Detect Circuit section). This process takes approx-

imately 800 μs, after which time the drive signal pulses appear at

the DRVL and DRVH pins synchronously, and the output voltage

begins to rise in a controlled manner through the soft start

sequence.

TO ENABLE

ALL BLOCKS

630mV

Figure 66. Connecting EN Pin to VREG via a Pull-Up Resistor to Enable the

ADP1878/ADP1879

UNDERVOLTAGE LOCKOUT

The undervoltage lockout (UVLO) feature prevents the device

from operating both the high- and low-side N-channel MOSFETs

at extremely low or undefined input voltage (V_IN) ranges.

Operation at an undefined bias voltage can result in the

incorrect propagation of signals to the high-side power switches.

This, in turn, results in invalid output behavior that can cause

damage to the output devices, ultimately destroying the device

tied at the output. The UVLO level is set at 2.65 V (nominal).

The soft start and error amplifier blocks determine the rise time

of the output voltage (see the Soft Start section). At the beginning

of a soft start, the error amplifier charges the external compensa-

tion capacitor, causing the COMP pin to rise (see Figure 65).

Tying the VREG pin to the EN pin via a pull-up resistor causes

the voltage at the EN pin to rise above the enable threshold of

630 mV, thereby enabling the ADP1878/ADP1879.

COMP

ON-BOARD LOW DROPOUT (LDO) REGULATOR

The ADP1878/ADP1879 use an on-board LDO to bias the

internal digital and analog circuitry. With proper bypass

capacitors connected to the VREG pin (output of the internal

LDO), this pin also provides power for the internal MOSFET

drivers. It is recommended to float VREG if VIN is used for

greater than 5.5 V operation. The minimum voltage at which

bias is guaranteed to operate is 2.75 V at VREG (see Figure 67).

ON-BOARD REGULATOR

>2.4V

2.4V

HICCUP MODE INITIALIZED

MAXIMUM CURRENT (UPPER CLAMP)

VREG

VIN

1.0V

ZERO CURRENT

USABLE RANGE ONLY AFTER SOFT START

PERIOD IF CONTINUOUS CONDUCTION

MODE OF OPERATION IS SELECTED.

REF

500mV

LOWER CLAMP

Figure 67. On-Board Regulator

For applications where VIN is decoupled from VREG, the

minimum voltage at VIN must be 2.9 V. It is recommended to tie

VIN and VREG together if the VIN pin is subjected to a 2.75 V rail.

0V

Figure 65. COMP Voltage Range

SOFT START

The ADP1878 employs externally programmable, soft start

circuitry that charges up a capacitor tied to the SS pin to GND.

This prevents input inrush current through the external MOSFET

from the input supply (V_IN). The output tracks the ramping voltage

by producing PWM output pulses to the high-side MOSFET. The

purpose is to limit the inrush current from the high voltage

input supply (V_IN) to the output (V_OUT).

Rev. A | Page 18 of 40

Data Sheet

ADP1878/ADP1879

Table 5. Power Input and LDO Output Configurations

SW

CS

VIN

VREG

Comments

AMP

PGND

>5.5 V

<5.5 V

Float

Must use the LDO

ADC

Connect to VIN

LDO drop voltage is not

realized (that is, if VIN = 2.75 V,

then VREG = 2.75 V)

CS GAIN

SET

0.4V

<5.5 V

Float

LDO drop is realized

VIN ranging Float

above and

below 5.5 V

LDO drop is realized, minimum

VIN recommendation is 2.95 V

RES

Figure 69. RES Detect Circuit for Current Sense Gain Programming

THERMAL SHUTDOWN

Table 6. Current Sense Gain Programming

Thermal shutdown is a protection feature that prevents the IC

from damage caused by a very high operating junction temper-

ature. If the junction temperature of the device exceeds 155°C,

the device enters the thermal shutdown state. In this state, the

device shuts off both the high- and low-side MOSFETs and disables

the entire controller immediately, thus reducing the power con-

sumption of the IC. The device resumes operation after the

junction temperature of the device cools to less than 140°C.

Resistor

A_CS

47 kΩ

22 kΩ

Open

100 kΩ

3 V/V

6 V/V

12 V/V

24 V/V

VALLEY CURRENT-LIMIT SETTING

The architecture of the ADP1878/ADP1879 is based on valley

current-mode control. The current limit is determined by three

components: the R_ONof the low-side MOSFET, the output voltage

swing of the current sense amplifier, and the current sense gain.

The output range of the current sense amplifier is internally

fixed at 1.4 V. The current sense gain is programmable via an

external resistor at the RES pin (see the Programming Resistor

(RES) Detect Circuit section). The R_ONof the low-side MOSFET

can vary over temperature and usually has a positive T_C(meaning

that it increases with temperature); therefore, it is recommended to

program the current sense, gain resistor based on the rated R_ONof

the MOSFET at 125°C.

PROGRAMMING RESISTOR (RES) DETECT CIRCUIT

Upon startup, one of the first blocks to become active is the RES

detect circuit. This block powers up before soft start begins. It

forces a 0.4 V reference value at the RES pin (see Figure 68) and is

programmed to identify four possible resistor values: 47 kΩ, 22 kΩ,

open, and 100 kΩ.

The RES detect circuit digitizes the value of the resistor at the

RES pin (Pin 6). An internal ADC outputs a 2-bit digital code

that is used to program four separate gain configurations in the

current sense amplifier (see Figure 69). Each configuration corre-

sponds to a current sense gain (A_CS) of 3 V/V, 6 V/V, 12 V/V, or

24 V/V, respectively (see Table 6 and Table 7). This variable is used

for the valley current-limit setting, which sets up the appropriate

current sense gain for a given application and sets the compensation

necessary to achieve loop stability (see the Valley Current-Limit

Setting section and the Compensation Network section).

Because the ADP1878/ADP1879 are based on valley current

control, the relationship between I_CLIMand I_LOADis

ꢌ

ꢀ_ꢁꢂꢃꢄꢅ ꢀ_ꢂꢆꢇꢈꢉ ꢊ1 ꢋ ^ꢃꢍ

2

where:

K_Iis the ratio between the inductor ripple current and the

desired average load current (see Figure 70).

Q1

DRVH

I

_CLIMis the desired valley current limit.

_LOADis the current load.

SW

Q2

DRVL

Establishing K_Ihelps to determine the inductor value (see the

Inductor Selection section), but in most cases, K_I= 0.33.

RES

CS GAIN

PROGRAMMING

Figure 68. Programming Resistor Location

I

LOAD

3

RIPPLE CURRENT =

LOAD CURRENT

VALLEY CURRENT LIMIT

Figure 70. Valley Current Limit to Average Current Relation

Rev. A | Page 19 of 40

ADP1878/ADP1879

Data Sheet

When the desired valley current limit (I_CLIM) has been determined,

the current sense gain can be calculated as follows:

The valley current limit is programmed as listed in Table 7 and

shown in Figure 71. The inductor that is chosen must be rated

to handle the peak current, which is equal to the valley current

from Table 7 plus the peak-to-peak inductor ripple current (see

the Inductor Selection section). In addition, the peak current

value must be used to compute the worst-case power dissipation

in the MOSFETs (see Figure 72).

1.4ꢆV

ꢇ_ꢁꢈꢉ ꢊ_ꢋꢌ

ꢀ_ꢁꢂꢃꢄ

ꢅ

where:

_ONis the channel impedance of the low-side MOSFET.

R

A_CSis the current sense gain multiplier (see Table 6 and Table 7).

49A

Although the ADP1878/ADP1879 have only four discrete current

sense gain settings for a given R_ONvariable, Table 7 and Figure 71

outline several available options for the valley current setpoint

based on various R_ONvalues.

MAXIMUM DC LOAD

CURRENT

39.5A

SENSE

∆I = 65%

OF 37A

INDUCTOR

CURRENT

AMPLIFIER

OUTPUT

37A

35A

∆I = 45%

OF 32.25A

Table 7. Valley Current Limit Program (See Figure 71)

32.25A

∆I = 33%

OF 30A

Valley Current Level (A)¹

30A

47 kΩ,

(mΩ) A_CS= 3 V/V

22 kΩ,

A_CS= 6 V/V

Open,

A_CS= 12 V/V

100 kΩ,

A_CS= 24 V/V

38.9

29.2

23.3

19.5

16.7

13

11.7

10.6

5.83

7.5

3.25

R_ON

2.4V

VALLEY CURRENT-LIMIT

THRESHOLD (SET FOR 25A)

1.5

2

2.5

3

3.5

4.5

5

5.5

10

CS AMP

OUTPUT

SWING

39.0

33.4

26.0

23.4

21.25

11.7

7.75

6.5

0A

1V

Figure 72. Valley Current-Limit Threshold in Relation to Inductor Ripple Current

23.3

15.5

13.0

15

18

31.0

26.0

¹Blank cells are not applicable.

39

37

35

33

31

29

27

25

23

21

19

17

15

13

11

RES = 47kΩ

= 3V/V

A

CS

RES = 22kΩ

= 6V/V

A

RES = NO RES

= 12V/V

CS

A

CS

RES = 100kΩ

9

7

5

3

A

= 24V/V

CS

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20

(mΩ)

R

ON

Figure 71. Valley Current-Limit Value vs. R_ONof the Low-Side MOSFET

for Each Programming Resistor (RES)

Rev. A | Page 20 of 40

Data Sheet

ADP1878/ADP1879

REPEATED CURRENT-LIMIT

VIOLATION DETECTED

HS

A PREDETERMINED NUMBER SOFT START IS

OF PULSES IS COUNTED TO REINITIALIZED TO

ALLOW THE CONVERTER MONITOR IF THE

CLIM

TO COOL DOWN

VIOLATION

STILL EXISTS

ZERO

CURRENT

Figure 73. Idle Mode Entry Sequence Due to Current-Limit Violation

HICCUP MODE DURING SHORT CIRCUIT

HS

t_ON

A current-limit violation occurs when the current across the

source and drain of the low-side MOSFET exceeds the current-

limit setpoint. When 32 current-limit violations are detected,

the controller enters idle mode and turns off the MOSFETs for

6 ms, allowing the converter to cool down. Then, the controller

reestablishes soft start and begins to cause the output to ramp

up again (see Figure 73). While the output ramps up, the current

sense amplifier output is monitored to determine if the violation is

still present. If it is still present, the idle event occurs again, followed

by the full chip, power-down sequence. This cycle continues

until the violation no longer exists. If the violation disappears,

the converter is allowed to switch normally, maintaining

regulation.

HS AND LS ARE OFF

OR IN IDLE MODE

LS

t_OFF

AS THE INDUCTOR

CURRENT APPROACHES

ZERO CURRENT, THE STATE

MACHINE TURNS OFF THE

LOWER-SIDE MOSFET.

I

LOAD

0A

Figure 74. Discontinuous Mode of Operation (DCM)

SYNCHRONOUS RECTIFIER

To minimize the chance of negative inductor current buildup,

an on-board zero-cross comparator turns off all high- and low-

side switching activities when the inductor current approaches

the zero current line, causing the system to enter idle mode,

where the high- and low-side MOSFETs are turned off. To ensure

idle mode entry, a 10 mV offset, connected in series at the SW

node, is implemented (see Figure 75).

The ADP1878/ADP1879 employ internal MOSFET drivers for

the external high- and low-side MOSFETs. The low-side

synchronous rectifier not only improves overall conduction

efficiency, but it also ensures proper charging of the bootstrap

capacitor located at the high-side driver input. This is beneficial

during startup to provide sufficient drive signal to the external

high-side MOSFET and to attain fast turn-on response, which is

essential for minimizing switching losses. The integrated high-

and low-side MOSFET drivers operate in complementary

fashion with built-in anti cross conduction circuitry to prevent

unwanted shoot through current that may potentially damage the

MOSFETs or reduce efficiency because of excessive power loss.

ZERO-CROSS

COMPARATOR

SW

10mV

I

Q2

LS

ADP1879 POWER SAVING MODE (PSM)

Figure 75. Zero-Cross Comparator with 10 mV of Offset

A power saving mode is provided in the ADP1879. The ADP1879

operates in the discontinuous conduction mode (DCM) and

pulse skips at light to medium load currents. The controller outputs

pulses as necessary to maintain output regulation. Unlike the

continuous conduction mode (CCM), DCM operation prevents

negative current, thus allowing improved system efficiency at

light loads. Current in the reverse direction through this pathway,

however, results in power dissipation and, therefore, a decrease in

efficiency.

As soon as the forward current through the low-side MOSFET

decreases to a level where

10 mV = I_Q2× R_ON(Q2)

the zero-cross comparator (or I_REVcomparator) emits a signal to

turn off the low-side MOSFET. From this point, the slope of the

inductor current ramping down becomes steeper (see Figure 76)

as the body diode of the low-side MOSFET begins to conduct

current and continues conducting current until the remaining

energy stored in the inductor has been depleted.

Rev. A | Page 21 of 40

ADP1878/ADP1879

Data Sheet

ANOTHER t_ONEDGE IS

TRIGGERED WHEN V

FALLS BELOW REGULATION

The t_ONtimer uses a feedforward technique that, when applied

to the constant on-time control loop, makes it a pseudo fixed

frequency to a first-order approximation.

OUT

SW

t_ON

Second-order effects, such as dc losses in the external power

MOSFETs (see the Efficiency Consideration section), cause some

variation in frequency vs. load current and line voltage. These

effects are shown in Figure 23 to Figure 34. The variations in

frequency are much reduced compared with the variations

generated if the feedforward technique is not used.

HS AND LS

IN IDLE MODE

LS

The feedforward technique establishes the following relationship:

ZERO-CROSS COMPARATOR

DETECTS 10mV OFFSET AND

TURNS OFF LS

I

LOAD

0A

1

ꢊ

ꢋꢌ

ꢃ

ꢄ

where f_SWis the controller switching frequency (300 kHz,

600 kHz, and 1.0 MHz).

10mV = R

× I

LOAD

ON

Figure 76. 10 mV Offset to Ensure Prevention of Negative Inductor Current

The system remains in idle mode until the output voltage drops

below regulation. Next, a PWM pulse is produced, turning on the

high-side MOSFET to maintain system regulation. The ADP1879

does not have an internal clock; it switches purely as a hysteretic

controller, as described in this section.

The t_ONtimer senses V_INand V_OUTto minimize frequency

variation as previously explained. This provides pseudo fixed

frequency as explained in the Pseudo Fixed Frequency section.

To allow headroom for V_INand V_OUTsensing, adhere to the

following equations:

V

_REG≥ V_IN/8 + 1.5

_REG≥ V_OUT/4

TIMER OPERATION

The ADP1878/ADP1879 employ a constant on-time architecture,

which provides a variety of benefits, including improved load

and line transient response when compared with a constant

(fixed) frequency current-mode control loop of comparable

loop design. The constant on-time timer, or t_ONtimer, senses

For typical applications where V_REGis 5 V, these equations are

not relevant; however, for lower V_REGinputs, care may be required.

PSEUDO FIXED FREQUENCY

The ADP1878/ADP1879 employ a constant on-time control

scheme. During steady state operation, the switching frequency

stays relatively constant, or pseudo fixed. This is due to the one

shot t_ONtimer that produces a high-side PWM pulse with a

fixed duration, given that external conditions such as input

voltage, output voltage, and load current are also at steady state.

During load transients, the frequency momentarily changes for

the duration of the transient event so that the output comes

back within regulation quicker than if the frequency were fixed,

or if it were to remain unchanged. After the transient event is

complete, the frequency returns to a pseudo fixed value.

the high-side input voltage (V_IN) and the output voltage (V_OUT

)

using SW waveform information to produce an adjustable one

shot PWM pulse. The pulse varies the on-time of the high-side

MOSFET in response to dynamic changes in input voltage, output

voltage, and load current conditions to maintain output regula-

tion. The timer generates an on-time (t_ON) pulse that is inversely

proportional to V_IN.

ꢆ_ꢁꢇꢈ

ꢀ_ꢁꢂꢃ ꢄ ꢅ

ꢆ

ꢉꢂ

where K is a constant that is trimmed using an RC timer product

for the 300 kHz, 600 kHz, and 1.0 MHz frequency options.

To illustrate this feature more clearly, this section describes one

such load transient event—a positive load step—in detail. During

load transient events, the high-side driver output pulse width

stays relatively consistent from cycle to cycle; however, the off

time (DRVL on time) dynamically adjusts according to the

instantaneous changes in the external conditions mentioned.

V

IN

VREG

t_ON

C

I

SW

INFORMATION

When a positive load step occurs, the error amplifier (out of phase

with the output, V_OUT) produces new voltage information at its

output (COMP). In addition, the current sense amplifier senses

new inductor current information during this positive load

transient event. The output voltage reaction of the error amplifier is

compared with the new inductor current information that sets

the start of the next switching cycle. Because current information

is produced from valley current sensing, it is sensed at the down

ramp of the inductor current, whereas the voltage loop information

R (TRIMMED)

Figure 77. Constant On-Time Time

The constant on-time (t_ON) is not strictly constant because it

varies with V_INand V_OUT. However, this variation occurs in such

a way as to keep the switching frequency virtually independent

of V_INand V_OUT

.

Rev. A | Page 22 of 40

Data Sheet

ADP1878/ADP1879

is sensed through the counter action upswing of the output

(COMP) of the error amplifier.

the internal switch is turned on, PGOOD is internally pulled low

when the output voltage via the FB pin is outside this regulation

window.

The result is a convergence of these two signals (see Figure 78),

which allows an instantaneous increase in switching frequency

during the positive load transient event. In summary, a positive

load step causes V_OUTto transient down, which causes COMP to

transient up and, therefore, shortens the off time. This resulting

increase in frequency during a positive load transient helps to

quickly bring V_OUTback up in value and within the regulation

window.

The power-good window is defined with a typical upper speci-

fication of +90 mV and a lower specification of −70 mV below

the FB voltage of 600 mV. When an overvoltage event occurs at the

output, there is a typical propagation delay of 12 μs prior to the

deassertion (logic low) of the PGOOD pin. When the output

voltage reenters the regulation window, there is a propagation

delay of 12 μs prior to PGOOD reasserting back to a logic high

state. When the output is outside the regulation window, the

PGOOD open-drain switch is capable of sinking 1 mA of

current and providing 140 mV of drop across this switch. The

user is free to tie the external pull-up resistor (R_RES) to any

voltage rail up to 20 V. The following equation provides the

proper external pull-up resistor value:

Similarly, a negative load step causes the off time to lengthen in

response to V_OUTrising. This effectively increases the inductor

demagnetizing phase, helping to bring V_OUTwithin regulation.

In this case, the switching frequency decreases, or experiences a

foldback, to help facilitate output voltage recovery.

Because the ADP1878/ADP1879 have the ability to respond rapidly

to sudden changes in load demand, the recovery period in which

the output voltage settles back to its original steady state operating

point is much quicker than it would be for a fixed frequency

equivalent. Therefore, using a pseudo fixed frequency results in

significantly better load transient performance compared to

using a fixed frequency.

ꢅ_ꢆꢇꢈꢉ 140ꢊmV

ꢀ_ꢁꢂꢃ

where:

R

V

ꢄ

1ꢊmA

_PGDis the PGOOD external resistor.

_EXTis a user chosen voltage rail.

V

EXT

R

1mA

PGOOD

PGD

+

690mV

140mV

–

LOAD CURRENT

DEMAND

FB

600mV

CS AMP

OUTPUT

530mV

ERROR AMP

OUTPUT

VALLEY

TRIP POINTS

Figure 79. Power Good, Output Voltage Monitoring Circuit

OUTPUT OVERVOLTAGE

PGOOD DEASSERT

PWM OUTPUT

f_SW

>f_SW

690mV

PGOOD

HYSTERESIS (50mV)

REASSERT

640mV

FB

600mV

Figure 78. Load Transient Response Operation

530mV

PGOOD

ASSERTION

AT POWER-UP

PGOOD

DEASSERTION

AT POWER-DOWN

POWER-GOOD MONITORING

0V

SOFT START

The ADP1878/ADP1879 power-good circuitry monitors the

output voltage via the FB pin. The PGOOD pin is an open-

drain output that can be pulled up by an external resistor to a

voltage rail that does not necessarily have to be VREG. When

the internal NMOS switch is in high impedance (off state), this

means that the PGOOD pin is logic high and the output voltage

via the FB pin is within the specified regulation window. When

V

EXT

t_PGD

PGOOD

t_PGD

0V

Figure 80. Power-Good Timing Diagram, t_PGD= 12 μs (Diagram May Look

Disproportionate For Illustration Purposes)

Rev. A | Page 23 of 40

ADP1878/ADP1879

Data Sheet

APPLICATIONS INFORMATION

FEEDBACK RESISTOR DIVIDER

Table 8. Recommended Inductors

L

DCR

I_SAT

Dimensions

(mm)

Model

Number

The required resistor divider network can be determined for a

given V_OUTvalue because the internal band gap reference (V_REF

is fixed at 0.6 V. Selecting values for R_Tand R_Bdetermine the

minimum output load current of the converter. Therefore, for a

given value of R_B, the R_Tvalue can be determined through the

following expression:

(μH) (mΩ) (A)

Manufacturer

)

0.12

0.22

0.47

0.72

0.9

0.33

0.8

55

30

50

35

32

25

16

24

23

27.5

10.2 × 7

Würth Elek.

Sumida

744303012

744303022

744355147

744325072

744318120

744325120

7443552100

744318180

7443551200

CEP125U-0R8

10.2 × 7

14.2 × 12.8

10.5 × 10.2

14 × 12.8

10.5 × 10.2

10.2 × 10.2

14 × 12.8

10.2 × 10.2

1.65

1.6

1.2

1.8

ꢅ

ꢆ

ꢋ

_ꢇꢈꢁꢉ 0.6ꢊV

ꢀ_ꢁꢂ ꢀ_ꢃꢄ

1.0

3.8

0.6 V

1.4

3.2

INDUCTOR SELECTION

2.0

2.6

0.8

The inductor value is inversely proportional to the inductor

ripple current. The peak-to-peak ripple current is given by

OUTPUT RIPPLE VOLTAGE (ΔV_RR)

ꢌ_ꢍꢇꢐꢑ

∆ꢌ_ꢍꢂ ꢎ_ꢏꢄ ꢌ_ꢍꢇꢐꢑ

where K_Iis typically 0.33.

The equation for the inductor value is given by

ꢒ

The output ripple voltage is the ac component of the dc output

voltage during steady state. For a ripple error of 1.0%, the output

capacitor value needed to achieve this tolerance can be determined

using the following equation. (Note that an accuracy of 1.0% is

possible during steady state conditions only, not during load

transients.)

3

ꢅ

ꢋ

ꢆ

_ꢏꢔꢉ ꢆ_ꢇꢈꢁ

ꢆ_ꢇꢈꢁ

ꢓ ꢂ

ꢄ

∆ꢌ_ꢍꢄ ꢕ

ꢆ

ꢏꢔ

ꢖꢗ

ΔV_RR= (0.01) × V_OUT

where:

V_INis the high voltage input.

_OUTis the desired output voltage.

_SWis the controller switching frequency (300 kHz, 600 kHz, and

OUTPUT CAPACITOR SELECTION

V

f

The primary objective of the output capacitor is to facilitate the

reduction of the output voltage ripple; however, the output capacitor

also assists in the output voltage recovery during load transient

events. For a given load current step, the output voltage ripple

generated during this step event is inversely proportional to the

value chosen for the output capacitor. The speed at which the

output voltage settles during this recovery period depends on

where the crossover frequency (loop bandwidth) is set. This

crossover frequency is determined by the output capacitor, the

equivalent series resistance (ESR) of the capacitor, and the

compensation network.

1.0 MHz).

When selecting the inductor, choose an inductor saturation

rating that is above the peak current level, and then calculate

the inductor current ripple (see the Valley Current-Limit

Setting section and Figure 81).

52

50

∆I = 50%

∆I = 40%

48

46

44

42

40

38

36

34

32

30

28

26

24

22

20

18

16

14

12

10

8

To calculate the small signal voltage ripple (output ripple voltage) at

the steady state operating point, use the following equation:

∆I = 33%

1

ꢘ_ꢇꢈꢁꢂ ∆ꢌ_ꢍꢄ ꢙ

ꢡ

ꢚ

ꢅ

ꢋꢠ

8 ꢄ ꢕ_ꢖꢗꢄ ∆ꢆ_{ꢛꢏꢜꢜꢍꢝ}ꢉ ∆ꢌ_ꢍꢄ ꢞꢟꢀ

where ESR is the equivalent series resistance of the output

capacitors.

To calculate the output load step, use the following equation:

6

8

10 12 14 16 18 20 22 24 26 28 30

VALLEY CURRENT LIMIT (A)

∆ꢌ_ꢍꢇꢐꢑ

ꢘ_ꢇꢈꢁꢂ 2 ꢄ

ꢅ ꢋ

_ꢖꢗꢄ ꢢ∆ꢆ_{ꢑꢛꢇꢇꢜ}ꢉ ∆ꢌ_ꢍꢇꢐꢑꢄ ꢞꢟꢀ ꢣ

ꢕ

Figure 81. Peak Inductor Current vs. Valley Current Limit for 33%, 40%, and

50% of Inductor Ripple Current

where ΔV_DROOPis the amount that V_OUTis allowed to deviate for

a given positive load current step (ΔI_LOAD).

Rev. A | Page 24 of 40

Data Sheet

ADP1878/ADP1879

Ceramic capacitors are known to have low ESR. However, there

is a trade-off in using the popular X5R capacitor technology

because as much as 80% of its capacitance may be lost due to

derating as the voltage applied across the capacitor is increased

(see Figure 82). Although X7R series capacitors can also be

used, the available selection is limited to 22 μF maximum.

20

Error Amplifier Output Impedance (Z_COMP

)

Assuming C_C2is significantly smaller than C_COMP, C_C2can be

omitted from the output impedance equation of the error

amplifier. The transfer function simplifies to

ꢒ

ꢜ

ꢎ_ꢅꢋꢃꢏ

ꢁ

^ꢅꢋꢃꢏꢄ

ꢚ

ꢛ

^ꢜꢓ ꢚ

ꢅꢈꢋꢆꢆ ꢝꢉꢈꢋ

ꢚ

ꢅꢈꢋꢆꢆ

and

10

X7R (50V)

0

1

ꢚ

ꢅꢈꢋꢆꢆ

ꢁ

ꢄ ꢚ

ꢆꢞ

–10

–20

–30

–40

12

where f_ZERO, the zero frequency, is set to be 1/4^thof the crossover

frequency for the ADP1878.

Error Amplifier Gain (G_m)

The error amplifier gain (transconductance) is

G_m= 500 μA/V (μs)

–50

X5R (25V)

–60

–70

X5R (16V)

–80

10µF TDK 25V, X7R, 1210 C3225X7R1E106M

22µF MURATA 25V, X7R, 1210 GRM32ER71E226KE15L

47µF MURATA 16V, X5R, 1210 GRM32ER61C476KE15L

Current-Sense Loop Gain (G_CS)

The current-sense loop gain is

1

–90

–100

0

5

10

15

20

25

30

DC VOLTAGE (V

)

DC

ꢘ ⁄ ꢙ

ꢟ ꢇ

ꢂ_ꢅꢆ

ꢁ

ꢟ_ꢅꢆꢄ ꢒ_ꢋꢠ

Figure 82. Capacitance vs. DC Voltage Characteristics for Ceramic Capacitors

where:

Electrolytic capacitors satisfy the bulk capacitance requirements

for most high current applications. However, because the ESR of

electrolytic capacitors is much higher than that of ceramic capaci-

tors, mount several MLCCs in parallel with the electrolytic

capacitors to reduce the overall series resistance.

A_CS(V/V) is programmable for 3 V/V, 6 V/V, 12 V/V, and 24 V/V

(see the Programming Resistor (RES) Detect Circuit and Valley

Current-Limit Setting sections).

R

_ONis the channel impedance of the low-side MOSFET.

Crossover Frequency

COMPENSATION NETWORK

The crossover frequency is the frequency at which the overall

loop (system) gain is 0 dB (H = 1 V/V). It is recommended for

current-mode converters, such as the ADP1878, that the user set

the crossover frequency between 1/10^thand 1/15^thof the switching

frequency.

Due to its current-mode architecture, the ADP1878/ADP1879

require Type II compensation. To determine the component

values needed for compensation (resistance and capacitance

values), it is necessary to examine the overall loop gain (H) of the

converter at the unity-gain frequency (f_SW/10) when H = 1 V/V:

1

ꢇ_ꢈꢉꢊ

ꢚ

ꢁ

ꢚ

ꢆꢞ

ꢅꢈꢋꢆꢆ

⁄

ꢀ ꢁ 1 V V ꢁ ꢂ_ꢃꢄ ꢂ_ꢅꢆ

ꢄ

ꢄ ꢎ_ꢅꢋꢃꢏꢄ ꢎ_ꢊꢐꢑꢍ

12

ꢇ_ꢋꢌꢍ

The relationship between C_COMPand f_ZERO(zero frequency) is as

follows:

Examining each variable at high frequency enables the unity-

gain transfer function to be simplified to provide expressions

for the R_COMPand C_COMPcomponent values.

1

ꢚ

ꢝꢉꢈꢋ

ꢁ

2ꢡ ꢄ ꢒ_ꢅꢋꢃꢏꢄ ꢗ_ꢅꢋꢃꢏ

Output Filter Impedance (Z_FILT

)

The zero frequency is set to 1/4^thof the crossover frequency.

Examining the transfer function of the filter at high frequencies

simplifies to

Combining all of the above parameters results in

ꢒ_ꢅꢋꢃꢏ

ꢁ

1 ꢓ ꢔ ꢄ ꢕꢖꢒ ꢄ ꢗ_ꢋꢌꢍ

ꢎ_{ꢊꢐꢑꢍꢉꢈ}ꢁ ꢒ_ꢑꢄ

ꢢ

ꢘ

ꢙ

ꢚ

ꢛ1 ꢓ ꢘꢔ ꢒ_ꢑꢓ ꢕꢖꢒ ꢗ_ꢋꢌꢍꢙ^ꢢ

1

ꢅꢈꢋꢆꢆ

ꢘ

ꢙ

1 ꢓ ꢔ ꢒ_ꢑꢓ ꢕꢖꢒ ꢗ_ꢋꢌꢍ

ꢄ

ꢜ

^ꢜꢓ ꢚ

ꢛ

ꢛ1^ꢢꢓ ꢘꢔ ꢄ ꢕꢖꢒ ꢄ ꢗ_ꢋꢌꢍꢙ^ꢢ

ꢒ_ꢑ

ꢚ

ꢅꢈꢋꢆꢆ

ꢝꢉꢈꢋ

at the crossover frequency (s = 2πf_CROSS). ESR is the equivalent

series resistance of the output capacitors.

ꢇ

1

^ꢋꢌꢍꢄ

ꢇ_ꢈꢉꢊꢂ_ꢃꢂ_ꢅꢆ

where ESR is the equivalent series resistance of the output

capacitors.

1

ꢗ_ꢅꢋꢃꢏ

ꢁ

2 ꢄ ꢡ ꢄ ꢒ_ꢅꢋꢃꢏꢄ ꢚ

ꢝꢉꢈꢋ

Rev. A | Page 25 of 40

ADP1878/ADP1879

Data Sheet

800

720

640

560

480

400

320

240

160

80

EFFICIENCY CONSIDERATION

V

= 2.7V

= 3.6V

= 5.5V

REG

An important criteria to consider in constructing a dc-to-dc

converter is efficiency. By definition, efficiency is the ratio of the

output power to the input power. For high power applications at

load currents of up to 20 A, the following are important MOSFET

parameters that aid in the selection process:



V_{GS (TH)}is the MOSFET voltage applied between the gate

and the source that starts channel conduction.

R_{DS (ON)}is the on resistance of the MOSFET during channel

conduction.



Q_Gis the total gate charge.

+125°C

+25°C

–40°C

C_N1is the input capacitance of the high-side switch.

_N2is the input capacitance of the low-side switch.

C

300

400

500

600

700

800

900

1000

SWITCHING FREQUENCY (kHz)

The following are the losses experienced through the external

component during normal switching operation:

Figure 83. Internal Rectifier Voltage Drop vs. Switching Frequency

MOSFET Switching Loss



Channel conduction loss (both of the MOSFETs).

MOSFET driver loss.

MOSFET switching loss.

Body diode conduction loss (low-side MOSFET).

Inductor loss (copper and core loss).

The SW node transitions due to the switching activities of the

high- and low-side MOSFETs. This causes removal and reple-

nishing of charge to and from the gate oxide layer of the MOSFET,

as well as to and from the parasitic capacitance associated with

the gate oxide edge overlap and the drain and source terminals.

The current that enters and exits these charge paths presents

additional loss during these transition times. This can be approxi-

mately quantified by using the following equation, which represents

the time in which charge enters and exits these capacitive regions:

Channel Conduction Loss

During normal operation, the bulk of the loss in efficiency is due

to the power dissipated through MOSFET channel conduction.

Power loss through the high-side MOSFET is directly proportional

to the duty cycle (D) for each switching period, and the power

loss through the low-side MOSFET is directly proportional to

1 − D for each switching period. The selection of MOSFETs is

governed by the maximum dc load current that the converter is

expected to deliver. In particular, the selection of the low-side

MOSFET is dictated by the maximum load current because a

typical high current application employs duty cycles of less than

50%. Therefore, the low-side MOSFET is in the on state for

most of the switching period.

t

_SW-TRANS= R_GATE× C_TOTAL

where:

_TOTALis the C_GD+ C_GSof the external MOSFET.

_GATEis the gate input resistance of the external MOSFET.

C

R

The ratio of this time constant to the period of one switching cycle

is the multiplying factor to be used in the following expression:

ꢕ_ꢓꢔ-TRANS

ꢀ

ꢆ

ꢉ ꢏ_ꢄꢋꢐꢑꢉ ꢖ_ꢗꢁꢉ 2

ꢓꢔꢂꢄꢋꢓꢓꢅ

ꢕ_ꢓꢔ

ꢀ_{ꢁ1,ꢁ2ꢂꢃꢄꢅ}ꢆ ꢇꢈ ꢉ ꢊ_ꢁ1_ꢋꢁꢅꢌ 1 ꢍ ꢈ ꢉ ꢊ_{ꢁ2ꢂꢋꢁꢅ}ꢎ ꢉ ꢏ^ꢒ

ꢂ

ꢅ

ꢂ

ꢄꢋꢐꢑ

or

MOSFET Driver Loss

P

_SW(LOSS)= f_SW× R_GATE× C_TOTAL× I_LOAD× V_IN× 2

Other dissipative elements are the MOSFET drivers. The con-

tributing factors are the dc current flowing through the driver

during operation and the Q_GATEparameter of the external MOSFETs.

Body Diode Conduction Loss

The ADP1878/ADP1879 employ anti cross conduction circuitry

that prevents the high- and low-side MOSFETs from conducting

current simultaneously. This overlap control is beneficial, avoiding

large current flow that may lead to irreparable damage to the

external components of the power stage. However, this blanking

period comes with the trade-off of a diode conduction loss

occurring immediately after the MOSFETs change states and

continuing well into idle mode.

P

_DR(LOSS)= [V_DR× (f_SWC_upperFET

(f_SWC_lowerFETV_REG+ I_BIAS)]

where:

V_DR+ I_BIAS)] + [V_REG×

C_upperFETis the input gate capacitance of the high-side MOSFET.

C_lowerFETis the input gate capacitance of the low-side MOSFET.

I

V

_BIASis the dc current flowing into the high- and low-side drivers.

_DRis the driver bias voltage (that is, the low input voltage (V_REG

minus the rectifier drop (see Figure 83)).

_REGis the bias voltage.

)

V

Rev. A | Page 26 of 40

Data Sheet

ADP1878/ADP1879

The amount of loss through the body diode of the low-side

MOSFET during the anti overlap state is given by the following

expression:

capacitors have such high ESR that they cause undesired input

voltage ripple magnitudes and are generally not effective at high

switching frequencies.

ꢊ_{ꢁꢂꢃꢄꢅꢆꢂꢇꢇꢈ}

If bulk electrolytic capacitors are used, it is recommended to use

multilayered ceramic capacitors (MLCC) in parallel due to their

low ESR values. This dramatically reduces the input voltage ripple

amplitude as long as the MLCCs are mounted directly across the

drain of the high-side MOSFET and the source terminal of the

low-side MOSFET (see the Layout Considerations section).

Improper placement and mounting of these MLCCs may cancel

their effectiveness due to stray inductance and an increase in

trace impedance.

ꢀ_{ꢁꢂꢃꢄꢅꢆꢂꢇꢇꢈ}

ꢉ

ꢌ ꢍ_ꢆꢂꢎꢃꢌ ꢏ_ꢐꢌ 2

ꢊ_ꢇꢋ

where:

_BODY(LOSS)is the body conduction time (refer to Figure 84 for

dead time periods).

_SWis the period per switching cycle.

t

V_Fis the forward drop of the body diode during conduction.

(Refer to the selected external MOSFET data sheet for more

information about the V_Fparameter.)

80

ꢅ

ꢈ

ꢢꢏ_ꢂꢣꢤꢌ ꢏ_ꢞꢟꢥ ꢏ_ꢂꢣꢤ

+125°C

+25°C

–40°C

1MHz

300kHz

ꢍ_{ꢑꢞꢟ,ꢒꢠꢇ}ꢉ ꢍ_{ꢆꢂꢎꢃ,ꢠꢎꢡ}

ꢌ

72

64

56

48

40

32

24

16

8

ꢏ_ꢂꢣꢤ

The maximum input voltage ripple and maximum input capacitor

rms current occur at the end of the duration of 1 − D while the

high-side MOSFET is in the off state. The input capacitor rms

current reaches its maximum at time D. When calculating the

maximum input voltage ripple, account for the ESR of the input

capacitor as follows:

V

_MAX,RIPPLE= V_RIPP+ (I_LOAD,MAX× ESR)

where:

V

_RIPPis usually 1% of the minimum voltage input.

I

_LOAD,MAXis the maximum load current.

2.7

3.4

4.1

4.8

5.5

V

(V)

ESR is the equivalent series resistance rating of the input capacitor.

REG

Figure 84. Body Diode Conduction Time vs. Low Voltage Input (V_REG

)

Inserting V_MAX,RIPPLEinto the charge balance equation to

calculate the minimum input capacitor requirement gives

Inductor Loss

ꢅ

ꢈ

ꢍ_{ꢆꢂꢎꢃ,ꢠꢎꢡ}

ꢓ 1 ꢥ ꢓ

During normal conduction mode, further power loss is caused

by the conduction of current through the inductor windings,

which have dc resistance (DCR). Typically, larger sized inductors

have smaller DCR values.

ꢔ_{ꢞꢟ,ꢠꢞꢟ}

ꢉ

ꢌ

ꢏ_{ꢠꢎꢡ,ꢒꢞꢦꢦꢆꢧ}

ꢨ

ꢇꢋ

or

ꢍ_{ꢆꢂꢎꢃ,ꢠꢎꢡ}

4ꢨ_ꢇꢋꢏ_{ꢠꢎꢡ,ꢒꢞꢦꢦꢆꢧ}

ꢔ_{ꢞꢟ,ꢠꢞꢟ}

ꢉ

The inductor core loss is a result of the eddy currents generated

within the core material. These eddy currents are induced by the

changing flux, which is produced by the current flowing through

the windings. The amount of inductor core loss depends on the

core material, the flux swing, the frequency, and the core volume.

Ferrite inductors have the lowest core losses, whereas powdered iron

inductors have higher core losses. It is recommended to use shielded

ferrite core material type inductors with the ADP1878/ADP1879

for a high current, dc-to-dc switching application to achieve

minimal loss and negligible electromagnetic interference (EMI).

where D = 50%.

THERMAL CONSIDERATIONS

The ADP1878/ADP1879 are used for dc-to-dc, step down, high

current applications that have an on-board controller, an on-board

LDO, and on-board MOSFET drivers. Because applications may

require up to 20 A of load current and be subjected to high ambient

temperature, the selection of external high- and low-side MOSFETs

must be associated with careful thermal consideration to not

exceed the maximum allowable junction temperature of 125°C.

To avoid permanent or irreparable damage, if the junction temper-

ature reaches or exceeds 155°C, the part enters thermal shutdown,

turning off both external MOSFETs, and is not reenabled until

the junction temperature cools to 140°C (see the On-Board Low

Dropout (LDO) Regulator section).

ꢀ_{ꢃꢑꢒꢅꢆꢂꢇꢇꢈ}ꢉ ꢓꢔꢕ ꢌ ꢍ_ꢆ^ꢖ_ꢂꢎꢃꢗ ꢔꢘꢙꢚꢛꢜꢘꢝꢝ

INPUT CAPACITOR SELECTION

The goal in selecting an input capacitor is to reduce or minimize

input voltage ripple and to reduce the high frequency source

impedance, which is essential for achieving predictable loop

stability and transient performance.

In addition, it is important to consider the thermal impedance

of the package. Because the ADP1878/ADP1879 employ an

on-board LDO, the ac current (fxCxV) consumed by the internal

drivers to drive the external MOSFETs, adds another element of

The problem with using bulk capacitors, other than their physical

geometries, is their large equivalent series resistance (ESR) and

large equivalent series inductance (ESL). Aluminum electrolytic

Rev. A | Page 27 of 40

ADP1878/ADP1879

Data Sheet

power dissipation across the internal LDO. Equation 3 shows the

power dissipation calculations for the integrated drivers and for

the internal LDO. Table 9 lists the thermal impedance for the

ADP1878/ADP1879, which are available in a 14-lead LFCSP_WD.

The rise in package temperature is directly proportional to its

thermal impedance characteristics. The following equation

represents this proportionality relationship:

T_R= θ_JA× P_DR(LOSS)

where:

(2)

Table 9. Thermal Impedance for 14-Lead LFCSP_WD

θ_JAis the thermal resistance of the package from the junction to

Package

Thermal Impedance

the outside surface of the die, where it meets the surrounding air.

14-Lead LFCSP_WD θ_JA

4-Layer Board

P

_DR(LOSS)is the overall power dissipated by the IC.

30°C/W

The bulk of the power dissipated is due to the gate capacitance of

the external MOSFETs and current running through the on-board

LDO. The power loss equations for the MOSFET drivers and

internal low dropout regulator (see the MOSFET Driver Loss

section and the Efficiency Consideration section) are:

Figure 85 specifies the maximum allowable ambient temperature

that can surround the ADP1878/ADP1879 IC for a specified

high input voltage (V_IN). Figure 85 illustrates the temperature

derating conditions for each available switching frequency for

low, typical, and high output setpoints for the 14-lead LFCSP_WD

package. All temperature derating criteria are based on a

maximum IC junction temperature of 125°C.

P

_DR(LOSS)= [V_DR× (f_SWC_upperFET

[V_REG× (f_SWC_{lowerFET REG}+ I_BIAS)]

where:

V_DR+ I_BIAS)] +

V

(3)

130

C

_upperFETis the input gate capacitance of the high-side MOSFET.

_lowerFETis the input gate capacitance of the low-side MOSFET.

120

110

100

I

_BIASis the dc current (2 mA) flowing into the high- and low-

side drivers.

_DRis the driver bias voltage (the low input voltage (V_REG) minus

the rectifier drop (see Figure 83)).

_REGis the LDO output/bias voltage.

_DISS(LDO)= P_DR(LOSS)+ (V_IN– V_REG) × (f_SW× C_TOTAL

_REG+ I_BIAS

where P_DISS(LDO)is the power dissipated through the pass device

in the LDO block across V_INand V_REG

_DR(LOSS)is the MOSFET driver loss.

V_INis the high voltage input.

_REGis the LDO output voltage and bias voltage.

_TOTALis the C_GD+ C_GSof the external MOSFET.

_BIASis the dc input bias current.

V

P

×

300kHz

600kHz

1MHz

V

= 0.8V

= 1.8V

= HIGH SETPOINT

V

(4)

OUT

90

5.5

.

7.0

8.5 10.0 11.5 13.0 14.5 16.0 17.5 19.0

(V)

V

IN

P

Figure 85. Ambient Temperature vs. V_IN,

4-Layer Evaluation Board, C_IN= 4.3 nF (High-/Low-Side MOSFET)

V

C

I

The maximum junction temperature allowed for the ADP1878/

ADP1879 IC is 125°C. This means that the sum of the ambient

temperature (T_A) and the rise in package temperature (T_R), which is

caused by the thermal impedance of the package and the internal

power dissipation, should not exceed 125°C, as dictated by the

following expression:

For example, if the external MOSFET characteristics are θ_JA

(14-lead LFCSP_WD) = 30°C/W, f_SW= 300 kHz, I_BIAS= 2 mA,

C

_upperFET= 3.3 nF, C_lowerFET= 3.3 nF, V_DR= 4.62 V, and V_REG= 5.0 V,

then the power loss is

T_J= T_R× T_A

where:

T_Jis the maximum junction temperature.

T_Ris the rise in package temperature due to the power

dissipated from within.

(1)

P

_DR(LOSS)= [V_DR× (f_SWCupperFET

V

_DR+ I_BIAS)] +

[V_REG× (f_SWClowerFETV_REG+ I_BIAS)]

= (4.62 × (300 × 10³× 3.3 × 10⁻⁹× 4.62 + 0.002)) +

(5.0 × (300 × 10³× 3.3 × 10⁻⁹× 5.0 + 0.002))

= 57.12 mW

T_Ais the ambient temperature.

P

_DISS(LDO)= (V_IN– V_REG) × (f_SW× C_TOTAL× V_REG+ I_BIAS) =

(13 V – 5 V) × (300 × 10³× 3.3 × 10⁻⁹× 5 + 0.002)

= 55.6 mW

P

_DISS(TOTAL)= P_DISS(LDO)+ P_DR(LOSS)

= 77.13 mW + 55.6 mW

= 132.73 mW

Rev. A | Page 28 of 40

Data Sheet

ADP1878/ADP1879

The rise in package temperature (for a 14-lead LFCSP_WD) is

T_R= θ_JA× P_DR(LOSS)

Current-Limit Programming

The valley current is approximately

15 A − (5 A × 0.5) = 12.5 A

= 30°C × 132.05 mW

Assuming a low-side MOSFET R_ONof 4.5 mΩ and 13 A, as the

valley current limit from Table 7 and Figure 71 indicate, a pro-

gramming resistor (RES) of 100 kΩ corresponds to an A_CS

of 24 V/V.

= 4.0°C

Assuming a maximum ambient temperature environment of 85°C,

T_J= T_R× T_A= 4.0°C + 85°C = 89.0°C,

which is below the maximum junction temperature of 125°C.

DESIGN EXAMPLE

Choose a programmable resistor of R_RES= 100 kꢀ for a current

sense gain of 24 V/V.

Output Capacitor

The ADP1878/ADP1879 are easy to use, requiring only a few

design criteria. For example, the example outlined in this section

uses only four design criteria: V_OUT= 1.8 V, I_LOAD= 15 A (pulsing),

V_IN= 12 V (typical), and f_SW= 300 kHz.

Assume that a load step of 15 A occurs at the output and no more

than 5% output deviation is allowed from the steady state operating

point. In this case, the advantage of the ADP1878 is that because

the frequency is pseudo fixed, the converter is able to respond

quickly because of the immediate, though temporary, increase

in switching frequency.

Input Capacitor

The maximum input voltage ripple is usually 1% of the

minimum input voltage (11.8 V × 0.01 = 120 mV).

ΔV_DROOP= 0.05 × 1.8 V = 90 mV

V

_RIPP= 120 mV

Assuming the overall ESR of the output capacitor ranges from

5 mΩ to 10 mΩ,

_MAX,RIPPLE= V_RIPP− (I_LOAD,MAX× ESR)

= 120 mV − (15 A × 0.001) = 45 mV

∆ꢅ_ꢆꢇꢈꢉ

ꢞ

ꢅ_{ꢆꢇꢈꢉ,ꢃꢈꢊ}

15ꢒA

ꢀ_ꢇꢙꢚꢄ 2 ꢓ

ꢀ_{ꢁꢂ,ꢃꢁꢂ}

ꢄ

ꢟ

ꢋ_ꢌꢍꢓ ∆ꢎ_{ꢉꢏꢇꢇꢐ}

4ꢋ_ꢌꢍꢎ_{ꢃꢈꢊ,ꢏꢁꢐꢐꢆꢑ}4ꢒ ꢓ ꢒ300ꢒ ꢓꢒ10^ꢔꢒꢓ ꢒ105ꢒmV

15ꢒA

ꢄ 2 ꢓ

= 120 μF

ꢔ

ꢞ

ꢟ

300 ꢓ 10 ꢓ 90ꢒmV

Choose five 22 μF ceramic capacitors. The overall ESR of five

22 μF ceramic capacitors is less than 1 mΩ.

= 1.11 mF

Therefore, an appropriate inductor selection is five 270 μF

polymer capacitors with a combined ESR of 3.5 mΩ.

I

_RMS= I_LOAD/2 = 7.5 A

_CIN= (I_RMS)²× ESR = (7.5 A)²× 1 mΩ = 56.25 mW

P

Assuming an overshoot of 45 mV, determine if the output

capacitor that was calculated previously is adequate

Inductor

ꢢ

Determining inductor ripple current amplitude:

ꢞ

_{ꢒꢒꢆꢇꢈꢉ}ꢟ

ꢖ ꢓ ꢅ

ꢀ_ꢇꢙꢚ

ꢄ

ꢞꢎ_ꢇꢙꢚꢘ ∆ꢎ_{ꢇꢣꢌꢤꢚ}ꢟ^ꢢꢘ ꢞꢎ_ꢇꢙꢚ

1 ꢓ 10^ꢥꢦꢓ ꢞ15ꢒAꢟ^ꢢ

ꢞ1.8 ꢘ 45ꢒmVꢟ^ꢢꢘ ꢞ1.8ꢟ^ꢢ

= 1.4 mF

Choose five 270 μF polymer capacitors.

The rms current through the output capacitor is

ꢟ

ꢞ

^ꢢꢟ

ꢅ_ꢆꢇꢈꢉ

∆ꢅ_ꢆꢕ

ꢄ 5ꢒA

3

ꢄ

Then, calculating for the inductor value

ꢗꢎ_{ꢁꢂ,ꢃꢈꢊ}ꢘ ꢎ_ꢇꢙꢚ

∆ꢅ_ꢆ

ꢛ

ꢎ_ꢇꢙꢚ

ꢖ ꢄ

ꢓ

ꢎ

ꢁꢂ,ꢃꢈꢊ

13.2ꢒVꢒ– ꢒ1.8ꢒV

1.8ꢒV

ꢄ

ꢓ

5ꢒV ꢓ 300 ꢓ 10^ꢔ13.2ꢒV

1

2

1 ꢗꢎ_{ꢁꢂ,ꢃꢈꢊ}ꢘ ꢎ_ꢇꢙꢚ

ꢛ

ꢎ_ꢇꢙꢚ

= 1.03 μH

ꢅ_ꢏꢃꢌ

ꢄ

ꢓ

ꢖ ꢓ ꢋ

ꢎ

ꢁꢂ,ꢃꢈꢊ

3

√

ꢌꢍ

The inductor peak current is approximately

15 A + (5 A × 0.5) = 17.5 A

ꢞ

ꢟ

1

ꢄ

1

13.2ꢒVꢒ–ꢒ1.8ꢒV

1.8ꢒV

ꢓ

ꢄ1.49ꢒAꢒ

2

1ꢒμFꢓ300ꢓ10³13.2ꢒV

3

√

Therefore, an appropriate inductor selection is 1.0 μH with

DCR = 3.3 mΩ (Würth Elektronik 7443552100) with a peak

current handling of 20 A.

The power loss dissipated through the ESR of the output

capacitor is

P

_COUT= (I_RMS)²× ESR = (1.5 A)²× 1.4 mΩ = 3.15 mW

ꢜ_{ꢉꢝꢏꢞꢆꢇꢌꢌꢟ}ꢄ ꢠꢀꢡ ꢓ ꢅ_ꢆ^ꢢ

= 0.003 × (15 A)²= 675 mW

Rev. A | Page 29 of 40

ADP1878/ADP1879

Data Sheet

Feedback Resistor Network Setup

Loss Calculations

Choosing R_B= 1 kΩ as an example. Calculate R_Tas follows:

Duty cycle = 1.8/12 V = 0.15

ꢅ

ꢇ

1.8ꢃV ꢆ 0.6ꢃV

R

_ON(N2)= 5.4 mΩ

ꢀ_ꢁꢂ 1ꢃkΩ ꢄ

ꢂ 2ꢃkΩ

0.6ꢃV

t_BODY(LOSS)= 20 ns (body conduction time)

Compensation Network

V_F= 0.84 V (MOSFET forward voltage)

To calculate R_COMP, C_COMP, and C_PAR, the transconductance

parameter and the current sense gain variable are required. The

transconductance parameter (G_m) is 500 μA/V, and the current

sense loop gain is

C_IN= 3.3 nF (MOSFET gate input capacitance)

Q

_N1,N2= 17 nC (total MOSFET gate charge)

R_GATE= 1.5 Ω (MOSFET gate input resistance)

1

ꢤ_{ꢍ1,ꢍꢗꢅꢉꢙꢇ}ꢂ ꢥꢦ ꢄ ꢀ_{ꢍ1ꢅꢌꢍꢇ}ꢔ 1 ꢆ ꢦ ꢄ ꢀ_{ꢍꢗꢅꢌꢍꢇ}ꢧ ꢄ ꢨ_ꢙ^ꢗ_ꢌꢩꢪ

= (0.15 × 0.0054 + 0.85 × 0.0054) × (15 A)²

= 1.215 W

ꢅ

ꢇ

ꢈ_ꢉꢊ

ꢂ

ꢂ 8.33ꢃA/V

ꢋ_ꢉꢊꢀ_ꢌꢍ24 ꢄ 0.005

where A_CSand R_ONare taken from setting up the current limit

(see the Programming Resistor (RES) Detect Circuit section

and the Valley Current-Limit Setting section).

The crossover frequency is 1/12^thof the switching frequency:

ꢭ_{ꢫꢌꢪꢬꢅꢙꢌꢊꢊꢇ}

ꢤ_{ꢫꢌꢪꢬꢅꢙꢌꢊꢊꢇ}

ꢂ

ꢄ ꢨ_ꢙꢌꢩꢪꢄ ꢞ_ꢟꢄ 2

ꢭ_ꢊꢮ

= 20 ns × 300 × 10³× 15 A × 0.84 × 2

= 151.2 mW

300 kHz/12 = 25 kHz

The zero frequency is 1/4^thof the crossover frequency:

25 kHz/4 = 6.25 kHz

P

_SW(LOSS)= f_SW× R_GATE× C_TOTAL× I_LOAD× V_IN× 2

= 300 × 10³× 1.5 ꢀ × 3.3 × 10⁻⁹× 15 A × 12 × 2

= 534.6 mW

ꢀ_ꢉꢌꢎꢏ

ꢂ

ꢗ

ꢒ1 ꢔ ꢅꢘ ꢀ_ꢙꢔ ꢚꢛꢀ ꢜ_ꢌꢝꢁꢇ^ꢗ

P

_DR(LOSS)= [V_DR× (f_SWC_upperFET

V_DR+ I_BIAS)] + [V_REG×

ꢅ

ꢇ

ꢐ

ꢉꢑꢌꢊꢊ

ꢄ

ꢓ

^ꢓꢔ ꢐ

(f_SWC_{lowerFET REG}+I_BIAS)]

V

ꢒ

ꢒ1^ꢗꢔ ꢅꢘ ꢄ ꢚꢛꢀ ꢄ ꢜ_ꢌꢝꢁꢇ^ꢗ

ꢐ

ꢉꢑꢌꢊꢊ

ꢕꢖꢑꢌ

=(4.62 × (300 ×10³× 3.3 × 10⁻⁹× 4.62 + 0.002)) +

(5.0 × (300 × 10³× 3.3 × 10⁻⁹× 5.0 + 0.002))

= 57.12 mW

1

ꢞ_ꢌꢝꢁ

1

ꢄ

ꢀ_ꢙꢞ_ꢑꢖꢟꢈ_ꢎꢈ_ꢉꢊ

25ꢃkΩ

√25ꢃkΩ^ꢗꢔ 6.25ꢃkΩ^ꢗ

ꢀ_ꢉꢌꢎꢏ

ꢂ

ꢄ

P

_DISS(LDO)= (V_IN– V_REG) × (f_SW× C_TOTAL× V_REG+ I_BIAS)

ꢗ

ꢅ

ꢇ

ꢒ1 ꢔ ꢅ2π ꢄ 25ꢃkΩ ꢄ ꢅ 1.8/15 ꢔ 0.0035ꢇ ꢄ 0.0011ꢇ

= (13 V – 5 V) × (300 × 10³× 3.3 × 10⁻⁹× 5 + 0.002)

= 55.6 mW

ꢄ

ꢒ1^ꢗꢔ ꢅ2π ꢄ 25ꢃkΩ ꢄ 0.0035 ꢄ 0.0011ꢇ^ꢗ

1.8

1

15

P

_COUT= (I_RMS)²× ESR = (1.5 A)²× 1.4 mΩ = 3.15 mW

ꢄ

0.6 500 ꢄ 10^ꢠꢡꢄ 8.3 1.8

= 60.25 kΩ

= 0.003 × (15 A)²= 675 mW

P_DCR(LOSS) DCRI_L²_OAD

1

P

_CIN= (I_RMS)²× ESR = (7.5 A)²× 1 mΩ = 56.25 mW

ꢜ_ꢉꢌꢎꢏ

ꢂ

2ꢢꢀ_ꢉꢌꢎꢏ

ꢐ

ꢕꢖꢑꢌ

_LOSS= P_N1,N2+ P_BODY(LOSS)+ P_SW+ P_DCR+ P_DR+ P_DISS(LDO)+ P_COUT

1

+ P_CIN= 1.215 W + 151.2 mW + 534.6 mW + 57.12 mW +

55.6 + 3.15 mW + 675 mW + 56.25 mW = 2.655 W

ꢂ

2 ꢄ 3.14 ꢄ 60.25 ꢄ 10^ꢣꢄ 6.25 ꢄ 10^ꢣ

= 423 pF

Rev. A | Page 30 of 40

Data Sheet

ADP1878/ADP1879

EXTERNAL COMPONENT RECOMMENDATIONS

The configurations listed in Table 10 are with f_CROSS= 1/12 × f_SW, f_ZERO= ¼ × f_CROSS, R_RES= 100 kΩ, R_BOT= 1kΩ, R_ON= 5.4 mꢀ (BSC042N03MS G),

VREG = 5 V (float), and a maximum load current of 14 A. The ADP1879 models listed in Table 10 are the PSM versions of the device.

Table 10. External Component Values

V_OUT

(V)

V_IN

(V)

13

16.5

5.5

13

16.5

5.5

13

C_IN

(μF)

L¹

(μH)

0.72

1.0

1.2

1.53

2.0

3.27

3.44

1.0

R_C

(kΩ)

C_COMP

(pF)

C_PAR

(pF)

R_TOP

(kΩ)

Model

C_OUT(μF)

5 × 560³

4 × 560³

4 × 270⁴

3 × 270⁴

2 × 330⁵

330⁵

22²+ ( 4 × 47⁶)

4 × 560³

4 × 270⁴

2 × 330⁵

2 × 150⁷

22²+ 4 × 47⁶

4 × 560³

4 × 270⁴

3 × 270⁴

3 × 180⁸

5 × 270⁴

3 × 330⁵

3 × 270⁴

2 × 270⁴

150⁷

4 × 270⁴

2 × 330⁵

3 × 270⁴

330⁵

4 × 47⁶

3 × 47⁶

4 × 270⁴

2 × 330⁵

3 × 180⁸

270⁴

ADP1878ACPZ-0.3-R7/

ADP1879ACPZ-0.3-R7

0.8

1.2

1.8

2.5

3.3

5

5 × 22²

4 × 22²

5 × 22²

4 × 22²

3 × 22²

5 × 22²

3 × 22²

5 × 10⁹

3 × 10⁹

4 × 10⁹

5 × 22²

3 × 22²

3 × 10⁹

4 × 10⁹

5 × 10⁹

4 × 10⁹

3 × 10⁹

4 × 10⁹

3 × 10⁹

56.9

57.6

56.9

40.7

56.9

57.6

56.9

41.2

40.7

56.2

56.9

56.2

57.6

40.7

56.9

53.6

57.6

53.0

41.2

40.7

54.9

49.3

56.9

54.9

53.6

56.9

54.9

56.2

40.7

56.9

56.2

40.7

620

470

680

620

470

510

680

300

270

220

360

270

240

360

300

270

360

300

200

220

130

200

180

220

270

220

200

180

220

180

62

47

68

62

47

51

68

300

27

22

36

27

24

36

30

27

36

30

20

22

13

20

18

22

27

22

20

18

22

18

0.3

1.0

2.0

3.2

4.5

7.3

10.7

1.0

2.0

3.2

4.5

7.3

10.7

0.3

1.0

2.0

3.2

1.0

2.0

3.2

4.5

7.3

1.0

2.0

3.2

4.5

7.3

10.7

0.3

1.0

2.0

3.2

1.0

2.0

3.2

4.5

7.3

1.0

2.0

3.2

4.5

7.3

10.7

7

1.2

1.8

2.5

3.3

5

1.0

1.67

2.00

3.84

4.44

0.22

0.47

0.90

1.00

1.76

0.47

0.72

0.90

1.0

7

ADP1878ACPZ-0.6-R7/

ADP1879ACPZ-0.6-R7

0.8

1.2

1.8

2.5

1.2

1.8

2.5

3.3

5

1.2

1.8

2.5

3.3

5

2.0

7

ADP1878ACPZ-1.0-R7/

ADP1879ACPZ-1.0-R7

0.8

1.2

1.8

2.5

1.2

1.8

2.5

3.3

5

0.22

0.47

0.72

1.0

0.47

0.72

1.2

3 × 330⁵

3 × 270⁴

270⁴

3 × 47⁶

4 × 270⁴

3 × 270⁴

3 × 180⁸

270⁴

3 × 47⁶

22²+ 47⁶

1.2

1.8

2.5

3.3

5

16.5

7

1.2

¹See the Inductor Selection section and Table 11.

²22 μF Murata 25 V, X7R, 1210 GRM32ER71E226KE15L (3.2 mm × 2.5 mm × 2.5 mm).

³560 μF Panasonic (SP-series) 2 V, 7 mΩ, 3.7 A EEFUE0D561LR (4.3 mm × 7.3 mm × 4.2 mm).

⁴270 μF Panasonic (SP-series) 4 V, 7 mΩ, 3.7 A EEFUE0G271LR (4.3 mm × 7.3 mm × 4.2 mm).

⁵330 μF Panasonic (SP-series) 4 V, 12 mΩ, 3.3 A EEFUE0G331R (4.3 mm × 7.3 mm × 4.2 mm).

⁶47 μF Murata 16 V, X5R, 1210 GRM32ER61C476KE15L (3.2 mm × 2.5 mm × 2.5 mm).

⁷150 μF Panasonic (SP-series) 6.3 V, 10 mΩ, 3.5 A EEFUE0J151XR (4.3 mm × 7.3 mm × 4.2 mm).

⁸180 μF Panasonic (SP-series) 4 V, 10 mΩ, 3.5 A EEFUE0G181XR (4.3 mm × 7.3 mm × 4.2 mm).

⁹10 μF TDK 25 V, X7R, 1210 C3225X7R1E106M.

Rev. A | Page 31 of 40

ADP1878/ADP1879

Data Sheet

Table 11. Recommended Inductors

L (μH)

0.12

0.22

0.47

0.72

0.9

1.2

1.0

1.4

2.0

DCR (mΩ)

0.33

0.8

1.65

1.6

1.8

3.8

3.2

2.6

I_SAT(A)

Dimension (mm)

10.2 × 7

14.2 × 12.8

10.5 × 10.2

14 × 12.8

10.5 × 10.2

10.2 × 10.2

14 × 12.8

Manufacturer

Würth Elektronik

Sumida

Model Number

55

30

50

35

32

25

16

24

744303012

744303022

744355147

744325072

744318120

744325120

7443552100

744318180

7443551200

CEP125U-0R8

23

27.5

10.2 × 10.2

0.8

Table 12. Recommended MOSFETs

V_GS= 4.5 V

R_ON(mΩ)

I_D(A) V_DS(V) C_IN(nF) Q_TOTAL(nC)

Package

PG-TDSON8

SO-8

Manufacturer

Model Number

High-Side MOSFET

(Q1/Q2)

5.4

10.2

6.0

47

53

19

14

47

82

19

30

3.2

1.6

20

10

35

25

20

10

35

Infineon

Vishay

International Rectifier

Infineon

BSC042N03MS G

BSC080N03MS G

Si4842DY

9

2.4

3.2

1.6

SO-8

IRF7811

Low-Side MOSFET

(Q3/Q4)

5.4

10.2

6.0

PG-TDSON8

SO-8

BSC042N03MS G

BSC080N03MS G

Si4842DY

Infineon

Vishay

Rev. A | Page 32 of 40

Data Sheet

ADP1878/ADP1879

LAYOUT CONSIDERATIONS

The performance of a dc-to-dc converter depends highly on

how the voltage and current paths are configured on the printed

circuit board (PCB). Optimizing the placement of sensitive

analog and power components are essential to minimize output

ripple, maintain tight regulation specifications, and reduce

PWM jitter and electromagnetic interference.

Figure 86 shows the schematic of a typical ADP1878/ADP1879

used for a high current application. Blue traces denote high current

pathways. VIN, PGND, and V_OUTtraces should be wide and

possibly replicated, descending down into the multiple layers.

Vias should populate, mainly around the positive and negative

terminals of the input and output capacitors, alongside the source

of Q1/Q2, the drain of Q3/Q4, and the inductor.

HIGH VOLTAGE INPUT

V

= 12V

IN

JP3

C

C3

22µF

C4

22µF

C5

22µF

C6

22µF

C7

22µF

C8

N/A

C9

N/A

VIN

22µF

C

430pF

R

57kΩ

C

ADP1878/

ADP1879

C

100nF

BST

C

53pF

PAR

C

1

2

3

14

Q1

Q3

Q2

VIN

BST

COMP

EN

SW 13

1.0µH

V

= 1.8V, 15A

+

C23

OUT

R7 10kΩ

2kΩ

V

12

11

DRVH

PGND

REG

+

R

C20

270µF

C21

270µF

C22

270µF

SNB

2Ω

R

TOP

270µF

V

Q4

4

5

FB

OUT

C

SNB

1.5nF

R

BOT

1kΩ

GND

DRVL 10

+

C24

N/A

C25

N/A

C26

N/A

C27

N/A

C14 TO C19

N/A

5kΩ

6

7

9

8

RES

PGOOD

SS

V

REG

R

RES

100kΩ

MURATA: (HIGH VOLTAGE INPUT CAPACITORS)

22µF, 25V, X7R, 1210 GRM32ER71E226KE15L

VREG

C

SS

C2

0.1µF

C1

1µF

PANASONIC: (OUTPUT CAPACITORS)

270µF, SP-SERIES, 4V, 7mΩ, EEFUE0G271LR

34nF

INFINEON FETs:

BSC042N03MS G (LOWER SIDE)

BSC080N03MS G (UPPER SIDE)

WÜRTH INDUCTORS:

1µH, 3.8mΩ, 16A, 7443552100

Figure 86. ADP1878 High Current Evaluation Board Schematic (Blue Traces Indicate High Current Paths)

SENSITIVE ANALOG

COMPONENTS

LOCATED FAR

FROM NOISY

POWER SECTION

SEPARATE ANALOG

OUTPUT

GROUND PLANE FOR

CAPACITORS

COMPENSATION AND

FEEDBACK RESISTORS

ARE MOUNTED

AT RIGHTMOST

AREA OF

EVALUATION

BOARD

INPUT CAPACITORS

ARE MOUNTED CLOSE

TO DRAIN OF Q1/Q2

AND SOURCE OF Q3/Q4

Figure 87. Overall Layout of the ADP1878/ADP1879 High Current Evaluation Board

Rev. A | Page 33 of 40

ADP1878/ADP1879

Data Sheet

Figure 88. Layer 2 of Evaluation Board

TOP RESISTOR

FEEDBACK TAP

VOUT SENSE TAP LINE

EXTENDING BACK TO THE

TOP RESISTOR IN THE

FEEDBACK DIVIDER

NETWORK. THIS OVERLAPS

WITH PGND SENSE TAP

LINE EXTENDING TO THE

ANALOG GROUND PLANE

Figure 89. Layer 3 of Evaluation Board

Rev. A | Page 34 of 40

Data Sheet

ADP1878/ADP1879

BOTTOM

RESISTOR TAP

TO ANALOG

GROUND PLANE

PGND SENSE TAP FROM

NEGATIVE TERMINALS OF

THE OUTPUT BULK

CAPACITORS. THIS

TRACK PLACEMENT

SHOULD BE DIRECTLY

BELOW THE VOUT SENSE

LINE OF LAYER 3.

Figure 90. Layer 4 (Bottom Layer) of Evaluation Board

(yellow arrow) is maintained as Q1/Q2 turns off and Q3/Q4 turns

on. When Q3/Q4 turns on, the current direction continues to be

maintained (red arrow) as it circles from the power ground

terminal of the bulk capacitor to the output capacitors, through

the Q3/Q4. Arranging the power planes in this manner minimizes

the area in which changes in flux occur if the current through

Q1/Q2 stops abruptly. Sudden changes in flux, usually at the

source terminals of Q1/Q2 and the drain terminal of Q3/Q4,

cause large dV/dt at the SW node.

IC SECTION (LEFT SIDE OF EVALUATION BOARD)

A dedicated plane for the analog ground plane (GND) should

be separate from the main power ground plane (PGND). With

the shortest path possible, connect the analog ground plane to

the GND pin (Pin 5). Place this plane on the top layer only of

the evaluation board. To avoid crosstalk interference, do not

allow any other voltage or current pathway directly below this

plane on Layer 2, Layer 3, or Layer 4. Connect the negative

terminals of all sensitive analog components to the analog

ground plane. Examples of such sensitive analog components

include the bottom resistor of the resistor divider, the high

frequency bypass capacitor for biasing (0.1 μF), and the

compensation network.

The SW node is near the top of the evaluation board. The SW

node should use the least amount of area possible and be away

from any sensitive analog circuitry and components. This is

because the SW node is where most sudden changes in flux

density occur. When possible, replicate this pad onto Layer 2

and Layer 3 for thermal relief and eliminate any other voltage and

current pathways directly beneath the SW node plane. Populate

the SW node plane with vias, mainly around the exposed pad of

the inductor terminal and around the perimeter of the source of

Q1/Q2 and the drain of Q3/Q4.

Mount a 1 μF bypass capacitor directly across the VREG pin

(Pin 7) and the PGND pin (Pin 11). In addition, tie a 0.1 μF

across the VREG pin (Pin 7) and the GND pin (Pin 5).

POWER SECTION

As shown in Figure 87, an appropriate configuration to localize

large current transfer from the high voltage input (V_IN) to the

output (V_OUT) and then back to the power ground is to put the

V_INplane on the left, the output plane on the right, and the main

power ground plane in between the two. Current transfers from

the input capacitors to the output capacitors, through Q1/Q2,

during the on state (see Figure 91). The direction of this current

The output voltage power plane (V_OUT) is at the rightmost end of

the evaluation board. This plane should be replicated, descending

down to multiple layers with vias surrounding the inductor

terminal and the positive terminals of the output bulk capacitors.

Ensure that the negative terminals of the output capacitors are

placed close to the main power ground (PGND), as previously

mentioned. All of these points form a tight circle (component

geometry permitting) that minimizes the area of flux change as

the event switches between D and 1 − D.

Rev. A | Page 35 of 40

ADP1878/ADP1879

Data Sheet

SW

PGND

LAYER 1: SENSE LINE FOR SW

(DRAIN OF LOWER MOSFET)

LAYER 1: SENSE LINE FOR PGND

(SOURCE OF LOWER MOSFET)

Figure 92. Drain/Source Tracking Tapping of the Low-Side MOSFET for CS

Amp Differential Sensing (Yellow Sense Line on Layer 2)

Figure 91. Primary Current Pathways During the On State of the High-Side

MOSFET (Left Arrow) and the On State of the Low-Side MOSFET (Right Arrow)

In addition, employ differential sensing between the outermost

output capacitor and the feedback resistor divider (see Figure 89

and Figure 90). Connect the positive terminal of the output

capacitor to the top resistor (R_T). Connect the negative terminal

of the output capacitor to the negative terminal of the bottom

resistor, which connects to the analog ground plane as well.

Keep both of these track lines, as previously mentioned, narrow

and away from any other active device or voltage/ current path.

DIFFERENTIAL SENSING

Because the ADP1878/ADP1879 operate in valley current-mode

control, a differential voltage reading is taken across the drain

and source of the low-side MOSFET. Connect the drain of the

low-side MOSFET s as close as possible to the SW pin (Pin 13) of

the IC. Likewise, connect the source as close as possible to the

PGND pin (Pin 11) of the IC. When possible, keep both of

these track lines narrow and away from any other active device

or voltage/current path.

Rev. A | Page 36 of 40

Data Sheet

ADP1878/ADP1879

TYPICAL APPLICATION CIRCUITS

12 A, 300 kHz HIGH CURRENT APPLICATION CIRCUIT

HIGH VOLTAGE INPUT

= 12V

V

IN

JP3

C

C3

22µF

C4

22µF

C5

22µF

C6

22µF

C7

22µF

C8

N/A

C9

N/A

VIN

22µF

C

560pF

R

C

ADP1878/

ADP1879

C

100nF

BST

C

56pF

PAR

C

1

2

3

14

13

12

Q1

Q3

Q2

VIN

BST

49.3kΩ

COMP

EN

SW

1.2µH

V

= 1.8V, 12A

+

C23

OUT

R7 10kΩ

2kΩ

V

DRVH

REG

+

R

C20

270µF

C21

270µF

C22

270µF

SNB

2Ω

R

TOP

270µF

V

Q4

4

5

11

10

FB

PGND

DRVL

OUT

C

SNB

1.5nF

R

BOT

1kΩ

GND

+

C24

N/A

C25

N/A

C26

N/A

C27

N/A

C14 TO C19

N/A

5kΩ

6

7

9

8

RES

PGOOD

SS

V

REG

R

RES

MURATA: (HIGH VOLTAGE INPUT CAPACITORS)

22µF, 25V, X7R, 1210 GRM32ER71E226KE15L

100kΩ

VREG

C

SS

PANASONIC: (OUTPUT CAPACITORS)

270µF (SP-SERIES), 4V, 7mΩ, EEFUE0G271LR

C2

0.1µF

C1

1µF

34nF

INFINEON MOSFETs:

BSC042N03MS G (LOWER SIDE)

BSC080N03MS G (UPPER SIDE)

WÜRTH INDUCTORS:

1.2µH, 2mΩ, 20A, 744325120

Figure 93. Application Circuit for 12 V Input, 1.8 V Output, 12 A, 300 kHz (Q2/Q4 No Connect)

5.5 V INPUT, 600 kHz CURRENT APPLICATION CIRCUIT

HIGH VOLTAGE INPUT

= 5.5V

V

IN

JP3

C

C3

22µF

C4

22µF

C5

22µF

C6

22µF

C7

22µF

C8

N/A

C9

N/A

VIN

22µF

C

220pF

R

C

ADP1878/

ADP1879

C

100nF

BST

C

22pF

F

C

1

2

3

14

Q1

Q3

Q2

VIN

BST

56.9kΩ

COMP

EN

SW 13

0.47µH

V

= 2.5V, 12A

+

C23

OUT

R7 10kΩ

32kΩ

V

12

11

DRVH

PGND

REG

+

R

C20

180µF

C21

180µF

C22

180µF

SNB

2Ω

R

TOP

N/A

V

Q4

4

5

FB

OUT

C

SNB

1.5nF

R

BOT

1kΩ

GND

DRVL 10

+

C24

N/A

C25

N/A

C26

N/A

C27

N/A

C14 TO C19

N/A

5kΩ

6

7

9

8

RES

PGOOD

SS

V

REG

R

RES

MURATA: (INPUT CAPACITORS)

22µF, 25V, X7R, 1210 GRM32ER71E226KE15L

100kΩ

VREG

C

SS

PANASONIC: (OUTPUT CAPACITORS)

180µF (SP-SERIES), 4V, 10mΩ, EEFUE0G181XR

C2

0.1µF

C1

1µF

34nF

INFINEON MOSFETs:

BSC042N03MS G (LOWER SIDE)

BSC080N03MS G (UPPER SIDE)

WÜRTH INDUCTORS:

0.47µH, 0.8mΩ, 30A, 744355147

Figure 94. Application Circuit for 5.5 V Input, 2.5 V Output, 12 A, 600 kHz (Q2/Q4 No Connect)

Rev. A | Page 37 of 40

ADP1878/ADP1879

Data Sheet

300 kHz HIGH CURRENT APPLICATION CIRCUIT

HIGH VOLTAGE INPUT

= 13V

V

IN

JP3

C

22µF

C3

22µF

C4

22µF

C5

22µF

C6

22µF

C7

22µF

C8

N/A

C9

N/A

VIN

C

560pF

R

C

ADP1878/

ADP1879

C

100nF

BST

C

56pF

PAR

C

1

2

3

14

13

12

Q1

Q3

Q2

VIN

BST

49.3kΩ

COMP

EN

SW

1.2µH

V

= 1.8V, 12A

+

C23

OUT

R7 10kΩ

2kΩ

V

DRVH

REG

+

R

C20

270µF

C21

270µF

C22

270µF

SNB

2Ω

R

TOP

270µF

V

Q4

4

5

11

10

FB

PGND

DRVL

OUT

C

SNB

1.5nF

R

BOT

1kΩ

GND

+

C24

N/A

C25

N/A

C26

N/A

C27

N/A

C14 TO C19

N/A

5kΩ

6

7

9

8

RES

PGOOD

SS

V

REG

R

RES

MURATA: (HIGH VOLTAGE INPUT CAPACITORS)

22µF, 25V, X7R, 1210 GRM32ER71E226KE15L

100kΩ

VREG

C

SS

PANASONIC: (OUTPUT CAPACITORS)

270µF (SP-SERIES), 4V, 7mΩ, EEFUE0G271LR

C2

0.1µF

C1

1µF

34nF

INFINEON MOSFETs:

BSC042N03MS G (LOWER SIDE)

BSC080N03MS G (UPPER SIDE)

WÜRTH INDUCTORS:

1.2µH, 2mΩ, 20A, 744325120

Figure 95. Application Circuit for 13 V Input, 1.8 V Output, 12 A, 300 kHz (Q2/Q4 No Connect)

Rev. A | Page 38 of 40

Data Sheet

ADP1878/ADP1879

PACKAGING AND ORDERING INFORMATION

OUTLINE DIMENSIONS

3.40

3.30

3.15

4.10

4.00

3.90

0.10

REF

0.20 MIN

8

7

14

0.90

3.10

3.00

2.90

1.80

1.70

1.55

EXPOSED

PAD

REF

PIN 1 INDICATOR

(LASER MARKING)

0.30

REF

1

0.50

0.40

0.30

BOTTOM VIEW

TOP VIEW

SIDE VIEW

END VIEW

0.80

0.75

0.70

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

0.05 MAX

0.02 NOM

COPLANARITY

0.08

SECTION OF THIS DATA SHEET.

SEATING

PLANE

0.15 REF

0.30

0.50 BSC

0.25

0.20

COMPLIANT TO JEDEC STANDARDS MO-229-WEGD

Figure 96. 14-Lead Lead Frame Chip Scale Package [LFCSP_WD]

4 mm × 3 mm Body, Very Very Thin Dual

(CP-14-2)

Dimensions shown in millimeters

Rev. A | Page 39 of 40

ADP1878/ADP1879

Data Sheet

ORDERING GUIDE

Model¹

Temperature Range

Package Description

Package Option

CP-14-2

ADP1878ACPZ-0.3-R7

ADP1878ACPZ-0.6-R7

ADP1878ACPZ-1.0-R7

ADP1878-0.3-EVALZ

ADP1878-0.6-EVALZ

ADP1878-1.0-EVALZ

ADP1879ACPZ-0.3-R7

ADP1879ACPZ-0.6-R7

ADP1879ACPZ-1.0-R7

ADP1879-0.3-EVALZ

ADP1879-0.6-EVALZ

ADP1879-1.0-EVALZ

−40°C to +125°C

14-Lead Frame Chip Scale Package [LFCSP_WD]

Evaluation Board

CP-14-2

−40°C to +125°C

14-Lead Frame Chip Scale Package [LFCSP_WD]

Evaluation Board

CP-14-2

¹Z = RoHS Compliant Part.

registered trademarks are the property of their respective owners.

D09441-0-6/12(A)

www.analog.com/ADP1878/ADP1879

Rev. A | Page 40 of 40


型号：	IRF7811
厂家：	ADI
描述：	Synchronous Buck Controller 同步降压控制器控制器
文件：	总40页 (文件大小：2501K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

IRF7811 [ADI]

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