LTC3600 [ADI]
Quad 17V, 1.25A Parallelable Synchronous Step-Down Regulator with Ultralow Quiescent Current;
| 型号： | LTC3600 |
| 厂家： | 
ADI |
| 描述： | Quad 17V, 1.25A Parallelable Synchronous Step-Down Regulator with Ultralow Quiescent Current |
| 文件： | 总20页 (文件大小：1547K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC3644/LTC3644-2
Quad 17V, 1.25A Parallelable Synchronous Step-
Down Regulator with Ultralow Quiescent Current
FEATURES
DESCRIPTION
n
n
n
n
Quad Step-down Outputs: 1.25A per Channel
Wide V Range: 2.7V to 17V
The LTC®3644/LTC3644-2 is a quad 1.25A output, high
efficiencysynchronousmonolithicstep-downregulatorcapable
of operating from input supplies up to 17V. The switching
frequency is internally fixed to 1MHz or 2.25MHz with a 50%
synchronizationrange.Theregulatorfeaturesultralowquiescent
IN
Wide V
Range: 0.6V to V
OUT
IN
1.25A/2.5A/3.75A/5A I
Configurable with
OUT
One Inductor
n
n
n
Integrated 300mΩ P-Channel/80mΩ N-Channel
MOSFETs Provide Up to 93% Efficiency
current and high efficiency over a wide V and V range.
IN OUT
The step-down regulator operates from an input voltage
range of 2.7V to 17V and provides an adjustable output
No-Load Burst Mode Operation I < 10µA with All
Q
Channels Enabled
range from 0.6V to V while delivering up to 1.25A of
IN
Constant Frequency (1MHz/2.25MHz) with 50%
Frequency Synchronization Range
1% Output Voltage Accuracy
output current per channel. LTC3644/LTC3644-2 can be
configuredforquad1.25Aoutputs,triple2.5A/1.25A/1.25A
outputs, dual 2.5A outputs, or dual 3.75A/1.25A outputs. A
user selectable mode input is provided to allow the user to
trade off ripple noise for light load efficiency; Burst Mode®
operationprovidesthehighestefficiencyatlightloads,while
forced-continuous mode provides the lowest ripple noise.
The regulators can be synchronized to an external clock.
n
n
Current Mode Operation for Excellent Line and Load
Transient Response
Full Dropout Operation (100% Duty Cycle)
Phase Shift Programmable with External Clock
5mm × 5mm × 1.72mm BGA Package
n
n
n
LTC3644 Options
APPLICATIONS
PART NAME
LTC3644
FREQUENCY
1.00MHz
V
OUT
n
Battery Powered Systems
Adjustable
Adjustable
n
Point-of-Load Supplies
LTC3644-2
2.25MHz
n
Portable – Handheld Scanners and Cameras
All registered trademarks and trademarks are the property of their respective owners. Protected
by U.S. patents, including 5481178, 6580258, 6498466, 6611131, 5705919.
TYPICAL APPLICATION
4-Channel 1.25A Quad-Output 1MHz Step-Down Regulator
ꢀ
Efficiency and Power Loss vs Load
at 1MHz in Burst Mode Operation
ꢀꢁ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀꢁꢂꢃ
ꢄꢄ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁ ꢂꢃ ꢄꢅꢁ
ꢀ
ꢃꢃꢄꢅ
ꢆꢇ
ꢁꢂ
ꢀꢁꢂꢃꢄꢅꢆꢇꢈ
ꢀ
ꢁꢀꢀ
ꢂ.ꢃꢄꢅ
ꢀ00
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
0
0.ꢀ
0.ꢀ
0.ꢀ
0.ꢀ
0.ꢀ
0.ꢀ
0.ꢀ
0
ꢀꢁ
ꢀ
ꢀ ꢁꢂꢃ
ꢀꢁ
ꢀꢁ
ꢀꢁꢂꢃꢄ
Rꢀꢁꢂ
Rꢀꢁꢂ
Rꢀꢁꢂ
Rꢀꢁꢂ
ꢀꢁꢁꢂꢃꢂꢀꢄꢃꢅ
ꢀꢁꢂꢂꢃꢄ
ꢀꢁꢂꢂꢃꢄ
ꢀꢁꢂꢂꢃꢄ
ꢀꢁꢂꢂꢃꢄ
ꢀꢁ
ꢂ.ꢂꢃꢄ
ꢀꢁ
ꢁ.ꢁꢂꢃ
ꢀ
ꢀ
ꢁꢂꢃꢄ
ꢁꢂꢃꢄ
ꢅ.ꢆꢀ ꢇꢃ ꢄ.ꢅꢆꢇ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂꢃR ꢄꢁꢅꢅ
ꢅ.ꢆꢀ ꢇꢃ ꢅ.ꢈꢉꢇ
ꢀ
ꢀ
ꢁꢁꢂ
Rꢀ
Rꢀ
ꢁꢁꢂ
ꢃꢃꢄꢁ
ꢀꢁꢂꢃꢄꢅꢅ
ꢃꢃꢄꢁ
ꢁꢀꢂꢃ
ꢁꢂꢃꢄ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀ
ꢀ
ꢅꢆꢇꢈ
ꢁꢂꢃꢄ
ꢅꢆꢇꢈ
ꢁꢂꢃꢄ
ꢀ
ꢀ
ꢀ
ꢀ ꢁ.0 ꢃ ꢄ ꢀ ꢅ.ꢆꢇꢈ
ꢀ ꢁ.ꢁ ꢃ ꢄ ꢀ ꢅ.ꢆꢇꢈ
ꢀ ꢁ.ꢂ ꢄ ꢅ ꢀ ꢆ.ꢆꢇꢈ
Rꢀ
ꢁꢂꢃꢄ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
Rꢀ
ꢁ0ꢂꢃ
ꢀꢁ
ꢂ.ꢃꢄꢅ
ꢀꢁ
ꢂ.ꢃꢄꢅ
0.00
0.ꢀꢁ
0.ꢀ0
0.ꢀꢁ
ꢀ.00
ꢀ.ꢁꢂ
ꢀ
ꢁꢂꢃꢄ
ꢅ.ꢅꢀ ꢆꢃ ꢇ.ꢄꢈꢆ
ꢀ
ꢁꢂꢃꢄ
ꢅꢀ ꢆꢃ ꢇ.ꢈꢅꢆ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂꢃ ꢄꢅRRꢆꢇꢈ ꢉꢂꢊ
ꢀ
Rꢀ
ꢁꢂꢃꢄ
ꢀ
ꢁꢁꢂ
ꢁꢁꢂ
ꢂꢂꢃꢁ
ꢀꢁꢂꢂ ꢃꢄ0ꢅꢆ
Rꢀ
ꢁꢂꢃꢄ
ꢃꢃꢄꢁ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀ
ꢅꢆꢇꢈ
ꢀ
ꢁꢂꢃꢄ
ꢁꢂꢃꢄ
Rꢀ
ꢀꢁ.ꢂꢃ
Rꢀ
ꢁꢂꢃꢄ
ꢄꢅꢆꢇ
ꢀꢁꢂ
ꢀꢁꢂꢂ ꢃꢄ0ꢅꢆ
Rev. 0
1
Document Feedback
For more information www.analog.com
LTC3644/LTC3644-2
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Note 1)
ꢟꢝꢍ ꢜꢛꢁꢚ
V
, V , V , V , SV .......................... –0.3V to 17V
IN
IN1 IN2 IN3 IN4
ꢇ
ꢆ
ꢉ
ꢈ
ꢊ
ꢋ
RUN1, RUN2, RUN3, RUN4.................–0.3V to SV + 0.3V
MODE/SYNC, FB1, FB2, FB3, FB4 ....–0.3V to INTV + 0.3V
IN
CC
ꢂ
ꢃ
ꢄ
ꢅ
ꢁ
ꢀ
ꢀꢁꢂ ꢀꢁꢂꢃ
ꢀꢁꢂ ꢀꢁꢂ ꢀꢁ
ꢀꢁꢂ
ꢄꢄ
ꢂꢃ
PGOOD1, PGOOD2, PGOOD3, PGOOD4, PHASE .. –0.3V to 6V
Operating Junction Temperature Range
(Note 2).................................................. –40°C to 125°C
Storage Temperature Range .................. –65°C to 150°C
Peak Solder Reflow Body Temperature.................260°C
ꢀ
ꢁꢂꢃ
ꢀꢁꢂꢂꢃꢄ ꢀꢁꢂ ꢀꢁꢂ ꢀꢁꢂꢂꢃꢄ ꢀ
ꢁꢂꢃ
ꢀꢁꢂ Rꢀꢁꢂ ꢀꢁꢂ ꢀꢁꢂ Rꢀꢁꢂ ꢀꢁꢂ
ꢀꢁꢂ ꢀꢁꢂꢃꢄꢅꢆꢇꢈ ꢀꢁꢂ ꢀꢁꢂ ꢀꢁꢂꢃꢄ ꢀꢁꢂ
ꢀ
ꢁꢂꢃ
ꢀꢁꢂꢂꢃꢄ ꢀꢁꢂ ꢀꢁꢂ ꢀꢁꢂꢂꢃꢄ ꢀ
ꢁꢂꢃ
ꢀꢁꢂ Rꢀꢁꢂ ꢀꢁꢂ ꢀꢁꢂ Rꢀꢁꢂ ꢀꢁꢂ
ꢃꢌꢂ ꢍꢂꢄꢎꢂꢌꢁ
ꢉꢋꢏꢃꢂꢐꢐ ꢑꢊꢒꢒ ꢓ ꢊꢒꢒ ꢓ ꢇ.ꢔꢆꢒꢒꢕ
θ
ꢖꢂ
ꢗ ꢆꢊꢘꢄꢙꢚ
θ
ꢅꢁRꢛꢜꢁꢅ ꢀRꢝꢞ ꢐꢟꢄꢉꢋꢈꢈ ꢅꢁꢞꢝ ꢃꢝꢂRꢅ
ꢖꢂ
θ
ꢗ ꢆꢣ.ꢤꢘꢄꢙꢚꢥ θ
ꢗ ꢋ.ꢇꢘꢄꢙꢚ
ꢖꢄꢠꢡꢢ
ꢖꢄꢦꢡꢠꢠꢡꢒ
θ
ꢂꢧꢅ θ
ꢂRꢁ ꢅꢁꢟꢁRꢞꢛꢧꢁꢅ ꢃꢨ ꢩꢛꢞꢪꢐꢂꢟꢛꢝꢧ ꢍꢁR
ꢖꢁꢩꢅꢊꢇ ꢄꢝꢧꢅꢛꢟꢛꢝꢧ
ꢖꢄꢠꢡꢢ
ꢖꢄꢦꢡꢠꢠꢡꢒ
ORDER INFORMATION
PART MARKING*
PACKAGE
TYPE
MSL
TEMPERATURE RANGE
PART NUMBER
TERMINAL FINISH
SAC305(RoHS)
SAC305(RoHS)
SAC305(RoHS)
SAC305(RoHS)
DEVICE
3644Y
FINISH CODE
RATING
(SEE NOTE 2)
LTC3644EY#PBF
LTC3644IY#PBF
LTC3644EY-2#PBF
LTC3644IY-2#PBF
e1
e1
e1
e1
BGA
BGA
BGA
BGA
3
3
3
3
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
3644Y
3644Y2
3644Y2
• Device temperature grade is indicated by a label on the shipping container.
• Pad or ball finish code is per IPC/JEDEC J-STD-609.
• BGA Package and Tray Drawings
• This product is moisture sensitive. For more information, go
to Recommended BGA PCB Assembly and Manufacturing
Procedures.
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°C (Note 2). SVIN = VIN1 = VIN2 = VIN3 = VIN4 = 12V, unless
otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
2.7
TYP
MAX
UNITS
V
V
, SV
Operating Voltage
Output Voltage
17
V
V
INX
IN
0.6
V
IN
OUT
I
Q
Input Quiescent Current
Forced Continuous Mode (Note 3)
Burst Mode, No Load
5
10
0.1
8
14
1
mA
µA
µA
Shutdown Mode; V
= V
= V
RUN2 RUN3
RUN1
= V
= 0V
RUN4
l
V
Regulated Feedback Voltage
FB Input Current
0.594
0.6
0.606
10
V
nA
FB
I
FB
Reference Voltage Line Regulation
Output Voltage Load Regulation
SV = 2.7V to 17V (Note 4)
0.01
0.1
0.025
0.3
%/V
IN
(Note 4)
%
Rev. 0
2
For more information www.analog.com
LTC3644/LTC3644-2
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°C (Note 2). SVIN = VIN1 = VIN2 = VIN3 = VIN4 = 12V, unless
otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
NMOS Switch Leakage
PMOS Switch Leakage
0.1
0.1
1
1
µA
µA
R
NMOS On Resistance
PMOS On Resistance
80
300
mΩ
mΩ
DS(ON)
t
Minimum On Time
(Note 6)
60
ns
V
ON(MIN)
V
RUN Input High
RUN Input Low
1.0
RUN
0.35
1.0
RUN Input Current
V
RUN
= 12V
0.1
10
nA
V
Pulse-Skipping Mode
Forced Continuous Mode
Burst Mode Operation
0.3
V
V
V
MODE/SYNC
V
V
– 1.2
INTVCC
V
V
– 0.4
+ 0.3V
INTVCC
INTVCC
MODE/SYNC Input Current
PHASE Input Threshold
0.1
100
nA
Input Low
Input High
0.4
V
V
– 0.4
INTVCC
PHASE Input Current
Internal Soft Start Time
Peak Current Limit
V
= 6V
0.1
1.1
100
nA
PHASE
t
I
ms
SS
1.25A Regulator
2.5A Regulator (2-Channel Combined)
3.75A Regulator (3-Channel Combined)
1.8
2.2
4.4
6.6
2.6
A
A
A
LIM
V
Undervoltage Lockout
SV Ramping Up
IN
2.35
18
2.5
250
19
2.65
20
V
mV
V
INTVCC
V
Undervoltage Lockout Hysteresis
INTVCC
l
V
V
Overvoltage Lockout Rising
IN
IN
Overvoltage Lockout Hysteresis
400
mV
l
l
f
Oscillator Frequency
LTC3644-2
LTC3644
1.8
0.82
2.25
1.00
2.60
1.16
MHz
MHz
OSC
SYNC Capture Range
% of Programmed Frequency
50
150
%
V
V
V
Voltage
SV > 5.5V
IN
5
INTVCC
INTVCC
Power Good Range
Power Good Resistance
PGOOD Delay
7.5
275
%
Ω
R
350
PGOOD
t
PGOOD Low to High
PGOOD High to Low
0
32
Cycles
Cycles
PGOOD
Phase Shift Between Channel 1/2 and
Channel 3/4
V
PHASE
V
PHASE
= 0V
0
180
Deg
Deg
= INTV , V
= 0V
CC MODE/SYNC
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
(T , in °C) is calculated from the ambient temperature (T , in °C) and
J A
power dissipation (P , in Watts) according to the formula:
D
T = T + (P • θ ),
J
A
D
JA
where θ (in °C/W) is the package thermal impedance.
JA
Note 2: The LTC3644/LTC3644-2 is tested under pulsed load conditions
Note 3: The quiescent current in active mode does not include switching
loss of the power FETs.
such that T ≈ T . The LTC3644E is guaranteed to meet specified
J
A
performance from 0°C to 85°C. Specifications over the –40°C to
125°C operating junction temperature range are assured by design,
characterization and correlation with statistical process controls. The
LTC3644I is guaranteed over the –40°C to 125°C operating junction
temperature range. Note that the maximum ambient temperature
consistent with these specifications is determined by specific operating
conditions in conjunction with board layout, the rated package thermal
impedance, and other environmental factors. The junction temperature
Note 4: The LTC3644 is tested in a proprietary test mode that connects
V
to the output of error amplifier.
FB
Note 5: This IC includes overtemperature protection that is intended to protect the
device during momentary overload conditions. Junction temperature will exceed
125°C when overtemperature protection is active. Continuous operation above the
specified maximum operating junction temperature may impair device reliability.
Note 6: The minimum on-time is determined by the speed of the top
switch driver and peak current comparator. The typical value listed here is
guaranteed by design.
Rev. 0
3
For more information www.analog.com
LTC3644/LTC3644-2
TA = 25°C, unless otherwise noted.
TYPICAL PERFORMANCE CHARACTERISTICS
Efficiency vs Load Current in
Burst Mode Operation
Efficiency vs Load Current in
Burst Mode Operation
Efficiency vs Load Current in
Burst Mode Operation
ꢀ00
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
0
ꢀ00
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
0
ꢀ00
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
0
ꢀ
ꢀ ꢁꢂꢃ
ꢀꢁ
ꢀ
ꢀ
ꢀ
ꢀ ꢁꢂꢃ
ꢀꢁꢂ
ꢀ ꢁ.ꢁꢂꢃꢄꢅ
ꢀꢁ
ꢀ
ꢀ ꢁꢂ
ꢀꢁꢂ
ꢀ ꢁꢂ
ꢀ
ꢀꢁ
ꢀ ꢁꢂꢃ
ꢀ ꢁ.ꢁꢂꢃꢄꢅ
ꢀꢁ
ꢀ
ꢀ ꢁꢂꢃꢄ
ꢀꢁ
ꢀ
ꢀꢁ
ꢀ.ꢁꢂꢃ ꢄꢅꢆꢇꢅ ꢈ ꢉ ꢊ ꢋ.ꢌꢍꢎ
ꢀ.ꢁ0ꢂ ꢃꢄꢅꢆꢄ ꢇ ꢈ ꢉ ꢀ.ꢀꢊꢋ
ꢀ.ꢁꢂꢃ ꢄꢅꢆꢇꢅ ꢈ ꢉ ꢊ ꢋ.ꢌꢍꢎ
ꢀ.ꢁꢂꢃ ꢄꢅꢆꢇꢅ ꢈ ꢉ ꢊ ꢁ.ꢁꢋꢌ
ꢀ.ꢁ0ꢂ ꢃꢄꢅꢆꢄ ꢇ ꢈ ꢉ ꢊ.ꢀꢋꢌ
ꢀ.ꢁꢂꢃ ꢄꢅꢆꢇꢅ ꢈ ꢉ ꢊ 0.ꢋꢌꢍꢎ
ꢀ
ꢀ
ꢀ
ꢀ ꢁ.0 ꢃ ꢄ ꢀ ꢅ.ꢅꢆꢇ
ꢀ ꢁ.ꢁ ꢃ ꢄ ꢀ ꢅ.ꢆꢇꢈ
ꢀ ꢁ.ꢂ ꢄ ꢅ ꢀ ꢆ.ꢁꢇꢈ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
0.00ꢀ
0.0ꢀ
0.ꢀ
ꢀ
ꢀ0
0.00ꢀ
0.0ꢀ
0.ꢀ
ꢀ
ꢀ0
0.00ꢀ
0.0ꢀ
0.ꢀ
ꢀ
ꢀ0
ꢀꢁꢂꢃ ꢄꢅRRꢆꢇꢈ ꢉꢂꢊ
ꢀꢁꢂꢃ ꢄꢅRRꢆꢇꢈ ꢉꢂꢊ
ꢀꢁꢂꢃ ꢄꢅRRꢆꢇꢈ ꢉꢂꢊ
ꢀꢁꢂꢂ ꢃ0ꢄ
ꢀꢁꢂꢂ ꢃ0ꢀ
ꢀꢁꢂꢂ ꢃ0ꢄ
Phase Shift with External Clock
Frequency Sync
180° Phase Operation
ꢀꢁꢂ
ꢀ0ꢁꢂꢃꢄꢁ
ꢀꢁꢂ
ꢀ0ꢁꢂꢃꢄꢁ
ꢀꢁꢂ ꢃꢄꢅ
ꢀꢁꢂꢃꢄꢁ
ꢀꢁꢂ
ꢀ0ꢁꢂꢃꢄꢁ
ꢀꢁꢂ
ꢀ0ꢁꢂꢃꢄꢁ
ꢀꢁꢂꢂ ꢃ0ꢂ
ꢀꢁꢂꢂ ꢃ0ꢄ
ꢀ00ꢁꢂꢃꢄꢅꢆ
ꢀ ꢁ.ꢂꢃ
ꢀ00ꢁꢂꢃꢄꢅꢆ
ꢀ
ꢀ ꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀ ꢁ.ꢂꢃꢄꢅ ꢆ ꢀ ꢁ.ꢁꢂꢃ
ꢀꢁ
ꢀ
ꢀ ꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢁ
ꢀ
ꢀ ꢁ.ꢁ ꢃ ꢂ
ꢀꢁꢂꢃ
ꢀ
ꢀ ꢁ.ꢁ ꢃ ꢂ
ꢀ ꢁ.ꢂꢃ
ꢀꢁꢂꢃ
ꢀ ꢁ.ꢂꢃꢄꢅ ꢆ ꢀ ꢁ.ꢁꢂꢃ
ꢀ
ꢀ
ꢀ
ꢊꢊ
ꢀ
ꢀ
ꢀ
ꢊꢊ
ꢀꢁꢂꢃꢄ ꢅ ꢆꢇꢈꢉ
ꢀꢁꢂꢃꢄ ꢅ ꢆꢇꢈꢉ
ꢀꢁꢂꢃꢄꢅꢆꢇꢈ ꢉ ꢃꢊꢋ ꢈꢌꢍ
ꢀꢁꢂꢃꢄꢅꢆꢇꢈ ꢉ ꢊ.ꢋꢌ
SW Leakage Current vs
Temperature
IQ vs Temperature
RDS(ON) vs Temperature
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
0
ꢀ00
ꢀ00
ꢀ00
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ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢇꢈꢉ
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ꢀꢁꢂꢂ ꢃ0ꢄ
ꢀꢁꢂꢂ ꢃ0ꢁ
Rev. 0
4
For more information www.analog.com
LTC3644/LTC3644-2
TA = 25°C, unless otherwise noted.
TYPICAL PERFORMANCE CHARACTERISTICS
Oscillator Frequency vs
Peak Current Limit vs
RDS(ON) vs Input Voltage
Temperature
Temperature
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ꢀ.ꢁ
ꢀ.ꢀ
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0.ꢀ
0.ꢀ
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0
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0
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0
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ꢀꢁꢂꢂ ꢃꢄ0
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Reference Voltage vs
Temperature
Line Regulation, No Load
Load Regulation
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0.ꢀ
0
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ꢀ0.ꢁ0
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ꢀ0.ꢁ
ꢀ0.ꢁ
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0
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0
0.ꢀꢁ
0.ꢀ0
0.ꢀꢁ
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0 ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ0ꢀꢀꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀꢁ
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ꢀꢁꢂꢃ ꢄꢅRRꢆꢇꢈ ꢉꢂꢊ
ꢀꢁꢂꢃꢄ ꢅꢆꢇꢄꢈꢉꢊ ꢋꢅꢌ
ꢀꢁꢂꢂ ꢃꢄꢅ
ꢀꢁꢂꢂ ꢃꢄꢂ
ꢀꢁꢂꢂ ꢃꢄꢀ
Rev. 0
5
For more information www.analog.com
LTC3644/LTC3644-2
TA = 25°C, unless otherwise noted.
Start-Up Operation
TYPICAL PERFORMANCE CHARACTERISTICS
Load Step at 1MHz
Load Step at 2.25MHz
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ꢀ0ꢁꢂꢃꢄꢅꢆ
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ꢀꢁ
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ꢀ ꢁꢂꢃꢄ
ꢀ ꢁ ꢂ.ꢂꢃꢄ
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ꢀ ꢁꢂꢃꢄ
ꢀ
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ꢀ
ꢀꢁꢂ
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Burst Mode Operation
Pulse-Skipping Operation
ꢀ
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ꢀ
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ꢀ0ꢁꢂꢃꢄꢅꢂ
ꢀꢁ
ꢀ0ꢁꢂꢃꢄꢁ
ꢀꢁ
ꢀ0ꢁꢂꢃꢄꢁ
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ꢀ00ꢁꢂꢃꢄꢅꢆ
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ꢀ
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ꢀꢁꢂꢃ
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ꢀꢁ
ꢀ ꢁ ꢂ.ꢃꢄꢅ
ꢀꢁ
ꢀ ꢁ ꢂ.ꢃꢄꢅ
PIN FUNCTIONS
FB1(A6):FeedbackInputtotheErrorAmplifierofChannel
1 Step-Down Regulator. Connect resistor divider tap to
this pin. The output voltage can be adjusted from 0.6V to
FB3 (F1): Feedback Input to the Error Amplifier of Channel
3Step-DownRegulator.Connectresistordividertaptothis
pin. The output voltage can be adjusted from 0.6V to V
IN
V by: V
= 0.6V • [1 + (R2/R1)].
by: V
= 0.6V • [1 + (R2/R1)]. Connecting this pin to
IN
OUT
OUT
INTV turnsthischannelintoaslavechanneltochannel4.
CC
FB2 (F6): Feedback Input to the Error Amplifier of Channel
2Step-DownRegulator.Connectresistordividertaptothis
FB4(A1):FeedbackInputtotheErrorAmplifierofChannel
4Step-DownRegulator.Connectresistordividertaptothis
pin. The output voltage can be adjusted from 0.6V to V
IN
by: V
= 0.6V • [1 + (R2/R1)]. Connecting this pin to
pin. The output voltage can be adjusted from 0.6V to V
OUT
IN
INTV turnsthischannelintoaslavechanneltochannel1.
by: V
= 0.6V • [1 + (R2/R1)]. Connecting this pin to
CC
OUT
INTV turnsthischannelintoaslavechanneltochannel1.
CC
Rev. 0
6
For more information www.analog.com
LTC3644/LTC3644-2
PIN FUNCTIONS
INTV (A2): Low Dropout Regulator. Bypass with a low
RUN1 (C5): Logic Controlled RUN Input to Channel 1.
Do not leave this pin floating. Logic High activates the
step-down regulator.
CC
ESR ceramic cap of at least 4.7µF to ground.
MODE/SYNC (D2): Burst Mode Select and External Clock
Synchronization of the Step-Down Regulator. Tie MODE/
RUN2 (F5): Logic Controlled RUN Input to Channel 2.
Do not leave this pin floating. Logic High activates the
step-down regulator.
SYNC to INTV for Burst Mode operation with a 550mA
CC
peak current clamp. Tie MODE/SYNC to GND for pulse
skipping operation, and tie MODE/SYNC to a voltage
RUN3 (F2): Logic Controlled RUN Input to Channel 3.
Do not leave this pin floating. Logic High activates the
step-down regulator.
between1VandINTV –1.2Vforforcedcontinuousmode.
CC
Furthermore, connecting this pin to an external clock will
synchronize the switch clock to the external clock and put
the part in forced continuous mode.
RUN4 (C2): Logic Controlled RUN Input to Channel 4.
Do not leave this pin floating. Logic High activates the
step-down regulator.
GND (A3, A4, B3, B4, C3, C4, D3, D4, E3, E4, F3, F4):
Groundbackplaneforpowerandsignalground.Thesepins
must be soldered to PCB ground for electrical contact and
ratedthermalperformance.ConnectallGNDpinstogether
with solid ground plane.
SV (A5): Signal V Pin. This input powers the INTV
IN
IN
CC
LDO. May be a different voltage than V , V , V
IN1
IN2
IN3
or V
Connect SV to whichever V is highest; for
IN4.
IN INX
applications where it is not known which V is highest,
IN
PHASE (D5): Phase Select Pin. Do not leave this pin
floating. Tie this pin to GND to run the regulators in phase
(0 degrees phase shift) between the SW rising edge of
connect external diode between SV to all V to ensure
IN
INX
that SV is less than a diode drop from the highest V .
IN
IN
SW1 (C6): Switch Node Connection to the Inductor of
Channel 1 Step-Down Regulator.
channel 1/2 and channel 3/4. Tie this pin to INTV to
CC
set 180 degrees phase shift between channel 1/2 and
channel 3/4. When this pin is high, the phase shift may
also be set by modulating the duty cycle of external clock
on the MODE/SYNC pin (channel 1/2 edge synced to
rising edge of clock, channel 3/4 edge synced to falling
edge of clock). For 5A output configuration, this pin
must be tied to ground. See the Applications Information
section for more details.
SW2 (D6): Switch Node Connection to the Inductor of
Channel 2 Step-Down Regulator.
SW3 (D1): Switch Node Connection to the Inductor of
Channel 3 Step-Down Regulator.
SW4 (C1): Switch Node Connection to the Inductor of
Channel 4 Step-Down Regulator.
PGOOD1 (B5): Open Drain Power Good Indicator for
Channel 1.
V
(B6):InputVoltageofChannel1Step-DownRegulator.
IN1
May be a different voltage than other channels’ V .
IN
PGOOD2 (E5): Open Drain Power Good Indicator for
Channel 2.
V
(E6):InputVoltageofChannel2Step-DownRegulator.
IN2
May be a different voltage than other channels’ V .
IN
PGOOD3 (E2): Open Drain Power Good Indicator for
Channel 3.
V
(E1):InputVoltageofChannel3Step-DownRegulator.
IN3
May be a different voltage than other channels’ V .
IN
PGOOD4 (B2): Open Drain Power Good Indicator for
Channel 4.
V
(B1):InputVoltageofChannel4Step-DownRegulator.
IN4
May be a different voltage than other channels’ V .
IN
Rev. 0
7
For more information www.analog.com
LTC3644/LTC3644-2
BLOCK DIAGRAM
Rev. 0
8
For more information www.analog.com
LTC3644/LTC3644-2
OPERATION
The LTC3644/LTC3644-2 is a quad high efficiency
monolithic step-down regulator, which uses a constant
frequency, peak current mode architecture. It operates
Tooptimizeefficiency,BurstModeoperationcanbeselected
by tying the MODE/SYNC pin to INTV . In Burst Mode
CC
operation, the peak inductor current is set to be at least
550mA, even if the output of the error amplifier demands
less.Thus,whentheswitcherisonatrelativelylightoutput
loads, FB voltage will rise and cause the ITH voltage to
drop. Once the ITH voltage goes below 0.2V, the switcher
goes into sleep mode with both power switches off. The
switchers remain in this sleep state until the external load
pulls the output voltage below its regulation point. When
all channels are in sleep mode, the part draws an ultralow
through a wide V range and regulates with ultralow
IN
quiescent current. The operation frequency is set at either
1MHz or 2.25MHz and can be synchronized to an external
oscillator 50% of the inherent frequency. To suit a variety
of applications, the selectable MODE/SYNC pin allows the
user to trade off output ripple for efficiency.
For each channel, the output voltage is set by an external
dividerreturnedtotheFBpin. Anerroramplifiercompares
the divided output voltage with a reference voltage of
0.6V and adjusts the peak inductor current accordingly.
Overvoltage and undervoltage comparators pull the
PGOOD output low if the output voltage is not within 7.5%
of the programmed value. The PGOOD output goes high
immediately after achieving regulation and goes low 32
clock cycles after falling out of regulation.
10µA of quiescent current from SV .
IN
To minimize V
ripple, pulse-skipping mode can be
OUT
selected by grounding the MODE/SYNC pin. In LTC3644,
pulse-skipping mode is implemented similarly to Burst
Mode operation with the peak inductor current set to be at
least90mA. ThisresultsinlowerripplethaninBurstMode
operation with the trade-off of slightly lower efficiency.
Main Control Loop
Forced Continuous Mode Operation
Duringnormaloperation,thetoppowerswitch(P-channel
MOSFET)isturnedonatthebeginningofaclockcycle.The
inductorcurrentisallowedtorampuptoapeaklevel.Once
the level is reached, the top power switch is turned off and
the bottom switch (N-channel MOSFET) is turned on until
the next clock cycle. The peak current level is controlled
by the internally compensated ITH voltage, which is the
output of the error amplifier. This amplifier compares the
FB voltage to the 0.6V internal reference. When the load
current increases, the FB voltage decreases slightly below
the reference, which causes the error amplifier to increase
the ITH voltage until the average inductor current matches
the new load current.
The LTC3644 also has the ability to operate in the forced
continuous mode by setting the MODE/SYNC voltage
between1VandV
–1.2V.Inforcedcontinuousmode,
INTVCC
the switcher switches cycle by cycle regardless of what
the output load current is. If forced continuous mode is
selected, the minimum peak current is set to be –250mA
in order to ensure that the part can operate continuously
at zero output load.
High Duty Cycle/Dropout Operation
Whentheinputsupplyvoltagedecreasestowardstheoutput
voltage, the duty cycle increases and slope compensation
is required to maintain the fixed switching frequency. The
LTC3644 has internal circuitry to accurately maintain the
The main control loop is shut down by pulling the RUN
pin to ground.
peak current limit (I ) of 2.2A even at high duty cycles.
LIM
As the duty cycle approaches 100%, the LTC3644 enters
dropoutoperation.Duringdropout,thetopPMOSswitchis
turnedoncontinuously,andallactivecircuitryiskeptalive.
Low Current Operation
Twodiscontinuousconductionmodes(DCM)areavailable
to control the operation of the LTC3644 at low currents.
Both modes, Burst Mode operation and pulse-skipping
mode, automatically switch from continuous operation to
the selected mode when the load current is low.
Rev. 0
9
For more information www.analog.com
LTC3644/LTC3644-2
OPERATION
V Overvoltage Protection
IN
(channel 1,2 edge synced to the rising edge of the external
clock, channel 3,4 edge synced to the falling edge of the
external clock), while keeping the PHASE pin voltage tied
In order to protect the internal power MOSFET devices
against transient voltage spikes, the LTC3644 constantly
to INTV . Figure 2 shows a 90° phase shift between
CC
monitors the V
pins for an overvoltage condition.
INX
channels 1, 2 and channels 3,4. Table 1 shows the phase
options set by the PHASE and MODE/SYNC pins.
When V rises above 19V, the corresponding regulator
INX
suspends operation by shutting off both power MOSFETs.
Once V drops below 18.6V, the regulator immediately
INX
resumes normal operation. The regulators execute soft-
ꢀꢁꢂ ꢃꢄꢅ
ꢀꢁꢂꢃꢄꢁ
start function when exiting an overvoltage condition.
Low Supply Operation
ꢀꢁꢂ
ꢀ0ꢁꢂꢃꢄꢁ
To ensure that the regulators will operate properly, the
LTC3644incorporatesanundervoltagelockoutcircuitthat
ꢀꢁꢂ
ꢀ0ꢁꢂꢃꢄꢁ
shuts down all channels if SV drops below 2.25V. Once
IN
ꢀꢁꢂꢂ ꢃ0ꢄ
ꢀ00ꢁꢂꢃꢄꢅꢆ
SV rises above this lower limit, all switchers will resume
IN
normal operation if their respective RUN pins are enabled.
Figure 2. 90° Phase Shift Set by External Clock
However, the R
of the top and bottom switch of each
DS(ON)
Table 1. Phase Selection
channels will be slightly higher than that specified in the
No External CLK
External CLK
electrical characteristics due to lack of gate drive. Refer
PHASE = 0
0 degrees phase shift
180 degrees phase shift
0 degrees phase shift
to graph of R
versus V for more details.
IN
DS(ON)
PHASE = INTV
Phase shift determined by
clock edges
CC
Phase Selection
Channels1,2andchannels3,4oftheLTC3644canoperate
in phase or 180° out-of-phase (anti-phase) depending on
whether the PHASE pin is low or high, respectively. Anti-
phase generally reduces input voltage and current ripple.
Crosstalk between switch nodes SWx and components
or sensitive lines connected to FBx can sometimes cause
unstable switching waveforms and unexpectedly large
input and output voltage ripple.
Soft-Start
The LTC3644 has an internal 1.1ms soft-start ramp for
each channel. During soft-start operation, the switcher
operates in pulse-skipping mode regardless of the mode
programmed on the MODE/SYNC pin. Once the soft start
period is complete, the part will transition into the desired
mode of operation.
Crosstalk can generally be avoided by carefully choosing
the phase shift such that the SW edges do not coincide.
Depending on the duty cycle of the two channels, choose
the phase option that keeps the SWx edges as far away
from each other as possible. However, there are often
situations where this is unavoidable, such as when all
channels are operating at near 50% duty cycle. In such
cases, the optimized phase shift can be set by modulating
the duty cycle of an external clock on the MODE/SYNC pin
Regulators with Combined Power Stages
The LTC3644 can be configured as quad 1.25A outputs,
triple 2.5A/1.25A/1.25A outputs, dual 2.5A outputs using
onlyoneinductorperoutput,ordual3.75A/1.25Aoutputs.
ByconnectingV
andV
together,SW1,2andSW3,4
IN1,2
IN3,4
together, andconnectingFB2andFB3toINTV , LTC3644
CC
supports dual 2.5A outputs using only one inductor per
output.Evenmore,byconnectingV
together,SW1,2,4
IN1,2,4
together, and FB2, FB4 to INTV , LTC3644 supports
CC
3.75A/1.25A outputs.
Rev. 0
10
For more information www.analog.com
LTC3644/LTC3644-2
APPLICATIONS INFORMATION
Output Voltage Programming
performance.FortheLTC3644/LTC3644-2,aminimumC
OUT
of47μFisrecommendedtoensureloopstabilityforV lower
OUT
The output voltage is set by external resistive divider
according to the following equation:
than2V.Forgoodstartingvalues,seetheTypicalApplication
section.
R2
R1
⎛
⎝
⎞
VOUT = 0.6V • 1+
Use X5R or X7R types. This choice will provide low
output ripple and good transient response. Transient
performance can be improved with a higher value output
capacitor and the addition of a feedforward capacitor
⎜
⎟
⎠
The resistive divider allows the FB pin to sense a fraction
of the output voltage as shown in Figure 3.
placed between V
and FB. Increasing the output
OUT
ꢀ
ꢁꢂꢃ
capacitance will also decrease the output voltage ripple.
A lower value of output capacitor can be used to save
space and cost but transient performance will suffer and
may cause loop instability. See the Typical Applications
in this data sheet for suggested capacitor values.
Rꢆ
Rꢇ
ꢄ
ꢅꢅ
ꢅꢋ
ꢏꢃꢄꢈꢉꢊꢊ
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When choosing a capacitor, special attention should be
giventothedatasheettocalculatetheeffectivecapacitance
undertherelevantoperatingconditionsofvoltagebiasand
temperature. A physically larger capacitor or one with a
higher voltage rating may be required.
ꢈꢉꢊꢊ ꢅ0ꢈ
Figure 3. Setting the Output Voltage
Input Capacitor (C ) Selection
IN
The LTC3644 has individual input supply pins for each
Ceramic Capacitors
buck switching regulator and a separate SV pin that
IN
Ceramic capacitors are small, robust and have very low
ESR. However, ceramic capacitors can cause problems
when used with the LTC3644 due to their piezoelectric
nature. When in Burst Mode operation, the LTC3644’s
switching frequency depends on the load current, and
at very light loads the LTC3644 can excite the ceramic
capacitor at audio frequencies, generating audible noise.
SincetheLTC3644operatesatalowercurrentlimitduring
Burst Mode operation, the noise is typically very quiet to a
casual ear. If this is unacceptable, use a high performance
tantalum or electrolytic capacitor at the output. Low noise
ceramic capacitors are also available.
supplies power to all top level control and logic. Each of
these pins must be decoupled with low ESR capacitors
to GND. These capacitors must be placed as close to
the pins as possible. Ceramic dielectric capacitors are a
good compromise between high dielectric constant and
stability versus temperature and DC bias. Note that the
capacitance of a capacitor deteriorates at higher DC bias.
It is important to consult manufacturer data sheets and
obtain the true capacitance of a capacitor at the DC bias
voltage it will be operated at. For this reason, avoid the
use of Y5V dielectric capacitors. The X5R/X7R dielectric
capacitors offer good overall performance.
Output Power Good
Output Capacitor (C ) Selection
OUT
WhentheLTC3644’soutputvoltagesarewithinthe 7.5%
windowoftheregulationpoint,theoutputvoltagesaregood
andthePGOODpinsarepulledhighwithexternalresistors.
Otherwise, internal open-drain pull-down devices (275Ω)
willpullthePGOODpinslow.TopreventunwantedPGOOD
The output capacitor has two essential functions. Along
with the inductor, it filters the square wave generated by the
LTC3644toproducetheDCoutput. Inthisroleitdetermines
the output ripple, thus low impedance at the switching
frequency is important. The second function is to store
energy in order to satisfy transient loads and stabilize the
LTC3644’s control loop. Ceramic capacitors have very low
equivalentseriesresistance(ESR)andprovidethebestripple
glitches during transients or dynamic V
changes, the
OUT
LTC3644’s PGOOD falling edge includes a blanking delay
of approximately 32 switching cycles.
Rev. 0
11
For more information www.analog.com
LTC3644/LTC3644-2
APPLICATIONS INFORMATION
Frequency Sync Capability
inductor ripple current and consequently output voltage
ripple. Do not allow the core to saturate!
The LTC3644 has the capability to sync to a 50% range
of the internal programmed frequency. Once engaged in
sync, the LTC3644 immediately runs at the external clock
frequency in forced continuous mode.
Different core materials and shapes will change the size/
current and price/current relationship of an inductor.
Toroid or shielded pot cores in ferrite or permalloy
materials are small and don’t radiate much energy, but
generally cost more than powdered iron core inductors
with similar characteristics. The choice of which style
inductor to use mainly depends on the price versus size
requirements and any radiated field/EMI requirements.
New designs for surface mount inductors are available
fromCoilcraft,Murata,Vishay,TDKandWürthElektronik.
Refer to Table 2 to Table 4 for more details.
Inductor Selection
Given the desired input and output voltages, the inductor
valueandoperatingfrequencydeterminetheripplecurrent:
⎛
⎞
VOUT
f•L
VOUT
ΔIL =
1−
⎜
⎟
V
⎝
⎠
IN(MAX)
Lower ripple current reduces power losses in the inductor,
ESR losses in the output capacitors and output voltage
ripple. Highest efficiency operation is obtained at low
frequency with small ripple current. However, achieving
this requires a large inductor. There is a trade-off between
component size, efficiency and operating frequency.
Efficiency Considerations
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Percent efficiency can
be expressed as:
A reasonable starting point is to choose a ripple current
this is about 40% of I
. When calculating the
OUT(MAX)
refers to the maximum output
ripple current, I
OUT(MAX)
% Efficiency = 100% - (L1 + L2 + L3 + …)
current of the regulator, not the maximum load current of
the intended application. To guarantee that ripple current
does not exceed a specified maximum, the inductance
should be chosen according to:
where L1, L2 etc. are the individual losses as a percentage
of input power. Although all dissipative elements in the
circuitproducelosses, threemainsourcesintheLTC3644
2
circuit are: 1) I R losses, 2) switching and biasing losses,
⎛
⎞
VOUT
f•ΔIL(MAX)
VOUT
V
IN(MAX)
3) other losses.
L =
1−
⎜
⎟
⎝
⎠
2
1. I R losses are calculated from the DC resistances
of the internal switches, R , and external inductor,
SW
Once the value for L is known, the type of inductor must
be selected. Actual core loss is independent of core size
for a fixed inductor value, but is very dependent on the
inductance selected. As the inductance or frequency
in-creases, core loss decrease. Unfortunately, increased
inductance requires more turns of wire and therefore
copper losses increase.
R . In continuous mode, the average output current
L
flows through inductor L but is “chopped” between
theinternaltopandbottompowerMOSFETs.Thus,the
series resistance looking into the SW pin is a function
of both the top and bottom MOSFET R
duty cycle (DC) as follows:
and the
DS(ON)
R
= (R
)(DC)+(R
)(1 – DC)
SW
DS(ON)TOP
DS(ON)BOT
Ferritedesignshaveverylowcorelossesandarepreferred
at high switching frequencies, so design goals can
concentrate on copper loss and preventing saturation.
Ferrite core material saturates “hard,” which means that
the inductance collapses abruptly when the peak design
current is exceeded. This results in an abrupt increase in
TheR
forboththetopandbottomMOSFETscanbe
DS(ON)
obtainedfromtheTypicalPerformanceCharacteristics
2
curves. Thus to obtain I R losses:
2
2
I R losses = I
(R + R )
SW L
OUT
Rev. 0
12
For more information www.analog.com
LTC3644/LTC3644-2
APPLICATIONS INFORMATION
Table 2. Recommended Inductors for 1.25A Buck Regulators
PART NUMBER
L (μH)
1.5
MAX DCR (mΩ)
MAX I (A)
SIZE IN mm (L × W × H)
MANUFACTURER
Murata
DC
DFE201612E1R5MP2
74438356015
72
15
3.2
5.8
3.3
5.6
5.5
3.6
5.2
2 × 1.6 × 1.2
4.1 × 4.1 × 2.1
3 × 3 × 0.8
1.5
Wurth Elektronik
Vishay
IHLP1212BZER2R2M11
XAL4020222ME
2.2
42.9
35.2
26
2.2
4 × 4 × 2.1
Coilcraft
XAL4030332ME
3.3
4 × 4 × 3.1
Coilcraft
74438356033
3.3
39.9
54
4.1 × 4.1 × 2.1
5.2 × 5.2 × 3
Wurth Elektronik
Vishay
IHLP2020CZER4R7M11
4.7
Table 3. Recommended Inductors for 2.5A Buck Regulators
PART NUMBER
XAL4020102ME
74437324010
L (μH)
1
MAX DCR (mΩ)
MAX I (A)
SIZE IN mm (L × W × H)
4 × 4 × 2.1
MANUFACTURER
Coilcraft
DC
13.25
27
8.7
5
1
4.5 × 4.1 × 1.8
4 × 4 × 2.1
Wurth Elektronik
Coilcraft
XAL4020152ME
74438356022
1.5
2.2
2.2
3.3
21.45
29
7.1
4.7
5.5
7.3
4.1 × 4.1 × 2.1
5.2 × 5.2 × 3
Wurth Elektronik
Vishay
IHLP2020CZER2R2M11
SPM6530T3R3M
22.5
27
7.1 × 6.5 × 3
TDK
Table 4. Recommended Inductors for 3.75A Buck Regulators
PART NUMBER
L (μH)
0.6
0.68
0.82
1
MAX DCR (mΩ)
MAX I (A)
SIZE IN mm (L × W × H)
4 × 4 × 2.1
MANUFACTURER
Coilcraft
DC
XAL4020601ME
744383560068
9.5
7.5
10.4
9.4
4.1 × 4.1 × 2.1
4 × 4 × 2.1
Wurth Elektronik
Coilcraft
XEL4020821ME
IHLP2020CZER1E0M11
FDV0530H1R0M
SPM5030T2R2MHZ
11.8
10
10.2
6.5
5.2 × 5.2 × 3
6.2 × 5.8 × 3
5.2 × 5 × 3
Vishay
1
11.2
19.3
8.4
Murata
2.2
8.5
TDK
2. The switching current is the sum of the MOSFET
driverandcontrolcurrents.ThepowerMOSFETdriver
current results from switching the gate capacitance of
the power MOSFETs. Each time a power MOSFET gate
is switched from low to high to low again, a packet of
The gate charge loss is proportional to V and f
IN OSC
and thus their effects will be more pronounced at
higher supply voltages and higher frequencies.
3. Other“hidden”lossessuchastransitionlossandcopper
trace and internal load resistances can account for
additional efficiency degradations in the overall power
system. It is very important to include these “system”
level losses in the design of a system. Transition loss
arises from the brief amount of time the top power
MOSFET spends in the saturated region during
switch node transitions. The LTC3644 internal power
devices switch quickly enough that these loses are not
significant compared to other sources. These losses
plus other losses, including diode conduction losses
charge dQ moves from V to ground. The resulting
IN
dQ/dt is a current out of V that is typically much
IN
larger than the DC control bias current. In continuous
mode, I
= f (Q + Q ), where Q and Q are
GATECHG OSC
the gate charges of the internal top and bottom power
T B T B
MOSFETs and f is the switching frequency. The
power loss is thus:
OSC
Switching Loss = I
• V
GATECHG
IN
Rev. 0
13
For more information www.analog.com
LTC3644/LTC3644-2
APPLICATIONS INFORMATION
during dead-time and inductor core losses, generally
account for less than 2% total additional loss.
For the BGA package, the θ is 25°C/W as measured
JA
on the LTC3644 demo board. Therefore, the junction
temperature of the regulator operating at 25°C ambient
temperature is approximately:
Thermal Conditions
In a majority of applications, the LTC3644 does not
dissipate much heat due to its high efficiency. However,
in applications where the LTC3644 is running at high
T = 349mW • 25°C/W + 25°C = 33.7°C
J
Remembering that the above junction temperature is
obtained from an R
at 25°C, we might recalculate
DS(ON)
ambient temperature, high V , high switching frequency,
IN
the junction temperature based on a higher R
since
DS(ON)
andmaximumoutputcurrentload,theheatdissipatedmay
exceed the maximum junction temperature of the part. If
the junction temperature reaches approximately 160°C,
all power switches will be turned off until the temperature
drops about 15°C cooler.
it increases with temperature. Redoing the calculation
assuming that R increased 5% at 33.7°C yields a new
SW
junction temperature of 34.1°C. If the application calls
for a higher ambient temperature and/or higher switching
frequency, care should be takentoreducethe temperature
rise of the part by using a heat sink or airflow.
To avoid the LTC3644 from exceeding the maximum
junction temperature, the user need to do some thermal
analysis. The goal of the thermal analysis is to determine
whether the power dissipated exceeds the maximum
junction temperature of the part. The temperature rise is
given by:
Board Layout Considerations
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the LTC3644 (refer to Figure 4). Check the following in
the layout:
T
RISE
= P • θ
D JA
As an example, consider the case when the LTC3644 is
used in applications whereV = 12V, I = I = I
1. Do the capacitors C connect to the V and GND as
IN IN
close as possible? These capacitors provide the AC
currenttotheinternalpowerMOSFETsandtheirdrivers.
IN
OUT1 OUT2 OUT3
= 1.8V. The equivalent
= I
= 0.8A, f = 1MHz, V
OUT4
OUT
power MOSFET resistance R is:
Does C connect to INTV as close as possible?
VCC CC
SW
2. Are C
and L closely connected? The (–) plate of
⎛
⎞
VOUT
VOUT
OUT
R
SW =RDS(ON)TOP
•
+RDS(ON)BOT • 1−
⎜
⎟
C
returns current to GND and the (–) plate of C .
OUT
IN
V
V
⎝
⎠
IN
IN
3. The resistive divider, R1 and R2, must be connected
1.8V
12V
1.8V
12V
⎛
⎝
⎞
⎟
⎠
= 300mΩ•
=113mΩ
+80mΩ• 1−
⎜
between the (+) plate of C
and a ground line
OUT
terminated near GND. The feedback signal V should
FB
be routed away from noisy components and traces,
such as the SW line, and its trace length should be
minimized. Keep R1 and R2 close to the IC.
The active current through V at 1MHz without load is
IN
about 5mA, which includes switching and internal biasing
currentloss,andtransitionloss.Therefore,thetotalpower
dissipated by the part is:
4. KeepsensitivecomponentsawayfromtheSWpin.The
input capacitor, C , feedback resistors, and INTV
IN
CC
bypass capacitors should be routed away from the
2
P = 4 • I
• R + V • I
SW IN IN(Q)
D
OUT
SW trace and the inductor.
2
= 4 • 0.8A • 113mΩ + 12V • 5mA
= 349mW
5. Agroundplaneispreferred.Useseveralviasconnected
to ground on the component side.
6. Flood all unused areas on all layers with copper, which
reduces the temperature rise of power components.
These copper areas should be connected to GND.
Rev. 0
14
For more information www.analog.com
LTC3644/LTC3644-2
APPLICATIONS INFORMATION
Design Example
Using standard values of L1 = 6.8µH, L2 = 4.7µH, L3 =
3.3µH and L4 = 3.3µH for inductors results in maximum
ripple currents of:
As a design example, consider using the LTC3644 in an
application with the following specifications:
⎛
⎜
5V
⎞
⎟
5V
13.2V
⎛
⎜
⎝
⎞
⎟
⎠
SV = V = V = V = V = 10.8V to 13.2V
ΔIL1=
1−
= 0.46A
= 0.53A
= 0.61A
= 0.47A
IN
IN1
IN2
IN3
IN4
⎝ 1MHz •6.8µH⎠
V
= 5V, V
= 3.3V, V
= 2.5V, V
= 1.8V
=1 A,
OUT1
OUT2
OUT3
OUT4
⎛
⎜
3.3V
⎝ 1MHz •4.7µH⎠
⎞
⎟
3.3V
13.2V
⎛
⎝
⎞
ΔIL2
ΔIL3
ΔIL4
=
=
=
1−
1−
1−
⎜
⎟
⎠
I
= I
= 400mA, I
LOAD3(MAX)
LOAD1(MAX)
LOAD4(MAX)
LOAD2(MAX)
= 1.25A
I
I
I
f
⎛
2.5V
1MHz •3.3µH
⎞
2.5V
13.2V
⎛
⎜
⎝
⎞
⎟
⎠
⎜
⎟
= 1.25A
⎝
⎠
OUT(MAX)
OUT(MIN)
⎛
⎜
1.8V
⎞
⎟
1.8V
13.2V
⎛
⎜
⎝
⎞
⎟
⎠
= 0
⎝ 1MHz •3.3µH⎠
= 1MHz
SW
Because efficiency is important at both high and low load
current, Burst Mode operation will be utilized.
C
will be selected based on the ESR that is required
OUT
to satisfy the output voltage ripple requirement and the
bulk capacitance needed for loop stability. For this design,
47µF ceramic capacitors will be used.
To reduce input voltage and current ripple on the common
inputsupply,thePHASEpinistiedtoINTV foranti-phase
CC
operation between channels 1,2 and channels 3,4.
To prevent large voltage transients, C should be sized
IN
Given the internal oscillator of 1MHz, we can calculate the
based on the maximum RMS current:
inductorsvalueforabout40%ripplecurrentatmaximumV :
IN
VOUT
V
IN
VOUT
5V
5V
13.2V
⎛
⎞ ⎛
⎞
I
RMS ≅IOUT(MAX)
−1
L1=
L2=
L3=
L4=
1−
1−
1−
= 6.21µH
= 4.95µH
= 4.05µH
= 3.11µH
⎜
⎝
⎟ ⎜
⎠ ⎝
⎟
⎠
V
1MHz •0.5A
IN
3.3V
1MHz •0.5A
3.3V
13.2V
⎛
⎞ ⎛
⎟ ⎜
⎠ ⎝
⎞
⎟
⎠
5V
13.2V
13.2V
5V
⎛
⎜
⎝
⎞
IRMS1=1.25A
IRMS2 =1.25A
IRMS3 =1.25A
IRMS4 =1.25A
−1= 0.606A
⎜
⎝
⎟
⎠
2.5V
1MHz •0.5A
2.5V
13.2V
⎛
⎜
⎝
⎞ ⎛
⎟ ⎜
⎠ ⎝
⎞
⎟
⎠
3.3V
13.2V
13.2
3.3V
⎛
⎜
⎝
⎞
⎟
⎠
−1= 0.541A
−1= 0.490A
−1= 0.429A
1.8V
1MHz •0.5A
1.8V
13.2V
⎛
⎜
⎝
⎞ ⎛
⎟ ⎜
⎠ ⎝
⎞
⎟
⎠
2.5V
13.2V
13.2
2.5V
⎛
⎜
⎝
⎞
⎟
⎠
1−
1.8V
13.2V
13.2
1.8V
⎛
⎜
⎝
⎞
⎟
⎠
IRMS =IRMS1+IRMS2 +IRMS3 +IRMS4 = 2.07A
DecouplingtheV pinseachwith22µFceramiccapacitors
INX
is adequate for most applications.
Rev. 0
15
For more information www.analog.com
LTC3644/LTC3644-2
APPLICATIONS INFORMATION
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Figure 4. Recommended Layout
Rev. 0
16
For more information www.analog.com
LTC3644/LTC3644-2
APPLICATIONS INFORMATION
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Figure 5. Dual 3.75A/1.25A 1MHz Step-Down Regulator with Common Input Supply
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ꢀꢁꢂꢃ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁ ꢂꢃ ꢄ.ꢅꢀꢂ
ꢀ
ꢀꢀꢁ
ꢀ
Rꢀ
ꢁꢀꢂꢃ
Rꢀ
ꢁꢂꢃꢄ
ꢀꢀꢁ
ꢀꢀꢁꢂ
ꢀꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂ
ꢀ
ꢀ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
Rꢀ
Rꢀ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢁꢂꢀꢃ
ꢁꢂ.ꢃꢄ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂ
ꢀꢁ
ꢂ.ꢃꢄꢅ
ꢀꢁ
ꢁ.ꢁꢂꢃ
ꢀ
ꢀ
ꢀꢁꢂꢃ
ꢀ.ꢁꢂ ꢃꢄ ꢀ.ꢅꢆꢃ
ꢀꢁꢂꢃ
ꢀ.ꢀꢁ ꢂꢃ ꢄ.ꢅꢆꢂ
ꢀ
ꢀ
Rꢀ
ꢁꢂꢃꢄ
Rꢀ
ꢁꢂꢃꢄ
ꢀꢀꢁ
ꢀꢀꢁ
ꢀꢀꢁꢂ
ꢀꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀ
ꢀ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
R
Rꢀ
ꢁ0ꢂꢃ
ꢀ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢁꢂ
ꢀꢁꢂꢂꢃ ꢄ0ꢁ
Figure 6. 5V/3.3V/2.5V/1.8V Output 2.25MHz Step-Down Regulator with Common Input Supply and Sequenced Turn-On
Rev. 0
17
For more information www.analog.com
LTC3644/LTC3644-2
TYPICAL APPLICATIONS
ꢀ
ꢀꢁ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀꢁꢂꢃ
ꢀꢀ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂꢃꢄ
ꢀ
ꢀꢁ
ꢀꢁꢂ
ꢀꢀꢁꢂ
ꢃꢄ
ꢀ
ꢀꢁꢁ
ꢀꢁ
ꢀ.ꢁꢂꢃ
ꢀꢁ
Rꢀꢁꢂ
Rꢀꢁꢂ
Rꢀꢁꢂ
Rꢀꢁꢂ
ꢀꢁꢂꢃꢄꢅꢅ
ꢀꢁꢂꢂꢃꢄ
ꢀꢁꢂꢂꢃꢄ
ꢀꢁꢂꢂꢃꢄ
ꢀꢁꢂꢂꢃꢄ
ꢀꢁ
ꢂ.ꢃꢄꢅ
ꢀ
ꢀꢁꢂꢃ
ꢀꢁꢂ
ꢀ.ꢀꢁ ꢂꢃ ꢄ.ꢅꢆꢂ
ꢀ
Rꢀ
ꢁꢀꢂꢃ
ꢀꢀꢁ
ꢀꢀꢁꢂ
ꢀꢁ
ꢁ.ꢁꢂꢃ
ꢀꢁꢂ
ꢀ
ꢀꢁꢂꢃ
ꢀꢁꢂ
ꢀꢁꢂ
Rꢀ
ꢁꢂꢃꢄ
ꢀ
ꢀꢁꢂꢃ
ꢀꢁ ꢂꢃ ꢄ.ꢀꢂ
Rꢀ
ꢁꢂꢃꢄ
ꢀ
ꢀꢀꢁ
ꢀꢀꢁꢂ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃꢄ
ꢀꢁ
ꢀꢁꢂ
ꢂ.ꢂꢃꢄ
Rꢀ
ꢁꢂ.ꢃꢄ
ꢀ
ꢀ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢁꢂ
ꢀꢁꢂꢃ
ꢄꢅ
ꢀ.ꢁꢂ ꢃꢄ ꢀ.ꢅꢆꢃ
ꢀ
Rꢀ
ꢁꢂꢃꢄ
ꢀꢀꢁ
ꢀꢀꢁꢂ
ꢀꢁꢂ
Rꢀ
ꢁ0ꢂꢃ
ꢀ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃꢄꢅꢆꢇꢈ ꢀꢁꢂꢃ
ꢀꢁꢂꢂ ꢃ0ꢄ
Figure 7. 2.5A/1.25A/1.25A 1MHz Step-Down Regulator with Common Input Supply
Rev. 0
18
For more information www.analog.com
LTC3644/LTC3644-2
PACKAGE DESCRIPTION
ꢡ
ꢬ ꢬ ꢛ ꢛ ꢛ ꢡ
ꢙ . 0
ꢎ . ꢙ
0 . ꢋ
0 . ꢋ
ꢎ . ꢙ
ꢙ . 0
0 . 0 0 0
ꢮ ꢮ ꢮ ꢡ ꢙ ꢱ
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
19
subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
LTC3644/LTC3644-2
TYPICAL APPLICATION
0.85A/2.5A Series Output 1MHz Step-Down Regulator
ꢀ
ꢀꢁ
ꢀ
ꢀꢁꢂꢃ
ꢀꢀ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁ
ꢀꢁꢂ
ꢀ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂꢃꢄꢅꢆꢇꢈ
ꢀꢁꢂ
ꢀ
ꢀꢁ
ꢀꢁ
ꢀꢀꢁꢂ
ꢃꢀ
Rꢀꢁꢂ
Rꢀꢁꢂ
ꢀꢁꢂ
ꢀ
ꢀꢁꢁ
ꢀ.ꢁꢂꢃ
Rꢀ
ꢁ0ꢂ
ꢀꢁꢂꢂꢃꢄ
ꢀꢁꢂꢂꢃꢄ
ꢀꢁꢂꢂꢃꢄ
ꢀꢁꢂꢂꢃꢄ
Rꢀꢁꢂ
Rꢀꢁꢂ
ꢀ
ꢀ
ꢁꢂꢃ
ꢁꢂꢃ
ꢀꢁꢂꢃꢄꢅꢅ
ꢀꢁ
ꢂ.ꢂꢃꢄ
ꢀꢁ
ꢁ.ꢁꢂꢃ
ꢀ
ꢀ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀ.ꢀꢁ ꢂꢃ ꢄ.ꢅꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁ ꢂꢃ 0.ꢄꢀꢂ
ꢀ
ꢀꢀꢁ
ꢀꢀꢁꢂ
ꢀ
ꢀꢀꢁ
ꢀꢀꢁꢂ
ꢅꢆ
Rꢀ
ꢁꢀꢂꢃ
Rꢀ
ꢁꢂꢃꢄ
ꢁꢆꢇꢈꢉꢊ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀ
ꢀ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
Rꢀ
ꢁꢂ.ꢃꢄ
Rꢀ
ꢁꢂꢃꢄ
ꢀꢁꢂꢃ
ꢄꢅ
ꢄꢅ
ꢀꢁꢂ
ꢀꢁꢂꢂ ꢃꢄ0ꢅ
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Rev. 0
03/21
www.analog.com
20
ANALOG DEVICES, INC. 2021
相关型号：
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