OP184FP [ADI]
Precision Rail-to-Rail Input & Output Operational Amplifiers; 精密轨到轨输入和输出运算放大器
| 型号： | OP184FP |
| 厂家： | 
ADI |
| 描述： | Precision Rail-to-Rail Input & Output Operational Amplifiers |
| 文件： | 总20页 (文件大小：524K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Precision Rail-to-Rail Input & Output
Operational Amplifiers
a
OP184/OP284/OP484
FEATURES
PIN CONFIGURATIONS
Single-Supply Operation
Wide Bandwidth: 4 MHz
Low Offset Voltage: 65 V
Unity-Gain Stable
High Slew Rate: 4.0 V/s
Low Noise: 3.9 nV/√Hz
8-Lead Epoxy DIP
(P Suffix)
8-Lead SO
(S Suffix)
APPLICATIONS
NC
1
2
3
4
8
7
6
5
NULL
–IN A
+IN A
V–
OP184
Battery Powered Instrumentation
Power Supply Control and Protection
Telecom
DAC Output Amplifier
ADC Input Buffer
V+
OUT A
NULL
NC = NO CONNECT
8-Lead Epoxy DIP
(P Suffix)
GENERAL DESCRIPTION
The OP184/OP284/OP484 are single, dual and quad single-
supply, 4 MHz bandwidth amplifiers featuring rail-to-rail inputs
and outputs. They are guaranteed to operate from +3 to +36 (or
±1.5 to ±18) volts and will function with a single supply as low
as +1.5 volts.
8-Lead SO
(S Suffix)
OP284
V+
1
2
3
4
8
7
6
5
OUT A
–IN A
+IN A
V–
OUT B
–IN B
+IN B
These amplifiers are superb for single supply applications re-
quiring both ac and precision dc performance. The combination
of bandwidth, low noise and precision makes the OP184/OP284/
OP484 useful in a wide variety of applications, including filters
and instrumentation.
Other applications for these amplifiers include portable telecom
equipment, power supply control and protection, and as amplifi-
ers or buffers for transducers with wide output ranges. Sensors
requiring a rail-to-rail input amplifier include Hall effect, piezo
electric, and resistive transducers.
14-Lead Epoxy DIP
(P Suffix)
14-Lead Narrow-Body SO
(S Suffix)
The ability to swing rail-to-rail at both the input and output en-
ables designers to build multistage filters in single-supply sys-
tems and to maintain high signal-to-noise ratios.
OUT A
–IN A
+IN A
V+
OUT D
–IN D
+IN D
V–
1
2
3
4
5
6
7
14
13
12
11
10
9
The OP184/OP284/OP484 are specified over the HOT extended
industrial (–40°C to +125°C) temperature range. The single
and dual are available in 8-pin plastic DIP plus SO surface
mount packages. The quad OP484 is available in 14-pin plastic
DIPs and 14-lead narrow-body SO packages.
OP484
+IN B
–IN B
OUT B
+IN C
–IN C
OUT C
8
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
World Wide Web Site: http://www.analog.com
© Analog Devices, Inc., 1996
OP184/OP284/OP484–SPECIFICATIONS
(@ V = +5.0 V, VCM = 2.5 V, TA = +25؇C unless otherwise noted)
ELECTRICAL CHARACTERISTICS
S
Parameter
Symbol Conditions
Min
Typ Max Units
INPUT CHARACTERISTICS
Offset Voltage “OP184/284E” Grade
VOS
VOS
VOS
VOS
IB
(Note 1)
–40°C ≤ TA ≤ +125°C
65
µV
165 µV
125 µV
350 µV
Offset Voltage “OP184/284F” Grade
Offset Voltage “OP484E” Grade
Offset Voltage “OP484F” Grade
Input Bias Current
–40°C ≤ TA ≤ +125°C
–40°C ≤ TA ≤ +125°C
–40°C ≤ TA ≤ +125°C
–40°C ≤ TA ≤ +125°C
–40°C ≤ TA ≤ +125°C
75
µV
175 µV
150 µV
450 µV
350 nA
575 nA
50
50
+5
60
2
Input Offset Current
IOS
nA
nA
V
Input Voltage Range
0
Common-Mode Rejection Ratio
Common-Mode Rejection Ratio
Large Signal Voltage Gain
CMRR
CMRR
AVO
V
V
CM = 0 V to 5 V
CM = 1.0 V to 4.0 V, –40°C ≤ TA ≤ +125°C
60
86
50
25
dB
dB
V/mV
V/mV
pA/°C
RL = 2 kΩ, 1 V ≤ VO ≤ 4 V
RL = 2 kΩ, –40°C ≤ TA ≤ +125°C
240
150
Bias Current Drift
∆IB/∆T
OUTPUT CHARACTERISTICS
Output Voltage High
Output Voltage Low
VOH
VOL
IOUT
IL = 1.0 mA
IL = 1.0 mA
+4.85
V
125 mV
mA
Output Current
±6.5
POWER SUPPLY
Power Supply Rejection Ratio
Supply Current/Amplifier
Supply Voltage Range
PSRR
ISY
VS
VS = +2.0 V to +10 V, –40°C ≤ TA ≤ +125°C
VO = 2.5 V, –40°C ≤ TA ≤ +125°C
76
dB
1.45 mA
+3
+36
V
DYNAMIC PERFORMANCE
Slew Rate
Settling Time
Gain Bandwidth Product
Phase Margin
SR
ts
GBP
Øo
RL = 2 kΩ
To 0.01%, 1.0 V Step
1.65
2.4
2.5
3.25
45
V/µs
µs
MHz
Degrees
NOISE PERFORMANCE
Voltage Noise
Voltage Noise Density
Current Noise Density
en p-p
en
in
0.1 Hz to 10 Hz
f = 1 kHz
0.3
3.9
0.4
µV p-p
nV/√Hz
pA/√Hz
NOTES
1Input Offset Voltage measurements are performed by automated test equipment approximately 0.5 seconds after application of power.
Specifications subject to change without notice.
–2–
REV. 0
OP184/OP284/OP484
ELECTRICAL CHARACTERISTICS(@ VS = +3.0 V, VCM = 1.5 V, TA = +25؇C unless otherwise noted)
Parameter
Symbol
Conditions
Min
Typ Max
Units
INPUT CHARACTERISTICS
Offset Voltage “OP184/284E” Grade
VOS
VOS
VOS
VOS
IB
(Note 1)
–40°C ≤ TA ≤ +125°C
65
µV
µV
µV
µV
µV
µV
µV
µV
nA
nA
nA
V
165
125
350
100
200
150
450
350
575
50
Offset Voltage “OP184/284F” Grade
Offset Voltage “OP484E” Grade
Offset Voltage “OP484F” Grade
Input Bias Current
–40°C ≤ TA ≤ +125°C
–40°C ≤ TA ≤ +125°C
–40°C ≤ TA ≤ +125°C
60
–40°C ≤ TA ≤ +125°C
–40°C ≤ TA ≤ +125°C
Input Offset Current
Input Voltage Range
IOS
0
+3
Common-Mode Rejection Ratio
Common-Mode Rejection Ratio
CMRR
CMRR
V
CM = 0 V to 3 V
60
56
dB
dB
VCM = 0 V to 3 V, –40°C ≤ TA ≤ +125°C
OUTPUT CHARACTERISTICS
Output Voltage High
Output Voltage Low
VOH
VOL
IL = 1.0 mA
IL = 1.0 mA
+2.85
76
V
mV
125
POWER SUPPLY
Power Supply Rejection Ratio
Supply Current/Amplifier
PSRR
ISY
VS = ±1.25 V to ±1.75 V
VO = 1.5 V, –40°C ≤ TA ≤ +125°C
dB
mA
1.35
DYNAMIC PERFORMANCE
Gain Bandwidth Product
GBP
en
3
MHz
NOISE PERFORMANCE
Voltage Noise Density
f = 1 kHz
3.9
nV/√Hz
NOTES
1Input Offset Voltage measurements are performed by automated test equipment approximately 0.5 seconds after application of power.
Specifications subject to change without notice.
REV. 0
–3–
OP184/OP284/OP484
(@ V = ؎15.0 V, VCM = 0 V, TA = +25؇C unless otherwise noted)
ELECTRICAL CHARACTERISTICS
S
Parameter
Symbol Conditions
Min Typ Max
Units
INPUT CHARACTERISTICS
Offset Voltage “OP184/284E” Grade VOS
(Note 1)
–40°C ≤ TA ≤ +125°C
100
200
175
375
150
300
250
500
350
575
50
µV
µV
µV
µV
µV
µV
µV
µV
nA
nA
nA
V
dB
dB
V/mV
V/mV
µV/°C
pA/°C
Offset Voltage “OP284F” Grade
Offset Voltage “OP484E” Grade
Offset Voltage “OP484F” Grade
Input Bias Current
VOS
VOS
VOS
IB
–40°C ≤ TA ≤ +125°C
–40°C ≤ TA ≤ +125°C
–40°C ≤ TA ≤ +125°C
80
90
–40°C ≤ TA ≤ +125°C
–40°C ≤ TA ≤ +125°C
–15
VCM = –14.0 V to +14.0 V, –40°C ≤ TA ≤ +125°C 86
VCM = –15.0 V to +15.0 V
RL = 2 kΩ, –10 V ≤ VO ≤ 10 V
RL = 2 kΩ, –40°C ≤ TA ≤ +125°C
Input Offset Current
Input Voltage Range
Common-Mode Rejection Ratio
Common-Mode Rejection Ratio
Large Signal Voltage Gain
IOS
+15
CMRR
CMRR
AVO
80
150 1000
75
Offset Voltage Drift “E” Grade
Bias Current Drift
∆VOS/∆T
∆IB/∆T
0.2
150
2.00
OUTPUT CHARACTERISTICS
Output Voltage High
Output Voltage Low
VOH
VOL
IOUT
IL = 1.0 mA
IL = 1.0 mA
+14.8
V
–14.875 V
mA
Output Current
±10
POWER SUPPLY
Power Supply Rejection Ratio
Supply Current/Amplifier
Supply Current/Amplifier
PSRR
ISY
ISY
VS = ±2.0 V to ±18 V, –40°C ≤ TA ≤ +125°C
VO = 0 V, –40°C ≤ TA ≤ +125°C
VS = ±18 V, –40°C ≤ TA ≤ +125°C
90
dB
mA
mA
2.0
2.25
DYNAMIC PERFORMANCE
Slew Rate
Full-Power Bandwidth
Settling Time
SR
BW
tS
RL = 2 kΩ
2.4 4.0
V/µs
kHz
µs
1% Distortion, RL = 2 kΩ, VO = 29 V p-p
To 0.01%, 10 V Step
35
4
p
Gain Bandwidth Product
Phase Margin
GBP
Øo
4.25
50
MHz
Degrees
NOISE PERFORMANCE
Voltage Noise
Voltage Noise Density
Current Noise Density
e
e
p-p
0.1 Hz to 10 Hz
f = 1 kHz
0.3
3.9
0.4
µV p-p
nV/√Hz
pA/√Hz
n
n
i
n
NOTES
1Input Offset Voltage measurements are performed by automated test equipment approximately 0.5 seconds after application of power.
Specifications subject to change without notice.
(@ V = +5.0 V, VCM = 2.5 V, TA = +25؇C unless otherwise noted)
WAFER TEST LIMITS
S
Parameter
Symbol
Conditions
Limit
Units
Offset Voltage OP284
Offset Voltage OP484
Input Bias Current
Input Offset Current
Input Voltage Range
Common-Mode Rejection Ratio
Power Supply Rejection Ratio
Large Signal Voltage Gain
Output Voltage High
Output Voltage Low
Supply Current/Amplifier
VOS
VOS
IB
65
75
350
50
V– to V+
86
90
50
4.85
125
1.45
µV max
µV max
nA max
nA max
V min
dB min
dB min
V/mV min
V min
IOS
VCM
CMRR
PSRR
AVO
VOH
VOL
ISY
V
CM = +1 V to +4 V
VS = ±2 V to ±18 V
RL = 2 kΩ
IL = 1.0 mA
IL = 1.0 mA
VO = 0 V, RL = ∞
mV max
mA max
NOTE
Electrical tests and wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard
product dice. Consult factory to negotiate specifications based on dice lot qualifications through sample lot assembly and testing.
–4–
REV. 0
OP184/OP284/OP484
ABSOLUTE MAXIMUM RATINGS1
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±18 V
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±18 V
Differential Input Voltage2 . . . . . . . . . . . . . . . . . . . . . ±0.6 V
Output Short-Circuit Duration to GND3 . . . . . . . . Indefinite
Storage Temperature Range
P, S Packages . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Operating Temperature Range
OP184/OP284/OP484E, F . . . . . . . . . . . . –40°C to +125°C
Junction Temperature Range
P, S Packages . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature Range (Soldering 60 sec) . . . . . . . . +300°C
3
Package Type
JC
Units
JA
8-Pin Plastic DIP (P)
8-Pin SOIC (S)
14-Pin Plastic DIP (P)
14-Pin SOIC (S)
103
158
83
43
43
39
27
°C/W
°C/W
°C/W
°C/W
OP284 Die Size 0.065 × 0.092 Inch, 5,980 Sq. Mils
Substrate (Die Backside) Is Connected to V–.
Transistor Count, 62.
92
NOTES
1Absolute maximum ratings apply to both DICE and packaged parts unless
otherwise noted.
2For input voltages greater than 0.6 volts, the input current should be limited to less
than 5 mA to prevent degradation or destruction of the input devices.
3θJA is specified for the worst case conditions; i.e., θJA is specified for device in socket
for cerdip and P-DIP packages; θJA is specified for device soldered in circuit board
for SOIC package.
ORDERING GUIDE
Temperature
Range
Package
Description
Package
Option
Model
OP184EP
OP184ES
OP184FP
OP184FS
–40°C to +125°C 8-Pin Plastic DIP N-8
–40°C to +125°C 8-Pin SOIC SO-8
–40°C to +125°C 8-Pin Plastic DIP N-8
–40°C to +125°C 8-Pin SOIC SO-8
OP284EP
OP284ES
OP284FP
OP284FS
–40°C to +125°C 8-Pin Plastic DIP N-8
–40°C to +125°C 8-Pin SOIC SO-8
–40°C to +125°C 8-Pin Plastic DIP N-8
–40°C to +125°C 8-Pin SOIC SO-8
OP484 Die Size 0.080 × 0.110 Inch, 8,800 Sq. Mils
Substrate (Die Backside) Is Connected to V–.
Transistor Count, 120.
OP484EP
OP484ES
OP484FP
OP484FS
–40°C to +125°C 14-Pin Plastic DIP N-14
–40°C to +125°C 14-Pin SOIC SO-14
–40°C to +125°C 14-Pin Plastic DIP N-14
–40°C to +125°C 14-Pin SOIC
SO-14
V
CC
R4
QB6
QB5
RB4
RB3
RB1
R3
Q3
R11
TP
Q16
Q17
Q12
Q11
Q9
JB1
Q8
QB9
Q7
Q5
QL1
Q1
Q4
Q2
QB10
–IN
+IN
CC2
Q10
OUT
QL2
O
C
C
FF
Q6
R6
QB2
Q18
CB1 N+
M P+
QB3
R7
QB8
QB4
RB2
Q14
Q15
Q13
R8
QB7
QB1
R9
R1
R2
CC1
R5
R10
JB2
V
EE
Figure 1. Simplified Schematic
–5–
REV. 0
OP184/OP284/OP484–Typical Performance Characteristics
300
270
240
210
180
150
120
90
300
250
200
150
100
50
500
400
V
T
= +3V
V
= ±15V
S
S
V
= +5V
S
= +25°C
= 1.5V
A
–40°C ≤ T ≤ +125°C
300
A
V
CM
200
100
0
–100
–200
–300
–400
–500
60
30
0
0
–15
–10
–5
0
5
10
15
0
0.25
0.50
0.75
1.0
1.25
1.5
–100 –75 –50 –25
0
25
50
75 100
OFFSET VOLTAGE DRIFT, TCV – µV/°C
COMMON MODE VOLTAGE – Volts
INPUT OFFSET VOLTAGE – µV
OS
Figure 2. Input Offset Voltage
Distribution
Figure 5. Input Offset Voltage Drift
Distribution
Figure 8. Input Bias Current vs.
Common-Mode Voltage
1,000
300
300
V
T
= +5V
S
V
= ±15V
270
240
210
180
150
120
90
S
V
= ±15V
S
= +25°C
= 2.5V
250
200
150
100
50
A
–40°C ≤ T ≤ +125°C
A
V
CM
SOURCE
100
SINK
60
30
0
10
0.01
0
0
0.25
0.50
0.75
1.0
1.25
OS
1.5
0.1
1
10
–100 –75 –50 –25
0
25
50
75 100
OFFSET VOLTAGE DRIFT, TCV – µV/°C
INPUT OFFSET VOLTAGE – µV
LOAD CURRENT – mA
Figure 3. Input Offset Voltage
Distribution
Figure 6. Input Offset Voltage Drift
Distribution
Figure 9. Output Voltage to Supply
Rail vs. Load Current
200
–40
–45
1.2
1.1
V
T
= ±15V
= +25°C
S
175
150
125
100
75
A
V
= V /2
S
CM
V
= ±15V
S
–50
–55
–60
1.0
0.9
0.8
0.7
0.6
0.5
V
S
= +5V
V
V
= +5V
= +3V
–65
–70
–75
S
50
S
V
= ±15V
S
25
0
–80
–40
25
85
125
–40
25
85
125
–125 –100 –75 –50 –25
0
25 50 75 100 125
TEMPERATURE – °C
INPUT OFFSET VOLTAGE – µV
TEMPERATURE – °C
Figure 4. Input Offset Voltage
Distribution
Figure 7. Bias Current vs.
Temperature
Figure 10. Supply Current vs.
Temperature
–6–
REV. 0
OP184/OP284/OP484
1.50
1.25
1.0
80
60
60
V
= +5V
= 2kΩ
= +25°C
S
50
40
V
T
= +3V
S
R
T
L
= +25°C
A
50
A
NO LOAD
30
40
0
20
30
45
0.75
0.5
10
20
90
T
= +25°C
A
0
10
135
180
225
270
–10
–20
–30
–40
0
–10
–20
–30
0.25
0
10
100
1k
10k
0
±2.5 ±5.0 ±7.5 ±10 ±12.5 ±15 ±17.5 ±20
100k
1M
10M
10k
100k
1M
10M
SUPPLY VOLTAGE – Volts
FREQUENCY – Hz
FREQUENCY – Hz
Figure 11. Supply Current vs. Supply
Voltage
Figure 14. Open-Loop Gain and Phase
vs. Frequency (No Load)
Figure 17. Closed-Loop Gain vs.
Frequency (2 kΩ Load)
50
60
80
V
= ±15V
= 2kΩ
= +25°C
S
V
T
= ±15V
50
40
60
50
S
R
T
V
= ±15V
L
S
= +25°C
A
40
30
20
10
0
A
NO LOAD
+I
SC
30
40
0
–I
SC
20
30
45
–I
SC
10
20
90
0
10
135
180
225
270
+I
SC
V
–10
–20
–30
–40
0
–10
–20
–30
= +5V, V
25
= +2.5V
75
S
CM
–50 –25
0
50
100 125
10
100
1k
10k
100k
1M
10M
10k
100k
FREQUENCY – Hz
1M
10M
TEMPERATURE – °C
FREQUENCY – Hz
Figure 12. Short Circuit Current vs.
Temperature
Figure 15. Open-Loop Gain and Phase
vs. Frequency (No Load)
Figure 18. Closed-Loop Gain vs.
Frequency (2 kΩ Load)
80
60
2.5k
2k
V
= +3V
S
50
40
V
T
= +5V
60
50
S
R
T
= 2kΩ
= +25°C
L
= +25°C
A
A
NO LOAD
30
40
0
V
= ±15V
S
20
1.5k
1k
30
45
–10V < V < 10V
R
O
= 2kΩ
10
L
20
90
0
10
135
180
225
270
–10
–20
–30
–40
0
V
= +5V
S
1V < V < 4V
500
0
O
–10
–20
–30
R
= 2kΩ
L
–50 –25
0
25
50
75
100 125
10
100
1k
10k
100k
1M
10M
10k
100k
FREQUENCY – Hz
1M
10M
TEMPERATURE – °C
FREQUENCY – Hz
Figure 16. Open-Loop Gain vs.
Temperature
Figure 13. Open-Loop Gain and Phase
vs. Frequency (No Load)
Figure 19. Closed-Loop Gain vs.
Frequency (2 kΩ Load)
REV. 0
–7–
OP184/OP284/OP484–Typical Performance Characteristics
300
270
240
160
140
120
5
4
3
2
1
0
V
T
= +5V
= +25°C
T
= +25°C
S
A
A
A
= 10
V
210
180
150
120
90
100
80
A
= 100
V
60
V
= ±15V
S
40
V
= +5V
S
V
V
= +5V
20
S
= 0.5–4.5V
IN
60
0
R
T
= 2kΩ
= +25°C
L
V
= +3V
1M
S
30
–20
–40
A
A
= 1
V
0
100
10M
10M
1k
10k
100k
1M
100
1k
10k
100k
1k
10k
100k
FREQUENCY – Hz
1M
10M
FREQUENCY – Hz
FREQUENCY – Hz
Figure 20. Output Impedance vs.
Frequency
Figure 23. Maximum Output Swing
vs. Frequency
Figure 26. PSRR vs. Frequency
300
30
80
V
T
= ±15V
= +25°C
V
V
= ±15V
= ±14V
= 2kΩ
S
270
240
210
180
150
120
90
S
V
T
V
= ±2.5V
70
60
50
40
30
20
10
0
S
A
IN
25
20
15
10
5
= +25°C, A
= ±50mV
= 1
VCL
A
–OS
+OS
R
T
L
IN
= +25°C
A
A
= 100
V
A
= 10
V
60
30
A
= 1
V
0
100
0
1k
10M
1k
10k
100k
1M
10
100
CAPACITIVE LOAD – pF
1000
10k
100k
FREQUENCY – Hz
1M
10M
FREQUENCY – Hz
Figure 21. Output Impedance vs.
Frequency
Figure 24. Maximum Output Swing
vs. Frequency
Figure 27. Small Signal Overshoot
vs. Capacitive Load
300
180
7
V
T
= +3V
= +25°C
T
= +25°C
A
= 100
S
A
270
240
210
180
150
120
90
V
160
140
120
100
80
V
R
= ±15V
= 2kΩ
A
S
6
5
4
3
L
+SLEW RATE
–SLEW RATE
V
= ±15V
S
+SLEW RATE
–SLEW RATE
60
V
= +3V
40
S
2
1
0
V
= +5V
S
60
A
= 10
20
V
V
= +5V
S
30
A
= 1
0
V
R
= 2kΩ
L
0
100
–20
100
1k
10k
100k
1M
10M
10M
1k
10k
100k
1M
–50 –25
0
25
50
75
100 125
FREQUENCY – Hz
FREQUENCY – Hz
TEMPERATURE – °C
Figure 22. Output Impedance vs.
Frequency
Figure 25. CMRR vs. Frequency
Figure 28. Slew Rate vs. Temperature
–8–
REV. 0
OP184/OP284/OP484
160
10
8
30
25
20
V
T
= ±15V
T
= +25°C
S
A
140
120
100
80
±2.5V ≤ V ≤ ±15V
S
= +25°C
T
= +25°C
A
A
6
V
= ±15V
S
4
2
V
= +3V
60
S
0
15
10
5
0.1%
0.01%
40
–2
–4
–6
–8
–10
20
0
–20
–40
0
0
1
2
3
4
5
6
100
1k
10k
100k
1M
10M
1
10
100
1000
SETTLING TIME – µs
FREQUENCY – Hz
FREQUENCY – Hz
Figure 32. Settling Time vs. Step Size
Figure 29. Voltage Noise Density
vs. Frequency
Figure 35. Channel Separation
vs. Frequency
10
V
= +5V
= 1
= OPEN
= 300pF
= +25°C
1s
S
±2.5V ≤ V ≤ ±15V
V
= ±15V
= 100k
= 0.3µVp-p
S
S
A
R
C
T
V
L
L
100
90
T
= +25°C
A
e
V
A
100
90
8
6
4
2
0
+400mV
n
A
10
0V
10
0%
0%
100mV
1µs
10mV
1
10
100
1000
FREQUENCY – Hz
Figure 30. Current Noise Density
vs. Frequency
Figure 36. Small Signal Transient
Response
Figure 33. 0.1 Hz to 10 Hz Noise
5
V
T
= +5V
S
1s
4
3
V
A
= +5V, 0V
= 100k
= 0.3µVp-p
V
= +5V
= 1
S
S
= +25°C
A
A
R
C
T
V
V
L
L
100
90
100
90
e
n
= 2kΩ
= 300pF
- +25°C
400mV
2
A
1
0.1%
0.01%
0
–1
–2
–3
–4
–5
10
10
0V
0%
0%
10mV
100mV
1µs
0
1
2
3
4
5
6
SETTLING TIME – µs
Figure 37. Small Signal Transient
Response
Figure 34. 0.1 Hz to 10 Hz Noise
Figure 31. Settling Time vs. Step Size
REV. 0
–9–
OP184/OP284/OP484
0.1
V
= ±0.75V
V
S
= ±1.5V
= 1
S
V
= ±0.75V
O
A
= 1
A
V
V
100
100
90
NO LOAD
= +25°C
NO LOAD
90
200mV
0V
200mV
0V
A
V
R
= 1000
= ±2.5V
= 2kΩ
T
V
T
= +25°C
A
A
S
0.010
L
V
= ±2.5V
= ±1.5V
O
10
–200mV
10
–200mV
0%
0%
V
O
0.001
100mV
500ns
100mV
1µs
0.0005
20
100
1k
FREQUENCY – Hz
10k 20k
Figure 40. Total Harmonic Distortion
vs. Frequency
Figure 38. Small Signal Transient
Response
Figure 39. Small Signal Transient
Response
APPLICATIONS
Functional Description
stage. A key issue in the input stage is the behavior of the input
bias currents over the input common-mode voltage range. Input
bias currents in the OP284 are the arithmetic sum of the base
currents in Q1-Q3 and in Q2-Q4. As a result of this design
approach, the input bias currents in the OP284 not only exhibit
different amplitudes, but also exhibit different polarities. This
effect is best illustrated in Figure 8. It is, therefore, of para-
mount importance that the effective source impedances con-
nected to the OP284’s inputs be balanced for optimum dc and
ac performance.
The OP284 and OP484 are precision single-supply, rail-to-rail
operational amplifiers. Intended for the portable instrumenta-
tion marketplace, the OP184/OP284/OP484 combines the at-
tributes of precision, wide bandwidth, and low noise to make it
a superb choice in those single supply applications that require
both ac and precision dc performance. Other low supply voltage
applications for which the OP284 is well suited are active filters,
audio microphone preamplifiers, power supply control, and tele-
com. To combine all of these attributes with rail-to-rail input/
output operation, novel circuit design techniques are used.
To achieve rail-to-rail output, the OP284 output stage design
employs a unique topology for both sourcing and sinking cur-
rent. This circuit topology is illustrated in Figure 42. As previ-
ously mentioned, the output stage is voltage-driven from the
second gain stage. The signal path through the output stage is
inverting; that is, for positive input signals, Q1 provides the base
current drive to Q6 so that it conducts (sinks) current. For
negative input signals, the signal path via Q1-Q2-D1-Q4-Q3
provides the base current drive for Q5 to conduct (source) cur-
rent. Both amplifiers provide output current until they are
forced into saturation, which occurs at approximately 20 mV
from negative rail and 100 mV from the positive supply rail.
V
POS
R1
4k
R2
4k
I1
V
01
D1
D2
Q4
Q1
Q3
Q2
–IN
+IN
V
02
R3
3k
R4
3k
I2
V
POS
V
NEG
R4
I2
INPUT FROM
SECOND GAIN
STAGE
Q5
Q6
Q3
Q1
Figure 41. OP284 Equivalent Input Circuit
V
For example, Figure 41 illustrates a simplified equivalent circuit
for the OP184/OP284/OP484’s input stage. It is comprised of
an NPN differential pair, Q1-Q2, and a PNP differential pair,
Q3-Q4, operating concurrently. Diode network D1-D2 serves
to clamp the applied differential input voltage to the OP284,
thereby protecting the input transistors against avalanche dam-
age. Input stage voltage gains are kept low for input rail-to-rail
operation. The two pairs of differential output voltages are con-
nected to the OP284’s second stage, which is a compound folded
cascode gain stage. It is also in the second gain stage where the
two pairs of differential output voltages are combined into a
single-ended output signal voltage used to drive the output
OUT
R1
R2
Q4
D1
R5
Q2
R3
I1
R6
V
NEG
Figure 42. OP284 Equivalent Output Circuit
–10–
REV. 0
OP184/OP284/OP484
R2
Thus, the saturation voltage of the output transistors sets the
limit on the OP284’s maximum output voltage swing. Output
short circuit current limiting is determined by the maximum
signal current into the base of Q1 from the second gain stage.
Under output short circuit conditions, this input current level is
approximately 100 µA. With transistor current gains around
200, the short circuit current limits are typically 20 mA. The
output stage also exhibits voltage gain. This is accomplished by
use of common-emitter amplifiers, and as a result, the voltage
gain of the output stage (thus, the open-loop gain of the device)
exhibits a dependence to the total load resistance at the output
of the OP284.
1/2
OP284
V
OUT
R1
V
IN
Figure 44. A Resistance in Series with an Input Limits
Overvoltage Currents to Safe Values
For example, a 1 kΩ resistor will protect the OP284 against
input signals up to 5 V above and below the supplies. For other
configurations where both inputs are used, then each input
should be protected against abuse with a series resistor. Again,
in order to ensure optimum dc and ac performance, it is recom-
mended to balance source impedance levels. For more informa-
tion on the general overvoltage characteristics of amplifiers,
please refer to the 1993 System Applications Guide, Section 1,
pages 56-69. This reference textbook is available from the Ana-
log Devices Literature Center.
Input Overvoltage Protection
As with any semiconductor device, if conditions exist where the
applied input voltages to the device exceed either supply voltage,
the device’s input overvoltage I-V characteristic must be consid-
ered. When an overvoltage occurs, the amplifier could be dam-
aged, depending on the magnitude of the applied voltage and
the magnitude of the fault current. Figure 43 illustrates the over
voltage I-V characteristic of the OP284. This graph was gener-
ated with the supply pins connected to GND and a curve
tracer’s collector output drive connected to the input.
Output Phase Reversal
Some operational amplifiers designed for single-supply opera-
tion exhibit an output voltage phase reversal when their inputs
are driven beyond their useful common-mode range. Typically
for single-supply bipolar op amps, the negative supply deter-
mines the lower limit of their common-mode range. With these
devices, external clamping diodes, with the anode connected to
ground and the cathode to the inputs, prevent input signal ex-
cursions from exceeding the device’s negative supply (i.e.,
GND), preventing a condition that could cause the output volt-
age to change phase. JFET-input amplifiers may also exhibit
phase reversal, and, if so, a series input resistor is usually re-
quired to prevent it.
5
4
3
2
1
0
–1
– 2
– 3
– 4
– 5
The OP284 is free from reasonable input voltage range restric-
tions, provided that input voltages no greater than the supply
voltages are applied. Although the device’s output will not
change phase, large currents can flow through the input protec-
tion diodes as was shown in Figure 43. Therefore, the technique
recommended in the Input Overvoltage Protection section
should be applied to those applications where the likelihood of
input voltages exceeding the supply voltages is high.
– 5 – 4 – 3 – 2 –1
0
1
2
3
4
5
INPUT VOLTAGE – Volts
Figure 43. Input Overvoltage I-V Characteristics of the
OP284
As shown in the figure, internal p-n junctions to the OP284 en-
ergize and permit current flow from the inputs to the supplies
when the input is 1.8 V more positive and 0.6 V more negative
than the respective supply rails. As illustrated in the simplified
equivalent circuit shown in Figure 41, the OP284 does not have
any internal current limiting resistors; thus, fault currents can
quickly rise to damaging levels.
Designing Low Noise Circuits in Single Supply Applications
In single supply applications, devices like the OP284 extend the
dynamic range of the application through the use of rail-to-rail
operation. In fact, the OP284 family is the first of its kind to
combine single supply, rail-to-rail operation and low noise in
one device. It is the first device in the industry to exhibit an
input noise voltage spectral density of less than 4 nV/√Hz at
1 kHz. It was also designed specifically for low-noise, single-
supply applications, and as such, some discussion on circuit
noise concepts in single supply applications is appropriate.
This input current is not inherently damaging to the device,
provided that it is limited to 5 mA or less. For the OP284, once
the input exceeds the negative supply by 0.6 V, the input cur-
rent quickly exceeds 5 mA. If this condition continues to exist,
an external series resistor should be added at the expense of ad-
ditional thermal noise. Figure 44 illustrates a typical noninvert-
ing configuration for an overvoltage protected amplifier where
the series resistance, RS, is chosen such that:
VIN (MAX ) –VSUPPLY
RS =
5 mA
REV. 0
–11–
OP184/OP284/OP484
Referring to the op amp noise model circuit configuration illus-
trated in Figure 45, the expression for an amplifier’s total
equivalent input noise voltage for a source resistance level RS is
given by:
Since circuit SNR is the critical parameter in the final analysis,
the noise behavior of a circuit is often expressed in terms of its
noise figure, NF. Noise figure is defined as the ratio of a
circuit’s output signal-to-noise to its input signal-to-noise. An
expression of a circuit’s NF in dB, and in terms of the opera-
tional amplifier’s voltage and current noise parameters defined
previously, is given by:
2 e 2 + i
× R 2
)
V
enT
=
+ e
(
2, units in
nOA
(
)
(
)
nR
nOA
[
]
Hz
where RS = 2R = Effective, or equivalent, circuit source
resistance,
2
e
2 + i
R
S
(
)
(
)
nOA
nOA
NF (dB) = 10 log 1+
2
(enOA)2 = Op amp equivalent input noise voltage spectral
power (1 Hz BW),
e
(
)
nRS
(inOA)2 = Op amp equivalent input noise current spectral
power (1 Hz BW),
where NF (dB) = Noise figure of the circuit, expressed in dB,
RS = Effective, or equivalent, source resistance presented
to amplifier,
(enR)2 = Source resistance thermal noise voltage power =
(4kTR),
(enOA)2 = OP284 noise voltage spectral power (1 Hz BW),
(inOA)2 = OP284 noise current spectral power (1 Hz BW),
(enRS)2 = Source resistance thermal noise voltage power
= (4kTRS),
k = Boltzmann’s constant = 1.38 × 10–23 J/K, and
T = Ambient temperature of the circuit, in Kelvin, =
273.15 + TA (°C)
Circuit noise figure is straightforward to calculate because the
signal level in the application is not required to determine it.
However, many designers using NF calculations as the basis for
achieving optimum SNR believe that low noise figure is equal to
low total noise. In fact, the opposite is true, as illustrated in
Figure 47. Here, the noise figure of the OP284 is expressed as a
function of the source resistance level. Note that the lowest
noise figure for the OP284 occurs at a source resistance level of
10 kΩ. However, Figure 46 shows that this source resistance
level and the OP284 generate approximately 14 nV/√Hz of total
equivalent circuit noise. Signal levels in the application would
invariably be increased to maximize circuit SNR—not an option
in low voltage, single supply applications.
e
e
NR
NOA
R
"NOISELESS"
i
NOA
IDEAL
NOISELESS
OP AMP
e
NR
R
"NOISELESS"
i
NOA
R
= 2R
S
Figure 45. Op Amp Noise Circuit Model Used to
Determine Total Circuit Equivalent Input Noise Voltage
and Noise Figure
As a design aid, Figure 46 illustrates the total equivalent input
noise of the OP284 and the total thermal noise of a resistor for
comparison. Note that for source resistance less than 1 kΩ, the
equivalent input noise voltage of the OP284 is dominant.
10
FREQUENCY = 1kHz
9
T
= +25°C
A
8
7
100
6
5
4
3
FREQUENCY = 1kHz
T
= +25°C
A
OP284 TOTAL
EQUIVALENT NOISE
2
1
10
0
100
1k
10k
100k
TOTAL SOURCE RESISTANCE, R – Ω
S
RESISTOR THERMAL
NOISE ONLY
Figure 47. OP284 Noise Figure vs. Source Resistance
1
100
1k
10k
100k
In single supply applications, therefore, it is recommended for
optimum circuit SNR to choose an operational amplifier with
the lowest equivalent input noise voltage and to choose source
resistance levels consistent in maintaining low total circuit noise.
TOTAL SOURCE RESISTANCE, R – Ω
S
Figure 46. OP284 Total Noise vs. Source Resistance
–12–
REV. 0
OP184/OP284/OP484
RP1
Overdrive Recovery
1kΩ
+3V
The overdrive recovery time of an operational amplifier is the
time required for the output voltage to recover to its linear re-
gion from a saturated condition. The recovery time is important
in applications where the amplifier must recover quickly after a
large transient event. The circuit shown in Figure 48 was used
to evaluate the OP284’s overload recovery time. The OP284
takes approximately 2 µs to recover from positive saturation and
approximately 1 µs to recover from negative saturation.
5
8
V
RP2
1kΩ
IN
7
3
2
R3
1.1kΩ
A2
V
OUT
6
1
A1
4
R2
1.1kΩ
R4
10kΩ
C1
R1
9.53kΩ
AC CMRR
TRIM
5pF–40pF
A1, A2 = 1/2 OP284
C2
R4
R2
R1
GAIN = 1 + –––
P1
500Ω
R3
SET R2 = R3
R1 + P1 = R4
10kΩ
10kΩ
+5V
8
Figure 49. A Single Supply, +3 V Low Noise Instrumenta-
tion Amplifier
2
3
1
R3
9kΩ
1/2
OP284
V
OUT
A +2.5 V Reference from a +3 V Supply
4
V
IN
10V STEP
In many single-supply applications, the need for a 2.5 V refer-
ence often arises. Many commercially available monolithic
2.5 V references require at least a minimum operating supply of
4 V. The problem is exacerbated when the minimum operating
supply voltage is +3 V. The circuit illustrated in Figure 50 is an
example of a +2.5 V reference that operates from a single +3 V
supply. The circuit takes advantage of the OP284’s rail-to-rail
input/output voltage ranges to amplify an AD589’s 1.235 V
output to +2.5 V. The OP284’s low TCVOS of 1.5 µV/°C helps
maintain an output voltage temperature coefficient that is domi-
nated by the temperature coefficients of R2 and R3. In this
circuit with 100 ppm/°C TCR resistors, the output voltage
exhibits a temperature coefficient of 200 ppm/°C. Lower tempco
resistors are recommended for more accurate performance over
temperature.
–5V
Figure 48. Output Overload Recovery Test Circuit
A Single-Supply, +3 V Instrumentation Amplifier
The OP284’s low noise, wide bandwidth, and rail-to-rail input/
output operation makes it ideal for low supply voltage applica-
tions such as in a two op amp instrumentation amplifier as
shown in Figure 49. The circuit uses the classic two op amp in-
strumentation amplifier topology with four resistors to set the
gain. The transfer equation of the circuit is identical to that of a
noninverting amplifier. Resistors R2 and R3 should be closely
matched to each other as well as to resistors (R1 + P1) and R4
to ensure good common-mode rejection performance. Resistor
networks should be used in this circuit for R2 and R3 because
they exhibit the necessary relative tolerance matching for good
performance. Matched networks also exhibit tight relative resis-
tor temperature coefficients for good circuit temperature stabil-
ity. Trimming potentiometer P1 is used for optimum dc CMR
adjustment, and C1 is used to optimize ac CMR. With the cir-
cuit values as shown, circuit CMR is better than 80 dB over the
frequency range of 20 Hz to 20 kHz. Circuit RTI (Referred-to-
Input) noise in the 0.1 Hz to 10 Hz band is an impressively low
0.45 µV p-p. Resistors RP1 and RP2 serve to protect the
OP284’s inputs against input overvoltage abuse. Capacitor C2
can be included to the limit circuit bandwidth and, therefore,
wide bandwidth noise in sensitive applications. The value of
this capacitor should be adjusted depending on the required
closed-loop bandwidth of the circuit. The R4-C2 time constant
creates a pole at a frequency equal to:
One measure of the performance of a voltage reference is its
capacity to recover from sudden changes in load current. While
sourcing a steady-state load current of 1 mA, this circuit recov-
ers to 0.01% of the programmed output voltage in 1.5 µs for a
total change in load current of ±1 mA.
+3V
+3V
R1
17.4kΩ
3
8
0.1µF
1
1/2
OP284
+2.5V
REF
2
AD589
4
R3
100kΩ
R2
100kΩ
P1
5kΩ
1
f (3 dB) =
RESISTORS = 1%, 100ppm/°C
POTENTIOMETER = 10 TURN, 100ppm/°C
2 π R4 C2
Figure 50. A +2.5 V Reference that Operates on a Single
+3 V Supply
REV. 0
–13–
OP184/OP284/OP484
A +5 V Only, 12-Bit DAC Swings Rail-to-Rail
For the element values shown, the Monitor Output’s transfer
characteristic is 2.5 V/A.
The OP284 is ideal for use with a CMOS DAC to generate a
digitally-controlled voltage with a wide output range. Figure 51
shows a DAC8043 used in conjunction with the AD589 to gen-
erate a voltage output from 0 V to 1.23 V. The DAC is actually
operating in “voltage switching” mode where the reference is
connected to the current output, IOUT, and the output voltage is
taken from the VREF pin. This topology is inherently noninvert-
ing as opposed to the classic current output mode, which is
inverting and not usable in single supply applications.
R
0.1Ω
I
SENSE
L
+3V
+3V
+3V
0.1µF
1
R1
100Ω
3
2
8
1/2
AD284
4
S
G
M1
Si9433
+5V
D
MONITOR
OUTPUT
8
R1
17.8kΩ
R2
2
1
V
DD
R
FB
2.49kΩ
3
V
REF
1.23V
I
OUT
DAC8043
+5V
8
1/2
OP284
AD589
GND CLK SR1 LD
Figure 52. A High-Side Load Current Monitor
3
2
4
7
6
5
1
D
4096
Capacitive Load Drive Capability
V
= –––– (5V)
OUT
The OP284 exhibits excellent capacitive load driving capabili-
ties. It can drive up to 1 nF as shown in Figure 27. Even
though the device is stable, a capacitive load does not come
without penalty in bandwidth. The bandwidth is reduced to
under 1 MHz for loads greater than 2 nF. A “snubber” network
on the output does not increase the bandwidth, but it does sig-
nificantly reduce the amount of overshoot for a given capacitive
load. A snubber consists of a series R-C network (RS, CS), as
shown in Figure 53, connected from the output of the device to
ground. This network operates in parallel with the load capaci-
tor, CL, to provide the necessary phase lag compensation. The
value of the resistor and capacitor is best determined empirically.
DIGITAL
CONTROL
4
R3
232Ω
1%
R2
32.4kΩ
1%
R4
100kΩ
1%
Figure 51. A +5 V Only, 12-Bit DAC Swings Rail-to-Rail
In this application the OP284 serves two functions. First, it
buffers the high output impedance of the DAC’s VREF pin,
which is on the order of 10 kΩ. The op amp provides a low
impedance output to drive any following circuitry. Second, the
op amp amplifies the output signal to provide a rail-to-rail out-
put swing. In this particular case, the gain is set to 4.1 so that
the circuit generates a 5 V output when the DAC output is at
full scale. If other output voltage ranges are needed, such as 0 V
≤ VOUT ≤ 4.095 V, the gain can be easily changed by adjusting
the values of R2 and R3.
+5V
0.1µF
1/2
OP284
V
OUT
V
IN
100mVp-p
R
50Ω
S
C
A High-Side Current Monitor
L
1nF
C
S
In the design of power supply control circuits, a great deal of
design effort is focused on ensuring a pass transistor’s long-term
reliability over a wide range of load current conditions. As a
result, monitoring and limiting device power dissipation is of
prime importance in these designs. The circuit illustrated in
Figure 52 is an example of a +3 V, single-supply high-side cur-
rent monitor that can be incorporated into the design of a volt-
age regulator with fold-back current limiting or a high current
power supply with crowbar protection. This design uses an
OP284’s rail-to-rail input voltage range to sense the voltage
drop across a 0.1 Ω current shunt. A p-channel MOSFET used
as the feedback element in the circuit converts the op amp’s dif-
ferential input voltage into a current. This current is applied to
R2 to generate a voltage that is a linear representation of the
load current. The transfer equation for the current monitor is
given by:
100nF
Figure 53. Snubber Network Compensates for Capacitive
Load
The first step is to determine the value of the resistor RS. A
good starting value is 100 Ω (typically, the optimum value will
be less than 100 Ω). This value is reduced until the small-signal
transient response is optimized. Next, CS is determined—10 µF
is a good starting point. This value is reduced to the smallest
value for acceptable performance (typically, 1 µF). For the case
of a 10 nF load capacitor on the OP284, the optimal snubber
network is a 20 Ω in series with 1 µF. The benefit is immedi-
ately apparent as shown in the scope photo in Figure 54. The
top trace was taken with a 1 nF load, and the bottom trace was
taken with the 50 Ω, 100 nF snubber network in place. The
amount of overshoot and ringing is dramatically reduced. Table I
below illustrates a few sample snubber networks for large load
capacitors.
RSENSE
Monitor Output = R2 ×
× IL
R1
–14–
REV. 0
OP184/OP284/OP484
Figure 55 shows such a regulator set up using an OP284 plus a
low RDS(ON), P-channel MOSFET pass device. Part of the low
dropout performance of this circuit is provided by Q1, which
has a rating of 0.11 Ω with a gate drive voltage of only 2.7 V.
This relatively low gate drive threshold allows operation of the
regulator on supplies as low as 3 V without compromising over-
all performance.
µs
100
90
1nF LOAD
ONLY
SNUBBER
IN
CIRCUIT
10
0%
The circuit’s main voltage control loop operation is provided by
U1B, half of the OP284. This voltage control amplifier ampli-
fies the 2.5 V reference voltage produced by three terminal U2,
a REF192. The regulated output voltage VOUT is then:
50m
50m
v
v
2µs
Figure 54. Overshoot and Ringing Is Reduced by Adding a
“Snubber” Network in Parallel with the 1 nF Load
R2
VOUT =VOUT 2 1+
(
)
R3
Table I. Snubber Networks for Large Capacitive Loads
For this example, since VOUT of 4.5 V with VOUT2 = 2.5 V re-
quires a U1B gain of 1.8 times, R3 and R2 are chosen for a ratio
of 1.2:1 or 10.0 kΩ:8.06 kΩ (using closest 1% values). Note
that for the lowest VOUT dc error, R2ʈR3 should be maintained
equal to R1 (as here), and the R2-R3 resistors should be stable,
close tolerance metal film types. The table in Figure 55 sum-
marizes R1-R3 values for some popular voltages. However,
note that, in general, the output can be anywhere between
Load Capacitance
(CL)
Snubber Network
(RS, CS)
1 nF
10 nF
100 nF
50 Ω, 100 nF
20 Ω, 1 µF
5 Ω, 10 µF
VOUT2 and the 12 V maximum rating of Q1.
A Low Dropout Regulator with Current Limiting
While the low voltage saturation characteristic of Q1 is a key
part of the low dropout, another component is a low current
sense comparison threshold with good dc accuracy. Here, this
is provided by current sense amplifier U1A, which is provided
by a 20 mV reference from the 1.235 V AD589 reference diode
D2 and the R7-R8 divider. When the product of the output
current and the RS value match this voltage threshold, the cur-
rent control loop is activated, and U1A drives Q1’s gate through
D1. This causes the overall circuit operation to enter current
mode control with a current limit ILIMIT defined as:
Many circuits require stable regulated voltages relatively close,
in potential to an unregulated input source. This “low dropout”
type of regulator is readily implemented with a rail-to-rail out-
put op amp such as the OP284 because the wide output swing
allows easy drive to a low saturation voltage pass device. Fur-
thermore, it is particularly useful when the op amp also enjoys a
rail-rail input feature, as this factor allows it to perform high-
side current sensing for positive rail current limiting. Typical ex-
amples are voltages developed from 3 V to 9 V range system
sources or anywhere where low dropout performance is required
for power efficiency. The 4.5 V case here works from 5 V nomi-
nal sources with worst-case levels down to 4.6 V or less.
VR(D2)
RS
R7
R7 + R8
ILIMIT
=
(
)
C4
0.1µF
R
S
Q1
SI9433DY
0.05Ω
+V
S
V
>
V
+ 0.1V
R7
4.99kΩ
S
OUT
R6
4.99kΩ
R5
22.1kΩ
U1A
OP284
D1
1N4148
D2
AD589
3
2
8
4
1
R8
301kΩ
R4
2.21kΩ
C 1
0.01µF
C 5
0.01µF
R9
27.4kΩ
6
5
7
D 3
1N4148
R11
1kΩ
R2
8.06kΩ
U1B
OP284
R1
4.53kΩ
V
=
OUT
4.5V @ 350mA
(SEE TABLE)
U2
OUTPUT TABLE
R2 R3
REF192
6
2
V
R1
OUT
C3
R3
10kΩ
V
2.5V
0.1µF
5.0V
4.5V
3.3V
3.0V
4.99k 10.0k 10.0k
4.53k 8.06k 10.0k
2.43k 3.24k 10.0k
1.69k 2.00k 10.0k
OUT
2
3
C6
10µF
V
C
R10
1kΩ
C 2
1µF
OPTIONAL
4
ON/OFF CONTROL INPUT
CMOS HI (OR OPEN) = ON
LO = OFF
V
COMMON
V
COMMON
IN
OUT
Figure 55. A Low Dropout Regulator with Current Limiting
–15–
REV. 0
OP184/OP284/OP484
Obviously, it is desirable to keep this comparison voltage small,
since it becomes a significant portion of the overall dropout
voltage. Here, the 20 mV reference is higher than the typical
offset of the OP284 but still reasonably low as a percentage of
physiological signals, such as heart rates, blood pressure read-
ings, EEGs, EKGs, etc. This notch filter effectively squelches
60 Hz pickup at a filter Q of 0.75. Substituting 3.16 kΩ resis-
tors for the 2.67 kΩ in the twin-T section (R1 through R5)
configures the active filter to reject 50 Hz interference.
V
OUT (< 0.5%). In adapting the limiter for other ILIMIT levels,
sense resistor RS should be adjusted along with R7-R8, to main-
tain this threshold voltage between 20 mV and 50 mV.
R2
2.67kΩ
+3V
R1
Performance of the circuit is excellent. For the 4.5 V output
version, the measured dc output change for a 225 mA load
change was on the order of a few microvolts while the dropout
voltage at this same current level was about 30 mV. The current
limit as shown is 400 mA, which allows the circuit to be used at
levels up to 300 mA or more. While the Q1 device can actually
support currents of several amperes, a practical current rating
takes into account the SO-8 device’s 2.5 W, 25°C dissipation.
Because a short circuit current of 400 mA at an input level of 5
V will cause a 2 W dissipation in Q1, other input conditions
should be considered carefully in terms of Q1’s potential over-
heating. Of course, if higher powered devices are used for Q1,
this circuit can support outputs of tens of amperes as well as the
higher VOUT levels noted above.
C1
1µF
C 2
1µF
2.67kΩ
4
2
3
5
6
1
A1
7
V
O
V
A2
11
IN
R3
2.67kΩ
R4
2.67kΩ
R6
10kΩ
R7
1kΩ
C3
2µF
(1µF x 2)
R5
1.33kΩ
(2.67kΩ ÷ 2)
R8
1kΩ
R11
10kΩ
Q = 0.75
C5
0.03µF
NOTE: FOR 50Hz APPLICATIONS
+3V
CHANGE R1–R4 TO 3.1kΩ
AND R5 TO 1.58kΩ (3.16kΩ ÷ 2).
R12
150Ω
9
R9
8
20kΩ
A3
The circuit shown can be used either as a standard low dropout
regulator, or it can be used with ON/OFF control. By
1.5V
C6
1µF
10
R10
C4
1µF
20kΩ
driving Pin 3 of U1 with the optional logic control signal VC, the
output is switched between ON and OFF. Note that when the
output is OFF in this circuit, it is still active (i.e., not an open cir-
cuit). This is because the OFF state simply reduces the voltage
input to R1, leaving the U1A/B amplifiers and Q1 still active.
A1, A2, A3 = OP484
Figure 56. A +3 V Single Supply, 50/60 Hz Active Notch
Filter with False Ground
Amplifier A3 is the heart of the false-ground bias circuit. It
simply buffers the voltage developed at R9 and R10 and is the
reference for the active notch filter. Since the OP484 exhibits a
rail-to-rail input common-mode range, R9 and R10 are chosen
to split the +3 V supply symmetrically. An in-the-loop compen-
sation scheme is used around the OP484 that allows the op amp
to drive C6, a 1 µF capacitor, without oscillation. C6 maintains
a low impedance ac ground over the operating frequency range
of the filter.
When ON/OFF control is used, resistor R10 should be used
with U1 to speed ON-OFF switching and to allow the output of
the circuit to settle to a nominal zero voltage. Components D3
and R11 also aid in speeding up the ON-OFF transition by pro-
viding a dynamic discharge path for C2. OFF-ON transition
time is less than 1 ms, while the ON-OFF transition is longer
but under 10 ms.
A +3 V, 50 Hz/60 Hz Active Notch Filter with False Ground
To process signals in a single-supply system, it is often best
to use a false ground biasing scheme. A circuit that uses this
approach is illustrated in Figure 56. In this circuit, a false-ground
circuit biases an active notch filter used to reject 50 Hz/60 Hz
power line interference in portable patient monitoring equip-
ment. Notch filters are quite commonly used to reject power
line frequency interference that often obscures low frequency
The filter section uses a OP484 in a twin-T configuration whose
frequency selectivity is very sensitive to the relative matching of
the capacitors and resistors in the twin-T section. Mylar is the
material of choice for the capacitors, and the relative matching
of the capacitors and resistors determines the filter’s pass band
symmetry. Using 1% resistors and 5% capacitors produces
satisfactory results.
–16–
REV. 0
OP184/OP284/OP484
DN5
DN6
*
19
23
23
24
DIN
DIN
*OP284 SPICE Macro-model
*
*
9/94 / Rev. A
ARG/ADI
* GAIN STAGE
*
* Copyright 1995 by Analog Devices
*
* Refer to “README.DOC” file for License Statement. Use of
EREF 98
0
POLY(2) (99,0) (50,0) 0 0.5 0.5
POLY(2) (6,5) (8,7) 0 0.5E-3 0.5E-3
1E3
G1
R9
*
98
20
20
98
this model
* indicates your acceptance of the terms and provisions in the
License
* COMMON MODE STAGE WITH ZERO AT 100Hz
*
* Statement.
*
* Node assignments
*
*
*
*
*
ECM
R10
R11
C4
98
21
22
21
21
22
98
22
POLY(2) (1,98) (2,98) 0 0.5 0.5
1
100E-6
1.592E-3
noninverting input
| inverting input
| | positive supply
*
| |
| |
| |
|
|
|
negative supply
| output
| |
* NEGATIVE ZERO AT 20MHz
*
*
E1
27
27
28
25
25
26
27
98
28
98
26
98
98
28
(20,98) 1E6
1
1E-6
7.958E-9
(27,28) 1
DC 0
.SUBCKT OP284
*
* INPUT STAGE
*
1 2 99 50 45
R17
R18
C8
ENZ
VNZ
FNZ
*
Q1
5
2
11
2
11
11
2
9
9
10
10
5
3
3
4
4
QIN 1
QIN 1
QIP 1
QIP 1
Q2
6
VNZ -1
Q3
7
Q4
8
* POLE AT 40MHz
*
DC1
DC2
Q5
2
11
4
DC
DC
99
99
50
50
4E3
4E3
4E3
4E3
G4
R19
C9
*
98
29
29
29
98
98
(28,98) 1
1
3.979E-9
QIP 1
QIP 1
QIN 1
QIN 1
Q6
9
Q7
3
Q8
R1
R2
R3
10
99
99
7
* POLE AT 40MHz
*
6
G5
R20
C10
*
98
30
30
30
98
98
(29,98) 1
1
3.979E-9
50
50
10
11
1
2
1
2
R4
8
IREF
EOS
IOS
CIN
GN1
GN2
*
9
1
2
1
98
98
50.5E-6
POLY(2) (22,98) (14,98) -25E-6 1E-2 1
* OUTPUT STAGE
*
5E-9
2E-12
(17,98) 1E-3
(23,98) 1E-3
ISY
GIN
RIN
VB
Q11
R21
I1
R22
Q12
I2
R23
R24
Q13
Q14
R25
Q15
R26
R27
Q16
Q17
R28
99
50
31
99
32
33
34
99
36
36
99
34
39
39
40
39
41
99
44
44
42
50
31
50
32
31
34
50
35
36
50
37
38
36
38
50
39
42
43
44
39
50
97
0.276E-3
POLY(1) (30,98) .862574E-6 505.879E-6
2.75E6
0.7
* VOLTAGE NOISE SOURCE WITH FLICKER NOISE
*
33
QON 1
4.5E3
50E-6
6E3
35
VN1
VN2
DN1
DN2
*
13
98
13
14
98
15
14
15
DC 2
DC 2
DEN
DEN
QOP 1
50E-6
2.6E3
5E3
37
* CURRENT NOISE SOURCE WITH FLICKER NOISE
*
QOP 1
VN3
VN4
DN3
DN4
*
16
98
16
17
98
18
17
18
DC 2
DC 2
DIN
DIN
40
QON 1.5
40
41
QON 1
1E3
220
43
* 2ND CURRENT NOISE SOURCE WITH FLICKER
NOISE
*
QOP 1.5
QON 1
42
2E3
DC 0
VN5
VN6
19
98
98
24
DC 2
DC 2
VSCP 99
REV. 0
–17–
OP184/OP284/OP484
FSCP 46
RSCP 46
99
99
46
44
34
50
47
50
47
45
34
42
45
45
99
45
VSCP 1
40
Q20
Q18
Q19
44
45
45
99
QOP 1
97
51
QOP 4.5
QON 4.5
VSCN 51
FSCN 50
RSCN 47
DC 0
VSCN 1
40
Q21
CC2
CF1
CF2
CO1
CO2
D3
34
31
31
31
34
42
45
50
50
QON 1
20E-12
15E-12
15E-12
15E-12
5E-12
DX
D4
DX
.MODEL DC D(IS=130E-21)
.MODEL DX D()
.MODEL DEN D(RS=100 KF=12E-15 AF=1)
.MODEL DIN D(RS=5.358 KF=56E-15 AF=1)
.MODEL QIN NPN(BF=200 VA=200 IS=0.5E-16)
.MODEL QIP PNP(BF=100 VA=60 IS=0.5E-16)
.MODEL QON NPN(BF=200 VA=200 IS=0.5E-16 RC=50)
.MODEL QOP PNP(BF=200 VA=200 IS=0.5E-16 RC=160)
.ENDS
–18–
REV. 0
OP184/OP284/OP484
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
8-Lead Epoxy DIP
(P Suffix)
14-Lead Epoxy DIP
(P Suffix)
0.795 (20.19)
0.725 (18.42)
0.430 (10.92)
0.348 (8.84)
14
1
8
7
8
5
4
0.280 (7.11)
0.240 (6.10)
0.280 (7.11)
0.240 (6.10)
1
0.325 (8.25)
0.300 (7.62)
0.325 (8.25)
0.300 (7.62)
0.195 (4.95)
0.115 (2.93)
0.060 (1.52)
0.015 (0.38)
0.060 (1.52)
0.015 (0.38)
PIN 1
PIN 1
0.195 (4.95)
0.115 (2.93)
0.210 (5.33)
MAX
0.210 (5.33)
MAX
0.130
0.130
(3.30)
MIN
(3.30)
MIN
0.160 (4.06)
0.115 (2.93)
0.160 (4.06)
0.115 (2.93)
0.015 (0.381)
0.008 (0.204)
0.015 (0.381)
0.008 (0.204)
SEATING
PLANE
SEATING
PLANE
0.100 0.070 (1.77)
0.022 (0.558)
0.070 (1.77)
0.045 (1.15)
0.022 (0.558)
0.014 (0.356)
0.100
(2.54)
BSC
(2.54)
BSC
0.045 (1.15)
0.014 (0.356)
8-Lead SO
(S Suffix)
14-Lead Narrow-Body SO
(S Suffix)
0.1968 (5.00)
0.1890 (4.80)
0.3444 (8.75)
0.3367 (8.55)
8
1
5
14
1
8
0.2440 (6.20)
0.2440 (6.20)
0.2284 (5.80)
0.1574 (4.00)
0.1497 (3.80)
0.1574 (4.00)
0.2284 (5.80)
0.1497 (3.80)
7
4
0.0688 (1.75)
0.0688 (1.75)
0.0532 (1.35)
0.0196 (0.50)
PIN 1
0.0196 (0.50)
PIN 1
x 45°
x 45°
0.0532 (1.35)
0.0099 (0.25)
0.0099 (0.25)
0.0098 (0.25)
0.0040 (0.10)
0.0098 (0.25)
0.0040 (0.10)
8°
0°
8°
0°
0.0500 0.0192 (0.49)
0.0500
(1.27)
BSC
0.0192 (0.49)
0.0500 (1.27)
0.0160 (0.41)
0.0500 (1.27)
0.0160 (0.41)
0.0098 (0.25)
0.0075 (0.19)
0.0098 (0.25)
0.0075 (0.19)
SEATING
PLANE
SEATING
PLANE
(1.27)
0.0138 (0.35)
0.0138 (0.35)
BSC
REV. 0
–19–
–20–
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