OPZ275GPZ [ADI]
IC DUAL OP-AMP, 1250 uV OFFSET-MAX, 9 MHz BAND WIDTH, PDIP8, PLASTIC, DIP-8, Operational Amplifier;
| 型号： | OPZ275GPZ |
| 厂家： | 
ADI |
| 描述： | IC DUAL OP-AMP, 1250 uV OFFSET-MAX, 9 MHz BAND WIDTH, PDIP8, PLASTIC, DIP-8, Operational Amplifier 放大器 光电二极管 |
| 文件： | 总12页 (文件大小：282K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Dual Bipolar/JFET, Audio
Operational Amplifier
OP275
FEATURES
PIN CONNECTIONS
Excellent Sonic Characteristics
Low Noise: 6 nV/ Hz
8-Lead Narrow-Body SOIC
(S Suffix)
8-Lead PDIP
(P Suffix)
Low Distortion: 0.0006%
High Slew Rate: 22V/s
Wide Bandwidth: 9 MHz
Low Supply Current: 5 mA
Low OffsetVoltage: 1 mV
Low Offset Current: 2 nA
Unity Gain Stable
1
8
7
6
5
OUT A
–IN A
+IN A
V–
V+
OP275
8
V+
1
2
3
4
OUT A
–IN A
+IN A
V–
2
3
4
OUT B
–IN B
+IN B
OP275
7
6
5
OUT B
–IN B
+IN B
SOIC-8 Package
PDIP-8 Package
APPLICATIONS
High Performance Audio
Active Filters
Fast Amplifiers
Integrators
GENERAL DESCRIPTION
Improved dc performance is also provided with bias and offset
currents greatly reduced over purely bipolar designs. Input offset
voltage is guaranteed at 1 mV and is typically less than 200 µV.
This allows the OP275 to be used in many dc-coupled or sum-
ming applications without the need for special selections or the
added noise of additional offset adjustment circuitry.
The OP275 is the first amplifier to feature the Butler Amplifier
front end.This new front end design combines both bipolar
and JFET transistors to attain amplifiers with the accuracy and
low noise performance of bipolar transistors, and the speed and
sound quality of JFETs. Total Harmonic Distortion plus Noise
equals that of previous audio amplifiers, but at much lower
supply currents.
The output is capable of driving 600 loads to 10V rms while
maintaining low distortion.THD + Noise at 3V rms is a low
0.0006%.
A very low l/f corner of below 6 Hz maintains a flat noise density
response.Whether noise is measured at either 30 Hz or 1 kHz,
The OP275 is specified over the extended industrial (–40°C to
+85°C) temperature range. OP275s are available in both plas-
tic DIP and SOIC-8 packages. SOIC-8 packages are available
in 2500-piece reels. Many audio amplifiers are not offered
in SOIC-8 surface-mount packages for a variety of reasons;
however, the OP275 was designed so that it would offer full
performance in surface-mount packaging.
it is only 6 nV Hz.The JFET portion of the input stage gives
the OP275 its high slew rates to keep distortion low, even when
large output swings are required, and the 22V/µs slew rate of the
OP275 is the fastest of any standard audio amplifier. Best of all,
this low noise and high speed are accomplished using less than
5 mA of supply current, lower than any standard audio amplifier.
REV.C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed byAnalog Devices for its
use, nor for any infringements of patents or other rights of third parties
that may result from its use. No license is granted by implication or oth-
erwise under any patent or patent rights of Analog Devices.Trademarks
and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
www.analog.com
© 2004 Analog Devices, Inc. All rights reserved.
OP275–SPECIFICATIONS
(@ V = 15.0 V, T = 25C, unless otherwise noted.)
ELECTRICAL CHARACTERISTICS
S
A
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
AUDIO PERFORMANCE
THD + Noise
VIN = 3V rms,
RL = 2 k, f = 1 kHz
f = 30 Hz
f = 1 kHz
f = 1 kHz
THD + Noise 0.01%,
RL = 2 k,VS = ±18V
0.006
7
6
%
nV Hz
nV Hz
pA Hz
Voltage Noise Density
en
in
Current Noise Density
Headroom
1.5
>12.9
dBu
INPUT CHARACTERISTICS
OffsetVoltage
VOS
IB
1
mV
mV
nA
nA
nA
nA
V
–40°C TA +85°C
VCM = 0V
VCM = 0V, –40°C TA +85°C
VCM = 0V
1.25
350
400
50
100
+10.5
Input Bias Current
Input Offset Current
100
100
2
IOS
VCM = 0V, –40°C TA +85°C
2
InputVoltage Range
VCM
–10.5
Common-Mode Rejection Ratio
CMRR
VCM = ±10.5V,
–40°C TA +85°C
RL = 2 k
RL = 2 k, –40°C TA +85°C
RL = 600
80
250
175
106
dB
Large SignalVoltage Gain
AVO
V/mV
V/mV
V/mV
µV/°C
200
2
OffsetVoltage Drift
VOS/T
OUTPUT CHARACTERISTICS
OutputVoltage Swing
VO
RL = 2 k
RL = 2 k, –40°C TA +85°C
RL = 600 ,VS = ±18V
–13.5
–13
±13.9
±13.9
+14, –16
+13.5
+13
V
V
V
POWER SUPPLY
Power Supply Rejection Ratio
PSRR
ISY
VS = ±4.5V to ±18V
VS = ±4.5V to ±18V,
–40°C TA +85°C
VS = ±4.5V to ±18V,VO = 0V,
RL = , –40°C TA +85°C
VS = ±22V,VO = 0V, RL = ,
–40°C TA +85°C
85
80
111
4
dB
dB
mA
Supply Current
5
5.5
±22
mA
V
SupplyVoltage Range
VS
±4.5
15
DYNAMIC PERFORMANCE
Slew Rate
SR
RL = 2 k
22
V/µs
Full-Power Bandwidth
Gain Bandwidth Product
Phase Margin
BWP
GBP
Øm
kHz
MHz
Degrees
9
62
Overshoot Factor
VIN = 100 mV, AV = +1,
RL = 600 , CL = 100 pF
10
%
Specifications subject to change without notice.
–2–
REV. C
OP275
ABSOLUTE MAXIMUM RATINGS1
SupplyVoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±22V
InputVoltage2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±22V
Differential InputVoltage2 . . . . . . . . . . . . . . . . . . . . . . . ±7.5V
Output Short-Circuit Duration to GND3 . . . . . . . . . . Indefinite
StorageTemperature Range
P, S Packages . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
OperatingTemperature Range
OP275G . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
JunctionTemperature Range
P, S Packages . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
LeadTemperature Range (Soldering, 60 sec) . . . . . . . . . .300°C
4
PackageType
JA
JC
Unit
8-Lead Plastic DIP (P)
8-Lead SOIC (S)
103
158
43
43
°C/W
°C/W
NOTES
1Absolute maximum ratings apply to packaged parts, unless otherwise noted.
2For supply voltages greater than ±22V, the absolute maximum input voltage is equal
to the supply voltage.
3Shorts to either supply may destroy the device. See data sheet for full details.
4JA is specified for the worst-case conditions, i.e., JA is specified for device in socket
for PDIP packages; JA is specified for device soldered in circuit board for SOIC
packages.
ORDERING GUIDE
Model
Temperature Range
Package Description
Package Option
OP275GP
OP275GS
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
8-Lead PDIP
8-Lead SOIC
8-Lead SOIC
8-Lead SOIC
8-Lead SOIC
8-Lead SOIC
8-Lead SOIC
N-8
R-8
R-8
R-8
R-8
R-8
R-8
OP275GS-REEL
OP275GS-REEL7
OP275GSZ*
OP275GSZ-REEL*
OP275GSZ-REEL7*
*Z = Pb-free part.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily accumulate
on the human body and test equipment and can discharge without detection. Although the OP275 features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
REV. C
–3–
OP275–Typical Performance Characteristics
25
1500
1250
1000
750
500
250
0
T
R
= 25C
= 2k
V
V
=
=
15V
15V
A
40
30
20
180
20
S
L
V
= 15V
O
S
A
15
135
90
+GAIN
= 2k
T
= 25
C
+VOM
R
L
10
5
10
0
45
–GAIN
0
0
R
= 2k
L
+GAIN
= 600
–10
–20
–30
–40
–45
–90
–135
–5
R
L
–10
–15
–20
–25
–VOM
–GAIN
= 600
R
L
–180
1M
FREQUENCY – Hz
10M
10k
100k
–50
–25
0
25
50
75
100
0
5
10
15
20
25
TEMPERATURE – C
SUPPLY VOLTAGE – V
TPC 2. Open-Loop Gain vs.
Temperature
TPC 1. Output Voltage Swing
vs. Supply Voltage
TPC 3. Closed-Loop Gain and
Phase, AV = +1
50
40
60
50
MARKER 15 309.059Hz
MAG (A/H)
60.115dB
V
T
=
= 25
15V
60
50
40
S
V
T
= 15V
= 25C
V
=
15V
C
S
S
A
A
A
= +100
VCL
A
T
= 25
C
30
A
= +1
VCL
40
30
20
10
0
20
135
90
30
20
A
= +10
A
A
= +10
= +1
VCL
VCL
VCL
10
A
= +100
VCL
MARKER 15 309.058Hz
PHASE (A/R) 90.606Deg
10
45
0
0
0
–10
–20
–30
–10
–20
–45
–90
1k
10k
100k
1M
10M
100M
100
1k
10k
100k
1M
10M
1M
FREQUENCY – Hz
10M
10k
100k
FREQUENCY – Hz
FREQUENCY – Hz
TPC 4. Open-Loop Gain,
Phase vs. Frequency
TPC 5. Closed-Loop Gain vs.
Frequency
TPC 6. Closed-Loop Output
Impedance vs. Frequency
120
100
80
60
40
20
0
120
100
80
V
=
= 2k
= 25C
15V
S
V
T
= 15V
= 25C
0
S
A
R
T
L
100
80
60
40
20
0
GAIN
+PSRR
A
60
45
40
90
Ø
= 58
m
V
T
=
=
25C
15V
S
A
PHASE
20
135
180
225
270
–PSRR
0
–20
–40
–60
10
100
1k
10k
100k
1M
1k
10k
100k
1M
10M
100M
100
1k
10k
100k
1M
10M
FREQUENCY – Hz
FREQUENCY – Hz
FREQUENCY – Hz
TPC 7. Common-Mode
Rejection vs. Frequency
TPC 8. Power Supply Rejection vs.
Frequency
TPC 9. Open-Loop Gain,
Phase vs. Frequency
–4–
REV. C
OP275
11
10
9
100
90
80
70
60
50
40
30
20
10
0
65
60
55
50
40
16
A
= +1
VCL
NEGATIVE EDGE
14
12
–VOM
Øm
10
8
A
= +1
VCL
POSITIVE EDGE
+VOM
GBW
6
4
2
0
V
= 15V
S
8
R
= 2k
= 100mV p-p
L
T
V
= 25C
A
V
IN
= 15V
S
7
0
100
200
300
400
500
–50
–25
0
25
50
75
100
100
1k
LOAD RESISTANCE –
10k
LOAD CAPACITANCE – pF
TEMPERATURE – C
TPC 11. Small Signal Overshoot vs.
Load Capacitance
TPC 10. Gain Bandwidth Product,
Phase Margin vs.Temperature
TPC 12. Maximum Output
Voltage vs. Load Resistance
30
25
20
15
5.0
4.5
120
110
100
90
V
= 15V
S
SINK
T
T
T
= +85C
= +25C
= –40C
A
80
4.0
3.5
3.0
A
70
T
V
A
R
= 25C
60
A
S
A
=
= +1
15V
10
5
50
VCL
L
= 2k
40
SOURCE
30
0
20
–50
0
5
10
15
20
25
1k
10k
100k
FREQUENCY – Hz
1M
10M
–25
0
25
50
75
100
SUPPLY VOLTAGE – V
TEMPERATURE – C
TPC 13. Maximum Output
Swing vs. Frequency
TPC 14. Supply Current vs.
Supply Voltage
TPC 15. Short-Circuit Current
vs.Temperature
5
300
250
200
150
100
50
500
400
300
200
100
0
V
S
= 15V
= 25C
V
=
15V
V
= ±15V
S
S
T
A
–40
C to +85C
4
3
BASED ON 920 OP AMPS
2
1
0
–50
10
100
1k
100k
–25
0
25
50
75
100
0
1
2
3
4
5
6
7
8
9
10
FREQUENCY – Hz
TEMPERATURE – C
TCV – V/C
OS
TPC 16. Input Bias Current vs.
Temperature
TPC 17. Current Noise Density
vs. Frequency
TPC 18.TCVOS Distribution
REV. C
–5–
OP275
10
8
50
45
40
35
30
25
20
200
V
=
= 25
15V
C
BASED ON 920 OP AMPS
T
=
25
V = 15V
S
C
S
A
T
A
160
120
80
6
+0.1%
+0.01%
4
2
0
–SR
+SR
–2
–4
–6
–8
–10
–0.01%
–0.1%
40
0
0
100
200
300
400
500
–400–300–200
–500 –100
0
100 200
300
INPUT OFFSET VOLTAGE – V
400
500
0
100 200 300 400 500 600 700 800 900
SETTLING TIME – ns
CAPACITIVE LOAD – pF
TPC 19. Input Offset (VOS
Distribution
)
TPC 20. Step Size vs. Settling
Time
TPC 21. Slew Rate vs. Capacitive
Load
40
35
30
25
50
45
40
35
30
25
20
V
=
15V
S
V
R
=
= 2k
15V
S
R
= 2k
L
100
90
–SR
+SR
L
T
= 25C
A
20
15
10
5
10
0%
5V
200ns
0
–50
–25
0
25
50
75
100
0
0.2
0.4
0.6
0.8
1.0
TEMPERATURE –
C
DIFFERENTIAL INPUT VOLTAGE – V
TPC 22. Slew Rate vs. Differential
Input Voltage
TPC 23. Slew Rate vs.Temperature
TPC 24. Negative Slew Rate
RL = 2 k , VS = ±15 V, AV = +1
CH A: 80.0 V FS
MKR: 6.23 nV/ Hz
10.0 V/DIV
100
90
100
90
10
10
0%
0%
0 Hz
MKR:
2.5 kHz
BW: 15.0 MHz
5V
50mV
200ns
100ns
1 000 Hz
TPC 25. Positive Slew Rate
RL = 2 k , VS = ±15 V, AV = +1
TPC 26. Small Signal Response
RL = 2 k , VS = ±5 V, AV = +1
TPC 27. Voltage Noise Density
vs. Frequency VS = ±15 V
–6–
REV. C
OP275
0.010
APPLICATIONS
Circuit Protection
OP275 has been designed with inherent short-circuit protection
V
R
= 18V
= 600
S
L
to ground. An internal 30
limits the output current at room temperature to ISC+ = 40 mA
and ISC– = –90 mA, typically, with ±15V supplies.
resistor, in series with the output,
0.001
However, shorts to either supply may destroy the device when
excessive voltages or currents are applied. If it is possible for a
user to short an output to a supply for safe operation, the output
current of the OP275 should be design-limited to ±30 mA, as
shown in Figure 1.
0.0001
0.5
1
10
OUTPUT SWING – V rms
Figure 4. Headroom,THD + Noise vs. Output
Amplitude (V rms); RLOAD = 600 , VSUP = ±18 V
Total Harmonic Distortion
Total Harmonic Distortion + Noise (THD + N) of the OP275 is
The output of the OP275 is designed to maintain low harmonic
well below 0.001% with any load down to 600
. However, this is
distortion while driving 600
loads. However, driving 600
dependent upon the peak output swing. In Figure 2, the THD +
Noise with 3 V rms output is below 0.001%. In Figure 3, THD +
loads with very high output swings results in higher distortion if
clipping occurs. A common example of this is in attempting to
drive 10V rms into any load with ±15V supplies. Clipping will
occur and distortion will be very high. To attain low harmonic
distortion with large output swings, supply voltages may be
increased. Figure 5 shows the performance of the OP275 driving
Noise is below 0.001% for the 10 k and 2 k loads but increases
to above 0.1% for the 600 load condition. This is a result of the
output swing capability of the OP275. Notice the results in Figure 4,
showing THD versus VIN (V rms). This figure shows that the THD
+ Noise remains very low until the output reaches 9.5 V rms. This
performance is similar to competitive products.
600
loads with supply voltages varying from ±18 V to ±20 V.
Notice that with ±18V supplies the distortion is fairly high, while
with ±20V supplies it is a very low 0.0007%.
R
FB
0.0001
FEEDBAC
K
R
X
–
332
A1
V
OUT
0.001
+
A1 = 1/2 OP275
R
= 600
L
V
= 10V rms @ 1kHz
OUT
Figure 1. Recommended Output Short-Circuit Protection
0.01
0.1
0
0.010
R
= 600, 2k, 10k
L
V
= 15V
S
V
A
= 3V rms
= +1
IN
V
17
18
19
20
21
22
SUPPLY VOLTAGE – V
0.001
Figure 5.THD + Noise vs. Supply Voltage
0.0005
20
100
1k
FREQUENCY – Hz
10k
20k
Noise
The voltage noise density of the OP275 is below 7 nV/ Hz from
30 Hz.This enables low noise designs to have good performance
throughout the full audio range. Figure 6 shows a typical OP275
with a 1/f corner at 2.24 Hz.
Figure 2.THD + Noise vs. Frequency vs. RLOAD
1
600
CH A: 80.0
V FS
MKR: 45.6
10.0V/DIV
0.1
A
= +1
= 18V
V
V/ Hz
V
S
V
= 10V rms
IN
80kHz FILTER
0.010
0.001
2k
10k
0.0001
20
100
1k
10k
20k
FREQUENCY – Hz
0Hz
MKR:
Figure 3.THD + Noise vs. RLOAD; VIN =10 V rms
10Hz
BW: 0.145Hz
2.24Hz
Figure 6. 1/f Noise Corner, VS = ±15 V, AV = 1000
REV. C
–7–
OP275
NoiseTesting
prevent phase reversal; however, they will not prevent this effect
from occurring in noninverting applications. For these applications,
For audio applications, the noise density is usually the most
important noise parameter. For characterization, the OP275 is
tested using an Audio Precision, System One. The input signal
to the Audio Precision must be amplified enough to measure it
accurately. For the OP275, the noise is gained by approximately
1020 using the circuit shown in Figure 7. Any readings on the
Audio Precision must then be divided by the gain. In imple-
menting this test fixture, good supply bypassing is essential.
the fix is a simple one and is illustrated in Figure 9. A 3.92 k
resistor in series with the noninverting input of the OP275 cures
the problem.
R
*
FB
–
V
OUT
+
V
IN
R
R
L
100
S
3.92k
2k
909
*
R
IS OPTIONAL
FB
A
OP37
Figure 9. Output Voltage Phase Reversal Fix
Overload or Overdrive Recovery
OP37
OP275
B
OUTPUT
909
Overload or overdrive recovery time of an operational amplifier
is the time required for the output voltage to recover to a rated
output voltage from a saturated condition. This recovery time
is important in applications where the amplifier must recover
quickly after a large abnormal transient event. The circuit shown
in Figure 10 was used to evaluate the OP275’s overload recovery
4.42k
100
490
909
100
Figure 7. NoiseTest Fixture
Input Overcurrent Protection
time. The OP275 takes approximately 1.2 ms to recover to VOUT
+10 V and approximately 1.5 µs to recover to VOUT = –10 V.
=
The maximum input differential voltage that can be applied
to the OP275 is determined by a pair of internal Zener diodes
connected across its inputs. They limit the maximum differential
input voltage to ±7.5V.This is to prevent emitter-base junction
breakdown from occurring in the input stage of the OP275 when
very large differential voltages are applied. However, to preserve
the OP275’s low input noise voltage, internal resistances in series
with the inputs were not used to limit the current in the clamp
diodes. In small signal applications, this is not an issue; however,
in applications where large differential voltages can be inadvert-
ently applied to the device, large transient currents can flow
through these diodes. Although these diodes have been designed
to carry a current of ±5 mA, external resistors as shown in Figure 8
should be used in the event that the OP275’s differential voltage
were to exceed ±7.5V.
R1
1k
R2
10k
2
–
+
1
A1
V
OUT
3
V
IN
R
R
L
S
4V p-p
@100Hz
909k
2.43k
A1 = 1/2 OP275
Figure 10. Overload RecoveryTimeTest Circuit
Measuring SettlingTime
The design of OP275 combines a high slew rate and a wide gain
bandwidth product to produce a fast settling (tS < 1 µs) amplifier
for 8- and 12-bit applications. The test circuit designed to mea-
sure the settling time of the OP275 is shown in Figure 11.This
test method has advantages over false-sum node techniques in
that the actual output of the amplifier is measured, instead of an
error voltage at the sum node. Common-mode settling effects are
exercised in this circuit in addition to the slew rate and band-
width effects measured by the false-sum node method. Of course,
a reasonably flat-top pulse is required as the stimulus.
1.4k
2
–
6
OP275
1.4k
3
+
Figure 8. Input Overcurrent Protection
OutputVoltage Phase Reversal
The output waveform of the OP275 under test is clamped by
Schottky diodes and buffered by the JFET source follower.
The signal is amplified by a factor of 10 by the OP260 and
then Schottky-clamped at the output to prevent overloading the
oscilloscope’s input amplifier.The OP41 is configured as a fast
integrator, which provides overall dc offset nulling.
Since the OP275’s input stage combines bipolar transistors for
low noise and p-channel JFETs for high speed performance, the
output voltage of the OP275 may exhibit phase reversal if either
of its inputs exceeds its negative common-mode input voltage.
This might occur in very severe industrial applications where
a sensor or system fault might apply very large voltages on the
inputs of the OP275. Even though the input voltage range of the
OP275 is ±10.5V, an input voltage of approximately –13.5V will
cause output voltage phase reversal. In inverting amplifier con-
figurations, the OP275’s internal 7.5 V input clamping diodes will
High Speed Operation
As with most high speed amplifiers, care should be taken with
supply decoupling, lead dress, and component placement.
Recommended circuit configurations for inverting and nonin-
verting applications are shown in Figures 12 and 13.
–8–
REV. C
OP275
16V–20V
–
+
+15V
1k
OUTPUT
(TO SCOPE)
0.1F
R
L
D3
D4
+
V+
1k
2N4416
DUT
1/2 OP260AJ
+
–
V–
1F
D1
D2
–
0.1F
R
F
2k
10k
10k
–
+
+
–
IC2
16V–20V
R
G
222
5V
2N2222A
750
1N4148
15k
SCHOTTKY DIODES D1–D4 ARE
HEWLETT-PACKARD HP5082-2835
IC1 IS 1/2 OP260AJ
–15V
IC2 IS PMI OP41EJ
Figure 11. OP275’s SettlingTimeTest Fixture
C
+15V
FB
10F
+
R
FB
0.1F
–
+
2
3
8
–
V
R
S
C
S
C
OUT
IN
1/2
1
V
OUT
OP275
V
IN
+
R
L
4
0.1F
2k
10F
+
Figure 14. Compensating the Feedback Pole
Attention to Source Impedances Minimizes Distortion
–15V
Since the OP275 is a very low distortion amplifier, careful atten-
tion should be given to source impedances seen by both inputs.
As with many FET-type amplifiers, the p-channel JFETs in the
OP275’s input stage exhibit a gate-to-source capacitance that var-
ies with the applied input voltage. In an inverting configuration,
the inverting input is held at a virtual ground and, as such, does
not vary with input voltage.Thus, since the gate-to-source voltage
is constant, there is no distortion due to input capacitance modu-
lation. In noninverting applications, however, the gate-to-source
voltage is not constant.The resulting capacitance modulation
can cause distortion above 1 kHz if the input impedance is
Figure 12. Unity Gain Follower
+15V
10
+
F
0.1F
10pF
V
IN
4.99k
4.99k
2
3
8
–
1/2
OP275
1
greater than 2 k
and unbalanced.
V
OUT
+
2k
R
4
R
F
G
2.49k
10F
0.1F
+
–
OP275
V
R
OUT
S*
–15V
V
+
IN
*
R = R //R IF R //R > 2k
S G F G F
Figure 13. Unity Gain Inverter
FOR MINIMUM DISTORTION
In inverting and noninverting applications, the feedback resis-
tance forms a pole with the source resistance and capacitance
(RS and CS) and the OP275’s input capacitance (CIN), as shown
in Figure 14. With RS and RF in the kilohm range, this pole
can create excess phase shift and even oscillation. A small
capacitor, CFB, in parallel and RFB eliminates this problem.
By setting RS (CS + CIN) = RFBCFB, the effect of the feedback
pole is completely removed.
Figure 15. Balanced Input Impedance to Minimize
Distortion in Noninverting Amplifier Circuits
Figure 15 shows some guidelines for maximizing the distortion
performance of the OP275 in noninverting applications.The best
way to prevent unwanted distortion is to ensure that the parallel
combination of the feedback and gain setting resistors (RF and
RG) is less than 2 k. Keeping the values of these resistors small
has the added benefits of reducing the thermal noise of the circuit
REV. C
–9–
OP275
and dc offset errors. If the parallel combination of RF and RG is
larger than 2 k, then an additional resistor, RS, should be used
in series with the noninverting input.The value of RS is deter-
mined by the parallel combination of RF and RG to maintain the
low distortion performance of the OP275.
The design is a transformerless, balanced transmission system
where output common-mode rejection of noise is of paramount
importance. Like the transformer based design, either output can
be shorted to ground for unbalanced line driver applications
without changing the circuit gain of 1. Other circuit gains can be
set according to the equation in the diagram. This allows the
design to be easily set to noninverting, inverting, or differential
operation.
Driving Capacitive Loads
The OP275 was designed to drive both resistive loads to 600
and capacitive loads of over 1000 pF and maintain stability.While
there is a degradation in bandwidth when driving capacitive loads,
the designer need not worry about device stability.The graph in
Figure 16 shows the 0 dB bandwidth of the OP275 with capaci-
tive loads from 10 pF to 1000 pF.
A 3-Pole, 40 kHz Low-Pass Filter
The closely matched and uniform ac characteristics of the OP275
make it ideal for use in GIC (Generalized Impedance Converter)
and FDNR (Frequency-Dependent Negative Resistor) filter
applications. The circuit in Figure 18 illustrates a linear-phase,
3-pole, 40 kHz low-pass filter using an OP275 as an inductance
simulator (gyrator). The circuit uses one OP275 (A2 and A3) for
the FDNR and one OP275 (A1 and A4) as an input buffer and
bias current source for A3. Amplifier A4 is configured in a gain
of 2 to set the pass band magnitude response to 0 dB. The ben-
efits of this filter topology over classical approaches are that the
op amp used in the FDNR is not in the signal path and that the
filter’s performance is relatively insensitive to component varia-
tions. Also, the configuration is such that large signal levels can
be handled without overloading any of the filter’s internal nodes.
As shown in Figure 19, the OP275’s symmetric slew rate and low
distortion produce a clean, well behaved transient response.
10
9
8
7
6
5
4
3
2
1
0
R1
95.3k
0
200
400
600
800
1000
CLOAD – pF
C1
2200pF
2
3
–
A1
+
1
Figure 16. Bandwidth vs. CLOAD
High Speed, Low Noise Differential Line Driver
V
IN
R2
787
R6
4.12k
5
6
+
The circuit in Figure 17 is a unique line driver widely used in
industrial applications.With ±18 V supplies, the line driver can
7
A4
–
V
OUT
C4
2200pF
7
C2
2200pF
R7
5
6
+
100k
deliver a differential signal of 30 V p-p into a 2.5 k
load.The
A3
–
high slew rate and wide bandwidth of the OP275 combine to
yield a full power bandwidth of 130 kHz while the low noise
front end produces a referred-to-input noise voltage spectral
R3
1.82k
R8
1k
R9
1k
2
3
–
1
A2
C3
2200pF
+
density of 10 nV/ Hz.
R3
R4
1.87k
2k
A1, A4 = 1/2 OP275
A2, A3 = 1/2 OP275
R9
50
2
3
–
A2
+
1
V
R5
1.82k
O1
R11
1k
R1
R7
2k
2k
R4
Figure 18. A 3-Pole, 40 kHz Low-Pass Filter
2k
+
V
– V = V
O1
3
2
O2
IN
V
IN
1
P1
10k
A1
–
R5
2k
100
90
R6
2k
R2
2k
R12
1k
V
R10
OUT
6
5
–
A3
+
50
10V p-p
10kHz
7
V
O2
A1 = 1/2 OP275
R8
2k
A2, A3 = 1/2 OP275
R3
GAIN =
R1
10
0%
SET R2, R4, R5 = R1 AND R6, R7, R8 = R3
Figure 17. High Speed, Low Noise Differential Line Driver
SCALE: VERTICAL–2V/ DIV
HORIZONTAL–10s/ DIV
Figure 19. Low-Pass FilterTransient Response
–10–
REV. C
OP275
OP275 SPICE Model
*
* POLE/ZERO PAIR AT 1.5 MHz/2.7 MHz
*
* Node assignments
R8
R9
C4
G2
*
21 98
21 22
22 98
98 21
1E-3
*
noninverting input
inverting input
positive supply
negative supply
1.25E-3
47.2E-12
18
*
*
*
28
28
28
1E-3
*
**
output
* POLE AT 100 MHz
*
R10 23 98 1
.SUBCKT OP275
*
* INPUT STAGE & POLE AT 100 MHz
*
R3
R4
CIN
CM1
CM2
C2
1
2
99
50
34
C5
G3
*
23 98
98 23
1.59E-9
21
1
5
6
1
1
2
5
97
1
9
5
6
7
8
2
1
3
0
0
51
51
2
98
98
6
4
2
3
2
9
4
4
36
36
1
2
1
2.188
2.188
* POLE AT 100 MHz
*
R11 24 98 1
3.7E-12
7.5E-12
7.5E-12
364E-12
100E-3
1E-9
POLY(1) 26
7
8
1.672
1.672
DZ
DZ
10
C6
G4
*
24 98
98 24
1.59E-9
23
1
I1
* COMMON-MODE GAIN NETWORK WITH ZERO AT
IOS
EOS
Q1
Q2
R5
R6
D1
D2
EN
GN1
GN2
*
EREF
EP
1 kHz
*
R12 25 26 1E6
C7 25 26 1.5915E-12
R13 26 98 1
28
0.5E-3 1
QX
QX
E2
25 98
POLY(2) 1 98
2 98
0
2.50
2.50
*
0
0
0
1
1E-3
1E-3
* POLE AT 100 MHz
*
R14 27 98 1
13
16
C8
G5
*
27 98
98 27
1.59E-9
24
98
97
51
0
0
0
28
99
50
0
0
0
1
1
1
28
1
EM
*
* OUTPUT STAGE
*
* VOLTAGE NOISE SOURCE
*
R15
R16
C9
ISY
R17
R18
L2
G6
G7
G8
G9
V4
V5
F1
F2
D5
D6
D7
D8
28 99
28 50
28 50
99 50
29 99
29 50
29 34
32 50
33 50
29 99
50 29
30 29
29 31
100E3
100E3
1E-6
1.85E-3
100
100
1E-9
27
29
99
27
1.3
3.8
V4
V5
DX
DN1
DN2
VN1
VN2
*
35 10
10 11
DEN
DEN
DC
35
0
0
11
2
2
DC
* CURRENT NOISE SOURCE
*
29
27
27
50
10E-3
10E-3
10E-3
10E-3
DN3
DN4
VN3
VN4
*
12 13
13 14
DIN
DIN
DC
12
0
0
14
2
2
DC
29
0
0
29
1
1
* CURRENT NOISE SOURCE
*
27 30
31 27
99 32
99 33
50 32
50 33
DN5
DN6
VN5
VN6
*
15 16
16 17
DIN
DIN
DC
DX
DX
DX
DY
15
0
0
17
2
2
DC
D9
D10
*
DY
* GAIN STAGE & DOMINANT POLE AT 32 Hz
*
* MODELS USED
*
R7
C3
G1
V2
V3
D3
D4
18 98
18 98
98 18
97 19
20 51
18 19
20 18
1.09E6
4.55E-9
5
1.35
1.35
DX
.MODEL QX
.MODEL DX
.MODEL DY
.MODEL DZ
.MODEL DEN
AF=1)
PNP(BF=5E5)
D(IS=1E-12)
D(IS=1E-15 BV=50)
D(IS=1E-15 BV=7.0)
6
4.57E-1
D(IS=1E-12 RS=4.35K KF=1.95E-15
DX
.MODEL DIN
.ENDS
D(IS=1E-12 RS=268 KF=1.08E-15 AF=1)
REV. C
–11–
OP275
OUTLINE DIMENSIONS
8-Lead Standard Small Outline Package [SOIC]
(S Suffix)
(R-8)
Dimensions shown in millimeters and (inches)
5.00 (0.1968)
4.80 (0.1890)
8
1
5
4
6.20 (0.2440)
5.80 (0.2284)
4.00 (0.1574)
3.80 (0.1497)
0.50 (0.0196)
0.25 (0.0099)
1.27 (0.0500)
BSC
45
1.75 (0.0688)
1.35 (0.0532)
0.25 (0.0098)
0.10 (0.0040)
8
0.51 (0.0201)
0.31 (0.0122)
0 1.27 (0.0500)
COPLANARITY
0.10
0.25 (0.0098)
0.17 (0.0067)
SEATING
PLANE
0.40 (0.0157)
COMPLIANT TO JEDEC STANDARDS MS-012AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
8-Lead Plastic Dual-in-Line Package [PDIP]
(P Suffix)
(N-8)
Dimensions shown in inches and (millimeters)
0.375 (9.53)
0.365 (9.27)
0.355 (9.02)
8
1
5
0.295 (7.49)
0.285 (7.24)
0.275 (6.98)
4
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
0.100 (2.54)
BSC
0.150 (3.81)
0.135 (3.43)
0.120 (3.05)
0.015
(0.38)
MIN
0.180
(4.57)
MAX
0.015 (0.38)
0.010 (0.25)
0.008 (0.20)
0.150 (3.81)
0.130 (3.30)
0.110 (2.79)
0.022 (0.56)
0.018 (0.46)
0.014 (0.36)
SEATING
PLANE
0.060 (1.52)
0.050 (1.27)
0.045 (1.14)
COMPLIANT TO JEDEC STANDARDS MO-095AA
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
Revision History
Location
Page
2/04—Data Sheet changed from REV. B to REV. C.
Changes to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1/03—Data Sheet changed from REV. A to REV. B.
DeletedWAFERTEST LIMITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Edits to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Edits to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Deleted DICE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
–12–
REV. C
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