SSM2519ACBZ-RL [ADI]
Digital Input 2 W Class-D Audio Power Amplifier;
| 型号： | SSM2519ACBZ-RL |
| 厂家： | 
ADI |
| 描述： | Digital Input 2 W Class-D Audio Power Amplifier |
| 文件： | 总28页 (文件大小：1030K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Digital Input 2 W Class-D
Audio Power Amplifier
SSM2519
Data Sheet
FEATURES
APPLICATIONS
Filterless digital input Class-D amplifier
Standalone operation or I2C control
Serial digital audio interface supports common formats: I2S,
left justified, right justified, TDM1-16, and PCM
2.31 W into 4 Ω and 1.35 W into 8 Ω at 5 V supply with
1% THD + N
Mobile phones
Portable media players
Laptop PCs
Wireless speakers
Portable gaming
Navigation systems
Available in 12-ball 1.4 mm × 1.7 mm × 0.4 mm pitch WLCSP
Efficiency 90% at full scale into 8 Ω
FUNCTIONAL BLOCK DIAGRAM
9 mW loaded idle power at 1.8 V/3.6 V
SNR = 98 dB, A-weighted
VDD
GND
PVDD
PSRR = 80 dB at 217 Hz, dither input
Supports wide range of sample rates: 8.0 kHz to 48.0 kHz
Autosample rate and MCLK rate detection
No BCLK required for operation
2.5 V to 5.5 V PVDD speaker operating supply voltage
1.5 V to 3.6 V VDD operating voltage
POWER-ON
RESET
LRCLK
BCLK
OUT+
OUT–
2
I S
DAC
Pop and click suppression
SDATA
Short-circuit and thermal protection with autorecovery
Smart power-down when no input signal detected
Power-on reset
CLOCKING POWER
CONTROL
2
I C
SD
SSM2519
Low EMI emissions
MCLK
GAIN/SDA
LR_FORMAT/SCL
Figure 1.
GENERAL DESCRIPTION
The SSM2519 is a digital input, Class-D power amplifier that com-
bines a digital-to-analog converter (DAC) and a sigma-delta
(Σ-Δ) Class-D modulator. This unique architecture enables
extremely low, real-world power consumption from digital
audio sources with excellent audio performance. The SSM2519
is ideal for power sensitive applications, such as mobile phones
and portable media players, where system noise can corrupt
small analog signals such as those sent to an analog input audio
amplifier.
Input is provided via a serial audio interface, programmable to
accept all common audio formats including I2S, left justified (LJ),
right justified (RJ), TDM, and PCM. The SSM2519 is designed to
operate with or without a control interface such as I2C, which is
typically required for this type of device. Several control pins
offer selection of operation when I2C control is not used. The
SSM2519 can accept a variety of input MCLK frequencies and
can use BCLK as the clock source in some configurations. Both
the input sample rate and MCLK rates are automatically
detected.
Using the SSM2519, audio data can be transmitted to the amplifier
over a standard digital audio serial interface, thereby significantly
reducing the effect of noise sources such as GSM interference or
other digital signals on the transmitted audio. The closed-loop
digital input design retains the benefits of a completely digital
amplifier, yet enables very good PSRR and audio performance.
The three-level, Σ-Δ Class-D modulator is designed to provide
the least amount of EMI interference, the lowest quiescent
power dissipation, and the highest audio efficiency without
sacrificing audio quality.
The architecture of the SSM2519 provides a solution that offers
lower power and higher performance than existing DAC plus
Class-D solutions. Its digital interface also offers a better system
solution for other products whose sole audio source is digital,
such as wireless speakers, laptop PCs, portable digital televisions,
and navigation systems.
The SSM2519 is specified over the industrial temperature range
of −40C to +85C. It has built-in thermal shutdown and output
short-circuit protection. It is available in a 12-ball, 1.4 mm ×
1.7 mm wafer level chip scale package (WLCSP).
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2012 Analog Devices, Inc. All rights reserved.
SSM2519
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Volume Control.......................................................................... 14
Analog Gain ................................................................................ 14
Fault Detection and Recovery .................................................. 14
Digital Audio Formats ................................................................... 15
Stereo Mode ................................................................................ 15
TDM, 50% Duty Cycle Mode ................................................... 15
TDM, Pulse Mode...................................................................... 15
PCM, Multichannel Mode ........................................................ 16
PCM, Mono Mode ..................................................................... 16
I2C Configuration Interface .......................................................... 17
Overview ..................................................................................... 17
Register Summary .......................................................................... 19
Register Details ............................................................................... 20
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Performance Specifications......................................................... 3
Power Supply Requirements ....................................................... 4
Digital Input/Output.................................................................... 4
Digital Timing............................................................................... 4
Absolute Maximum Ratings............................................................ 6
Thermal Resistance ...................................................................... 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Descriptions............................. 7
Typical Performance Characteristics ............................................. 8
Theory of Operation ...................................................................... 12
Overview...................................................................................... 12
Standalone and I2C Operational Mode ................................... 12
Master and Bit Clock.................................................................. 12
Digital Input Serial Audio Interface......................................... 13
Channel Mapping....................................................................... 13
Power Supplies ............................................................................ 13
Power Control............................................................................. 14
Power-On Reset/Voltage Supervisor ....................................... 14
Low Power Modes ...................................................................... 14
Software Reset and Master Software Power-Down Control
Register ........................................................................................ 20
Edge Speed, Power, and Clocking Control Register.............. 21
Serial Audio Interface and Sample Rate Control Register.... 22
Serial Audio Interface Control Register.................................. 23
Channel Mapping Control Register......................................... 24
Volume Control Register........................................................... 25
Gain and Mute Control Register.............................................. 26
Fault Control Register................................................................ 27
Outline Dimensions....................................................................... 28
Ordering Guide .......................................................................... 28
REVISION HISTORY
7/12—Revision 0: Initial Version
Rev. 0 | Page 2 of 28
Data Sheet
SSM2519
SPECIFICATIONS
All conditions at PVDD = 5.0 V; VDD = 1.8 V; fS = 48 kHz; MCLK = 128 × fS; TA = 25oC; RL = 8 Ω + 15 μH; default I2C settings; volume
control 0 dB setting, unless otherwise noted.
PERFORMANCE SPECIFICATIONS
Table 1.
Parameter
Symbol
Test Conditions/Comments
Min
Typ Max Unit
DEVICE CHARACTERISTICS
Output Power
POUT
RL = 4 Ω, THD + N = 1%, f = 1 kHz, BW = 20 kHz, PVDD = 5.0V
RL = 4 Ω, THD + N = 10%, f = 1 kHz, BW = 20 kHz, PVDD = 5.0V
RL = 8 Ω, THD + N = 1%, f = 1 kHz, BW = 20 kHz, PVDD = 5.0V
RL = 8 Ω, THD + N = 10%, f = 1 kHz, BW = 20 kHz, PVDD = 5.0V
RL = 4 Ω, THD + N = 1%, f = 1 kHz, BW = 20 kHz, PVDD = 3.6V
RL = 4 Ω, THD + N = 10%, f = 1 kHz, BW = 20 kHz, PVDD = 3.6 V
RL = 8 Ω, THD + N = 1%, f = 1 kHz, BW = 20 kHz, PVDD = 3.6V
RL = 8 Ω, THD + N = 10%, f = 1 kHz, BW = 20 kHz, PVDD = 3.6V
RL = 4 Ω, THD + N = 1%, f = 1 kHz, BW = 20 kHz, PVDD = 2.5V
RL = 4 Ω, THD + N = 10%, f = 1 kHz, BW = 20 kHz, PVDD = 2.5 V
RL = 8 Ω, THD + N = 1%, f = 1 kHz, BW = 20 kHz, PVDD = 2.5V
RL = 8 Ω, THD + N = 10%, f = 1 kHz, BW = 20 kHz, PVDD = 2.5V
POUT = 2 W, 4 Ω, PVDD = 5.0 V
2.31
2.75
1.35
1.68
1.13
1.4
0.69
0.85
0.48
0.6
0.31
0.39
84
90.2
0.03
W
W
W
W
W
W
W
W
W
W
W
W
%
%
%
Efficiency
η
POUT = 1.4 W, 8 Ω, PVDD = 5.0 V, normal operation
POUT = 1 W into 8 Ω, f = 1 kHz, PVDD = 5.0V
Total Harmonic Distortion
Plus Noise
THD + N
POUT = 0.5 W into 8 Ω, f = 1 kHz, PVDD = 3.6V
0.03
305
%
kHz
Average Switching
Frequency
fSW
Differential Output Offset
Power Supply Rejection
Ratio
VOOS
PSRRDC
1
82
mV
dB
PVDD = 2.5 V to 5.0 V
70
PSRRGSM
IPVDD
VRIPPLE = 100 mV rms at 217 Hz, dither input
Dither input, 8 Ω + 15 μH load, PVDD = 5.0 V
Dither input, 8 Ω + 15 μH load, PVDD = 3.6 V
Dither input, 8 Ω + 15 μH load, PVDD = 2.5 V
Dither input, 8 Ω + 15 μH load, PVDD = 3.6 V (DAC_LPM = 0 and
AMP_LPM = 0)
80
dB
Supply Current, PVDD
2.64
2.24
2.02
2.5
mA
mA
mA
mA
Hardware shutdown
Dither input, VDD = 3.3 V
Dither input, VDD = 1.8 V
Software shutdown, clock present, VDD = 1.8 V
Software shutdown, clock removed, VDD = 1.8 V
Hardware shutdown
PVDD = 5.0 V, f = 20 Hz to 20 kHz, dither input, A-weighted
PVDD = 3.6 V, f = 20 Hz to 20 kHz, dither input, A-weighted, gain
= 3.6 V
200
1.14
0.6
86
5
200
37
nA
mA
mA
μA
μA
nA
μV
μV
Supply Current, VDD
Output Noise Voltage
IVDD
en
41
Signal-to-Noise Ratio
Closed-Loop Gain
SNR
Gain
A-weighted reference to 0 dBFS, PVDD = 5.0 V
0 dBFS input, BTL output, f = 1 kHz
Gain = 5.0 V
Gain = 4.2 V
Gain = 3.6 V
98
dB
4.94
4.21
3.69
1.98
V pk
V pk
V pk
V pk
Gain = 2 V
Rev. 0 | Page 3 of 28
SSM2519
Data Sheet
POWER SUPPLY REQUIREMENTS
Table 2.
Parameter
Min
2.5
Typ
3.6
Max
5.5
Unit
V
PVDD
VDD
1.5
1.8
3.6
V
DIGITAL INPUT/OUTPUT
Table 3.
Parameter
INPUT VOLTAGE
High (VIH)
Min
Typ
Max
Unit
Test Conditions/Comments
0.7 × VDD
1.35
3.6
5.5
V
V
V
V
MCLK, BCLK, LRCLK, SDATA
SD, SDA, SCL
Low (VIL)
−0.3
−0.3
+0.3 × VDD
+0.35
MCLK, BCLK, LRCLK, SDATA
SD, SDA, SCL
INPUT LEAKAGE CURRENT
High (IIH)
Low (IIL)
1
1
μA
μA
Excluding MCLK
Excluding MCLK and bidirectional pin
MCLK INPUT LEAKAGE CURRENT
High (IIH)
Low (IIL)
3
3
5
μA
μA
pF
INPUT CAPACITANCE
DIGITAL TIMING
All timing specifications are given for the default setting (I2S mode) of the serial input port.
Table 4.
Limit
Parameter
Min
Max
Unit
Description
MASTER CLOCK
tMP
tMP
74
148
136
271
ns
ns
MCLK period, 256 × fS mode (MCS = b0010)
MCLK period, 128 × fS mode (MCS = b0001)
SERIAL PORT
tBIL
tBIH
tLIS
tLIH
tSIS
tSIH
I2C PORT
40
40
10
10
10
10
ns
ns
ns
ns
ns
ns
BCLK low pulse width
BCLK high pulse width
Setup time from LRCLK or SDATA edge to BCLK rising edge
Hold time from BCLK rising edge to LRCLK or SDATA edge
SDATA setup time to BCLK rising
SDATA hold time from BCLK rising
fSCL
400
kHz
μs
μs
μs
μs
ns
ns
ns
ns
ns
μs
SCL frequency
SCL high
SCL low
Setup time; relevant for repeated start condition
Hold time; after this period, the first clock is generated
Data setup time
SCL rise time
SCL fall time
tSCLH
tSCLL
tSCS
tSCH
tDS
tSCR
tSCF
tSDR
tSDF
0.6
1.3
0.6
0.6
100
300
300
300
300
SDA rise time
SDA fall time
Bus-free time (time between stop and start)
tBFT
0.6
Rev. 0 | Page 4 of 28
Data Sheet
SSM2519
Digital Timing Diagrams
tBIH
tBP
BCLK
tBIL
tLIS
tLIH
LRCLK
tSIS
SDATA
LEFT-JUSTIFIED
MODE
MSB
MSB – 1
tSIH
tSIS
SDATA
2
I C-JUSTIFIED
MSB
MODE
tSIH
tSIS
tSIS
SDATA
RIGHT-JUSTIFIED
MODE
MSB
LSB
tSIH
tSIH
Figure 2. Serial Input Port Timing
tDS
tSCH
tSCH
SDA
SCL
tSCLH
tSCS
tSCR
tSCLL
tSCF
tBFT
START
CONDITION
STOP
CONDITION
Figure 3. I2C Port Timing
Rev. 0 | Page 5 of 28
SSM2519
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Absolute maximum ratings apply at 25°C, unless otherwise noted.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 5.
Parameter
Rating
PVDD Supply Voltage
VDD Supply Voltage
Input Voltage (MCLK, BCLK, SD,
LRCLK, LR_FORMAT, GAIN, SDATA)
ESD Susceptibility
−0.3 V to 6 V
−0.3 V to 3.6 V
−0.3 V to 3.6 V
Table 6. Thermal Resistance
Package Type
θJA
Unit
12-ball, 1.4 mm × 1.7 mm WLCSP
56.1
°C/W
4 kV
Storage Temperature Range
Operating Temperature Range
Junction Temperature Range
Lead Temperature (Soldering, 60 sec)
−65°C to +150°C
−40°C to +85°C
−65°C to +165°C
300°C
ESD CAUTION
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to
7absolute maximum rating conditions for extended periods
may affect device reliability.
Rev. 0 | Page 6 of 28
Data Sheet
SSM2519
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
BALL A1
INDICATOR
1
2
3
OUT+
MCLK
OUT–
A
B
C
D
PVDD
GND
BCLK
LRCLK
SDATA
VDD
SD
LR_FORMAT/
SCL
GAIN/
SDA
SSM2519
TOP VIEW
(BALL SIDE DOWN)
Not to Scale
Figure 4. Pin Configuration—Top View
Table 7. Pin Function Descriptions
Ball Number
Pin Name
Function1
Description
A1
A2
A3
B1
B2
B3
C1
C2
C3
D1
D2
D3
OUT+
OUT−
MCLK
PVDD
VDD
BCLK
GND
SD
O
O
I
P
P
I
Amplifier Output Positive
Amplifier Output Negative
Serial Audio Interface Master Clock
2.5 V to 5.5 V Amplifier Power
1.5 V to 3.6 V Digital and Analog Power
I2S Bit Clock/Generated BCLK Rate Select
Ground
Power-Down Control—Active Low
I2S Left/Right Frame Clock
Left/Right Channel Selection and Serial Format Selection/I2C Clock
Digital and Analog Gain Selection/I2C Serial Data
I2S Serial Data
P
I
LRCLK
I
I
LR_FORMAT/SCL
GAIN/SDA
SDATA
I/O
I
1 I = input, O = output, P = power.
Rev. 0 | Page 7 of 28
SSM2519
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
100
10
100
2.5V
3.6V
5V
2.5V
3.6V
5V
10
1
1
0.1
0.1
0.01
0.001
0.01
0.01
0.1
(W)
1
10
0.001
0.01
0.1
(W)
1
10
P
P
OUT
OUT
Figure 5. THD + N vs. Output Power into 8 Ω, 5.0 V Gain Setting
Figure 8. THD + N vs. Output Power into 8 Ω, 3.6 V Gain Setting
100
2.5V
3.6V
5V
100
2.5V
3.6V
5V
10
10
1
1
0.1
0.01
0.1
0.01
0.001
0.01
0.1
(W)
1
10
0.001
0.01
0.1
P (W)
OUT
1
10
P
OUT
Figure 6. THD + N vs. Output Power into 4 Ω, 5.0 V Gain Setting
Figure 9. THD + N vs. Output Power into 4 Ω, 3.6 V Gain Setting
1
100
250mW
500W
1W
500mW
1W
10
0.1
1
0.1
0.01
0.01
0.001
0.001
10
100
1k
10k
100k
10
100
1k
10k
100k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 7. THD + N vs. Frequency into 8 Ω, PVDD = 5.0 V
Figure 10. THD + N vs. Frequency into 4 Ω, PVDD = 5.0 V
Rev. 0 | Page 8 of 28
Data Sheet
SSM2519
1
100
10
500mW
250mW
125mW
250mW
125mW
0.1
1
0.1
0.01
0.01
0.001
10
0.001
100
1k
10k
100k
100k
100k
10
100
1k
10k
100k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 11. THD + N vs. Frequency into 8 Ω, PVDD = 3.6 V
Figure 14. THD + N vs. Frequency into 4 Ω, PVDD = 2.5 V
100
10
10
500mW
250mW
NO LOAD
8Ω
4Ω
9
8
7
6
5
4
3
1
0.1
0.01
0.001
10
100
1k
10k
2.5
3.0
3.5
4.0
4.5
5.0
PV (V)
FREQUENCY (Hz)
DD
Figure 12. THD + N vs. Frequency into 4 Ω, PVDD = 3.6 V
Figure 15. Quiescent Current vs. Supply Voltage PVDD
100
10
1.8
1.5
1.2
0.9
0.6
0.3
0
62.5mW
125mW
250mW
8kHz
24kHz
48kHz
1
0.1
0.01
0.001
10
100
1k
10k
1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
FREQUENCY (Hz)
V
(V)
DD
Figure 13. THD + N vs. Frequency into 8 Ω, PVDD = 2.5 V
Figure 16. Quiescent Current vs. Supply Voltage VDD
Rev. 0 | Page 9 of 28
SSM2519
Data Sheet
1.8
1.5
1.2
0.9
0.6
0.3
0
0.8
0.7
2.5V
3.6V
5V
0.6
0.5
0.4
0.3
0.2
0.1
0
1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
0
0.5
1.0
1.5
P (W)
OUT
2.0
2.5
3.0
V
(V)
DD
Figure 17. Quiescent Current vs. Supply Voltage VDD
Figure 20. Power Supply Current vs. POUT, 4 Ω
2.0
1.5
100
80
60
40
20
0
2.5V
3.6V
5V
THD + N = 10%
THD + N = 1%
1.0
0.5
0
2.5
3.0
3.5
4.0
4.5
5.0
0
0.4
0.8
1.2
P
1.6
(W)
2.0
2.4
2.8
PV (V)
DD
OUT
Figure 18. Maximum Output Power vs. PVDD
(fIN = 1 kHz, RL = 8 Ω)
Figure 21. Class-D Efficiency vs. POUT, 4 Ω
3.0
2.5
2.0
1.5
1.0
0.5
0
0.8
0.7
2.5V
3.6V
5V
0.6
0.5
0.4
0.3
0.2
0.1
0
THD + N = 10%
THD + N = 1%
2.5
3.0
3.5
4.0
4.5
5.0
0
0.5
1.0
1.5
(W)
2.0
2.5
3.0
PV (V)
P
DD
OUT
Figure 19. Maximum Output Power vs. PVDD
(fIN = 1 kHz, RL = 4 Ω)
Figure 22. Power Supply Current vs. POUT, 8 Ω
Rev. 0 | Page 10 of 28
Data Sheet
SSM2519
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
100
PVDD = 5V
2.5V
3.6V
5V
PVDD = 3.6V
PVDD = 2.5V
80
60
40
20
0
0
10
100
1k
10k
100k
0.3
0.6
0.9
1.2
1.5
P
(W)
FREQUENCY (Hz)
OUT
Figure 25. PSRR vs. Frequency
Figure 23. Class-D Efficiency vs. POUT, 8 Ω
0
–20
–40
–60
–80
–100
–120
–140
–160
–180
2.5V
3.6V
5V
10
100
1k
10k
100k
FREQUENCY (Hz)
Figure 24. Output Spectrum, 100 mW, 8 Ω
Rev. 0 | Page 11 of 28
SSM2519
Data Sheet
THEORY OF OPERATION
OVERVIEW
MASTER AND BIT CLOCK
The SSM2519 is a fully integrated digital switching audio
amplifier. The SSM2519 receives digital audio inputs and
produces the PDM differential switching outputs using an
internal power stage. The part has built-in protections against
overtemperature as well as overcurrent. The SSM2519 also has
built-in soft turn-on and soft turn-off for pop and click
suppression.
The SSM2519 requires an external clock present at the MCLK
input pin to operate. This clock must be fully synchronous with
the incoming digital audio on the serial interface. Internal to the
IC, a clock frequency of 2.048 MHz to 24.576 MHz is required.
This internal clock is derived from the external MCLK by
dividing, passing through, or doubling in frequency the external
MCLK signal.
STANDALONE AND I2C OPERATIONAL MODE
The SSM2519 supports both standalone and I2C control modes.
Different rates for MCLK are supported at different sample
rates. Refer to Table 9 for all available options. The MCLK rate
as well as sample rate can be automatically detected by setting
the AMCS and ASR bits in Register 0x01, or they can be manu-
ally set (MCS bits in Register 0x00, and FS bits in Register 0x02)
if AMCS or ASR is cleared.
SD
The setting on the
pin determines which mode is used.
Table 8.
Pin Settings
SD
SD Pin
Operation
When in standalone mode or in I2C mode and auto clock rate
detection is enabled (Register 0x01, Bit 1, AMCS = 1), the
internal clock generation circuitry is automatically configured.
When autosample rate detection is disabled (AMCS = 0), the
MCS bits in Register 0x00 must be set with the correct value to
generate the internal clock.
Tie to VDD Through 20 kΩ
Connect to VDD Without 20 kΩ
Connect to GND (Shorted or with 20 kΩ)
I2C
Standalone mode
Shutdown mode
When the SSM2519 has entered its power-down state, it is
possible to gate this clock to conserve additional system power.
However, a master clock must be present for the audio amplifier
to operate.
If the serial interface bit clock (BCLK) is in the range of acceptable
internal master clock frequencies (between 2.048 MHz and
6.144 MHz), it can serve as both master clock and the bit clock.
Setting NO_BCLK (Bit 5 of Register 0x00) routes the signal on
the MCLK pin to serve as the internal bit clock as well. In this
case, tie the BCLK pin to ground.
Table 9. Supported MCLK Rate for Different Sample Frequencies
Sample Rates
Supported MCLK Rates
Supported MCLK Frequencies
2.048 MHz to 24.576 MHz
2.048 MHz to 24.576 MHz
2.048 MHz to 24.576 MHz
3.2 MHz to 19.2 MHz
8 kHz to 12 kHz
16 kHz to 24 kHz
32 kHz to 48 kHz
8 kHz to 12 kHz
16 kHz to 24 kHz
32 kHz to 48 kHz
256 × fS/512 × fS/1024 × fS/1536 × fS/2048 × fS
128 × fS/256 × fS/512 × fS/768 × fS/1024 × fS
64 × fS/128 × fS/256 × fS/384 × fS/512 × fS
400 × fS/800 × fS/1600 × fS
200 × fS/400 × fS/800 × fS
100 × fS/200 × fS/400 × fS
3.2 MHz to 19.2 MHz
3.2 MHz to 19.2 MHz
Rev. 0 | Page 12 of 28
Data Sheet
SSM2519
Table 10. Master Clock Select (MCS) Bit Settings: MCLK, Ratio, and Frequency
Input
Sample
Rate
Ratio/ Setting 0,
Setting 1,
b0001
Setting 2,
b0010
Setting 3,
b0011
Setting 4,
b0100
Setting 5,
b0101
Setting 6, Setting 7, Setting 8,
MCLK b0000
b0110
b0111
b1000
1
8 kHz
Ratio
256 × fS
512 × fS
1024 × fS
8.192 MHz
1024 × fS
1536 × fS
2048 × fS
3072 × fS
400 × fS
3.20 MHz
400 × fS
800 × fS
6.40 MHz
800 × fS
8.82 MHz
800 × fS
9.60 MHz
400 × fS
6.40 MHz
400 × fS
8.82 MHz
400 × fS
9.60 MHz
200 × fS
6.40 MHz
200 × fS
8.82 MHz
200 × fS
9.60 MHz
1600 × fS
12.80 MHz
1600 × fS
17.64 MHz
1600 × fS
19.20 MHz
800 × fS
MCLK
2.048 MHz
4.096 MHz
512 × fS
12.288 MHz
1536 × fS
16.384 MHz
2048 × fS
24.576 MHz
3072 × fS
1
11.025 kHz Ratio
MCLK
256 × fS
2.822 MHz
5.6448 MHz 11.2896 MHz 16.9344 MHz 22.5792 MHz 33.8688 MHz 4.41 MHz
1
12 kHz
Ratio
MCLK
Ratio
MCLK
Ratio
MCLK
Ratio
MCLK
Ratio
MCLK
Ratio
MCLK
Ratio
MCLK
512 × fS
1024 × fS
12.288 MHz
384 × fS
1536 × fS
18.432 MHz
768 × fS
2048 × fS
3072 × fS
400 × fS
4.80 MHz
200 × fS
3.20 MHz
200 × fS
256 × fS
3.072 MHz
6.144 MHz
256 × fS
24.576 MHz
1024 × fS
38.864 MHz
1536 × fS
1
16 kHz
128 × fS
2.048 MHz
4.096 MHz
256 × fS
8.192 MHz
512 × fS
12.288 MHz
768 × fS
16.384 MHz
1024 × fS
24.576 MHz
1536 × fS
12.80 MHz
800 × fS
1
22.05 kHz
24 kHz
128 × fS
2.822 MHz
5.6448 MHz 11.2896 MHz 16.9344 MHz 22.5792 MHz 33.8688 MHz 4.41 MHz
17.64 MHz
800 × fS
1
256 × fS
512 × fS
768 × fS
1024 × fS
24.576 MHz
512 × fS
1536 × fS
38.864 MHz
768 × fS
200 × fS
4.80 MHz
100 × fS
3.20 MHz
100 × fS
128 × fS
3.072 MHz
6.144 MHz
128 × fS
12.288 MHz
256 × fS
18.432 MHz
384 × fS
19.20 MHz
400 × fS
1
32 kHz
64 × fS
2.048 MHz
4.096 MHz
128 × fS
8.192 MHz
256 × fS
12.288 MHz
384 × fS
16.384 MHz
512 × fS
24.576 MHz
768 × fS
12.80 MHz
400 × fS
1
44.1 kHz
48 kHz
64 × fS
2.822 MHz
5.6448 MHz 11.2896 MHz 16.9344 MHz 22.5792 MHz 33.8688 MHz 4.41 MHz
17.64 MHz
400 × fS
1
128 × fS
256 × fS
384 × fS
512 × fS
768 × fS
100 × fS
64 × fS
3.072 MHz
6.144 MHz
12.288 MHz
18.432 MHz
24.576 MHz
38.864 MHz
4.80 MHz
19.20 MHz
1 When using MCS = 0/64 fS mode, the chip automatically operates in low power mode.
DIGITAL INPUT SERIAL AUDIO INTERFACE
CHANNEL MAPPING
It is capable of receiving stereo I2S, left justified, or right
justified data. Mono, stereo, and multichannel PCM/TDM
interface formats are available. The data and interface formats
are selected by adjusting the SDATA_FMT and SAI bits in
Register 0x02. Note that, when operating in right justified
mode, the proper data width must be chosen. The BCLK signal
does not have to be provided to the SSM2519. It can internally
generate the appropriate BCLK signal. To operate without a
BCLK, the BCLK pin should be tied to VDD or GND to select
the appropriate BCLK rate for the SDATA input.
Stereo audio formats and TDM formats with two, four, eight, or
16 channels are available. In these modes, the amplifier audio
can be chosen from any of the available TDM slots using the
CH_SEL bits in Register 0x04. For most digital interface
formats, many of these options are not present. For example, in
stereo modes, only Channel 0 and Channel 1 are valid, and in
four-slot TDM mode, only Channel 0, Channel 1, Channel 2,
and Channel 3 are valid.
POWER SUPPLIES
The SSM2519 has two internal power supplies that must be
provided. PVDD supplies power to the full-bridge power stage
of MOSFETs and its associated drive, control, and protection
circuitry. PVDD can operate from 2.5 V to 5.5 V and must be
present to obtain audio output. Lowering the PVDD supply
results in lower output power and correspondingly lower power
consumption. This does not affect audio performance.
Table 11. BCLK Pin Connection Options
BCLK Pin
Generation
BCLK Rate
Connected to External External
Clock Source
Any
Tied to VDD
Tied to GND
Internal
Internal
16 bit clocks/channel
32 bit clocks/channel
When the SSM2519 is set up in standalone mode, a subset of serial
interface formats are available. Selection of these serial formats
and input channel are determined by the LR_FORMAT pin.
VDD provides power to the digital logic, analog components,
and I/O circuitry. VDD can operate from 1.5 V to 3.6 V and
must be provided to obtain audio output. Lowering the supply
voltage results in lower power consumption, but does not result
in lower audio performance.
Table 12. LR_FORMAT Pin Configuration Controls
LR_FORMAT Pin
Configuration
Serial Format/Channel Select
Tie to VDD
I2S/left channel
Tie to VDD Through 150 kΩ Special gain case1 (I2S/left channel)
Tie to VDD Through 47 kΩ
Tie to VDD Through 15 kΩ
Tie to GND
PCM/left channel
LJ/left channel
I2S/right channel
1 See Table 14.
Rev. 0 | Page 13 of 28
SSM2519
Data Sheet
POWER CONTROL
VOLUME CONTROL
The IC starts up in software power-down mode, where all blocks
except for the I2C interface are disabled. To fully power up the
amplifier, clear SPWDN (Bit 0 of Register 0x00). In addition to
the software power-down, the software master mute control
(M_MUTE) is enabled at the initial state of the amplifier;
therefore, no audio is output until Bit 0 of Register 0x06 is
cleared.
The SSM2519 has a digital volume control. There are 255 levels
available, providing a range from +24 dB to −71.25 dB in
0.375 dB increments. This is a soft volume control, meaning
that the gain is adjusted continuously from one value to
another. This continuously adjusted gain prevents the audible
pop that occurs with an instantaneous gain adjustment.
ANALOG GAIN
The SSM2519 contains a smart power-down feature that, when
enabled, analyzes the incoming digital audio and, if the audio is
zero for 512 consecutive samples, regardless of sample rate,
places the IC in the smart power-down state. In this state, all
circuitry except the I2S ports are placed in a low power state.
After this state is entered, the I2S input and master clock
(MCLK) can be removed to place the part in its lowest power
state. When a single nonzero input is received, the SSM2519
leaves this state and resumes normal operation.
The SSM2519 has selectable digital and analog gain. Selection
of these gains occurs via the GAIN pin. The analog gain settings
are optimized for operation at 2.5 V, 3.6 V, 4.2 V, or 5 V PVDD.
Table 13. GAIN Pin Configuration Control
GAIN Pin
Configuration
Analog Gain/Digital Gain
Tie to VDD
5 V optimized analog/0 dB digital gain
5 V optimized analog/6 dB digital gain
Tie to VDD
Through 150 kΩ
The SSM2519 can also be powered down to its lowest power
Tie to VDD
Through 47 kΩ
Tie to VDD
Through 15 kΩ
4.2 V optimized analog/0 dB digital gain
3.6 V optimized analog/−3 dB digital gain
3.6 V optimized analog/0 dB digital gain
SD
state by pulling the
pin low.
POWER-ON RESET/VOLTAGE SUPERVISOR
The SSM2519 includes an internal power-on reset and voltage
supervisor circuit. This circuit provides an internal reset to all
circuitry during initial power-up. It also monitors the power
supplies to the IC, mutes the output, and issues a reset when the
voltages fall below the minimum operating range. This is done
to ensure that no damage occurs due to low voltage operation
and that no pops can occur under nearly any power removal
condition.
Tie to GND
Table 14. Special Gain Case (LR_FORMAT Tied to VDD
Through 150 kΩ) GAIN Pin Configuration Control
GAIN Pin
Configuration
Analog Gain/Digital Gain
Tie to VDD
2.5 V optimized analog/−6.75 dB digital
gain
A soft reset of the chip can be issued through I2C by setting
Bit 7 of Register 0x00 (S_RST).
Tie to GND
3.6 V optimized analog/0 dB digital gain
FAULT DETECTION AND RECOVERY
LOW POWER MODES
Two fault conditions are detected by the SSM2519 fault
detection system: overcurrent and overtemperature. When
either of these is detected, the amplifier shuts down and a read-
only I2C bit is set to indicate the cause of the shutdown. The OC
and OT fault indicators are Bit 6 and Bit 5, respectively, of
Register 0x07. An autorecovery feature can be enabled for
temperature faults, current faults, or both, depending on the
state of ARCV (Bits[1:0] of Register 0x07).
Two low power modes are available. If DAC_LPM (Bit 5 of
Register 0x01) is set, the digital-to-analog converter (DAC)
runs at half speed, reducing the quiescent current. This half
speed mode is also active when the MCS setting (Bits[4:1] of
Register 0x00) is set to its lowest value (MCS = 0000) because
the slowest acceptable MCLK rates can only support half speed
DAC operation.
If AMP_LPM (Bit 6 of Register 0x01) is set, the Σ-Δ modulator
runs in a special mode that offers lower quiescent current when
the output power is small, at the expense of slightly degraded
audio performance.
Rev. 0 | Page 14 of 28
Data Sheet
SSM2519
DIGITAL AUDIO FORMATS
STEREO MODE
0x02[4:2], SAI = 0 (stereo: I2S, LJ, RJ)
0x02[6:5], SDATA_FMT = 0 (I2S), 1 (LJ), 2 (RJ 24-bit), 3 (RJ 16-bit)
BCLK
ANY NUMBER BCLKs
LRCLK
2
LEFT CHANNEL
8 TO 32 BCLKs
RIGHT CHANNEL
8 TO 32 BCLKs
SDATA I S
RIGHT CHANNEL
8 TO 32 BCLKs
LEFT CHANNEL
8 TO 32 BCLKs
SDATA LJ
SDATA RJ
RIGHT CHANNEL
8 TO 32 BCLKs
LEFT CHANNEL
8 TO 32 BCLKs
Figure 26. Stereo Modes: I2S, Left Justified, and Right Justified
TDM, 50% DUTY CYCLE MODE
0x02[4:2], SAI = 1 (2 channels), 2 (4 channels), 3 (8 channels), 4 (16 channels)
0x02[6:5], SDATA_FMT = 0 (I2S), 1 (LJ), 2 (RJ 24-bit), 3 (RJ 16-bit)
0x03[1], BCLK_EDGE = 0 (rising BCLK edge used)
0x03[6], LRCLK_MODE = 0 (50% duty cycl LRCLK)
0x03[3:2], SLOT_WIDTH = 0 (32 BCLK cycles), 1 (24 BCLK cycles), 2 (16 BCLK cycles)
BCLK
32/24/16 BCLKs
32/24/16 BCLKs
32/24/16 BCLKs
LRCLK
2
SDATA I S
CHANNEL 1
CHANNEL 2
CHANNEL N
8 TO 32 BCLKs
8 TO 32 BCLKs
8 TO 32 BCLKs
CHANNEL N
CHANNEL 1
CHANNEL 2
SDATA LJ
SDATA RJ
8 TO 32 BCLKs
8 TO 32 BCLKs
8 TO 32 BCLKs
CHANNEL 1
24 TO 16 BCLKs
CHANNEL 2
24 OR 16 BCLKs
CHANNEL N
24 OR 16 BCLKs
Figure 27. TDM Modes with 50% Duty Cycle LRCLK
TDM, PULSE MODE
0x02[4:2], SAI = 1 (2 channels), 2 (4 channels), 3 (8 channels), 4 (16 channels)
0x02[6:5], SDATA_FMT = 0 (I2S), 1 (LJ), 2 (RJ 24-bit), 3 (RJ 16-bit)
0x03[1], BCLK_EDGE = 0 (rising BCLK edge used)
0x03[6], LRCLK_MODE = 1 (pulse mode LRCLK)
0x03[3:2], SLOT_WIDTH = 0 (32 BCLK cycles), 1 (24 BCLK cycles), 2 (16 BCLK cycles)
BCLK
32/24/16 BCLKs
32/24/16 BCLKs
32/24/16 BCLKs
LRCLK
2
SDATA I S
CHANNEL 1
8 TO 32 BCLKs
CHANNEL 2
8 TO 32 BCLKs
CHANNEL N
8 TO 32 BCLKs
CHANNEL 2
8 TO 32 BCLKs
CHANNEL N
8 TO 32 BCLKs
CHANNEL 1
8 TO 32 BCLKs
SDATA LJ
SDATA RJ
CHANNEL 1
24 OR 16 BCLKs
CHANNEL N
24 OR 16 BCLKs
CHANNEL 2
24 OR 16 BCLKs
Figure 28. TDM Modes with Pulse Mode LRCLK
Rev. 0 | Page 15 of 28
SSM2519
Data Sheet
PCM, MULTICHANNEL MODE
0x02[4:2], SAI = 1 (2 channels), 2 (4 channels), 3 (8 channels), 4 (16 channels)
0x02[6:5], SDATA_FMT = 0 (I2S), 1 (LJ), 2 (RJ 24-bit), 3 (RJ 16-bit)
0x03[1], BCLK_EDGE = 1 (falling BCLK edge used)
0x03[6], LRCLK_MODE = 1 (pulse mode LRCLK)
0x03[3:2], SLOT_WIDTH = 0 (32 cycles), 1 (24 cycles), 2 (16 cycles)
BCLK
32/24/16 BCLKs
32/24/16 BCLKs
32/24/16 BCLKs
LRCLK
2
CHANNEL 1
8 TO 32 BCLKs
CHANNEL N
8 TO 32 BCLKs
SDATA I S
CHANNEL 2
8 TO 32 BCLKs
CHANNEL 2
8 TO 32 BCLKs
CHANNEL 1
8 TO 32 BCLKs
CHANNEL N
8 TO 32 BCLKs
SDATA LJ
SDATA RJ
CHANNEL 1
24 OR 16 BCLKs
CHANNEL 2
24 OR 16 BCLKs
CHANNEL N
24 OR 16 BCLKs
Figure 29. Multichannel PCM Modes
PCM, MONO MODE
0x02[4:2], SAI = 5
0x02[6:5], SDATA_FMT = 0 (I2S), 1 (LJ), 2 (RJ 24-bit), 3 (RJ 16-bit)
0x03[1], BCLK_EDGE = 1 (falling BCLK edge used)
0x03[6], LRCLK_MODE = 1 (pulse mode LRCLK)
BCLK
ANY NUMBER BCLKs
LRCLK
2
SDATA I S
SDATA LJ
SDATA RJ
MONO CHANNEL
8 TO 32 BCLKs
MONO CHANNEL
8 TO 32 BCLKs
MONO CHANNEL
8 TO 32 BCLKs
Figure 30. Mono PCM Modes
Rev. 0 | Page 16 of 28
Data Sheet
SSM2519
I2C CONFIGURATION INTERFACE
Stop and start conditions can be detected at any stage during the
data transfer. If these conditions are asserted out of sequence with
normal read and write operations, the SSM2519 immediately
jumps to the idle condition. During a given SCL high period,
the user should issue only one start condition, one stop condition,
or a single stop condition followed by a single start condition. If
an invalid subaddress is issued by the user, the SSM2519 does
not issue an acknowledge and returns to the idle condition. If
the user exceeds the highest subaddress while in auto-increment
mode, one of two actions is taken. In read mode, the SSM2519
outputs the highest subaddress register contents until the master
device issues a no acknowledge, indicating the end of a read. A
no acknowledge condition is where the SDA line is not pulled
low on the ninth clock pulse of SCL. If the highest subaddress
location is reached while in write mode, the data for the invalid
byte is not loaded into any subaddress register, a no acknowledge
is issued by the SSM2519, and the part returns to the idle
condition.
OVERVIEW
The SSM2519 supports a 2-wire serial (I2C-compatible) micro-
processor bus driving multiple peripherals. Two pins, serial data
(SDA) and serial clock (SCL), carry information between the
SSM2519 and the system I2C master controller. The SSM2519
is always a slave on the bus, meaning it cannot initiate a data
transfer. Each slave device is recognized by a unique device
address. The device address byte format is shown in Figure 31.
The address resides in the first seven bits of the I2C write. The
LSB (Bit 7) of this byte sets either a read or write operation.
Logic Level 1 corresponds to a read operation, and Logic Level 0
corresponds to a write operation. The full byte addresses are
shown in Figure 31, where the subaddresses are automatically
incremented at word boundaries and can be used for writing
large amounts of data to contiguous memory locations. This
increment happens automatically after a single word write,
unless a stop condition is encountered. A data transfer is always
terminated by a stop condition.
I2C Read and Write Operations
Both SDA and SCL should have a 2.2 kΩ pull-up resistor on the
lines connected to them.
Figure 33 shows the timing of a single-word write operation.
Every ninth clock, the SSM2519 issues an acknowledge by
pulling SDA low.
The device address is 0x70.
Figure 34 shows the timing of a burst mode write sequence.
This figure shows an example where the target destination
registers are two bytes. The SSM2519 knows to increment its
subaddress register every byte because the requested subaddress
corresponds to a register or memory area with a byte word
length.
BIT 0
1
BIT 1
1
BIT 2
1
BIT 3
0
BIT 4
0
BIT 5
0
BIT 6
0
BIT 7
R/W
Figure 31. I2C Device Address Byte Format
Addressing
Initially, each device on the I2C bus is in an idle state,
monitoring the SDA and SCL lines for a start condition and
the proper address. The I2C master initiates a data transfer by
establishing a start condition, defined by a high-to-low transition
on SDA while SCL remains high. This indicates that an
address/data stream follows. All devices on the bus respond to
the start condition and shift the next eight bits (the 7-bit
The timing of a single-word read operation is shown in
W
Figure 35. Note that the first R/ bit is 0, indicating a write
operation. This is because the subaddress still needs to be
written to set up the internal address. After the SSM2519
acknowledges the receipt of the subaddress, the master must
issue a repeated start command followed by the chip address
W
address plus the R/ bit) MSB first. The device that recognizes
W
byte with the R/ bit set to 1 (read). This causes the SSM2519
the transmitted address responds by pulling the data line low
during the ninth clock pulse. This ninth bit is known as an
acknowledge bit. All other devices withdraw from the bus at
SDA to reverse and begin driving data back to the master. The
master then responds every ninth pulse with an acknowledge
pulse to the SSM2519.
W
this point and return to the idle condition. The R/ bit
Figure 36 shows the timing of a burst mode read sequence. This
figure shows an example where the target destination registers
are two bytes. The SSM2519 knows to increment its subaddress
register at every byte because the requested subaddress corresponds
to a register or memory area with a byte word length.
determines the direction of the data. A Logic 0 on the LSB of
the first byte means that the master writes information to the
peripheral, whereas a Logic 1 means that the master reads
information from the peripheral after writing the subaddress
and repeating the start address. A data transfer takes place until
a stop condition is encountered. A stop condition occurs when
SDA transitions from low to high while SCL is held high. The
timing for the I2C port is shown in Figure 3.
Rev. 0 | Page 17 of 28
SSM2519
Data Sheet
SCL
SDA
R/W
ACK
ACK
START BY
MASTER
FRAME 2
SUBADDRESS BYTE
FRAME 1
CHIP ADDRESS BYTE
SCL
(CONTINUED)
SDA
(CONTINUED)
ACK
ACK
STOP BY
MASTER
FRAME 3
DATA BYTE 1
FRAME 4
DATA BYTE 2
Figure 32. I2C Read/Write Timing
START CHIP ADDRESS
ACK BY
SLAVE
SUBADDRESS
(8 BITS)
ACK BY
SLAVE
DATA BYTE 1
(8 BITS)
STOP
BIT
R/W = 0
BIT
(7 BITS)
Figure 33. Single-Word I2C Write Format
START CHIP ADDRESS ACK BY
ACK BY
SLAVE
DATA- ACK BY
DATA- ACK BY
STOP
BIT
SUBADDRESS
BIT
SLAVE
WORD 1 SLAVE WORD 2 SLAVE
R/W = 0
Figure 34. Burst Mode I2C Write Format
START CHIP ADDRESS ACK BY
ACK BY
SLAVE
CHIP ADDRESS ACK BY
DATA
ACK BY
STOP
BIT
START
BIT
SUBADDRESS
BIT
SLAVE
SLAVE
BYTE 1 MASTER
R/W = 0
R/W = 1
Figure 35. Single-Word I2C Read Format
DATA-
WORD 1
START CHIP ADDRESS ACK BY
ACK BY
SLAVE
CHIP ADDRESS ACK BY
ACK BY
MASTER
STOP
BIT
START
BIT
SUBADDRESS
BIT
SLAVE
SLAVE
R/W = 0
R/W = 1
Figure 36. Burst Mode I2C Read Format
Rev. 0 | Page 18 of 28
Data Sheet
SSM2519
REGISTER SUMMARY
Table 15. Register Summary
Reg Name
Bits
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
MCS
Bit 1
Bit 0
Reset
0x05
0x30
0x02
0x00
0x00
0x40
0x11
0x0C
RW
RW
RW
RW
RW
RW
RW
RW
RW
0x00 PWR_CTRL
0x01 SYS_CTRL
0x02 SAI_FMT1
0x03 SAI_FMT2
0x04 CH_SEL
[7:0] S_RST
[7:0] HPF_EN
[7:0] RESERVED
[7:0] BCLK_GEN
[7:0]
RESERVED
AMP_LPM
NO_BCLK
DAC_LPM
SPWDN
ASR
APWDN_EN
SAI_MSB
EDGE
AMCS
SDATA_FMT
SAI
FS
LRCLK_MODE LRCLK_POL
RESERVED
SLOT_WIDTH
BCLK_EDGE
RESERVED
CH_SEL
0x05 VOL_CTRL
0x06 GAIN_CTRL
[7:0]
VOL
[7:0] AMUTE
RESERVED
OC
ANA_GAIN
RESERVED
MAX_AR
M_MUTE
0x07 FAULT_CTRL1 [7:0] RESERVED
OT
MRCV
ARCV
Rev. 0 | Page 19 of 28
SSM2519
Data Sheet
REGISTER DETAILS
SOFTWARE RESET AND MASTER SOFTWARE POWER-DOWN CONTROL REGISTER
Address: 0x00, Reset: 0x05, Name: PWR_CTRL
Table 16. Bit Descriptions for PWR_CTRL
Bits
Bit Name
Settings
Description
Reset
Access
7
S_RST
Software reset. The software reset bit resets all internal blocks, including
I2C registers, to their default states.
0x0
RW
0
1
Normal operation
Software reset
6
5
RESERVED
NO_BCLK
Reserved.
0x0
0x0
RW
RW
No BCLK operational mode. MCLK also used as BCLK.
BCLK used as BCLK
MCLK used as BCLK. No signal needed on BCLK pin.
0
1
[4:1]
MCS
Master clock select. MCS must be set according to the input MCLK ratio
relative to the input sample frequency. Refer to Table 10.
0x2
RW
0000 64 × fS MCLK
0001 128 × fS MCLK
0010 256 × fS MCLK
0011 384 × fS MCLK
0100 512 × fS MCLK
0101 768 × fS MCLK
0110 100 × fS MCLK
0111 200 × fS MCLK
1000 400 × fS MCLK
1001 Reserved
0
SPWDN
Master software power-down. Software power-down puts all blocks
0x1
RW
except the I2C interface in a low power state.
Normal operation
0
1
Software master power-down
Rev. 0 | Page 20 of 28
Data Sheet
SSM2519
EDGE SPEED, POWER, AND CLOCKING CONTROL REGISTER
Address: 0x01, Reset: 0x30, Name: SYS_CTRL
Table 17. Bit Descriptions for SYS_CTRL
Bits
Bit Name
Settings
Description
Reset
Access
7
HPF_EN
DC blocking high-pass filter enable. The SSM2519 contains a selectable
high-pass filter. The −3 dB frequency is at 6 Hz with a 48 kHz sample rate.
This frequency increases linearly with lower sample rates.
0x0
RW
0
1
High-pass filter off
High-pass filter on
6
5
4
AMP_LPM
DAC_LPM
APWDN_EN
Amplifier low power mode.
Normal operation
Low power (return to zero) Class-D mode
DAC low power mode.
Normal operation
Low power operation mode. DAC runs at half speed.
0x0
0x1
0x1
RW
RW
RW
0
1
0
1
Auto power-down enable. Auto power-down automatically puts the IC in
a low power state when 2048 consecutive zero input samples have been
received.
0
1
Auto power-down disabled
Auto power-down enabled
[3:2]
EDGE
Edge rate control. This controls the edge speed of the power stage. The
low EMI operation mode reduces the edge speed, lowering EMI and
power efficiency.
0x0
RW
00 Normal operation
01 Lower EMI mode operation
10 Lower EMI mode operation
11 Lowest EMI mode operation
Auto MCLK select.
1
0
AMCS
ASR
0x0
0x0
RW
RW
0
1
Master clock rate determined by MCS bits in Register 0x00
Master clock rate automatically detected
Autosample rate.
0
1
Sample rate setting determined by FS bit in Register 0x02
Autosample and MCLK rate detection enabled
Rev. 0 | Page 21 of 28
SSM2519
Data Sheet
SERIAL AUDIO INTERFACE AND SAMPLE RATE CONTROL REGISTER
Address: 0x02, Reset: 0x02, Name: SAI_FMT1
Table 18. Bit Descriptions for SAI_FMT1
Bits
Bit Name
RESERVED
SDATA_FMT
Settings
Description
Reset
0x0
Access
RW
7
Reserved.
[6:5]
Serial data format.
00 I2S, BCLK delay by 1
0x0
RW
01 Left justified
10 Right justified 24-bit data
11 Right justified 16-bit data
Serial audio interface format.
[4:2]
SAI
0x0
RW
000 Stereo: I2S, LJ, RJ
001 TDM2
010 TDM4
011 TDM8
100 TDM16
101 Mono PCM
110 Reserved
111 Reserved
[1:0]
FS
Sample rate selection.
0x2
RW
00 8 kHz to 12 kHz
01 16 kHz to 24 kHz
10 32 kHz to 48 kHz
11 Reserved
Rev. 0 | Page 22 of 28
Data Sheet
SSM2519
SERIAL AUDIO INTERFACE CONTROL REGISTER
Address: 0x03, Reset: 0x00, Name: SAI_FMT2
Table 19. Bit Descriptions for SAI_FMT2
Bits
Bit Name
Settings
Description
Reset
Access
7
BCLK_GEN
BCLK internal generation. When BCLK_GEN is enabled, an internally
generated BCLK is used. Therefore, routing the BCLK signal to the pin is
not required.
0x0
RW
0
1
External BCLK used
Internally generated BCLK used
LRCLK mode selection for TDM operation.
50% duty cycle LRCLK
6
LRCLK_MODE
LRCLK_POL
SAI_MSB
0x0
0x0
0x0
0x0
RW
RW
RW
RW
0
1
Pulse mode LRCLK
5
LRCLK polarity control.
0
1
Normal LRCLK operation
Inverted LRCLK operation
SDATA bit stream order.
MSB first SDATA
4
0
1
LSB first SDATA
[3:2]
SLOT_WIDTH
BCLK cycles per frame in TDM modes select.
00 32 BCLK cycles per slot
01 24 BCLK cycles per slot
10 16 BCLK cycles per slot
11 Reserved
1
0
BCLK_EDGE
RESERVED
BCLK active edge select.
0x0
0x0
RW
RW
0
1
Rising BCLK edge used
Falling BCLK edge used
Reserved.
Rev. 0 | Page 23 of 28
SSM2519
Data Sheet
CHANNEL MAPPING CONTROL REGISTER
Address: 0x04, Reset: 0x00, Name: CH_SEL
(Channel 1) are valid because these modes can only contain two
channels. In TDM4, Setting 0000 to Setting 0011 are supported.
In TDM8, Setting 0000 to Setting 0111 are supported. In
TDM16, Setting 0000 to Setting 1111 are supported.
Note that not all the settings of CH_SEL are available in all
serial interface modes. For example, in stereo and TDM2
modes, only Setting 0000 (Channel 0) and Setting 0001
Table 20. Bit Descriptions for CH_SEL
Bits
[7:4]
[3:0]
Bit Name
RESERVED
CH_SEL
Settings
Description
Reset
0x0
Access
RW
Reserved.
Channel mapping select. Select input SDATA channel to map to left
channel output.
0x0
RW
0000 Channel 0 from SAI to output
0001 Channel 1 from SAI to output
0010 Channel 2 from SAI to output
0011 Channel 3 from SAI to output
0100 Channel 4 from SAI to output
0101 Channel 5 from SAI to output
0110 Channel 6 from SAI to output
0111 Channel 7 from SAI to output
1000 Channel 8 from SAI to output
1001 Channel 9 from SAI to output
1010 Channel 10 from SAI to output
1011 Channel 11 from SAI to output
1100 Channel 12 from SAI to output
1101 Channel 13 from SAI to output
1110 Channel 14 from SAI to output
1111 Channel 15 from SAI to output
Rev. 0 | Page 24 of 28
Data Sheet
SSM2519
VOLUME CONTROL REGISTER
Address: 0x05, Reset: 0x40, Name: VOL_CTRL
Table 21. Bit Descriptions for VOL_CTRL
Bits
Bit Name
Settings
Description
Reset
0x40
Access
[7:0]
VOL
Volume control.
RW
00000000 +24 dB
00000001 +23.625 dB
00000010 +23.35 dB
00000011 +22.875 dB
00000100 +22.5 dB
00000101 Decreasing in 0.375 dB steps
00111111 +0.375 dB
01000000
0
01000001 −0.375 dB
01000010 Decreasing in 0.375 dB steps
11111101 −70.875 dB
11111110 −71.25 dB
11111111 Mute
Rev. 0 | Page 25 of 28
SSM2519
Data Sheet
GAIN AND MUTE CONTROL REGISTER
Address: 0x06, Reset: 0x11, Name: GAIN_CTRL
Table 22. Bit Descriptions for GAIN_CTRL
Bits
Bit Name
Settings
Description
Reset
Access
7
AMUTE
Automatic mute enable. When the automatic mute function is enabled,
after 2048 consecutive zero input samples have been received, the
outputs are automatically muted.
0x0
RW
0
1
Automute enabled
Automute disabled
Reserved.
6
RESERVED
ANA_GAIN
0x0
0x1
RW
RW
[5:4]
Analog gain control. This controls the analog gain of the Class-D
modulator. There are two settings optimized for 3.6 V operation from a
lithium ion battery and for 5 V operation.
00 2 V gain
01 3.6 V gain
10 4.2 V gain
11 5 V gain
Reserved.
[3:1]
0
RESERVED
M_MUTE
0x0
0x1
RW
RW
Master mute control. Setting the master mute control bit soft-mutes both
channels.
0
1
Normal operation
Master mute
Rev. 0 | Page 26 of 28
Data Sheet
SSM2519
FAULT CONTROL REGISTER
Address: 0x07, Reset: 0x0C, Name: FAULT_CTRL1
Table 23. Bit Descriptions for FAULT_CTRL1
Bits Bit Name Settings Description
Reset Access
7
6
RESERVED
OC
Reserved.
0x0
0x0
RW
R
Overcurrent fault.
0
1
Normal operation
Overcurrent fault
5
4
OT
Overtemperture fault status.
Normal operation
Overtemperature fault
0x0
0x0
0x3
R
0
1
MRCV
Manual fault recovery.
Normal operation
Writing Logic 1 causes a manual fault recovery attempt when ARCV = 11
W
RW
0
1
[3:2] MAX_AR
Maximum fault recovery attempts. The maximum automatic fault recovery bit
determines how many attempts at autorecovery are performed.
00 One autorecovery attempt
01 Three autorecovery attempts
10 Seven autorecovery attempts
11 Unlimited autorecovery attempts
Autofault recovery control.
[1:0] ARCV
0x0
RW
00 Autofault recovery for overtemperature and overcurrent faults
01 Autofault recovery for overtemperature fault only
10 Autofault recovery for overcurrent fault only
11 No autofault recovery
Rev. 0 | Page 27 of 28
SSM2519
Data Sheet
OUTLINE DIMENSIONS
1.455
1.415
1.375
BOTTOM VIEW
(BALL SIDE UP)
3
2
1
A
BALL A1
IDENTIFIER
1.705
1.665
1.625
1.20
REF
B
C
D
0.40
BSC
TOP VIEW
(BALL SIDE DOWN)
0.80
REF
0.560
0.500
0.440
END VIEW
COPLANARITY
0.05
SEATING
PLANE
0.230
0.200
0.170
0.300
0.260
0.220
Figure 37. 12-Ball Wafer Level Chip Scale Package [WLCSP]
(CB-12-6)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Temperature Range
Package Description
Package Option
CB-12-6
CB-12-6
Branding
Y4B
Y4B
SSM2519ACBZ-R7
SSM2519ACBZ-RL
EVAL-SSM2519Z
−40°C to +85°C
−40°C to +85°C
12-Ball Wafer Level Chip Scale Package [WLCSP]
12-Ball Wafer Level Chip Scale Package [WLCSP]
Evaluation Board
1 Z = RoHS Compliant Part.
©2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D10750-0-7/12(0)
Rev. 0 | Page 28 of 28
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