SSM2602CPZ-REEL1 [ADI]
Low Power Audio Codec; 低功耗音频编解码器
| 型号： | SSM2602CPZ-REEL1 |
| 厂家： | 
ADI |
| 描述： | Low Power Audio Codec |
| 文件： | 总28页 (文件大小：448K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Low Power Audio Codec
SSM2602
Preliminary Technical Data
FEATURES
GENERAL DESCRIPTION
Stereo, 24-bit analog-to-digital and digital-to-analog converters
DAC SNR: 98 dB (A-weighted), THD: −80 dB at 48 kHz, 3.3 V
ADC SNR: 90 dB (A-weighted), THD: −80 dB at 48 kHz, 3.3 V
Highly efficient headphone amplifier
Complete stereo/mono or microphone/line interface
Low power
7 mW stereo playback (1.8 V/1.8 V supplies)
14 mW record and playback (1.8 V/1.8 V supplies)
Low supply voltages
The SSM2602 is a low power, high quality stereo audio codec
for portable digital audio applications with stereo programmable
gain amplifier (PGA) line and monaural microphone inputs. It
features two 24-bit analog-to-digital converter (ADC) channels
and two 24-bit digital-to-audio (DAC) converter channels.
The SSM2602 can operate as a master or a slave. It offers
various master clock frequencies, including 12 MHz or 24 MHz
for USB devices; standard 256 fS rates, such as 12.288 MHz and
24.576 MHz; and many common audio-sampling rates, such as
96 kHz, 88.2 kHz, 48 kHz, 44.1 kHz, 32 kHz, 16 kHz, and 8 kHz.
Analog: 1.8 V to 3.6 V
Digital core: 1.8 V to 3.6 V
The SSM2602 can operate at power supplies as low as 1.8 V for
the analog circuitry and 1.5 V for the digital circuitry. The
maximum voltage supply is 3.6 V for all supplies.
Digital I/O: 1.8 V/3.6 V
256 fS/384 fS or USB master clock rate: 12 MHz, 24 MHz
Audio sample rates: 8 kHz,16 kHz, 32 kHz, 44.1 kHz, 48 kHz,
88.2 kHz, and 96 kHz
The SSM2602 software-programmable output options provide
the user with many application options, such as speaker driver,
headphone driver, or both. Its volume control functions provide
a large range of gain control of the audio signal.
28-lead, 5 mm × 5 mm LFCSP (QFN) package
APPLICATIONS
Mobile phones
MP3 players
Portable gaming
Portable electronics
Educational toys
The SSM2602 is specified over the industrial temperature range
of −40°C to +85°C. It is available in a 28-lead, 5 mm × 5 mm
lead frame chip scale package (LFCSP).
FUNCTIONAL BLOCK DIAGRAM
AVDD VMID AGND
DBVDD DGND DCVDD
HPVDD PGND
SSM2602
MICBIAS
BYPASS/MUTE 3dB STEP
6dB~15dB/MUTE 3dB STEP
ATTEN
ATTEN
–73dB~+6dB,
1dB STEP
–34.5dB~+33dB,
1.5dB STEP
RHPOUT
ROUT
RLINEIN
MICIN
MUX
MUX
ADC
ADC
DAC
DIGITAL
PROCESSOR
LOUT
14dB/34dB
DAC
LLINEIN
LHPOUT
–34.5dB~+33dB,
1.5dB STEP
–73dB~+6dB,
1dB STEP
6dB~15dB/MUTE 3dB STEP
BYPASS/MUTE 3dB STEP
ATTEN
ATTEN
CLK
DIGITAL AUDIO INTERFACE
CONTROL INTERFACE
MCLK/ XTO CLKOUT
XTI
DACDAT ADCDAT BCLK DACLRC ADCLRC MODE CSB SDIN SCLK
Figure 1.
Rev. PrB
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2007 Analog Devices, Inc. All rights reserved.
SSM2602
Preliminary Technical Data
TABLE OF CONTENTS
Features .............................................................................................. 1
Software Control Interface........................................................ 13
Applications..................................................................................... 14
Typical Application Circuits ......................................................... 15
Register Map ................................................................................... 17
Register Map Details ...................................................................... 18
Left-Channel ADC Input Volume, Address 0x00.................. 18
Right-Channel ADC Input Volume, Address 0x01 ............... 19
Left-Channel DAC Volume, Address 0x02............................. 20
Right-Channel DAC Volume, Address 0x03 .......................... 20
Analog Audio Path, Address 0x04 ........................................... 21
Digital Audio Path Control, Address 0x05 ............................. 21
Power Management, Address 0x06.......................................... 22
Power Consumption .................................................................. 22
Digital Audio I/F, Address 0x07 ............................................... 23
Sampling Rate, Address 0x08.................................................... 23
ACTIVE, Address 0x09 ............................................................. 25
RESET, Address 0x0F................................................................. 25
ALC Control 1, Address 0x10................................................... 25
ALC Control 2, Address 0x11................................................... 26
Noise Gate, Address 0x12.......................................................... 26
Outline Dimensions....................................................................... 27
Ordering Guide .......................................................................... 27
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Recommended Operating Conditions ...................................... 4
Digital Filter Characteristics ....................................................... 4
Timing Characteristics ................................................................ 5
Timing Diagrams.......................................................................... 5
Absolute Maximum Ratings............................................................ 6
Thermal Resistance ...................................................................... 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Descriptions............................. 7
Typical Performance Characteristics ............................................. 8
Converter Filter Response........................................................... 8
Digital De-Emphasis Characteristics......................................... 9
Theory of Operation ...................................................................... 10
ADC High-Pass Filter ................................................................ 10
Automatic Level Control (ALC)............................................... 10
Analog Interface ......................................................................... 11
Digital Audio Interface .............................................................. 11
REVISION HISTORY
9/07—Revision PrB: Preliminary Version
Rev. PrB | Page 2 of 28
Preliminary Technical Data
SPECIFICATIONS
SSM2602
TA = 25°C, AVDD = DVDD = 3.3 V, PVDD = 3.3 V, 1 kHz signal, fS = 48 kHz, PGA gain = 0 dB, 24-bit audio data, unless otherwise noted.
Table 1.
Parameter
Min
Typ
Max
Unit
Conditions
OPERATING CONDITIONS
Analog Voltage Supply (AVDD)
Digital Power Supply
Ground (AGND, PGND, DGND)
POWER CONSUMPTION
Power-Up
1.8
1.5
3.3
3.3
0
3.6
3.6
V
V
V
Stereo Record (1.8 V)
Stereo Record (3.3 V)
Stereo Playback (1.8 V)
Stereo Playback (3.3 V)
Power-Down
7
22
7
mW
mW
mW
mW
μW
22
40
LINE INPUT
Input Signal Level (0 dB)
Input Impedance
1 × AVDD/3.3
200
10
480
10
V rms
kΩ
kΩ
kΩ
pF
PGA gain = 0 dB
PGA gain = +33 dB
PGA gain = −34.5 dB
Input Capacitance
Signal-to-Noise Ratio (A-weighted)
85
90
87
−80
−75
80
0
1.5
−80
dB
dB
dB
dB
dB
dB
dB
dB
PGA gain = 0 dB, AVDD = 3.3 V
PGA gain = 0 dB, AVDD = 1.8 V
−1 dBFS input, AVDD = 3.3 V
−1 dBFS input, AVDD = 1.8 V
Total Harmonic Distortion (THD)
Channel Separation
Programmable Gain
Gain Step
−34.5
33.5
Mute Attenuation
MICROPHONE INPUT
Input Signal Level
Signal-to-Noise Ratio (A-weighted)
Total Harmonic Distortion
Power Supply Rejection Ratio
Mute Attenuation
1
V rms
dB
dB
dB
dB
85
−70
50
80
10
10
Microphone gain = 0 dB (RSOURCE = 40 kΩ)
0 dBFS input, 0 dB gain
Input Resistance
Input Capacitance
kΩ
pF
MICROPHONE BIAS
Bias Voltage
Bias Current Source
Noise in the Signal Bandwidth
LINE OUTPUT
0.75 × AVDD
40
V
mA
nV/√Hz
3
20 Hz to 20 kHz
DAC
−1 dBFS input DAC + line output
Full-Scale Output
Signal-to-Noise Ratio (A-Weighted)
1 × AVDD/3.3
100
98
V rms
dB
AVDD = 3.3 V
AVDD = 1.8 V
AVDD = 3.3 V
AVDD = 1.8 V
THD + N
−80
−75
50
dB
Power Supply Rejection Ratio
Channel Separation
dB
dB
80
Rev. PrB | Page 3 of 28
SSM2602
Preliminary Technical Data
Parameter
Min
Typ
Max
Unit
Conditions
HEADPHONE OUTPUT
Full-Scale Output Voltage
Maximum Output Power
1 × AVDD/3.3
30
60
100
−50
−55
50
V rms
mW
mW
dB
dB
dB
RL = 32 Ω
RL = 16 Ω
Signal-to-Noise Ratio (A-Weighted) 92
THD + N
POUT = 10 mW
POUT = 20 mW
Power Supply Rejection Ratio
Mute Attenuation
dB
dB
80
LINE INPUT TO LINE OUTPUT
Full-Scale Output Voltage
Signal-to-Noise Ratio (A-Weighted)
Total Harmonic Distortion
Power Supply Rejection
1 × AVDD/3.3
96
−80
50
V rms
dB
dB
dB
MICROPHONE INPUT TO
HEADPHONE OUTPUT
Full-Scale Output Voltage
Signal-to-Noise Ratio (A-Weighted)
Power Supply Rejection Ratio
1 × AVDD/3.3
98
50
V rms
dB
dB
Programmable Attenuation
Gain Step
6
15
dB
dB
3
Mute Attenuation
80
dB
RECOMMENDED OPERATING CONDITIONS
Table 2.
Parameter
Min
1.8
1.5
Typ
3.3
3.3
0
Max
3.6
3.6
Unit
Analog Voltage Supply (AVDD)
Digital Power Supply
Ground (AGND, PGND, DGND
V
V
V
DIGITAL FILTER CHARACTERISTICS
Table 3.
Parameter
ADC FILTER
Pass Band
Min
Typ
Max
Unit
Conditions
0
0.445 fS
0.04
Hz
Hz
dB
Hz
dB
Hz
Hz
Hz
0.04 dB
−6 dB
0.5 fS
Pass-Band Ripple
Stop Band
Stop-Band Attenuation
High-Pass Filter Corner Frequency
0.555 fS
−60
f > 0.567 fS
−3 dB
−0.5 dB
−0.1 dB
3.7
10.4
21.6
DAC FILTER
Pass Band
0
0.445 fS
0.04
Hz
Hz
dB
Hz
dB
0.03 dB
−6 dB
0.5 fS
Pass-Band Ripple
Stop Band
Stop-Band Attenuation
0.555 fS
−58
f > 0.565 fS
Rev. PrB | Page 4 of 28
4
Preliminary Technical Data
SSM2602
TIMING CHARACTERISTICS
Table 4.
Limit
tMAX
Parameter
fSCLK
tSCLKPL
tSCLKPH
tSCH
tMIN
0
Unit
kHz
ꢀs
ns
ns
Description
550
SCLK frequency
1.3
600
600
600
100
SCLK low pulse width
SCLK high pulse width
Hold time (start condition)
Setup time (start condition)
Data setup time
tSCS
tDS
ns
ns
tSDIN-SCLKR
tSDIN-SCLKF
tHCS
300
300
ns
ns
ns
ns
SDIN, SCLK rise time
SDIN, SCLK fall time
Setup time (hold condition)
Data hold time
600
tDH
900
TIMING DIAGRAMS
TBD
Rev. PrB | Page 5 of 28
SSM2602
Preliminary Technical Data
ABSOLUTE MAXIMUM RATINGS
At 25°C, unless otherwise noted.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 5.
Parameter
Rating
Supply Voltage
Input Voltage
5 V
VDD
VDD
Table 6. Thermal Resistance
Package Type
28-Lead, 5 mm × 5 mm LFCSP
θJA
θJC
Unit
Common-Mode Input Voltage
Storage Temperature Range
Operating Temperature Range
Junction Temperature Range
Lead Temperature (Soldering, 60 sec)
TBD
TBD
°C/W
−65°C to +150°C
−40°C to +85°C
−65°C to +165°C
300°C
ESD CAUTION
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev. PrB | Page 6 of 28
6
Preliminary Technical Data
SSM2602
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PIN 1
INDICATOR
MCLK/XTI
XTO
DCVDD
DGND
DBVDD
INT/CLKOUT
BCLK
1
2
3
4
5
6
7
21 MICBIAS
20 VMID
19 AGND
18 AVDD
17 ROUT
16 LOUT
15 PGND
SSM2602
TOP VIEW
(Not to Scale)
Figure 2. Pin Configuration of SSM2602
Table 7. Pin Function Descriptions
Pin No.
Mnemonic
MCLK/XTI
XTO
DCVDD
DGND
DBVDD
CLKOUT
BCLK
DACDAT
DACLRC
Type
Description
1
2
3
4
5
6
7
8
9
Digital Input
Master Clock Input/Crystal Input
Crystal Output
Digital Core Supply
Digital Ground
Digital I/O Supply
Buffered Clock Output
Digital Audio Bit Clock. This pin is pulled down when the ACTIVE register is set to 0.
DAC Digital Audio Data Input
Digital Output
Digital Supply
Digital Ground
Digital Supply
Digital Output
Digital Input/Output
Digital Input
Digital Input/Output
DAC Sample Rate Clock (from Left and Right Channels). This pin is pulled down
when the ACTIVE register is set to 0.
10
11
ADCDAT
ADCLRC
Digital Output
Digital Input/Output
ADC Digital Audio Data Output
ADC Sample Rate Clock (from Left and Right Channels). This pin is pulled down
when the ACTIVE register is set to 0.
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
HPVDD
LHPOUT
RHPOUT
PGND
LOUT
ROUT
AVDD
AGND
VMID
MICBIAS
MICIN
RLINEIN
LLINEIN
MODE
CSB
Analog Supply
Analog Output
Analog Output
Analog Ground
Analog Output
Analog Output
Analog Supply
Analog Ground
Analog Output
Analog Output
Analog Input
Analog Input
Analog Input
Digital Input
Headphone Supply
Left-Channel Headphone Output
Right-Channel Headphone Output
Headphone Ground
Left-Channel Line Output
Right-Channel Line Output
Analog Supply
Analog Ground
Middle Voltage Decoupling Capacitor
Microphone Bias
Microphone Input Signal
Right-Channel Line/Microphone Input
Left-Channel Line/Microphone Input
Control Interface Selection to Select I2C®/SPI
3-Wire MPU Chip Select/2-Wire MPU Interface Address Selection, Active Low. This pin is
pulled up when the ACTIVE register is set to 0.
Digital Input
27
28
SDIN
SCLK
Digital Input/Output
Digital Input
3-Wire MPU Data Input/2-Wire MPU Data Input/Output
3-Wire MPU Clock Input/2-Wire MPU Clock Input
Rev. PrB | Page 7 of 28
SSM2602
Preliminary Technical Data
TYPICAL PERFORMANCE CHARACTERISTICS
CONVERTER FILTER RESPONSE
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
0
0.5
1.0
1.5
2.0
2.5
3.0
0
0.5
1.0
1.5
2.0
2.5
3.0
FREQUENCY (fS
)
FREQUENCY (fS)
Figure 3. ADC Digital Filter Frequency Response
Figure 5. DAC Digital Filter Frequency Response
0.04
0.03
0.02
0.01
0
0.04
0.03
0.02
0.01
0
–0.01
–0.02
–0.03
–0.04
–0.01
–0.02
–0.03
–0.04
0
0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50
FREQUENCY (fS
0
0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50
FREQUENCY (fS
)
)
Figure 6. DAC Digital Filter Ripple
Figure 4. ADC Digital Filter Ripple
Rev. PrB | Page 8 of 28
8
Preliminary Technical Data
SSM2602
DIGITAL DE-EMPHASIS CHARACTERISTICS
0
0.20
0.15
0.10
0.05
0
–1
–2
–3
–4
–5
–6
–0.05
–0.10
–0.15
–0.20
–7
–8
–9
–10
0
2
4
6
8
10
12
14
16
0
2
4
6
8
10
12
14
16
18
20
FREQUENCY (kHz
)
FREQUENCY (kHz
)
Figure 7. De-Emphasis Frequency Response (32 kHz)
Figure 10. De-Emphasis Error (44.1 kHz)
0
–1
–2
–3
–4
–5
–6
–7
–8
–9
–10
0.20
0.15
0.10
0.05
0
–0.05
–0.10
–0.15
–0.20
0
2
4
6
8
10 12 14 16 18 20 22
0
2
4
6
8
10
12
14
FREQUENCY (kHz
)
FREQUENCY (kHz
)
Figure 8. De-Emphasis Error (32 kHz)
Figure 11. De-Emphasis Frequency Response (48 kHz)
0
–1
–2
–3
–4
–5
–6
–7
–8
–9
–10
0.20
0.15
0.10
0.05
0
–0.05
–0.10
–0.15
–0.20
0
2
4
6
8
10 12 14 16 18 20 22 24
0
2
4
6
8
10
12
14
16
18
20
FREQUENCY (kHz
)
FREQUENCY (kHz
)
Figure 9. De-Emphasis Frequency Response (44.1 kHz)
Figure 12. De-Emphasis Error (48 kHz)
Rev. PrB | Page 9 of 28
SSM2602
Preliminary Technical Data
THEORY OF OPERATION
Decay (Gain Ramp-Up) Time
ADC HIGH-PASS FILTER
This is the time for the PGA gain to ramp up through 90% of its
range. The time for the recording level to return to its target value
therefore depends on both the decay time and the gain adjustment
required. If the gain adjustment is small, the time to return to
the target value will be less than the decay time.
DC offset can be removed by using the SSM2602 adjustable
digital high-pass filter (see Table 3 for characteristics).
Digital Filter Characteristics
The ADC and DAC employ separate digital filters.
AUTOMATIC LEVEL CONTROL (ALC)
Attack (Gain Ramp-Down) Time
Codec has an automatic level control that aims to keep a constant
recording volume irrespective of the input signal level. This is
achieved by continuously adjusting the PGA gain so that the
signal level at the ADC input remains constant. A digital peak
detector monitors the ADC output and changes the PGA gain if
necessary.
This is the time for the PGA gain to ramp down through 90% of
its range. The time for the recording level to return to its target
value therefore depends on both the attack time and the gain
adjustment required. If the gain adjustment is small, the time
to return to the target value will be less than the attack time.
INPUT SIGNAL
PGA
SIGNAL
AFTER
ALC
ALC TARGET
VALUE
DECAY TIME
ATTACK TIME
Figure 13. PGA and ALC Decay Time and Attack Time Definitions
Rev. PrB | Page 10 of 28
Preliminary Technical Data
SSM2602
ANALOG INTERFACE
Microphone Input
High impedance input MIC
TBD
DIGITAL AUDIO INTERFACE
The digital audio input can support various communication
protocols:
•
•
•
•
Right justified
Left justified
Headphone Output
TBD
I2S mode
Digital-signal processor (DSP) mode
Sidetone Insertion
TBD
The mode selection is performed by writing to the FORMAT [1:0]
bits of the digital audio interface register (Register R7). All
modes are MSB first and operate with data of 16 to 32 bits.
1/fS
LEFT CHANNEL
RIGHT CHANNEL
ADCLRC/
DACLRC
BCLK
ADCDAT/
DACDAT
1
2
3
4
N
1
2
3
N
Figure 14. Left-Justified Audio Interface
1/fS
LEFT CHANNEL
RIGHT CHANNEL
ADCLRC/
DACLRC
BCLK
ADCDAT/
DACDAT
N
4
3
2
1
N
4
3
2
1
Figure 15. Right-Justified Audio Interface
1/fS
LEFT CHANNEL
RIGHT CHANNEL
ADCLRC/
DACLRC
BCLK
ADCDAT/
DACDAT
1
2
3
4
N
1
2
3
N
Figure 16. I2S Audio Interface
Rev. PrB | Page 11 of 28
SSM2602
Preliminary Technical Data
1/fS
LEFT CHANNEL
RIGHT CHANNEL
ADCLRC/
DACLRC
BCLK
1
2
3
N
1
2
3
N
ADCDAT/
DACDAT
Figure 17. DSP/Pulse Code Modulation (PCM) Mode Audio Interface Submode 1 (SM1) [Bit LRP = 0]
1/fS
LEFT CHANNEL
RIGHT CHANNEL
ADCLRC/
DACLRC
FALLING EDGE CAN OCCUR ANY WHERE IN THIS AREA
BCLK
1
2
3
N
1
2
3
N
ADCDAT/
DACDAT
Figure 18. DSP/PCM Mode Audio Interface Submode 2 (SM2) [Bit LRP = 1]
Rev. PrB | Page 12 of 28
Preliminary Technical Data
SSM2602
In 3-wire (SPI) mode, SDIN is used for the program data, SCLK
is used to clock in the program data, and CSB is used to latch in
the program data. In 2-wire (I2C) mode, SDIN is used for serial
data, SCLK is used for the serial clock, and the state of the CSB
pin allows the user to select one of two addresses (see Table 9).
SOFTWARE CONTROL INTERFACE
The software control interface can be operated with a 3-wire (SPI)
or 2-wire (I2C) interface. Selection of the interface format is
achieved by setting the state of the MODE pin.
Table 8. Selecting the Interface Format
Table 9. Selecting the Address
MODE Pin Setting
Interface
2-wire (I2C) interface
CSB Pin Setting
Address
0011010
0011011
0
1
0
1
3-wire (SPI) interface
CSB
CCLK
B15
B14 B13 B12 B11 B10 B09 B08 B07 B06 B05 B04 B03 B02 B01 B0
SDIN
NOTES
1. B15 TO B9 ARE REGISTER MAP ADDRESS.
2. B8 TO B0 ARE REGISTER DATA.
Figure 19. SPI Serial Interface
SDATA
SCLOCK
S
1 – 7
8
9
1 – 7
8
9
1 – 7
8
9
P
START
ADDR
R/W
ACK
SUBADDRESS
ACK
DATA
ACK
STOP
Figure 20. SSM2602 2-Wire I2C Generalized Clocking Diagram
WRITE
SEQUENCE
S
A7 ... A1 A0 A(S) B15 ... B9 B8 A(S) B7 ... B0 A(S)
0
P
DEVICE
ADDRESS
REGISTER
ADDRESS
REGISTER
DATA
READ
SEQUENCE
S
A7 ... A1 A0 A(S)
0
B15 ... B9
0
A(S)
S
A7 ... A1 A0 A(S)
1
B7 ... B0 A(M)
...
0
B8 A(M)
0
P
DEVICE
ADDRESS
REGISTER
ADDRESS
DEVICE
ADDRESS
REGISTER
DATA
(SLAVE DRIVE)
S/P = START/STOP BIT.
2
A0 = I C R/W BIT.
A(S) = ACKNOWLEGE BY SLAVE.
A(M) = ACKNOWLEGE BY MASTER.
A(M) = ACKNOWLEGE BY MASTER.
Figure 21. SSM2602 I2C Write and Read Sequences
Rev. PrB | Page 13 of 28
SSM2602
Preliminary Technical Data
APPLICATIONS
TBD
Rev. PrB | Page 14 of 28
Preliminary Technical Data
SSM2602
TYPICAL APPLICATION CIRCUITS
AVDD VMID AVSS
DBVDD DVSS DCVDD
HPVDD HPVSS
SSM2602
PWRPD
REF
ATTEN
ATTEN
MICBIAS
MICBPD
ADCPD
DACPD
RHPOUT
ROUT
RLINEIN
MUX
ADC
DAC
LHPPD
LINPD
LADCPD
LDACPD
DIGITAL
PROCESSOR
MICIN
OUTPD
MICPD
LOUT
ADC
DAC
MUX
LLINEIN
LHPOUT
LINEPD
RINPD
RADCPD
RDACPD
RHPPD
ATTEN
ATTEN
OSCPD
OSC
CLKOUTPD
CLK GEN
DIGITAL AUDIO INTERFACE
CONTROL INTERFACE
MCLK/XTI
XTO
CLKOUT
DACDAT ADCDAT BCLK DACLRC ADCLRC MODE CSB SDINS CLK
Figure 22. SSM2602 Power Management Functional Location Diagram
Rev. PrB | Page 15 of 28
SSM2602
Preliminary Technical Data
+3.3V_VAA
L2
FB
L1
FB
C23
0.1uF
C21
+
C22
10uF
C20
10uF +
0.1uF
+3,3V_VDD
C18
+
10uF
C19
0.1uF
C24
0.1uF
+
C25
10uF
U1
J1
R1
0
C1
1
C2
J4
R2
C12
1uF
R11
1uF
BNC
NC
L
C4
220PF
100
24
17
16
1
L_LINE_IN
ROUT
J5
BNC
1uF
23
1
R_LINE_IN
LOUT
J2
R3
0
R12
100
C13
1uF
C14
1
R9
47K
R10
47K
21
22
13
14
MIC_BIAS
MIC_IN
LHP_OUT
RHP_OUT
R4
C15
C5
220PF
NC
220uF
R
I2S[0..4]
220uF
SSM2602KCPZ
DACLRC
9
8
10
11
7
DACLRC
DACDAT
ADCDAT
ADCLRC
BCLK
DACDAT
ADCDAT
ADCLRC
BCLK
J6
C27
220PF
1
2
3
4
5
+3.3V_VAA
6
INT/CLKOUT
R14
47K
J7
R7
C26
220PF
R13
47K
680
R5 100K
R6 NC
25
26
27
28
MODE
CSB
SDIN
SCLK
MIC_IN
CSB
1
20
VMID
SDIN
SCLK
PHONEJACK STEREO SW
C10
R8
SPI[0..2]
R15
47K
C6
0.1uF
+
C3
10uF
0
1
2
1uF
MCLK/XTI
POR/XTO
C11
220PF
Y1
12.288MHz
C7
22pF
C8
22pF
Connection under chip
Figure 23. SSM2602 Typical Application Circuit
Rev. PrB | Page 16 of 28
Preliminary Technical Data
SSM2602
REGISTER MAP
Table 10. Register Map
Reg. Address Name
D8
D7
D6
D5
D4
D3
D2
D1
D0
Default
R0 0x00
R1 0x01
Left-Channel
ADC Input Volume
LRINBOTH LINMUTE
0
LINVOL [5:0]
010010111
Right-Channel
ADC Input Volume
RLINBOTH RINMUTE
0
RINVOL [5:0]
010010111
R2 0x02
R3 0x03
Left-Channel
DAC Volume
LRHPBOTH LZCEN
RLHPBOTH RZCEN
LHPVOL [6:0]
RHPVOL [6:0]
001111001
001111001
Right-Channel
DAC Volume
R4 0x04
R5 0x05
R6 0x06
R7 0x07
R8 0x08
R9 0x09
R15 0x0F
R16 0x10
R17 0x11
Analog
Audio Path
MICBOOST2 SIDETONE_ATT [1:0] SIDETONE_EN DACSEL BYPASS
INSEL
MUTEMIC MICBOOST 000001010
Digital
Audio Path
0
0
0
0
0
0
0
0
HPOR
DACMU
DEEMPH [1:0]
ADCHPD 000001000
LINEINPD 010011111
Power
Management
PWROFF CLKOUTPD OSCPD
OUTPD DACPD
LRP
ADCPD MICPD
Digital
Audio I/F
BCLKINV MS
LRSWAP
WL [1:0]
FORMAT [1:0]
000001010
000000000
000000000
000000000
001111011
000110010
Sampling
Rate
CLKODIV2 CLKDIV2
SR [3:0]
BOSR
0
USB
Active
0
0
0
0
0
0
ACTIVE
Software
Reset
RESET [8:0]
ALC
Control 1
ALCSEL [1:0]
MAXGAIN [2:0]
DCY [3:0]
ALCL [3:0]
ATK [3:0]
ALC
Control 2
0
0
R18 0x12
Noise Gate
NGTH [4:0]
NGG [1:0]
NGAT
000000000
Rev. PrB | Page 17 of 28
SSM2602
Preliminary Technical Data
REGISTER MAP DETAILS
LEFT-CHANNEL ADC INPUT VOLUME, ADDRESS 0x00
Table 11. Left-Channel ADC Input Volume Register Bit Map
D8
D7
D6
D5
D4
D3
D2
D1
D0
LRINBOTH
LINMUTE
0
LINVOL [5:0]
Table 12. Descriptions of Left-Channel ADC Input Volume Register Bits
Bit Name
Description
Settings
LRINBOTH
Left-channel line input volume update
0 = store LINVOL in intermediate latch (default)
1 = update left- and right-channel gains
0 = disable mute
LINMUTE
Left-channel input mute
1 = enable mute (default)
00 0000 = 34.5 dB
LINVOL [5:0]
Left-channel PGA volume control
… 1.5 dB step down
01 0111 = 0 dB (default)
… 1.5 dB step down
01 1111 = 12 dB
10 0000 = 13.5 dB
10 0001 = 15 dB
10 0010 = 16.5 dB
10 0011 = 18 dB
10 0100 = 19.5 dB
10 0101 = 21 dB
10 0110 = 22.5 dB
10 0111 = 24 dB
10 1000 = 25.5 dB
10 1001 = 27 dB
10 1010 = 28.5 dB
10 1011 = 30 dB
10 1100 = 31.5 dB
10 1101 = 33 dB
11 1111 to 10 1101 = 33 dB
Rev. PrB | Page 18 of 28
Preliminary Technical Data
SSM2602
RIGHT-CHANNEL ADC INPUT VOLUME, ADDRESS 0x01
Table 13. Right-Channel Input Volume Register Bit Map
D8
D7
D6
D5
D4
D3
D2
D1
D0
RLINBOTH
RINMUTE
0
RINVOL [5:0]
Table 14. Descriptions of Right Input Volume Register Bits
Bit Name
Description
Settings
RLINBOTH
Right-channel line input volume update
0 = store RINVOL in intermediate latch (default)
1 = update left- and right-channel gains
0 = disable mute
RINMUTE
Right-channel input mute
1 = enable mute (default)
00 0000 = 34.5 dB
RINVOL [5:0]
Right-channel PGA volume control
… 1.5 dB step down
01 0111 = 0 dB (default)
… 1.5 dB step down
01 1111 = 12 dB
10 0000 = 13.5 dB
10 0001 = 15 dB
10 0010 = 16.5 dB
10 0011 = 18 dB
10 0100 = 19.5 dB
10 0101 = 21 dB
10 0110 = 22.5 dB
10 0111 = 24 dB
10 1000 = 25.5 dB
10 1001 = 27 dB
10 1010 = 28.5 dB
10 1011 = 30 dB
10 1100 = 31.5 dB
10 1101 = 33 dB
11 1111 to 10 1101 = 33 dB
Rev. PrB | Page 19 of 28
SSM2602
Preliminary Technical Data
LEFT-CHANNEL DAC VOLUME, ADDRESS 0x02
Table 15. Left-Channel DAC Volume Register Bit Map
D8
D7
D6
D5
D4
D3
D2
D1
D0
LRHPBOTH
LZCEN
LHPVOL [6:0]
Table 16. Descriptions of Left-Channel DAC Volume Register Bits
Bit Name
Description
Settings
LRHPBOTH
Right-channel headphone volume update
0 = store LHPVOL in intermediate latch (default)
1 = update left- and right-channel gains
0 = disable (default)
LZCEN
Left-channel zero cross detect enable
Left-channel headphone volume control
1 = enable
LHPVOL [6:0]
000 0000 to 010 1111 = mute
011 0000 = −73 dB
…
111 1001 = 0 dB (default)
… 1 dB steps down to
111 1111 = +6 dB
RIGHT-CHANNEL DAC VOLUME, ADDRESS 0x03
Table 17. Right-Channel DAC Volume Register Bit Map
D8
D7
D6
D5
D4
D3
D2
D1
D0
RLHPBOTH
RZCEN
RHPVOL [6:0]
Table 18. Descriptions of Right-Channel DAC Volume Register Bits
Bit Name
Description
Settings
RLHPBOTH
Right-channel headphone volume update
Right-channel zero cross detect enable
Right-channel headphone volume control
0 = store RHPVOL in intermediate latch (default)
1 = update left- and right-channel gains
0 = disable (default)
RZCEN
1 = enable
RHPVOL [6:0]
000 0000 to 010 1111 = mute
011 0000 = −73 dB
…
111 1001 = 0 dB (default)
… 1 dB steps down to
111 1111 = +6 dB
Rev. PrB | Page 20 of 28
Preliminary Technical Data
SSM2602
ANALOG AUDIO PATH, ADDRESS 0x04
Table 19. Analog Audio Path Register Bit Map
D8
D7
D6
D5
D4
D3
D2
D1
D0
MICBOOST
MICBOOST2
SIDETONE_ATT [1:0]
SIDETONE_EN
DACSEL
BYPASS
INSEL
MUTEMIC
Table 20. Descriptions of Analog Audio Path Register Bits
Bit Name
Description
Settings
MICBOOST2
Additional microphone amplifier gain booster control
Microphone sidetone gain control
0 = 0 dB (default)
1 = 20 dB
SIDETONE_ATT [1:0]
00 = −6 dB (default)
01 = −9 dB
10 = −12 dB
11 = −15 dB
SIDETONE_EN
DACSEL
0 = sidetone disable (default)
1 = sidetone enable
0 = do not select DAC (default)
1 = select DAC
DAC select
BYPASS
Line input bypass to line output
Microphone/line level boost
Microphone mute control
0 = bypass disable
1 = bypass enable (default)
INSEL
0 = microphone input select to ADC (default)
1 = line input select to ADC
0 = mute disable
1 = mute enable (default)
0 = 0 dB (default)
MUTEMIC
MICBOOST
Primary microphone amplifier gain booster control
1 = 20 dB
DIGITAL AUDIO PATH CONTROL, ADDRESS 0x05
Table 21. Digital Audio Path Control Register Bit Map
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
HPOR
DACMU
DEEMPH [1:0]
ADCHPD
Table 22. Descriptions of Digital Audio Path Control Register Bits
Bit Name
Description
Settings
HPOR
Store dc offset when high-pass filter is disabled
0 = store offset disable (default)
1 = store offset enable
DACMU
DAC digital mute
0 = no mute (signal active)
1 = mute (default)
DEEMPH [1:0]
De-emphasis control
00 = no de-emphasis (default)
01 = 32 kHz sampling rate
10 = 44.1 kHz sampling rate
11 = 48 kHz sampling rate
ADCHPD
ADC high-pass filter control
0 = ADC high-pass filter disable (default)
1 = ADC high-pass filter enable
Rev. PrB | Page 21 of 28
SSM2602
Preliminary Technical Data
POWER MANAGEMENT, ADDRESS 0x06
Table 23. Power Management Register Bit Map
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
PWROFF
CLKOUTPD
OSCPD
OUTPD
DACPD
ADCPD
MICPD
LINEINPD
Table 24.
Bit Name
PWROFF
Description
Settings
0 = power up
1 = power down (default)
0 = power up (default)
1 = power down
Whole chip power-down control
Clock output power-down control
Crystal power-down control
Output power-down control
DAC power-down control
CLKOUTPD
OSCPD
0 = power up (default)
1 = power down
OUTPD
0 = power up
1 = power down (default)
0 = power up
DACPD
1 = power down (default)
0 = power up
1 = power down (default)
0 = power up
1 = power down (default)
0 = power up
ADCPD
MICPD
ADC power-down control
Microphone input power-down control
Line input power-down control
LINEINPD
1 = power down (default)
POWER CONSUMPTION
Table 25.
AVDD HPVDD DCVDD DBVDD
Mode
PWROFF CLKOUTPD OSCPD OUTPD DACPD ADCPD MICPD LINEINPD (3.3 V) (3.3 V)
(1.5 V)
(1.5 V)
Unit
Record and
Playback
0
0
0
0
0
0
0
0
8.36
1.7
TBD
TBD
mA
Playback Only
Oscillator
Enabled
0
0
0
1
0
1
0
0
0
0
1
1
1
1
1
1
3.1
3.1
1.7
1.7
TBD
TBD
TBD
TBD
mA
mA
External Clock
Record Only
Line Clock
0
0
0
0
0
0
0
0
0
1
0
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
0
0
0
0
1
1
3.15
3.15
3.45
3.45
-
-
-
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
mA
mA
mA
mA
Line Oscillator
Microphone 1
Microphone 2
Sidetone
(Microphone to
Headphone
Output)
External Clock
0
0
0
0
1
1
0
0
1
1
1
1
0
0
1
1
2.24
2.24
1.7
1.7
TBD
TBD
TBD
TBD
mA
mA
Internally
Generated
Clock
Analog Bypass
(Line Input or
Line Output)
External Line
0
0
0
0
1
1
0
0
1
1
1
1
1
1
0
0
1.94
1.94
1.7
1.7
TBD
TBD
TBD
TBD
mA
mA
Internally
Generated
Line
Power-Down
External Clock
Oscillator
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
mA
mA
Rev. PrB | Page 22 of 28
Preliminary Technical Data
SSM2602
DIGITAL AUDIO I/F, ADDRESS 0x07
Table 26. Digital Audio I/F Register Bit Map
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
BCLKINV
MS
LRSWAP
LRP
WL [1:0]
FORMAT [1:0]
Table 27. Descriptions of Digital Audio I/F Register Bits
Bit Name
Description
Settings
BCLKINV
BCLK inversion control
0 = BCLK not inverted (default)
1 = BCLK inverted
MS
Master mode enable
0 = enable slave mode (default)
1 = enable master mode
LRSWAP
Swap DAC data control
0 = output left- and right-channel data as normal
(default)
1 = swap left- and right-channel DAC data in audio
interface
LRP
Polarity control for clocks in right justified, left justified, and
I2S modes
0 = normal DACLRC and ADCLRC (default), or DSP
Submode 1
1 = invert DACLRC and ADCLRC polarity, or DSP
Submode 2
WL [1:0]
Data-word length control
00 = 16 bits
01 = 20 bits
10 = 24 bits (default)
11 = 32 bits
FORMAT [1:0]
Digital audio input format control
00 = right justified
01 = left justified
10 = I2S format (default)
11 = DSP mode
SAMPLING RATE, ADDRESS 0x08
Table 28. Sampling Rate Register Bit Map
D8
D7
D6
D5
D4
D3
SR [3:0]
D2
D1
D0
0
CLKODIV2
CLKDIV2
BOSR
USB
Table 29. Descriptions of Sampling Rate Register Bits
Bit Name
Description
Settings
CLKODIV2
CLKOUT divider select
0 = CLKOUT is core clock (default)
1 = CLKOUT is core clock divided by 2
0 = core clock is MCLK (default)
1= core clock is MCLK divided by 2
See Table 30 and Table 31.
USB mode:
CLKDIV2
Core clock divide select
SR [3:0]
BOSR
Clock setting condition
Base oversampling rate
0 = 250 fS (default)
1 = 272 fS
Normal mode:
0 = 256 fS (default)
1 = 384 fS
USB
USB mode select
0 = USB mode disable (default)
1 = USB mode enable
Rev. PrB | Page 23 of 28
SSM2602
Preliminary Technical Data
Table 30. Sampling Rate Lookup Table, USB Disabled
Sampling Rate Register Setting
Normal/USB
MCLK (MHz)
12.288
ADC Sampling Rate (kHz) DAC Sampling Rate (kHz)
BOSR
0
SR3
SR2
SR1
SR0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
48
48
1
18.432
0
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
12.288
18.432
48
8
0
1
12.288
18.432
8
48
0
1
12.288
18.432
8
8
0
1
12.288
18.432
12
12
0
1
12.288
18.432
16
16
0
1
12.288
18.432
32
32
0
1
12.288
18.432
96
96
0
1
11.2896
16.9344
11.2896
16.9344
11.2896
16.9344
11.2896
16.9344
11.2896
16.9344
11.2896
16.9344
11.2896
16.9344
11.2896
16.9344
44.1
44.1
8.02
8.02
11
44.1
8.02
44.1
8.02
11
0
1
0
1
0
1
0
1
0
1
22
22
0
1
24
24
0
88.2
88.2
1
Table 31. Sampling Rate Lookup Table, USB Enabled
Sampling Rate Register Setting
Normal/USB
MCLK (MHz)
ADC Sampling Rate (kHz) DAC Sampling Rate (kHz)
BOSR
SR3
0
1
0
1
0
1
0
1
0
0
1
1
SR2
0
0
0
0
0
0
0
0
1
1
1
1
SR1
0
0
0
0
1
1
1
1
0
0
0
0
SR0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
12
12
12
12
12
12
12
12
12
12
12
12
12
48
48
44.1
48
44.1
8
44.1
8
8.02
48
8.02
8
44.1
8
8.02
12
8.02
12
16
16
11
11
22
22
1
1
1
0
24
24
Rev. PrB | Page 24 of 28
Preliminary Technical Data
SSM2602
Sampling Rate Register Setting
Normal/USB
MCLK (MHz)
ADC Sampling Rate (kHz) DAC Sampling Rate (kHz)
BOSR
SR3
0
0
SR2
1
1
SR1
1
1
SR0
0
1
0
0
1
1
1
1
12
12
12
32
32
96
96
1
1
1
1
88.2
88.2
ACTIVE, ADDRESS 0x09
Table 32. Active Register Bit Map
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
0
ACTIVE
Table 33. Descriptions of Active Register Bit
Bit Name
Description
Settings
ACTIVE
Digital core activation control
0 = disable digital core (default)
1 = activate digital core
RESET, ADDRESS 0x0F
Table 34. Reset Register Bit Map
D8
D7
D6
D5
D4
D3
D2
D1
D0
RESET [8:0]
Table 35. Descriptions of Reset Register Bits
Bit Name
Description
Settings
RESET [8:0]
Write to RESET register to set all control registers to default 0 = reset (default)
setting.
ALC CONTROL 1, ADDRESS 0x10
Table 36. ALC Control 1 Register Bit Map
D8
D7
D6
D5
D4
D3
D2
D1
D0
ALCSEL [1:0]
MAXGAIN [2:0]
ALCL [[3:0]
Table 37. Descriptions of ALC Control 1 Register Bits
Bit Name
Description
Settings
00: ALC disabled (default)
ALCSEL [1:0]
ALC selection
01: ALC enabled, right channel only
10: ALC enabled, left channel only
11: N/A
MAXGAIN [2:0]
ALCL [3:0]
PGA maximum gain
ALC target level
000: −12 dB
001: −6 dB
… 6 dB steps up to
111: 30 dB (default)
0000: −28.5 dBFS
0001: −27 dBFS
…
1011: −12 dBFS (default)
… 1.5 dB steps up to
1111: −6 dBFS
Rev. PrB | Page 25 of 28
SSM2602
Preliminary Technical Data
ALC CONTROL 2, ADDRESS 0x11
Table 38. ALC Control 2 Register Bit Map
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
DCY [3:0]
ATK [3:0]
Table 39. Descriptions of ALC Control 2 Register Bits
Bit Name
Description
Settings
DCY [3:0]
Decay (release) time control
0000: 24 ms
0001: 48 ms
0010: 96 ms
0011: 192 ms (default)
… 24 ms steps up to
1010: 24.576 sec
0000: 6 ms
ATK [3:0]
ALC attack time control
0001: 12 ms
0010: 24 ms (default)
… 6 ms steps up to
1010: 6.144 sec
NOISE GATE, ADDRESS 0x12
Table 40. Noise Gate Register Bit Map
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
NGTH [4:0]
NGG [1:0]
NGAT
Table 41. Descriptions of Noise Gate Register Bits
Bit Name
Description
Settings
NGTH [4:0]
Noise gate threshold
00000: −76.5 dBFS (default)
00001: −75 dBFS
… 1.5 dB steps up to
11110: −31.5 dBFS
11111: −30 dBFS
NGG [1:0]
Noise gate type
Noise enable
X0: hold PGA gain constant (default)1
01: mute output
11: reserved
NGAT
0: noise disable (default)
1: noise enable
1 X = don’t care.
Rev. PrB | Page 26 of 28
Preliminary Technical Data
OUTLINE DIMENSIONS
SSM2602
5.00
BSC SQ
0.60 MAX
0.60 MAX
PIN 1
INDICATOR
22
28
1
21
0.50
BSC
PIN 1
INDICATOR
3.45
3.30 SQ
3.15
EXPOSED
PAD
(BOTTOM VIEW)
TOP
4.75
BSC SQ
VIEW
0.75
0.60
0.50
15
7
14
8
0.25 MIN
3.00 REF
0.80 MAX
0.65 TYP
12° MAX
1.00
0.85
0.80
0.05 MAX
0.02 NOM
COPLANARITY
0.08
SEATING
PLANE
0.30
0.23
0.18
0.20 REF
COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-1
Figure 24. 28-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
5 mm × 5 mm Body, Very Thin Quad
(CP-28-4)
Dimensions shown in millimeters
ORDERING GUIDE
Model
SSM2602CPZ-R21
SSM2602CPZ-REEL1
SSM2602CPZ-REEL71
SSM2602-EVALZ1
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
Package Option
CP-28-4
CP-28-4
28-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
28-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
28-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
Evaluation Board
CP-28-4
1 Z = RoHS Compliant Part.
Rev. PrB | Page 27 of 28
SSM2602
NOTES
Preliminary Technical Data
©2007 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
PR06858-0-9/07(PrB)
Rev. PrB | Page 28 of 28
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