SSM3515_17 [ADI]
Audio Amplifier;
| 型号： | SSM3515_17 |
| 厂家： | 
ADI |
| 描述： | Audio Amplifier |
| 文件： | 总41页 (文件大小：1030K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
31 W, Filterless, Class-D Digital Input
Audio Amplifier
Data Sheet
SSM3515
FEATURES
GENERAL DESCRIPTION
Filterless digital input, mono Class-D amplifier
Operates from a single 4.5 V to 17 V supply
The SSM3515 is a fully integrated, high efficiency, mono Class-D
audio amplifier with digital inputs. The application circuit
31.3 W output power, 17 V supply, and 4 Ω load at 1% THD + N
107 dB A-weighted signal-to-noise ratio
93.3% efficiency into 8 Ω load at 12 V
requires a minimum of external components and can operate
from a single 4.5 V to 17 V supply. It can deliver 8.4 W of output
power into an 8 Ω load or 15.8 W into an 4 Ω load from a 12 V
power supply, or 31.3 W into an 4 Ω load from a 17 V power
supply, all with 1% THD + N.
I2C control with up to 4 pin selectable slots/addresses
Supports multiple serial data formats up to TDM16
Digital interface supports sample rates from 8 kHz to 192 kHz
Flexible digital and analog gain adjustment
Flexible supply monitoring AGC function
6.55 mA quiescent current with single 17 V PVDD supply
Short-circuit and thermal protection, thermal warning
20-ball, 1.8 mm × 2.2 mm, 0.4 mm pitch WLCSP
Pop and click suppression
The SSM3515 features a high efficiency, low noise modulation
scheme that requires no external LC output filters. This scheme
provides high efficiency even at low output power. It operates
with 92% efficiency at 7 W into an 8 Ω load or 88% efficiency at
15 W into 4 Ω from a 12 V supply.
Spread spectrum pulse density modulation provides lower EMI
radiated emissions compared with other Class-D architectures,
particularly above 100 MHz.
User selectable ultralow EMI emissions mode
Power-on reset
The digital input eliminates the need for an external digital-to-
analog converter (DAC). The SSM3515 has a micropower
shutdown mode with a typical shutdown current of 39 nA at
the 12 V PVDD supply. The device also includes pop and click
suppression circuitry that minimizes voltage glitches at the
output during turn on and turn off.
APPLICATIONS
Notebooks
Portable electronics
Home audio
The SSM3515 operates with or without an I2C control interface.
The SSM3515 is specified over the commercial temperature range
(−40C to +85C). It has built in thermal shutdown and output
short-circuit protection. It is available in a halide-free, 20-ball,
1.8 mm × 2.2 mm wafer-level chip scale package (WLCSP).
FUNCTIONAL BLOCK DIAGRAM
5V
1.8V
VREG50/AVDD VREG18/DVDD
AGND
REG_EN
ADDR
BST+
SCL
SDA
2
I C
BCLK
FSYNC
SDATA
FULL
BRIDGE
POWER
STAGE
Σ-∆
TDM
2
DAC
OUT+
OUT–
CLASS-D
VOLUME
I S
MODULATOR
INPUT
BST–
SSM3515
PVDD
PGND
Figure 1.
Rev. A
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Tel: 781.329.4700 ©2015–2017 Analog Devices, Inc. All rights reserved.
Technical Support
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SSM3515
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
EMI Noise.................................................................................... 24
Output Modulation Description .............................................. 24
Faults and Limiter Status Reporting ........................................ 25
VBAT Sensing............................................................................. 25
Limiter and Battery Tracking Threshold Control.................. 25
Layout .......................................................................................... 28
Bootstrap Capacitors.................................................................. 28
Power Supply Decoupling ......................................................... 28
Register Summary .......................................................................... 29
Register Details ............................................................................... 30
Power Control Register ............................................................. 30
Gain and Edge Control Register............................................... 30
DAC Control Register................................................................ 31
DAC Volume Control Register................................................. 32
SAI Control 1 Register............................................................... 33
SAI Control 2 Register............................................................... 34
Battery Voltage Output Register............................................... 35
Limiter Control 1 Register ........................................................ 35
Limiter Control 2 Register ........................................................ 36
Limiter Control 3 Register ........................................................ 37
Status Register............................................................................. 37
Fault Control Register................................................................ 38
Typical Application Circuit........................................................... 40
Outline Dimensions....................................................................... 41
Ordering Guide .......................................................................... 41
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Digital Timing Characteristics ................................................... 6
Absolute Maximum Ratings............................................................ 8
Thermal Resistance ...................................................................... 8
ESD Caution.................................................................................. 8
Pin Configuration and Function Descriptions............................. 9
Typical Performance Characteristics ........................................... 10
Theory of Operation ...................................................................... 19
Overview...................................................................................... 19
Power Supplies ............................................................................ 19
Power-Up Sequence ................................................................... 19
Power-Down Operation ............................................................ 19
REG_EN Pin Setup and Control.............................................. 19
ADDR Pin Setup and Control .................................................. 20
Clocking....................................................................................... 20
Digital Audio Serial Interface ....................................................... 21
Stereo (I2S/Left Justified) Operating Mode............................. 21
TDM Operating Mode............................................................... 21
I2C Control .................................................................................. 21
Analog and Digital Gain............................................................ 24
Pop and Click Suppression........................................................ 24
REVISION HISTORY
1/2017—Rev. 0 to Rev. A
Changes to Figure 2 and Table 5..................................................... 6
6/2015—Revision 0: Initial Version
Rev. A| Page 2 of 41
Data Sheet
SSM3515
SPECIFICATIONS
PVDD = 12 V, VREG50/AVDD = 5 V (internal), VREG18/DVDD = 1.8 V (external), RL = 8 Ω + 33 μH, BCLK = 3.072 MHz and FSYNC =
48 kHz, TA = −40°C to +85°C, unless otherwise noted. The measurements are with a 20 kHz AES17 low-pass filt er. The other load
impedances used are 4 Ω + 15 μH and 3 Ω +10 μH. Measurements are with a 20 kHz AES17 low-pass filter, unless otherwise noted.
The sine wave output powers above 20 W in 4 Ω cannot be continuous and may invoke the thermal limit indicator based on the power
dissipation capability of the board.
Table 1.
Parameter
Symbol
Test Conditions/Comments
Min
Typ
Max
Unit
DEVICE CHARACTERISTICS
Output Power/Channel
RL = 8 Ω
POUT
f = 1 kHz
THD + N = 1%, PVDD = 17 V
THD + N = 1%, PVDD = 12 V
THD + N = 1%, PVDD = 7 V
16
8.4
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
%
%
%
%
%
2.8
1.4
19.7
10.5
3.5
THD + N = 1%, PVDD = 5 V
THD + N = 10%, PVDD = 17 V
THD + N = 10%, PVDD = 12 V
THD + N = 10%, PVDD = 7 V
THD + N = 10%, PVDD = 5 V
THD + N = 1%, PVDD = 17 V
THD + N = 1%, PVDD = 12 V
THD + N = 1%, PVDD = 7 V
1.8
RL = 4 Ω
31.3
15.8
5.4
THD + N = 1%, PVDD = 5 V
2.8
THD + N = 10%, PVDD = 17 V
THD + N = 10%, PVDD = 12 V
THD + N = 10%, PVDD = 7 V
THD + N = 10%, PVDD = 5 V
POUT = 9 W, RL = 8 Ω, PVDD = 12 V
POUT = 9 W, RL = 8 Ω, PVDD = 12 V (low EMI mode)
POUT = 30 W, RL = 4 Ω, PVDD = 17 V
POUT = 30 W, RL = 4 Ω, PVDD = 17 V (low EMI mode)
POUT = 5 W into RL = 8 Ω, f = 1 kHz, PVDD = 16 V
39.3
19.7
6.7
3.4
Efficiency
η
93.3
93.2
88
87.8
0.004
Total Harmonic
THD + N
Distortion + Noise
Load Resistance
Load Inductance
3
5
Ω
μH
10
Output FET On Resistance RON
110
mΩ
A peak
Overcurrent Protection
Trip Point
IOC
5.8
Average Switching
Frequency
Differential Output DC
Offset Voltage
fSW
300
1
kHz
mV
VOOS
Gain = 12.6 V
5.0
POWER SUPPLIES
Supply Voltage Range
PVDD
Guaranteed from PSRR test
Internal
4.5
4.5
17
V
V
VREG50/AVDD
VREG18/DVDD
PSRRAC
5.0
1.80
87
5.5
1.98
73
Internal or external
VRIPPLE = 1 V rms at 1 kHz
1.62
V
dB
AC Power Supply
Rejection Ratio
GAIN CONTROL
Measured with 0 dBFS input at 1 kHz
Output Voltage Peak
Analog gain setting = 8.4 V/V with PVDD = 17 V
Analog gain setting = 12.6 V/V with PVDD = 17 V
Analog gain setting = 14.0 V/V with PVDD = 17 V
Analog gain setting = 15.0 V/V with PVDD = 17 V
8.4
12.6
14
V peak
V peak
V peak
V peak
15
Rev. A| Page 3 of 41
SSM3515
Data Sheet
Parameter
Symbol
Test Conditions/Comments
Min
Typ
Max
Unit
SHUTDOWN CONTROL1
Tur n On Time, Volume
Ramp Disabled
Time from SPWDN = 0 to output switching,
DAC_HV = 1 or DAC_MUTE = 1, tWU = 4 FSYNC
cycles to 7 FSYNC cycles + 7.68 ms
tWU
fS = 12 kHz
fS = 24 kHz
fS = 48 kHz
fS = 96 kHz
8.01
7.84
7.76
7.72
7.70
8.27
7.98
7.83
7.76
7.72
ms
ms
ms
ms
ms
fS = 192 kHz
Tur n On Time, Volume
Ramp Enabled
Time from SPWDN = 0 to full volume output
switching, DAC_HV = 0 and DAC_MUTE = 0,
VOL = 0x40
tWUR
fS = 12 kHz
fS = 24 kHz
fS = 48 kHz
fS = 96 kHz
fS = 192 kHz
Tur n Off Time, Volume
Ramp Disabled
tWUR = tWU + 15.83 ms
tWUR = tWU + 15.83 ms
tWUR = tWU + 15.83 ms
tWUR = tWU + 7.92 ms
tWUR = tWU + 0.99 ms
Time from SPWDN = 1 to full power-down,
DAC_HV = 1 or DAC_MUTE = 1
23.84
23.67
23.59
15.64
8.69
24.10
23.81
23.66
15.68
8.71
ms
ms
ms
ms
ms
µs
tSD
100
Tur n O ff Time, Volume
Ramp Enabled
Time from SPWDN = 1 to full power-down,
DAC_HV = 0 and DAC_MUTE = 0, VOL = 0x40
tSDR
fS = 12 kHz
fS = 24 kHz
fS = 48 kHz
tSDR = tSD + 15.83 ms
tSDR = tSD + 15.83 ms
tSDR = tSD + 15.83 ms
tSDR = tSD + 7.92 ms
tSDR = tSD + 0.99 ms
15.932
15.932
15.932
8.016
1.09
ms
ms
ms
ms
ms
kΩ
fS = 96 kHz
fS = 192 kHz
Output Impedance
NOISE PERFORMANCE2
Output Voltage Noise
ZOUT
en
100
f = 20 Hz to 20 kHz, A-weighted, PVDD = 12 V
f = 20 Hz to 20 kHz, A-weighted, PVDD = 17 V
POUT = 8.2 W, RL = 8 Ω, A-weighted, PVDD = 12 V
POUT = 31 W, RL = 4 Ω, A-weighted, PVDD = 17 V
37.5
48
107
107
µV rms
µV rms
dB
Signal-to-Noise Ratio
SNR
dB
PVDD ADC PERFORMANCE
PVDD Sense Full-Scale
Range
PVDD Sense Absolute
Accuracy
PVDD with full-scale ADC out
PVDD = 15 V
3.8
−8
−6
16.2
+8
V
LSB
PVDD = 5 V
Unsigned 8-bit output with 3.8 V offset
+6
LSB
Bits
Resolution
8
DIE TEMPERATURE
Overtemperature
Warning
Overtemperature
Protection
117
145
°C
°C
1 Guaranteed by design.
2 Noise performance is based on the bench data for TA = −40°C to +85°C.
Rev. A| Page 4 of 41
Data Sheet
SSM3515
Software master power-down indicates that the clocks are turned off. Auto power-down indicates that there is no dither or zero input
signal with clocks on; the device enters soft power-down after2048 cyclesof zero input values. Quiescent indicates triangular dither with
zero input signal. All specifications are typical, with a 48 kHz sample rate, unless otherwise noted.
Table 2. Power Supply Current Consumption1
No Load
IPVDD
12 V 17 V 1.8 V 5 V
4 Ω + 15 µH
IPVDD
8 Ω + 33 µH
IPVDD
Edge Rate
Control
Mode
Test Conditions
REG_EN Pin PVDD
IR EG18
IR EG18
IR EG18
5 V
12 V 17 V 1.8 V 5 V
12 V 17 V 1.8 V Unit
Normal
Low
Software master
power-down
0.01
0.03
0.03
7
0.01
0.03
0.03
7
0.01
0.03
0.03
7
μA
Auto power-down
Quiescent
0.01
4.10
0.01
0.03
5.00
0.03
0.03
5.60
0.03
54
0.01
4.10
0.01
0.03
5.12
0.03
0.03
5.90
0.03
54
0.01
4.10
0.01
0.03
5.10
0.03
0.03
5.80
0.03
54
μA
mA
μA
0.48
N/A
0.48
N/A
0.48
N/A
PVDD
Low
Software master
power-down
Auto power-down
310
4.64
0.01
310
5.60
0.03
316
6.26
0.03
N/A
N/A
7
310
4.74
0.01
310
5.85
0.03
316
6.55
0.03
N/A
N/A
7
310
4.74
0.01
310
5.85
0.03
316
6.55
0.03
N/A
N/A
7
μA
mA
μA
Quiescent
Low EMI
Software master
power-down
Auto power-down
Quiescent
0.01
4.00
0.03
4.95
0.03
5.54
54
0.48
0.01
4.70
0.03
3.99
0.03
5.59
54
0.48
0.01
4.02
0.03
4.98
0.03
5.63
54
0.48
μA
mA
PVDD
Software master
power-down
0.01
0.03
0.03
N/A
0.01
0.03
0.03
N/A
0.01
0.03
0.03
N/A
μA
Auto power-down
Quiescent
310
310
316
N/A
N/A
310
310
316
N/A
N/A
310
310
316
N/A
N/A
μA
4.60
5.60
6.17
4.60
5.65
6.35
4.60
5.60
6.40
mA
1 N/A means not applicable.
Table 3. Power-Down Current
Parameter
Symbol Test Conditions/Comments
Min Typ Max Unit
POWER-DOWN CURRENT
VREG18/DVDD = 1.8 Vexternal, softwar e master power-down, no BCLK/FSYNC
IPVDD
PVDD = 5 V
PVDD = 12 V
PVDD = 17 V
VREG18/DVDD = 1.8 V external
27
30
30
38
39
39
7
95
nA
100 nA
152 nA
27
IDVDD
μA
Table 4. Digital Input/Output
Parameter
Min
Typ
Max
Unit
Test Comments/Comments
INPUT VOLTAGE1
High (VIH)
BCLK, FSYNC, SCL, SDA
SDATA, ADDR
1.13
5.5
1.98
V
V
0.7 × VREG18/DVDD
Low (VIL)
BCLK, FSYNC, SDATA, SCL, SDA
ADDR
−0.3
−0.3
+0.54
+1.98
V
V
INPUT LEAKAGE
High (IIH)
Low (IIL)
INPUT CAPACITANCE
OUTPUT VOLTAGE (SDATA)
1
1
5
µA
µA
pF
High (VOH
Low (VOL)
)
1.17
V
V
0.45
OUTPUT DRIVE STRENGTH1
SDA
SDATA
BCLK Frequency (BCLK)
Sample Rate (FSYNC)
3
2
5
24
24.576
192
mA
mA
MHz
kHz
2.048
8
1 The pull-up resistor for SCL and SDA must be scaled according to the external pull-up voltage in the system. The typical value for a pull-up resistor for 1.8 V is 2.2 kΩ.
Rev. A| Page 5 of 41
SSM3515
Data Sheet
DIGITAL TIMING CHARACTERISTICS
All timing specifications are given for the default setting (I2S mode) of the serial input port.
Table 5. I2C Port Timing
Limit
Parameter
I2C PORT
fSCL
tSCLH
tSCLL
tSCS
Min
Max
Unit
Description
400
kHz
µs
µs
µs
µs
ns
ns
ns
ns
ns
µs
ns
ns
SCL frequency
SCL high
SCL low
Setup time; relevant for repeated start condition
Hold time; after this period, the first clock is generated
Data setup time
SCL rise time
SCL fall time
0.6
1.3
0.6
0.6
100
tSCH
tDS
tSCR
tSCF
300
300
300
300
tR
tF
tBFT
tHOLD
SDA rise time, not shown in Figure 2
SDA fall time, not shown in Figure 2
Bus-free time (time between stop and start)
SCL falling to SDA rising
SCL falling to SDA falling
0.6
0
140
Table 6. Digital Input Timing
Limit
TMAX
Parameter
TMIN
Unit
Description
SERIAL PORT
tBIL
tBIH
tSIS
tSIH
tLIS
tLIH
tBP
15
15
6
ns
ns
ns
ns
ns
ns
ns
BCLK low pulse width
BCLK high pulse width
SDATA se t up, time to BCLK rising
SDATA ho l d, time from BCLK rising
FSYNC setup time to BCLK rising
FSYNC hold time to BCLK rising
Minimum BCLK period
6
10
5
40
Digital Timing Diagrams
tDS
tSCH
tSCH
SDA
tSCLH
tSCS
tSCR
SCL
tSCLL
tSCF
tHOLD
tBFT
START
CONDITION
STOP
CONDITION
Figure 2. I2C Port Timing
Rev. A| Page 6 of 41
Data Sheet
SSM3515
tBIH
tBP
BCLK
tBIL
tLIS
tLIH
FSYNC
tSIS
SDATA
LEFT-JUSTIFIED
MODE
MSB
tSIH
MSB – 1
tSIS
MSB
tSIH
SDATA
2
I C-JUSTIFIED
MODE
tSIS
tSIS
LSB
SDATA
RIGHT-JUSTIFIED
MODE
MSB
tSIH
tSIH
Figure 3. Serial Input Port Timing
PVDD
tWU
PVDD/2
OUTPUT
0V
2
I C POWER-UP COMMAND
Figure 4. Turn On Hard Volume
tSD
PVDD
OUTPUT
0V
2
I C POWER-DOWN COMMAND
Figure 5. Turn Off Hard Volume
Rev. A| Page 7 of 41
SSM3515
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Absolute maximum ratings apply at TA = 25°C, unless otherwise
noted.
THERMAL RESISTANCE
θJA (junction to air) is specified for worst case conditions, that is,
a device soldered in a circuit board for surface-mount packages. θJA
and θJB are determined according to JESD51-9 on a 4-layer
printed circuit board (PCB) with natural convection cooling.
Table 7.
Parameter
Rating
PVDD Supply Voltage
−0.3 V to +18 V
−0.3 V to +1.98 V
−0.3 V to +5.5 V
0.3 V
−0.3 V to +1.98 V
−0.3 V to +5.5 V
−0.3 V to +18 V
−65°C to +150°C
−40°C to +85°C
−65°C to +165°C
300°C
VREG18/DVDD Supply Voltage
VREG50/AVDD Supply Voltage
PGND and AGND Differential
ADDR, SDATA Input Voltage
SCL, SDA, BCLK, FSYNC Input Voltage
REG_EN Input Voltage
Storage Temperature Range
Operating Temperature Range
Junction Temperature Range
Table 8. Thermal Resistance
Package Type
θJA
Unit
20-Ball, 1.8 mm × 2.2 mm WLCSP
55.5
°C/W
ESD CAUTION
Lead Temperature Range
(Soldering, 60 sec)
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Rev. A| Page 8 of 41
Data Sheet
SSM3515
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
VREG50/
AVDD
A
AGND
PGND
BST–
SDA
SCL
ADDR
REG_EN
FSYNC
BCLK
OUT–
B
OUT–
PVDD
OUT+
PGND
C
D
PVDD
OUT+
BST+
VREG18/
DVDD
E
SDATA
Figure 6. Pin Configuration (Top Side View)
Table 9. Pin Function Descriptions
Pin No. Mnemonic
Type1 Description
VREG50/AVDD AOUT 5 V Regulator Output.
A1
A2
A3
AGND
PGND
PWR
PWR
Analog Ground. It is recommended to connect the AGND pin to a single ground plane on the board.
Power Stage Ground. The PGND pin is shorted internally. It is recommended to connect PGND to a
single ground plane on the board.
A4
B1
B2
B3
B4
C1
C2
C3
C4
D1
D2
D3
D4
E1
E2
E3
BST−
SDA
ADDR
OUT−
OUT−
SCL
REG_EN
PVDD
PVDD
AIN
DIO
DIN
Bootstrap Capacitor for OUT−.
I2C Serial Data.
I2C Address Selection.
AOUT Power Stage Inverting Output.
AOUT Power Stage Inverting Output.
DIN
AIN
PWR
PWR
I2C Clock.
Regulator Enable Tie to PVDD to Enable Regulators.
Power Stage Supply.
Power Stage Supply.
1.8 V Regulator Output/DVDD Input.
TDM Frame Sync Input.
VREG18/DVDD PWR
FSYNC
OUT+
OUT+
SDATA
BCLK
DIN
AOUT Power Stage Noninverting Output.
AOUT Power Stage Noninverting Output.
DIO
DIN
PWR
Serial Data Input to DAC.
TDM Bit Clock Input.
Power Stage Ground. The PGND pin is shorted internally. It is recommended to connect PGND to a
single ground plane on the board.
PGND
E4
BST+
AIN
Bootstrap Capacitor for OUT+.
1 AOUT is analog output; PWR is power supply or ground pin; AIN is analog input; DIO is digital input/output; DIN is digital input.
Rev. A| Page 9 of 41
SSM3515
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
20
10
20
10
0
0
–10
–10
–20
–20
–30
–30
–40
–40
–50
–50
–60
–60
–70
–70
–80
–80
–90
–90
–100
–110
–120
–130
–140
–150
–160
–170
–180
–100
–110
–120
–130
–140
–150
–160
–170
–180
20
100
1k
10k
20
100
1k
10k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 7. Fast Fourier Transform (FFT), 60 dBFS Input, Analog Gain = 8.4,
RL = 4 Ω
Figure 10. FFT, 60 dBFS Input, Analog Gain = 15, RL = 4 Ω
20
10
0
20
10
0
–10
–10
–20
–20
–30
–30
–40
–40
–50
–50
–60
–60
–70
–70
–80
–80
–90
–90
–100
–110
–120
–130
–140
–150
–160
–170
–180
–100
–110
–120
–130
–140
–150
–160
–170
–180
20
100
1k
10k
20
100
1k
10k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 8. FFT, 60 dBFS Input, Analog Gain = 12.6, RL = 4 Ω
Figure 11. FFT, No Signal, Analog Gain = 8.4, RL = 4 Ω
20
10
0
20
10
0
–10
–10
–20
–20
–30
–30
–40
–40
–50
–50
–60
–60
–70
–70
–80
–80
–90
–90
–100
–110
–120
–130
–140
–150
–160
–170
–180
–100
–110
–120
–130
–140
–150
–160
–170
–180
20
100
1k
10k
20
100
1k
10k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 9. FFT, 60 dBFS Analog Gain = 14, RL = 4 Ω
Figure 12. FFT, No Signal, Analog Gain =12.6, RL = 4 Ω
Rev. A| Page 10 of 41
Data Sheet
SSM3515
20
10
0
1
100mW
1W
5W
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
–140
–150
–160
–170
0.1
0.01
0.001
–180
20
100
1k
10k
20
100
1k
10k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 13. FFT, No Signal, Analog Gain = 14, RL = 4 Ω
Figure 16. THD + N vs. Frequency, RL = 4 Ω, PVDD = 12 V
1
20
10
0
100mW
1W
10W
–10
–20
–30
–40
–50
0.1
–60
–70
–80
–90
–100
–110
–120
–130
–140
–150
–160
–170
–180
0.01
0.001
20
100
1k
10k
20
100
1k
10k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 14. FFT, No Signal, Analog Gain = 15, RL = 4 Ω
Figure 17. THD + N vs. Frequency, RL = 4 Ω, PVDD = 17 V
1
1
100mW
1W
100mW
1W
0.1
0.1
0.01
0.01
0.001
0.001
20
100
1k
10k
20
100
1k
10k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 15. THD + N vs. Frequency into RL = 4 Ω, PVDD = 4.5 V
Figure 18. THD + N vs. Frequency, RL = 8 Ω, PVDD = 4.5 V
Rev. A| Page 11 of 41
SSM3515
Data Sheet
1
10
1
100mW
1W
5W
4.5V
12V
17V
0.1
0.01
0.1
0.01
0.001
0.001
20
100
1k
10k
10µ
100µ
1m
10m
100m
1
10
FREQUENCY (Hz)
POWER (W)
Figure 19. THD + N vs. Frequency, RL = 8 Ω, PVDD = 12 V
Figure 22. THD + N vs. Output Power, RL = 4 Ω, Analog Gain = 12.6
10
1
4.5V
14V
17V
100mW
1W
5W
1
0.1
0.1
0.01
0.01
0.001
0.001
10µ
100µ
1m
10m
100m
1
10
20
100
1k
10k
POWER (W)
FREQUENCY (Hz)
Figure 20. THD + N vs. Frequency, RL = 8 Ω, PVDD = 17 V
Figure 23. THD + N vs. Output Power, RL = 4 Ω, Analog Gain = 14
10
1
10
8V
4.5V
17V
4.5V
15V
17V
1
0.1
0.1
0.01
0.01
0.001
0.001
10µ
100µ
1m
10m
100m
1
10
10µ
100µ
1m
10m
100m
1
10
POWER (W)
POWER (W)
Figure 21. THD + N vs. Output Power, RL = 4 Ω, Analog Gain = 8.4
Figure 24. THD + N vs. Output Power, RL = 4 Ω, Analog Gain = 15
Rev. A| Page 12 of 41
Data Sheet
SSM3515
10
10
1
4.5V
14V
17V
4.5V
15V
17V
1
0.1
0.1
0.01
0.001
0.01
0.001
10µ
100µ
1m
10m
100m
1
10
10µ
100µ
1m
10m
100m
1
10
POWER (W)
POWER (W)
Figure 25. THD + N vs. Output Power, RL = 8 Ω, Analog Gain = 8.4
Figure 28. THD + N vs. Output Power, RL = 8 Ω, Analog Gain = 15
14
10
4.5V
12V
14V
P
P
10%, 8V GAIN
1%, 8V GAIN
OUT
OUT
12
10
8
1
0.1
6
4
0.01
0.001
2
0
10µ
100µ
1m
10m
100m
1
10
5
6
7
8
9
10
11
12
13
14
POWER (W)
PV (V)
DD
Figure 26. THD + N vs. Output Power, RL = 8 Ω, Analog Gain = 12.6
Figure 29. Output Power vs. PVDD Supply Voltage (PVDD), RL = 4 Ω,
Analog Gain = 8.4
10
30
4.5V
14V
16V
P
P
10%
1%
OUT
OUT
25
20
15
10
5
1
0.1
0.01
0.001
10µ
100µ
1m
10m
100m
1
10
0
5
6
7
8
9
10 11 12 13 14 15 16 17
PV (V)
POWER (W)
DD
Figure 30. Output Power vs. PVDD, RL = 4 Ω, Analog Gain = 12.6
Figure 27. THD + N vs. Output Power, RL = 8 Ω, Analog Gain = 14
Rev. A| Page 13 of 41
SSM3515
Data Sheet
35
100
90
80
70
60
50
40
30
20
10
0
P
P
10%
1%
OUT
OUT
30
25
20
15
10
5
5V FB NORMAL
5V FB LOW
0
5
6
7
8
9
10 11 12 13 14 15 16 17
PV (V)
0
0.5
1.0
1.5
2.0
2.5
(W)
OUT
3.0
3.5
4.0
4.5
5.0
P
DD
Figure 31. Output Power vs. PVDD, RL = 4 Ω, Analog Gain = 14
Figure 34. Efficiency vs. POUT, RL = 4 Ω, FB and 220 pF Capacitor, PVDD = 5 V,
Analog Gain = 8.4
40
35
30
100
90
80
70
60
50
40
30
20
P
P
10%
1%
OUT
OUT
25
20
15
10
5
10
12V NO FB NORMAL
12V NO FB LOW
0
0
5
6
7
8
9
10 11 12 13 14 15 16 17
0
5
10
15
20
25
PV (V)
DD
P
(W)
OUT
Figure 32. Output Power vs. PVDD, RL = 4 Ω, Analog Gain = 15
Figure 35. Efficiency vs. POUT, RL = 4 Ω, No FB and 220 pF, PVDD = 12 V,
Analog Gain = 12.6
100
100
90
80
70
60
50
40
30
20
90
80
70
60
50
40
30
20
10
0
10
5V NO FB NORMAL
5V NO FB LOW
12V FB NORMAL
12V FB LOW
0
0
0.5
1.0
1.5
2.0
2.5
(W)
3.0
3.5
4.0
4.5
5.0
0
5
10
15
20
25
P
P
(W)
OUT
OUT
Figure 33. Efficiency vs. Output Power (POUT), RL = 4 Ω, No Ferrite Bead (FB)
and 220 pF Capacitor, PVDD = 5 V, Analog Gain = 8.4
Figure 36. Efficiency vs. POUT, RL = 4 Ω, FB and 220 pF Capacitor, PVDD = 12 V,
Analog Gain = 12.6
Rev. A| Page 14 of 41
Data Sheet
SSM3515
100
90
80
70
60
50
40
30
20
10
0
0.010
0.009
0.008
0.007
0.006
0.005
0.004
0.003
0.002
0.001
0
4Ω + 15µH FB 220pF LOW MODE
4Ω + 15µH FB 220pF NORMAL MODE
17V FB NORMAL
17V FB LOW
5
7
9
11
13
15
17
19
0
5
10
15
20
25
30
35
40
P
(W)
PV (V)
OUT
DD
Figure 37. Efficiency vs. POUT, RL = 4 Ω, FB and 220 pF Capacitor, PVDD = 17 V,
Analog Gain = 14
Figure 40. Quiescent Current, RL = 4 Ω, FB and 220 pF Capacitor,
Analog Gain = 12
100
90
80
70
60
50
40
30
20
7
P
P
10%
1%
OUT
OUT
6
5
4
3
2
1
0
10
17V NO FB NORMAL
17V NO FB LOW
0
5
6
7
8
9
10
11
12
13
14
0
5
10
15
20
25
30
35
40
45
P
(W)
PV (V)
OUT
DD
Figure 38. Efficiency vs . PO UT , RL = 4 Ω, No FB and 220 pF Capacitor, PVDD = 17 V,
Analog Gain = 14
Figure 41. Output Power vs. PVDD, RL = 8 Ω, Analog Gain = 8
14
12
10
8
0.007
P
P
10%
1%
NO LOAD NO FB NORMAL MODE
NO LOAD NO FB LOW MODE
OUT
OUT
0.006
0.005
0.004
0.003
0.002
0.001
0
6
4
2
0
5.0
7.5
10
12.5
5
7
9
11
13
15
17
PV (V)
DD
PV (V)
DD
Figure 39. Quiescent Current, RL = 4 Ω, No FB and 220 pF Capacitor,
Analog Gain = 12
Figure 42. Output Power vs. PVDD, RL = 8 Ω, Analog Gain = 12
Rev. A| Page 15 of 41
SSM3515
Data Sheet
100
90
80
70
60
50
40
30
20
10
0
18
P
P
10%
1%
OUT
OUT
16
14
12
10
8
6
4
2
NORMAL NO FB/220pF
LOW NO FB/220pF
0
0
2
4
6
8
10
12
5
10
PV (V)
15
P
(W)
OUT
DD
Figure 43. Output Power vs. PVDD, RL = 8 Ω, Analog Gain = 14
Figure 46. Efficiency vs. POUT, RL = 8 Ω, No FB and 220 pF Capacitor,
PVDD = 12 V, Analog Gain = 12.6
20
100
17V NO FB NORMAL
17V NO FB LOW
P
P
10%
1%
OUT
OUT
80
15
10
5
60
40
20
0
0
5
10
PV (V)
15
0
5
10
15
20
P
(W)
DD
OUT
Figure 44. Output Power vs. PVDD, RL = 8 Ω, Analog Gain = 15
Figure 47. Efficiency vs. POUT, RL = 8 Ω, No FB and 220 pF Capacitor,
PVDD = 17 V, Analog Gain = 14
100
90
80
70
60
50
40
30
20
100
5V NO FB NORMAL
5V NO FB LOW
80
60
40
20
0
10
5V NO FB NORMAL
5V NO FB LOW
0
0
1
2
3
0
1
2
3
P
(W)
P
(W)
OUT
OUT
Figure 45. Efficiency vs. POUT, RL = 8 Ω, No FB and 220 pF Capacitor,
PVDD = 5 V, Analog Gain = 8.4
Figure 48. Efficiency vs. POUT, RL = 8 Ω, FB and 220 pF Capacitor,
PVDD = 5 V, Analog Gain = 8.4
Rev. A| Page 16 of 41
Data Sheet
SSM3515
100
90
80
70
60
50
40
30
20
10
0
100
80
60
40
20
0
12V NO FB NORMAL
12V NO FB LOW
NORMAL FB/220pF
LOW FB/220pF
0
2
4
6
8
10
12
14
0
10
20
30
P
(W)
P
(W)
OUT
OUT
Figure 49. Efficiency vs. POUT, RL = 8 Ω, FB and 220 pF Capacitor,
PVDD = 12 V, Analog Gain = 12.6
Figure 52. Efficiency vs. POUT, RL = 3 Ω, No FB and 220 pF Capacitor,
PVDD = 12 V, Analog Gain = 12.6
100
100
17V FB LOW
17V FB NORMAL
17V NO FB NORMAL
17V NO FB LOW
80
80
60
40
20
0
60
40
20
0
0
5
10
15
20
0
5
10
15
20
25
30
35
40
45
50
P
(W)
P
(W)
OUT
OUT
Figure 50. Efficiency vs. POUT, RL = 8 Ω, FB and 220 pF Capacitor, PVDD = 17 V,
Analog Gain = 14
Figure 53. Efficiency vs. POUT, RL = 3 Ω, No FB and 220 pF Capacitor,
PVDD = 17 V, Analog Gain = 14
100
80
60
40
20
100
5V FB NORMAL
5V FB LOW
80
60
40
20
0
5V NO FB NORMAL
5V NO FB LOW
0
0
2
4
6
0
2
4
6
P
(W)
P
(W)
OUT
OUT
Figure 51. Efficiency vs. POUT, RL = 3 Ω, No FB and 220 pF Capacitor,
PVDD = 5 V, Analog Gain = 8.4
Figure 54. Efficiency vs. POUT, RL = 3 Ω, FB and 220 pF Capacitor, PVDD = 5 V,
Analog Gain = 8.4
Rev. A| Page 17 of 41
SSM3515
Data Sheet
100
40
35
30
25
20
15
10
5
12V FB NORMAL
12V FB LOW
P
P
10%
1%
OUT
OUT
80
60
40
20
0
0
0
10
20
30
8
10
12
14
P
(W)
PV (V)
DD
OUT
Figure 55. Efficiency vs. POUT, RL = 3 Ω, FB and 220 pF Capacitor, PVDD = 12 V,
Analog Gain = 12.6
Figure 58. Output Power vs. PVDD, RL = 3 Ω, Analog Gain = 12.6
100
50
17V FB LOW
17V FB NORMAL
P
P
10%
1%
OUT
OUT
80
60
40
20
0
40
30
20
10
0
0
5
10
15
20
25
30
35
40
45
50
5
10
15
P
(W)
PV (V)
OUT
DD
Figure 56. Efficiency vs. POUT,, RL = 3 Ω, FB and 220 pF Capacitor, PVDD = 17 V,
Analog Gain = 14
Figure 59. Output Power vs. PVDD, RL = 3 Ω, Analog Gain = 14
18
50
P
P
10%
1%
P
P
10%
1%
OUT
OUT
OUT
OUT
16
14
12
10
8
40
30
20
10
0
6
4
2
0
5
6
7
8
9
10
11
12
13
14
5
10
15
PV (V)
PV (V)
DD
DD
Figure 57. Output Power vs. PVDD, RL = 3 Ω, Analog Gain = 8.4
Figure 60. Output Power vs. PVDD, RL = 3 Ω, Analog Gain = 15
Rev. A| Page 18 of 41
Data Sheet
SSM3515
THEORY OF OPERATION
OVERVIEW
POWER-UP SEQUENCE
The SSM3515Class-D audio amplifier features a filterless
modulation scheme that greatlyreduces the external component
count, conserving board space and reducing system cost. The
SSM3515 does not require an output filter; it relies on the
inherent inductance of the speaker coil and the natural filtering
of the speaker and human ear to recover the audio component
of the square wave output.
If the REG_EN pin is tied to PVDD, the power-up sequence is
performed internally. As the PVDD voltage ramps up, the
VREG18/DVDD voltage (generated internally) also ramps up.
The typical wait time before the I2C commands can be sent to
the device depends on the PVDD supply ramp-up time.
If the REG_EN pin is tied low, ensure that 1.8 V is supplied
externally and that PVDD is greater than 4.5 V before sending
I2C commands to enable the device.
Most Class-D amplifiers use some variation of pulse-width
modulation (PWM), but the SSM3515 uses Σ-Δ modulation to
determine the switching pattern of the output devices, resulting
in a number of importantbenefits.Σ-Δ modulators do notproduce
a sharp peak with many harmonics in the AM broadcast band, as
pulse-width modulators often do. Σ-Δ modulation reduces the
amplitude of spectral components at high frequencies, reducing
EMI emission that may otherwise be radiated by speakers and
long cable traces. Due to the inherent spread spectrum nature of
Σ-Δ modulation,the need for oscillator synchronization is elimi-
nated for designs incorporatingmultiple SSM3515 amplifiers.
POWER-DOWN OPERATION
The SSM3515offers several power down options via I2C.
Register 0x00 provides multiple options for setting the various
power-down modes.
Set the SPWDN bit to 1 to fully power down the device. Only
the I2C, 1.8 V regulator is kept alive.
The SSM3515monitors both the BCLK and FSYNC pins for clock
presence when in 2-wire mode. When no BCLK or FSYNCsignals
are present, the device automatically powers down all internal
circuitry to its lowest power state. When a BCLK or FSYNC
signal returns, the device automatically powers up following
its usual power up sequence.
The SSM3515also integrates overcurrent and temperature
protection and a thermal warning with optional programmable
gain reduction.
POWER SUPPLIES
When enabled, the APWDN_EN bit (auto power down),
activatesa low power state as soon as 2048 consecutive zero
input samples are received. Only the I2C and digital audio input
blocks are kept active.
The power supply pins on the SSM3515 are PVDD, VREG50/
AVDD, and VREG18/DVDD.
PVDD, the battery supply, is used for the output stage and also
supplies power to the 5 V reg ulat or. In addition, it can be used
to supply power to the 1.8 V reg ulat or. This pin must be
decoupled to ground using a 100 nF capacitor in parallel with a
1 µF MLCC capacitor to ground as close as possible to the
respective pins. In addition, a bulk electrolytic capacitor maybe
required depending onthe output power to supplythe current at
low frequency output. Typically, 220µF and 25 V is
REG_EN PIN SETUP AND CONTROL
The REG_EN (regulator enable) pin enables or disables the
internal 1.8 V reg ulat or.
Table 10. Regulator Enable Pin Function
REG_EN
Ground
PVDD
1.8 V Regulator
Comment
Disabled
External 1.8 V
Internal 1.8 V
Enabled
recommended. This must be sized according to the power
supply regulation in the system.
The status of the REG_EN pin determines if the 1.8 V supply is
generated internally or if it must be provided externally. If the
REG_EN pin is tied to PVDD, the internal 1.8 V regulator is
enabled. If the REG_EN pin is tied to ground, a 1.8 V supply
must be supplied externally to the VREG18/DVDD pin for the
device to operate. For the device to respond to I2C commands,
the 1.8 V supply must be stable.
VREG50/AVDD (5 V) is the analog supply used for the input
stage, modulator, power stage driver, and other blocks. It uses
the VREG50/AVDD pin. It is generated internally by the
integrated 5 V linear regulat or. This pin must be decoupled to
ground using the 100 nF and 10 µF capacitor.
VREG18/DVDD (1.8 V) is the supply for the digital circuitry. It
uses the VREG18/DVDD pin. It can be generated internally
using an integrated 1.8 V linear regulator. Alternatively, an
external 1.8 V supply can be used to save the power dissipation.
The VREG18/DVDD pin must be decoupled to ground using
100 nF and 10 µF MLCC capacitors close to the pin.
Rev. A| Page 19 of 41
SSM3515
Data Sheet
signal must have a minimum frequencyof 2.048 MHz. The BCLK
signal is used for internal clocking of the device. The BCLK rate
is detected automatically, but the sampling frequency must be
known to the device. The supported BCLK rates at 32 kHz to 48
kHz are 50, 64, 100, 128, 192, 200, 256, 384, 400, and 512 times
the sample rate.
ADDR PIN SETUP AND CONTROL
The ADDR pin setsthe device I2C address. See Table 11 for details.
CLOCKING
In 3-wire mode (BCLK, FSYNC, SDATA), a BCLK signal must
be provided to the SSM3515 for correct operation. The BCLK
Table 11. Pin Setup List
ADDR Pin
SCL Pin
SDA Pin
Control Mode
7-Bit I2C Address
TDM Slot
Connected to Ground Using a 47 kΩ Resistor SCL
SDA
SDA
SDA
SDA
I2C
I2C
I2C
I2C
0x14
0x15
0x16
0x17
1
2
3
4
Open (No Connection)
SCL
SCL
SCL
Connected to 1.8 V Using a 47 kΩ Resistor
Connected to 1.8 V
Rev. A| Page 20 of 41
Data Sheet
SSM3515
DIGITAL AUDIO SERIAL INTERFACE
The SSM3515includes a standard serial audio interface that is
slave only. The interface is capable of receiving I2S, left justified,
PCM, or TDM formatted data.
I2C CONTROL
The SSM3515supports a 2-wire serial (I2C-compatible)
microprocessor bus driving multiple peripherals. Two pins,
serial data (SDA) and serial clock (SCL), carry information
between the SSM3515 and the system I2C master controller. The
SSM3515 is always a slave on the bus, meaning it cannot initiate
a data transfer. Each slavedeviceis recognized bya unique address.
Using the ADDR pin provides the four device addresses, which are
listed in Table 11. The address byte format is shown in Table 13.
The address resides in the first seven bits of the I2C write. The
LSB of this byte sets either a read or write operation.Logic Level 1
corresponds to a read operation, and Logic Level 0 corresponds
to a write operation.
The serial interface has three main operating modes, listed in
Table 12.
Table 12. Operating Modes
Mode
Format
Comments
Register control
using I2C port
2-Channel (Stereo)
I2S/left justified
Register control
using I2C port
Multichannel TDM
I2S/left justified
Stereo modes, typically I2S or left justified, are used when there
is one or two devices on the interface bus. Standard multi-
channel TDM modes are more flexible and offer the ability to
have multiple devices on the bus. In both of these cases, the
register control uses an I2C port.
Connect 2.2 kΩ pull-up resistors on the lines connected to the
SDA and SCL pins. The voltage on these signal lines must not
be more than 5 V.
STEREO (I2S/LEFT JUSTIFIED)OPERATING MODE
Addressing
Initially, each deviceon the I2C bus is in an idle state, monitoring
the SDA and SCL lines for a start condition and the proper
address. The I2C master initiates a data transfer by establishing a
start condition, defined by a high to low transition on SDA while
SCL remains high. This indicates that an address or data stream
follows. All devices on the bus respond to the start condition
Stereo modes use both edges of FSYNC to determine placement
of data. Stereo mode is enabled when SAI_MODE = 0 and the
data format is determined by the SDATA_FMT register setting.
The I2S or left justified interface formats accept any number of
BCLK cycles per FSYNC cycle. Sample rates from 8 kHz to
192 kHz are accepted. The maximum BCLK rate is 24.576 MHz.
and shift the next eight bits(the 7-bit address plus the R/ bit)
W
TDM OPERATING MODE
MSB first. The device that recognizes the transmitted address
responds by pulling the data line low during the ninthclock
pulse. This ninth bit is an acknowledge bit. All other devices
withdraw from the bus at this point and return to the idle con-
dition. The device address for the SSM3515is determined by the
state of the ADDR pin. See Table 11 for four available addresses.
The TDM operating mode allows multiple chips to use a single
serial interface bus for audio data.
The FSYNC signal operates at the desired sample rate. A rising
edge of the FSYNC signal indicates the start of a new frame. For
proper operation, this signal must be one BCLK cycle wide,
transitioning on a falling BCLK edge. The MSB of data must be
present on the SDATA one BCLK cycle later. The SDATA signal
latches on the rising edge of BCLK.
The R/ bit determines the direction of the data. A Logic 0 on
W
the LSB of the first byte means the master writes information to
the peripheral, whereas a Logic 1 means the master reads
information from the peripheral after writing the subaddress
and repeating the start address. A data transfer occurs until a
stop condition is encountered. A stop condition occurs when
SDA transitions from low to high while SCL is held high. The
timing for the I2C port is shown in Figure 61.
Each chip on the TDM bus can occupy 16, 24, 32,48,or64 BCLK
cycles. This is set with the TDM_BCLKS bits and all devices on
the bus must have the same setting.Up to 16 SSM3515 devices can
be used on a single TDM bus, but only 4 unique I2C device
addresses are available. The SSM3515automatically determines
how many possible devices can be placed on the bus from the
BCLK rate. There is no limit to the total numberof BCLK cycles
per FSYNC pulse.
Stop and start conditionscan be detected at anystage during the
data transfer. Ifthese conditions are asserted out ofsequence with
normal read and write operations, the SSM3515 immediately
jumps to the idle condition. During a given SCL high period,
the user must issue only one start condition, one stop condition, or
a single stop condition followed by a single start condition. If
the user issues an invalid subaddress, the SSM3515does not
issue an acknowledge and returns to the idle condition. If the
user exceeds the highest subaddress while in auto-incrementmode,
one of two actions is taken.
Which chip slot each SSM3515uses is determined by theADDR
pin settings(see Table 11 for details), or by the TDM_SLOT bits
in Register 0x05.
The input data width to the DAC can be either 16-bit or 24-bit.
Rev. A| Page 21 of 41
SSM3515
Data Sheet
In read mode, the SSM3515outputs the highest subaddress register
contents until the master device issues a no acknowledge, indi-
cating the end of a read. A no acknowledge condition is when the
SDA line is not pulled low on the ninthclock pulse on SCL. Ifthe
highest subaddress location is reached while in write mode, the
data for the invalid byte is notloaded into anysubaddress register,
a no acknowledge is issued by the SSM3515, and the device
returns to the idle condition.
every byte because therequested subaddress corresponds to a
register or memory area with a byte word length.
The timing of a single word read operation is shown in Figure 64.
Note that the first R/ bit is 0, indicating a write operation.
W
This is because the subaddress still must be written to set up the
internal address. After the SSM3515 acknowledges the receipt of
the subaddress, the master must issue a repeated start command
followed by the chip address byte with the R/ set to 1 (read).
W
I2C Read and Write Operations
This causes the SSM3515SDA to reverse and begin driving data
back to the master. The master then responds every ninth pulse
with an acknowledge pulse to the SSM3515. See Table 15 for a
list of abbreviations in Figure 62 through Figure 65.
Figure 62 shows the timing of a single-word write operation.
Every ninth clock, the SSM3515issues an acknowledge (ACK)
by pulling SDA low.
Figure 63 shows the timing of a burst mode writesequence. This
figure shows an example in which the targetdestinationregisters
are two bytes. The SSM3515incrementsits subaddress register
Table 13. I2C Device Address Byte Format Using the ADDR Pin1
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
R/
0
0
1
0
1
X
X
W
1 X means don’t care.
Table 14. ADDR Pin to I2C Device Address Mapping
ADDR Pin
ADDR Voltage
I2C Address Bit 5
I2C Address Bit 6
GND
GND
Not applicable
Not applicable
Pull-Down 47 kΩ Resistor
Open
Pull-Up 47 kΩ Resistor
DVDD
0.25 × VREG18/DVDD
0.5 × VREG18/DVDD
0.75 × VREG18/DVDD
DVDD
0
0
1
1
0
1
0
1
Table 15. Abbreviations for Figure 62 Through Figure 65
Symbol
Meaning
S
Start bit
P
Stop bit
AM
AS
Acknowledge by master
Acknowledge by slave
Rev. A| Page 22 of 41
Data Sheet
SSM3515
SCK
ACK
ACK
SDA
R/W
START BY
MASTER
FRAME 2
SUBADDRESS BYTE
FRAME 1
CHIP ADDRESS BYTE
SCK
(CONTINUED)
SDA
(CONTINUED)
ACK
ACK
STOP BY
MASTER
FRAME 4
DATA BYTE 2
FRAME 3
DATA BYTE 1
Figure 61. I2C Read/Write Timing
2
START
BIT
I C ADDRESS
(7 BITS)
ACK BY
SLAVE
SUBADDRESS
(8 BITS)
ACK BY
SLAVE
DATA BYTE 1
(8 BITS)
STOP
BIT
R/W = 0
Figure 62. Single Word I2C Write Format
CHIP ADDRESS,
DATA
WORD 1
DATA
WORD 2
S
A
SUBADDRESS
A
A
A
S
…
P
S
S
S
R/W = 0
Figure 63. Burst Mode I2C Write Format
DATA
BYTE 1
DATA
BYTE N
CHIP ADDRESS,
R/W = 0
CHIP ADDRESS,
S
A
SUBADDRESS
A
S
A
S
A
M
P
S
S
R/W = 1
Figure 64. Single Word I2C Read Format
DATA
WORD 1
CHIP ADDRESS,
R/W = 0
CHIP ADDRESS,
S
A
SUBADDRESS
A
S
A
S
A
M
…
P
S
S
R/W = 1
Figure 65. Burst Mode I2C Read Format
Rev. A| Page 23 of 41
SSM3515
Data Sheet
ANALOG AND DIGITAL GAIN
EMI NOISE
Several selectable settings are available for the analog gain of the
system. These provide optimal gain settings at various PVDD supply
voltages. The ANA_GAIN bits are available in Register 0x01,
Bits[1:0].
The SSM3515 uses a proprietary modulation and spread
spectrum technology to minimize EMI emissions from the
device. The SSM3515 can pass FCC Class B emissions testing
with an unshielded 20-inch cable using ferrite bead-based
filtering. For applications that have difficulty passing FCC Class B
emission tests, the SSM3515 includes a modulation select pin
(ultralow EMI emission mode) that significantly reduces the
radiated emissions at the Class-D outputs, particularly above
100 MHz. Note that reducing the supply voltage greatly reduces
radiated emissions.
The available options are as shown in Table 16.
Table 16. Analog Gain Options
Amplifier Analog Gain
ANA_GAIN Selection
PVDD
5 V to 9 V
9 V to 13 V
13 V to 14 V
14 V to 16 V
00
01
10
11
8.4 V full-scale gain mapping
12.6 V full-scale gain mapping
14 V full-scale gain mapping
15 V full-scale gain mapping
OUTPUT MODULATION DESCRIPTION
The SSM3515 uses three-level, Σ-Δ output modulation. Each
output can swing from GND to PVDD and vice versa. Ideally, when
no input signal is present, the output differential voltage is 0 V
because there is no need to generate a pulse. In a real-world
situation, there are always noise sources present.
There is also a digital gain or volume control that provides fine
control in 0.375 dB steps from −70 dB to +24 dB.
POP AND CLICK SUPPRESSION
Voltage transients at the output of audio amplifiers may occur
when shutdown is activated or deactivated. Voltage transients
as small as 10 mV can be heard as an audible pop in the speaker.
Clicks and pops are defined as undesirable audible transients
generated by the amplifier system that do not come from the
system input signal.
Due to this constant presence of noise, a differential pulse is
occasionally generated in response to this stimulus. A small
amount of current flows into the inductive load when the
differential pulse is generated. However, most of the time, the
output differential voltage is 0 V. This feature ensures that the
current flowing through the inductive load is small.
Such transients may be generated when the amplifier system
changes its operating mode. For example, system power-up and
power-down can be sources of audible transients.
When the user sends an input signal, an output pulse is generated
to follow the input voltage. The differential pulse density is
increased by raising the input signal level. Figure 66 depicts
three-level, Σ-Δ output modulation with and without input
stimulus.
The SSM3515 has a pop and click suppression architecture that
reduces these output transients, resulting in noiseless activation and
deactivation.
Either mute or power-down must be set before the BCLK is
removed to ensure a pop free power-down.
OUTPUT = 0V
OUT+
+5V
0V
+5V
OUT–
VOUT
0V
+5V
0V
–5V
OUTPUT > 0V
OUT+
+5V
0V
+5V
OUT–
VOUT
0V
+5V
0V
OUTPUT < 0V
OUT+
+5V
0V
+5V
OUT–
0V
0V
–5V
NOTES
1. VOUT = (OUT+) – (OUT−) MEASURED ACROSS THE LOAD.
Figure 66. Three-Level, Σ-Δ Output Modulation With and Without Input Stimulus
Rev. A| Page 24 of 41
Data Sheet
SSM3515
FAULTS AND LIMITERSTATUS REPORTING
VBAT SENSING
The SSM3515offers comprehensive protections against the
faultsat the outputs and reporting to help with system design.
The faults listed in Table 17are reported using the status registers.
The SSM3515contains an 8-bit ADC that measures the voltage
of the battery voltage (VBAT) supply. The battery voltage
information is stored in Register 0x06 as an 8-bit unsigned format.
The ADC input range is fixed internally as 3.8 V to 16.2 V. To
convert the hexidecimal (hex) value to the voltage value, use the
following steps:
Table 17. Register 0x0A, Faults
Status Reported
Fault Type
Flag Set Condition
Register
1. Convert the hex value to decimal. For example, if the hex
value is 0xA9, the decimal value = 169.
2. Calculate the voltage using the following equation:
5 V Regulator UV
5 V regulator voltage at Register 0x0A,
VREG50/AVDD < 3.6 V
Bit 6, UVLO_VR EG
Limiter/GainReduction Limiter engaged
Engage
Register 0x0A,
Bit 5, LIM_EG
Voltage = 3.8 V + 12.4 V × Decimal Value/255
Clipping
DAC clipping
Register 0x0A,
Bit 4, CLIP
Register 0x0A,
Bit 3, AMP_OC
Register 0x0A,
Bit 2, OTF
Register 0x0A,
Bit 4, OTW
With a decimal value of 169,
Output Overcurrent
(OC)
Die Overtemperature Die temperature >
(OT) 145°C
Die Overtemperature Die temperature >
Warning (OTW)
Battery Voltage >
VBAT_INF
Output current > 6 A
peak
Voltage = 3.8 V + 12.4 V × 169/255 = 12.02 V
LIMITER AND BATTERY TRACKING THRESHOLD
CONTROL
117°C
Battery voltage PVDD
VBAT_INF
The SSM3515containsan output limiterthat can be used limit
the peak output voltage of the amplifier. The limiter works on
the rms and peak value of the signal. The limiter threshold,
slope, attack rate, and release rate are programmable using
Register 0x07, Register 0x08, and Register0x09. The limiter can
be enabled or disabled using LIM_EN,Bits[1:0] inRegister0x07.
>
Register 0x0A,
Bit 0, BAT_WARN
The faults listed in Table 17 are reported in Register 0x0A and
can be read via I2C by the microcontroller in the system.
In the event of a fault occurrence, how the device reacts to the
faults can be controlled by using Register 0x0B.
The threshold at which the output is limited is determined by
the LIM_THRES register setting, in Register 0x08, Bits[7:3].
When the ouput signal level exceeds the set therhold level, the
limiter activates and limits the signal level to the set limit. Below
the set threshold, the output level is not affected. The limiter
threshold can be set from 1 V peak to 15 V peak.
Table 18. Register 0x0B, Fault Recovery
Status Reported
Register
Fault Type
Flag Set Condition
OTW
The amount of gain
reduction applied if there
is an OTW
Use to attempt manual
recovery in case of a fault
event
Register 0x0B,
Bits[7:6], OTW_GAIN
The limiter threshold can be set above the maximum output
voltage of the amplifier. In this case, the limiter allows maximum
peak output; in other words, the output may clip depending on
the power supply voltage and not the limiter.
Manual
Recovery
Register 0x0B, Bit5,
MRCV
Autorecovery When autorecovery from
Attempts
Register 0x0B,
Bits[4:3], MAX_AR
faults is used, set the
number of attempts using
this bit
Recovery can be automatic Register 0x0B, Bit2,
or manual ARCV_UV
Recovery can be automatic Register 0x0B, Bit1,
or manual ARCV_OT
Recovery can be aut omatic Register 0x0B, Bit0,
or manual ARCV_OC
The limiter threshold can be set as fixed or to vary with the
battery voltage via the VBAT_TRACKbit (Register 0x07, Bit 2).
When set to fixed, the limiter threshold is fixed and does not
vary with battery voltage.The threshold canbe set from 1 Vpeak
to 15 V peak using the LIM_THRES bit (see Figure 68).
UV
Die OT
OC
When set to a variable threshold, the SSM3515monitorsthe
VBAT supply and automatically adjusts the limiter threshold
based on the VBAT supply voltage.
When the automatic recovery mode is set, the device attempts
to recover itself after the fault event and, in case the fault
persists, then the device sets the fault again. This process
repeats until the fault is resolved.
The VBAT supply voltage at which the limiter threshold level
begins to decrease the output level is determined by the VBAT
inflection point, the VBAT_INF bits (Register 0x09, Bits[7:0]).
When the manual recovery mode is used, the device shuts down
and the recovery must be attempted using the system
microcontroller.
Rev. A| Page 25 of 41
SSM3515
Data Sheet
The VBAT_INF point is defined as the battery voltage at which
the limiter either activates or deactivates depending on the
LIM_EN mode (see Table 19). When the battery voltage is
greater than VBAT_INF, the limiter is not active. When it
battery voltage is less than VBAT_INF, the limiter is activated.
The VBAT_INF bits can be set from 3.8 V to 16.2 V. The 8-bit
value for the voltage can be calculated using the following
equation.
The limiter, when active, reduces the gain of the amplifier. The rate
of gain reduction or attack rate is determined by the LIM_ATR bits
(Register 0x07, Bits[5:4]). Similarly, when the signal level drops
below the limiter threshold, the gain is restored. The gain release
rate is determined by the LIM_RRT bits (Register 0x07, Bits[7:6]).
LIM_EN = 00
VBAT_TRACK = 0
AMPLIFIER CLIPPING LEVEL
Voltage = 3.8 + 12.4 × Decimal Value/255
Convert the decimal value to an 8-bit hex value and use it to set
the VBAT_INF bits.
The rate at which the limiter threshold is lowered relative to
the amount change in VBAT below the VBAT_INF point is
determined by the slope bits (Register 0x08, Bits[1:0]).
The slope is the ratio of the limiter threshold reduction to the
VBAT voltage reduction.
INPUT LEVEL
Slope = ΔLimiter Threshold/ΔVBAT
Figure 67. Limiter Example (LIM_EN = 0b0, VBAT_TRACK = 0bx)
The slope ratio can be set from 1:1 to 4:1. This function is useful
to prevent early shutdown under low battery conditions. As the
VBAT voltage falls, the limiter threshold is lowered. This results in
the lower output level and therefore helps to reduce the current
drawn from the battery and in turn helps prevent early shutdown
due to low VBAT.
LIMITER THRESHOLD FIXEDAT SET VALUE
AND DOES NOT TRACK VBAT
LIM_THRES
The limiter offers various active modes which can be set using the
LIM_EN bits (Register 0x07, Bits[1:0]) and the VBAT_TRACK bit,
as shown in Table 19.
When LIM_EN = 01, the limiter is enabled. When LIM_EN = 10,
the limiter mutes the output if VBAT falls below VBAT_INF. When
LIM_EN = 11, the limiter engages only when the battery voltage
is lower than VBAT_INF. When VBAT is above VBAT_INF, no
limiting occurs. Note that there is hysteresis on VBAT_INF for the
limiter disengaging.
VBAT
Figure 68. Limiter Fixed (LIM_EN = 0b01, VBAT_TRACK = 0b0)
Table 19. Limiter Modes
LIM_EN
VBAT_TRACK
Limiter
No
Fixed
Variable
Fixed
Fixed
VBAT < VBAT_INF
Not applicable
Use the set threshold
Lowers the threshold
Mutes the output
VBAT > VBAT_INF
Not applicable
Use the set threshold
Use the set threshold
Use the set threshold
No limiting
Comments
00
01
01
10
11
11
0/1
0
1
0/1
0
1
See Figure 67
See Figure 68
See Figure 69 and Figure 70
Use the set threshold
Lowers the threshold
See Figure 71 and Figure 72
See Figure 73 and Figure 74
Variable
No limiting
Rev. A| Page 26 of 41
Data Sheet
SSM3515
LIM_EN = 01
VBAT_TRACK = 1
LIMITER THRESHOLD FIXED AT SET VALUE
AND DOES NOT TRACK VBAT
LIM_THRES
VBAT > VBAT_INF LIMITER
LIMITER THRESHOLD SETTING
LIMITER THRESHOLD CHANGE FOR VBAT < VBAT_INF
CHANGE IN LIM THRESHOLD = N × (VBAT_INF – VBAT)
WHERE N = 1 TO 4, SET USING SLOPE BIT IN REG 0x08
VBAT
INPUT LEVEL
Figure 69. Limiter Fixed (LIM_EN = 0b01, VBAT_TRACK = 0b1)
Figure 72. Limiter Fixed (LIM_EN = 0b11, VBAT_TRACK = 0b0)
LIM_EN = 11
VBAT_TRACK = 1
LIMITER THRESHOLD STAYS AT
THE SET VALUE FOR VBAT > VBAT_INF
VBAT > VBAT_INF LIMITER IS NOTACTIVE
AMPLIFIER CLIPPING LEVEL
VBAT_INF
LIM_THRES
LIMITER THRESHOLD SETTING
LIMITER THRESHOLD CHANGE FOR VBAT < VBAT_INF
SLOPE
LIMITER THRESHOLD LOWERS
FOR VBAT < VBAT_INF
CHANGE IN LIM THRESHOLD = N × (VBAT_INF – VBAT)
WHERE N = 1 TO 4, SET USING SLOPE BIT IN REG 0x08
VBAT
INPUT LEVEL
Figure 70. Output Level vs. VBAT in Limiter Tracking Mode (LIM_EN = 0b01,
VBAT_TRACK = 0b1)
Figure 73. Limiter Example (LIM_EN = 0b11, VBAT_TRACK = 0b1)
LIM_EN = 11
VBAT_TRACK = 0
LIMITER THRESHOLD INACTIVE FOR VBAT > VBAT_INF
VBAT_INF
AMPLIFIER CLIPPING LEVEL
SET LIM_THRES
LIMITER THRESHOLD SETTING
NO CHANGE IN LIM THRESHOLD PER VBAT
SLOPE
LIMITER THRESHOLD LOWERS
FOR VBAT < VBAT_INF
VBAT
Figure 74. Output Level vs. VBAT in Limiter Tracking Mode (LIM_EN = 0b11,
VBAT_TRACK = 0b1)
INPUT LEVEL
Figure 71. Limiter Example (LIM_EN = 0b11, VBAT_TRACK = 0)
Rev. A| Page 27 of 41
SSM3515
Data Sheet
If the system has separate analog and digital ground and power
planes, the analog ground plane must be directly beneath the
analog power plane, and, similarly, the digital ground plane must
be directly beneath the digital power plane. There must be no
overlap between analog and digital ground planes or between
analog and digital power planes.
LAYOUT
As output power increases, care must be taken to lay out PCB
traces and wires properly among the amplifier, load, and power
supply; a poor layout increases voltage drops, consequently
decreasing efficiency. A good practice is to use short, wide PCB
tracks to decrease voltage drops and minimize inductance. For
lowest dc resistance (DCR) and minimum inductance, ensure
that track widths are at least 200 mil for every inch of length
and use 1 oz or 2 oz copper. Use large traces for the power supply
inputs and amplifier outputs. Proper grounding guidelines
improve audio performance, minimize crosstalk between
channels, and prevent switching noise from coupling into the
audio signal.
BOOTSTRAP CAPACITORS
The output stage of the SSM3515 uses a high-side NM OS driv er,
rather than PMOS. Therefore, a bootstrap supply is needed to
drive the high-side NMOS. To generate the boosted gate driver
voltage for the high-side NMOS, a 0.22 μF bootstrap capacitor is
used from each output pin to BST pins. This capacitor boosts the
voltage at BST pins when the high-side NMOS turns on and
acts as a floating power supply for that particular switching
cycle. The bootstrap capacitor is charged during the low-side
NMOS active period.
To maintain high output swing and high peak output power, the
PCB traces that connect the output pins to the load and supply
pins must be as wide as possible to maintain the minimum trace
resistances. It is also recommended that a large ground plane be
used forminimum impedances. In addition, good PCB layout
isolates critical analog paths from sources of high interference.
Separate high frequency circuits (analog and digital) from low
frequency circuits.
POWER SUPPLY DECOUPLING
To ensure high efficiency, low total harmonic distortion (THD),
and high power supply rejection ratio (PSRR), proper power
supply decoupling is necessary. Noise transients on the power
supply lines are short duration voltage spikes. These spikes can
contain frequency components that extend into the hundreds of
megahertz. The power supply input must be decoupled with a
good quality, low ESL, low ESR bulk capacitor larger than
220 µF. This capacitor bypasses low frequency noises to the
ground plane.
Properly designed multilayer PCBs can reduce EMI emission
and increase immunity to the RF field by a factor of 10 or more,
compared with double-sided boards. A multilayer board allows
a complete layer to be used for the ground plane, whereas the
ground plane side of a double-sided board is often disrupted by
signal crossover.
For high frequency transient noises, place 1 µF capacitors as
close as possible to the PVDD pins of the device.
Rev. A| Page 28 of 41
Data Sheet
SSM3515
REGISTER SUMMARY
Table 20. Register Summary
Reg. Name
Bits Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset RW
0x00 Power Control
[7:0] APWDN_
EN
BSNS_
PWDN
RESERVED
S_RST
SPWDN
0x81 R/W
0x01 Gain and Edg e
Control
[7:0]
RESERVED
EDGE
RESERVED
ANA_GAIN
0x01 R/W
0x02 DAC Control
[7:0] DAC_HV
[7:0]
DAC_MUTE DAC_HPF DAC_LPM RESERVED
VOL
DAC_FS
0x32 R/W
0x40 R/W
0x03 DAC Volume
Control
0x04 SAI Control 1
[7:0] DAC_POL
BCLK_POL
RESERVED
TDM_BCLKS
FSYNC_
MODE
SDATA_
FMT
SAI_MODE 0x11 R/W
0x00 R/W
0x05 SAI Control 2
[7:0] DATA_
WIDTH
AUTO_
SLOT
TDM_SLOT
0x06 Battery Voltage
Output
[7:0]
VBAT
0x00
R
0x07 Limiter Control 1
[7:0]
LIM_RRT
LIM_ATR
LIM_THRES
RESERVED VBAT_
TRACK
LIM_EN
SLOPE
0xA4 R/W
0x08 Limiter Control 2
0x09 Limiter Control 3
0x0A Status
[7:0]
[7:0]
RESERVED
0x51 R/W
0x22 R/W
VBAT_INF
AMP_OC
MAX_AR
[7:0] RESERVED UVLO_VREG LIM_EG
[7:0] OTW_GAIN MRCV
CLIP
OTF
ARCV_UV
OTW
ARCV_OT
BAT_WARN 0x00
R
0x0B Fault Control
ARCV_OC
0x18 R/W
Rev. A| Page 29 of 41
SSM3515
Data Sheet
REGISTER DETAILS
POWER CONTROL REGISTER
Address: 0x00, Reset: 0x81, Name: Power Control
7
6
5
4
3
2
1
0
1
0
0
0
0
0
0
1
[7] APW DN_EN (R/W)
[0] SPW DN(R/W)
Auto Power-Down Enable
0: Auto Power-Down Disabled.
1: Auto Power-Down Enabled.
Master Software Power-D o wn
0: Normal Operation.
1: Software Master Power-Down.
[6] BSNS_PWDN (R/W)
[1] S_RST (W)
BatteryVoltage Sense Power-D o wn
Full Software Reset
0: BatteryVoltage Sense Powered On.
1: BatteryVoltage Sense Powered Off.
0: Normal Operation.
1: Reset all blocks and I2C registers.
[5:2] RESERVED
Table 21. Bit Descriptions for Power Control
Bits
Bit Name
Settings
Description
Reset Access
Auto Power-Down Enable. Auto power-down automatically puts the IC in a low
power state when 2048 consecutive zero input samples have been received.
7
APWDN_EN
0x1
R/W
0
Auto Power-Down Disabled.
Auto Power-Down Enabled. When APWDN_EN = 1 the device automatically
powers down when 2048 consecutive zero value input samples have been
received. The device automatically powers up when a single nonzero sample is
received.
1
6
BSNS_PWDN
Battery Voltage Sense Power-Down.
Battery Voltage Sense Powered On.
Battery Voltage Sense Powered Off.
Reserved.
0x0
R/W
0
1
[5:2] RESERVED
0x0
0x0
R/W
W
1
S_RST
Full Software Reset.
0
1
Normal Operation.
Reset all Blocks and I2C Registers.
Master Software Power-Down. Software power-down puts all blocks except the I2C
interface in a low-power state.
0
SPWDN
0x1
R/W
0
1
Normal Operation.
Software Master Power-Down.
GAIN AND EDGECONTROL REGISTER
Address: 0x01, Reset: 0x01, Name: Gain and Edge Control
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
1
[7:5] RESERVED
[1:0] ANA_GAIN (R/W)
Amp Analog Gain Selection
[4] EDGE (R/W)
Edge Rate Control
0: Normal Operation.
1: LowEMI Mode Operation.
00: 8.4V Full-Scale Gain Mapping.
01: 12.6V Full-Scale Gain Mapping.
10: 14V Full-Scale Gain Mapping.
11: 15V Full-Scale Gain Mapping.
[3:2] RESERVED
Table 22. Bit Descriptions for Gain and Edge Control
Bits
Bit Name
Settings
Description
Reset
Access
[7:5] RESERVED
Reserved.
0x0
R/W
Rev. A| Page 30 of 41
Data Sheet
SSM3515
Bits
Bit Name
Settings Description
Edge Rate Control. This controls the edge speed of the power stage. The low EMI
Reset
Access
4
EDGE
0x0
R/W
operation mode reduces the edge speed, lowering EMI and power efficiency
0
1
Normal Operation.
Low EMI Mode Operation.
Reserved.
[3:2] RESERVED
[1:0] ANA_GAIN
0x0
0x1
R/W
R/W
Amp Analog Gain Selection.
00 8.4 V Full-Scale Gain Mapping.
01 12.6 V Full-Scale Gain Mapping.
10 14 V Full-Scale Gain Mapping.
11 15 V Full-Scale Gain Mapping.
DAC CONTROL REGISTER
Address: 0x02, Reset: 0x32, Name: DAC Control
7
6
5
4
3
2
1
0
0
0
1
1
0
0
1
0
[7] DAC_HV (R/W)
DAC Hard Volume
[2:0] DAC_FS (R/W)
DAC Sample Rate Selection
0: Soft Volume Ramping.
1: Hard/Immediate Volume Change.
000: 8 kHz to 12 kHz Sample Rate.
001: 16 kHz to 24 kHz Sample Rate.
010: 32 kHz to 48 kHz Sample Rate.
011: 64 kHz to 96 kHz Sample Rate.
100: 128 kHz to 192 kHz Sample Rate.
101: 48 kHz to 72 kHz Sample Rate.
110: Reserved.
[6] DAC_MUTE (R/W)
DAC Mute Control
0: DAC Unmuted.
1: DAC Muted.
111: Reserved.
[5] DAC_HPF (R/W)
DAC High Pass Filter Enable
[3] RESERVED
0: DAC High Pass Filter Off.
1: DAC High Pass Filter On.
[4] DAC_LPM (R/W)
DAC Low Power Mode Enable
0: DAC Low Power Mode Off.
1: DAC Low Power Mode On.
Table 23. Bit Descriptions for DAC Control
Bits
Bit Name
Settings
Description
Reset
Access
7
DAC_HV
DAC Hard Volume.
0x0
R/W
0
1
Soft Volume Ramping.
Hard/Immediate Volume Change.
DAC Mute Control.
6
5
4
3
DAC_MUTE
DAC_HPF
DAC_LPM
RESERVED
0x0
0x1
0x1
0x0
R/W
R/W
R/W
R/W
0
1
DAC Unmuted.
DAC Muted.
DAC High-Pass Filter Enable.
DAC High-Pass Filter Off.
DAC High-Pass Filter On.
DAC Low Power Mode Enable.
DAC Low Power Mode Off.
DAC Low Power Mode On.
Reserved.
0
1
0
1
Rev. A| Page 31 of 41
SSM3515
Data Sheet
Bits
Bit Name
DAC_FS
Settings
Description
Reset
Access
[2:0]
DAC Sample Rate Selection.
0x2
R/W
000 8 kHz to 12 kHz Sample Rate.
001 16 kHz to 24 kHz Sample Rate.
010 32 kHz to 48 kHz Sample Rate.
011 64 kHz to 96 kHz Sample Rate.
100 128 kHz to 192 kHz Sample Rate.
101 48 kHz to 72 kHz Sample Rate.
110 Reserved.
111 Reserved.
DAC VOLUMECONTROL REGISTER
Address: 0x03, Reset: 0x40, Name: DAC Volume Control
7
6
5
4
3
2
1
0
0
1
0
0
0
0
0
0
[7:0] VOL (R/W)
Volume Control
00000000: +24 dB.
00000001: +23.625 dB.
00000010: +23.35 dB.
...
11111101: -70.875 dB.
11111110: -71.25 dB.
11111111: Mute.
Table 24. Bit Descriptions for DAC Volume Control
Bits
Bit Name
Settings
Description
Reset
Access
[7:0]
VOL
Volume Control.
0x40
R/W
00000000 +24 dB.
00000001 +23.625 dB.
00000010 +23.35 dB.
00000011 +22.875 dB.
00000100 +22.5 dB.
00000101 ...
00111111 +0.375 dB.
01000000 0.
01000001 −0.375 dB.
01000010 ...
11111101 −70.875 dB.
11111110 −71.25 dB.
11111111 Mute.
Rev. A| Page 32 of 41
Data Sheet
SSM3515
SAI CONTROL 1 REGISTER
Address: 0x04, Reset: 0x11, Name: SAI Control 1
7
6
5
4
3
2
1
0
0
0
0
1
0
0
0
1
[7] DAC_POL (R/W)
DAC Output Polarity
[0] SAI_MODE (R/W)
Serial Interface Mode Selection
0: Normal Operation.
1: Invert the Audio Output Signal.
0: Stereo Modes (I2S,LJ)
1: TDM/PCM Modes.
[6] BCLK_POL (R/W)
[1] SDATA_FMT (R/W)
BCLK PolarityControl
0: Rising Edge of BCLKis used to register
SDATA.
Serial Data Format
0: I2S/Delay by one from FSYNC edge.
1: Left Justified/No delayfrom FSYNC edge.
Falling Edge of BCLK is used to register
SDATA.
1:
[2] FSYNC_MODE (R/W)
FSYNC Mode Control
[5:3] TDM_BCLKS (R/W)
0: LowFSYNC is Left Channel in Stereo
Modes or Pulsed FSYNC Mode in TDM Modes.
Number of BCLKs per chip in TDM mode
000: 16 BCLKs per chip in TDM.
001: 24 BCLKs per chip in TDM.
010: 32 BCLKs per chip in TDM.
011: 48 BCLKs per chip in TDM.
100: 64 BCLKs per chip in TDM.
High FSYNC is Left Channel in Stereo
1:
Modes or 50% FSYNCMode in TDM Modes.
Table 25. Bit Descriptions for SAI Control 1
Bits
Bit Name
Settings
Description
Reset
Access
7
DAC_POL
DAC Output Polarity.
Normal Operation.
0x0
0x0
0x2
R/W
0
1
Invert the Audio Output Signal.
BCLK Polarity Control.
6
BCLK_POL
R/W
R/W
0
1
Rising Edge of BCLK is Used to Register SDATA.
Falling Edge of BCLK is Used to Register SDATA.
Number of BCLKs per Chip in TDM Mode. Any number of BCLK cycles per FSYNC
can be used in stereo modes (I2S/LJ) or in TDM mode with only one chip. When in
TDM mode and having multiple chips on the TDM bus, the number of BCLKs per
chip must be defined.
[5:3] TDM_BCLKS
000 16 BCLKs per Chip in TDM.
001 24 BCLKs per Chip in TDM.
010 32 BCLKs per Chip in TDM.
011 48 BCLKs per Chip in TDM.
100 64 BCLKs per Chip in TDM.
FSYNC Mode Control.
2
FSYNC_MODE
0x0
R/W
Low FSYNC is Left Channel in Stereo Modes or Pulsed FSYNC Mode in TDM
Modes.
0
1
High FSYNC is Left Channel in Stereo Modes or 50% FSYNC Mode in TDM Modes.
1
0
SDATA _ FM T
SAI_MODE
Serial Data Format.
0x0
0x1
R/W
R/W
0
1
I2S/Delay by One from FSYNC Edge.
Left Justified/No Delay from FSYNC Edge.
Serial Interface Mode Selection.
0
1
Stereo Modes (I2S, LJ).
TDM/PCM Modes.
Rev. A| Page 33 of 41
SSM3515
Data Sheet
SAI CONTROL 2 REGISTER
Address: 0x05, Reset: 0x00, Name: SAI Control 2
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7] DATA_W IDTH (R/W)
Audio Data W idth
[3:0] TDM_SLOT(R/W)
TDM Slot Selection
0: Audio input on SDATAis 24 bits.
1: Audio input on SDATAis 16 bits.
0000: Chip Slot 1 Used.
0001: Chip Slot 2 Used.
0010: Chip Slot 3 Used.
...
[6:5] RESERVED
1101: Chip Slot 14 Used.
1110: Chip Slot 15 Used.
1111: Chip Slot 16 Used.
[4] AUTO_SLOT (R/W)
Automatic TDM Slot Selection
0: TDM Slot determined byTDM_SLOTregister.
1: TDM Slot determined byADDR pin.
Table 26. Bit Descriptions for SAI Control 2
Bits
Bit Name
Settings
Description
Reset
Access
7
DATA_WIDTH
Audio Data Width.
0x0
R/W
0
1
Audio Input on SDATA is 24 Bits.
Audio Input on SDATA is 16 Bits.
Reserved.
[6:5]
4
RESERVED
0x0
0x0
R/W
R/W
AUTO_SLOT
Automatic TDM Slot Selection.
0
1
TDM Slot Determined by the TDM_SLOT Register.
TDM Slot Determined by the ADDR Pin.
TDM Slot Selection.
[3:0]
TDM_SLOT
0x0
R/W
0000 Chip Slot 1 Used.
0001 Chip Slot 2 Used.
0010 Chip Slot 3 Used.
0011 Chip Slot 4 Used.
0100 Chip Slot 5 Used.
0101 Chip Slot 6 Used.
0110 Chip Slot 7 Used.
0111 Chip Slot 8 Used.
1000 Chip Slot 9 Used.
1001 Chip Slot 10 Used.
1010 Chip Slot 11 Used.
1011 Chip Slot 12 Used.
1100 Chip Slot 13 Used.
1101 Chip Slot 14 Used.
1110 Chip Slot 15 Used.
1111 Chip Slot 16 Used.
Rev. A| Page 34 of 41
Data Sheet
SSM3515
BATTERY VOLTAGE OUTPUT REGISTER
Address: 0x06, Reset: 0x00, Name: Battery Voltage Output
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:0] VBAT (R)
8-Bit Unsigned BatteryVoltage
Table 27. Bit Descriptions for Battery Voltage Output
Bits
Bit Name
Settings
Description
Reset
Access
[7:0]
VBAT
8-Bit Unsigned Battery Voltage
0x0
R
LIMITERCONTROL 1 REGISTER
Address: 0x07, Reset: 0xA4, Name: Limiter Control 1
7
6
5
4
3
2
1
0
1
0
1
0
0
1
0
0
[7:6] LIM_RRT(R/W)
Limiter Release Rate
00: 3200 ms/dB.
01: 1600 ms/dB.
10: 1200 ms/dB.
11: 800 ms/dB.
[1:0] LIM_EN (R/W)
Limiter or Mute Mode Enable
00: Limiter and Mute Mode Off.
01: Limiter On.
10: Output mutes if VBAT is belowVBAT_INF.
Limiter On but onlyengages if VBAT
is below VBAT_INF.
11:
[5:4] LIM_ATR (R/W)
Limiter Attack Rate
[2] VBAT_TRACK (R/W)
Threshold BatteryTracking Enable
0: Limiter Attack Threshold Fixed.
1: Limiter Attack Threshold Varies or gain
reduction with BatteryVoltage.
00: 120 us/dB.
01: 60 us/dB.
10: 30 us/dB.
11: 20 us/dB.
[3] RESERVED
Table 28. Bit Descriptions for Limiter Control 1
Bits
Bit Name
Settings
Description
Limiter Release Rate.
00 3200 ms/dB.
Reset
Access
[7:6]
LIM_RRT
0x2
R/W
01 1600 ms/dB.
10 1200 ms/dB.
11 800 ms/dB.
[5:4]
LIM_ATR
Limiter Attack Rate.
0x2
R/W
00 120 µs/dB.
01 60 µs/dB.
10 30 µs/dB.
11 20 µs/dB.
Reserved.
3
2
RESERVED
0x0
0x1
R/W
R/W
VBAT_TRACK
Threshold Battery Tracking Enable.
Limiter Attack Threshold Fixed.
0
1
Limiter Attack Threshold Varies or Gain Reduction with Battery Voltage.
Limiter or Mute Mode Enable.
[1:0]
LIM_EN
0x0
R/W
00 Limiter and Mute Mode Off.
01 Limiter On.
10 Output Mutes if VBAT is Be l ow VBAT_ I NF.
11 Limiter On But Only Engages if VBAT is Be l ow VBAT_ I NF.
Rev. A| Page 35 of 41
SSM3515
Data Sheet
LIMITER CONTROL 2 REGISTER
Address: 0x08, Reset: 0x51, Name: Limiter Control 2
7
6
5
4
3
2
1
0
0
1
0
1
0
0
0
1
[7:3] LIM_THRES (R/W)
Limiter Attack Threshold
[1:0] SLOPE (R/W)
Slope of threshold reduction/batteryvoltage
change
00000: 15.0 V peak Output.
00001: 14.5 V peak Output.
00010: 14.0 V peak Output.
...
00: 1:1 Threshold/BatteryReduction.
01: 2:1 Threshold/BatteryReduction.
10: 3:1 Threshold/BatteryReduction.
11: 4:1 Threshold/BatteryReduction.
11101:
2.0 V peak Output.
11110: 1.5V V peak Output.
1.0 V peak Output.
[2] RESERVED
11111:
Table 29. Bit Descriptions for Limiter Control 2
Bits
Bit Name
Settings
Description
Reset
0xA
Access
[7:3]
LIM_THRES
Limiter Attack Threshold.
R/W
00000 15.0 V peak Output.
00001 14.5 V peak Output.
00010 14.0 V peak Output.
00011 13.5 V peak Output.
00100 13.0 V peak Output.
00101 12.5 V peak Output.
00110 12.0 V peak Output.
00111 11.5 V peak Output.
01000 11.0 V peak Output.
01001 10.5 V peak Output.
01010 10.0 V peak Output.
01011 9.5 V peak Output.
01100 9.0 V peak Output.
01101 8.5 V peak Output.
01110 8.25 V peak Output.
01111 8.0 V peak Output.
10000 7.75 V peak Output.
10001 7.5 V peak Output.
10010 7.25 V peak Output.
10011 7.0 V peak Output.
10100 6.5 V peak Output.
10101 6.0 V peak Output.
10110 5.5 V peak Output.
10111 5.0 V peak Output.
11000 4.5 V peak Output.
11001 4.0 V peak Output.
11010 3.5 V peak Output.
11011 3.0 V peak Output.
11100 2.5 V peak Output.
11101 2.0 V peak Output.
11110 1.5 V peak Output.
11111 1.0 V peak Output.
Rev. A| Page 36 of 41
Data Sheet
SSM3515
Bits
2
Bit Name
RESERVED
SLOPE
Settings
Description
Reset
0x0
Access
R/W
Reserved.
[1:0]
Slope of Threshold Reduction/Battery Voltage Change.
0x1
R/W
00 1:1 Threshold/Battery Reduction.
01 2:1 Threshold/Battery Reduction.
10 3:1 Threshold/Battery Reduction.
11 4:1 Threshold/Battery Reduction.
LIMITER CONTROL 3 REGISTER
Address: 0x09, Reset: 0x22, Name: Limiter Control 3
7
6
5
4
3
2
1
0
0
0
1
0
0
0
1
0
[7:0] VBAT_INF (R/W)
BatteryVoltage Inflection Point
Table 30. Bit Descriptions for Limiter Control 3
Bits Bit Name Settings Description
[7:0] VBAT_INF
Reset Access
Battery Voltage Inflection Point. This is the VBAT sense value at which the limiter either
activates or starts reducing the threshold. It corresponds to the value that can be read
in the VBAT read only status register. To calculate this value in volts, refer to the VBAT
Sensing section. Voltage = 3.8 + 12.4 × Decimal Value/255.
0x22
R/W
STATUS REGISTER
Address: 0x0A, Reset: 0x00, Name: Status
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7] RESERVED
[0] BAT_W ARN (R)
BatteryVoltage W arning
0: BatteryVoltage above VBAT_INF.
1: BatteryVoltage at or belowVBAT_INF.
[6] UVLO_VREG (R)
Regulator Undervoltage Fault Status
0: Normal Operation.
1: Voltage Regulator Fault Condition.
[1] OTW (R)
Over Temperature Warning Status
[5] LIM_EG (R)
Limiter/Gain Reduction Engaged
0: Normal Operation.
1: Over Temperature Warning Condition.
0: Normal Operation.
[2] OTF (R)
Over Temperature Fault Status
Limiter or Gain Reduction has Reduced
Gain.
1:
0: Normal Operation.
1: Over Temperature Fault Condition.
[4] CLIP (R)
Clip Detector
[3] AMP_OC (R)
0: Normal Operation.
Amplifier Over-Current Fault Status
1: Amplifier Clipping Detected.
0: Normal Operation.
1: Amp Over-Current Fault Condition.
Table 31. Bit Descriptions for Status
Bits
Bit Name
RESERVED
UVLO_VREG
Settings
Description
Reset
Access
7
Reserved.
0x0
0x0
R
R
6
Regulator Undervoltage Fault Status.
Normal Operation.
0
1
Voltage Regulator Fault Condition.
5
LIM_EG
Limiter/Gain Reduction Engaged.
Normal Operation.
0x0
R
0
1
Limiter or Gain Reduction has Reduced Gain.
Rev. A| Page 37 of 41
SSM3515
Data Sheet
Bits
Bit Name
Settings
Description
Reset
Access
4
CLIP
Clip Detector.
0x0
0x0
0x0
0x0
0x0
R
0
1
Normal Operation.
Amplifier Clipping Detected.
Amplifier Overcurrent Fault Status.
Normal Operation.
3
2
1
0
AMP_OC
OTF
R
R
R
R
0
1
Amp Over-Current Fault Condition.
Overtemperature Fault Status.
Normal Operation.
0
1
Overtemperature Fault Condition.
Overtemperature Warning Status.
Normal Operation.
OTW
0
1
Overtemperature Warning Condition.
Battery Voltage Warning.
Battery Voltage Above VBAT_ I NF.
Battery Voltage at or Be l ow VBAT_ I NF.
BAT_ WA RN
0
1
FAULT CONTROL REGISTER
Address: 0x0B, Reset: 0x18, Name: Fault Control
7
6
5
4
3
2
1
0
0
0
0
1
1
0
0
0
[7:6] OTW_GAIN (R/W)
[0] ARCV_OC (R/W)
Over Thermal W arning Gain Reduction
Over Current Automatic Fault RecoveryControl
00: No gain reduction inthermal warning.
Automatic Fault Recoveryfor Over-Current
0:
01: 1.5dB gain reduction in thermal warning.
10: 3dB gain reduction in thermal warning.
11: 5.625dB gain reduction in thermal warning.
Fault.
Manual Fault Recoveryfor Over-Current
Fault.
1:
[5] MRCV (W)
[1] ARCV_OT (R/W)
Manual Fault Recovery
0: Normal Operation.
Overtemperature Automatic Fault RecoveryControl
0: Automatic Fault Recoveryfor Overtemperature
Fault.
W riting of 1 causes a manual fault
recoveryattempt when ARCV=11.
1:
Manual Fault Recoveryfor Overtemperature
Fault.
1:
[4:3] MAX_AR (R/W)
Maximum Fault recoveryAttempts
[2] ARCV_UV (R/W)
Undervoltage Automatic Fault RecoveryControl
00: 1 Auto RecoveryAttempt.
01: 3 Auto RecoveryAttempts.
10: 7 Auto RecoveryAttempts.
11: Unlimited Auto RecoveryAttempts.
Automatic Fault Recoveryfor Undervoltage
Fault.
Manual Fault Recoveryfor Undervoltage
Fault.
0:
1:
Table 32. Bit Descriptions for Fault Control
Bits
Bit Name
Settings
Description
Over Thermal Warning Gain Reduction.
00 No Gain Reduction in Thermal Warning.
Reset
Access
[7:6] OTW_GAIN
0x0
R/W
01 1.5 dB Gain Reduction in Thermal Warning.
10 3 dB Gain Reduction in Thermal Warning.
11 5.625 dB Gain Reduction in Thermal Warning.
Manual Fault Recovery.
5
MRCV
0x0
W
0
1
Normal Operation.
Writing of 1 Causes a Manual Fault Recovery Attempt when ARCV = 11.
Rev. A| Page 38 of 41
Data Sheet
SSM3515
Bits
Bit Name
Settings
Description
Reset
Access
Maximum Fault Recovery Attempts. The maximum autorecovery register
determines how many attempts at autorecovery are performed.
[4:3] MAX_AR
0x3
R/W
00 1 Autorecovery Attempt.
01 3 Autorecovery Attempts.
10 7 Autorecovery Attempts.
11 Unlimited Autorecovery Attempts.
Undervoltage Automatic Fault Recovery Control.
2
1
0
ARCV_UV
ARCV_OT
ARCV_OC
0x0
0x0
0x0
R/W
R/W
R/W
0
1
Automatic Fault Recovery for Undervoltage Faul t .
Manual Fault Recovery for Undervoltage Faul t .
Overtemperature Automatic Fault Recovery Control.
Automatic Fault Recovery for Overtemperature Faul t .
Manual Fault Recovery for Overtemperature Faul t .
Overcurrent Automatic Fault Recovery Control.
Automatic Fault Recovery for Overcurrent Faul t .
Manual Fault Recovery for Overcurrent Faul t .
0
1
0
1
Rev. A| Page 39 of 41
SSM3515
Data Sheet
TYPICAL APPLICATION CIRCUIT
Figure 75 shows a typical application circuit for a single channel output.
REG_EN
R3 0Ω EXTERNAL DVDD
R4 0Ω INTERNAL DVDD
PVDD
R4
+5V (AVDD)
+1.8V (DVDD)
R3
+1.8V
PVDD
+4.5V TO +17V
C1
C2
C3
1µF
C6
470µF
2.2µF
C4
C5
10µF
0.1uF
0.1µF
R2
2.2kΩ
R1
2.2kΩ
VREG50/AVDD
REG_EN
VREG18/DVDD
PVDD
PVDD
BST+
SCL
SDA
2
I C
REG
AVDD
REG
DVDD
2
I C
OPTIONAL
C5
0.22µF
FB1
FB2
BCLK
FSYNC
SDATA
FULL
Σ-∆
2
TDM
I S/TDM
OUT+
OUT–
BRIDGE
POWER
STAGE
2
VOLUME
4Ω/8Ω
DAC
CLASS-D
I S
MODULATOR
INPUT
C7
220pF
C8
220pF
C6
0.22µF
BST–
PGND
SSM3515
ADDR
AGND
FB1/FB2: MURATA FERRITE BEAD NFZ2MSM181
SEE THE ADDR PIN SETUP AND CONTROL SECTION
Figure 75. Typical Application Circuit for Single Channel Output
Rev. A| Page 40 of 41
Data Sheet
SSM3515
OUTLINE DIMENSIONS
1.840
1.800
1.760
4
3
2
1
A
B
BALL A1
IDENTIFIER
2.240
2.200
2.160
1.60 REF
C
D
E
0.40
BSC
BOTTOM VIEW
(BALL SIDE UP)
TOP VIEW
(BALL SIDE DOWN)
1.20 REF
0.560
0.500
0.440
SIDE VIEW
COPLANARITY
0.05
0.300
0.260
0.220
0.230
0.200
0.170
SEATING
PLANE
Figure 76. 20-Ball Wafer Level Chip Scale Package [WLCSP]
(CB-20-10)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Temperature Range
Package Description
Package Option
SSM3515CCBZ-RL
SSM3515CCBZ-R7
EVAL-SSM3515Z
−40°C to +85°C
−40°C to +85°C
20-Ball Wafer Level Chip Scale Package [WLCSP]
20-Ball Wafer Level Chip Scale Package [WLCSP]
Evaluation Board
CB-20-10
CB-20-10
1 Z = RoHS Compliant Part.
I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).
©2015–2017 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D13327-0-1/17(A)
Rev. A| Page 41 of 41
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