AD8285 [ADI]
6-Channel LNA/PGA/AAF with ADC;
| 型号： | AD8285 |
| 厂家： | 
ADI |
| 描述： | 6-Channel LNA/PGA/AAF with ADC |
| 文件： | 总27页 (文件大小：596K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Radar Receive Path AFE:
6-Channel LNA/PGA/AAF with ADC
Data Sheet
AD8283
FEATURES
FUNCTIONAL BLOCK DIAGRAM
6 channels of LNA, PGA, AAF
1 channel of direct-to-ADC
Programmable gain amplifier (PGA)
Includes low noise preamplifier (LNA)
SPI-programmable gain = 16 dB to 34 dB in 6 dB steps
Antialiasing filter (AAF)
Programmable third-order low-pass elliptic filter (LPF) from
1 MHz to 12 MHz
Analog-to-digital converter (ADC)
12 bits of accuracy up to 72 MSPS
SNR = 67 dB
INA+
INA–
REFERENCE
LNA
LNA
LNA
LNA
LNA
PGA
PGA
PGA
PGA
PGA
AAF
AAF
AAF
INB+
INB–
DSYNC
D[0:11]
INC+
INC–
12-BIT
ADC
MUX
DRV
IND+
IND–
AAF
AAF
AAF
SFDR = 68 dB
INE+
INE–
Low power, 170 mW per channel at 12 bits/72 MSPS
Low noise, 3.5 nV/√Hz maximum of input referred
voltage noise
INF+
INF–
LNA
PGA
INADC+
INADC–
Power-down mode
72-lead, 10 mm × 10 mm, LFCSP package
Specified from −40°C to +105°C
Qualified for automotive applications
SPI
AD8283
APPLICATIONS
Automotive radar
Adaptive cruise control
Collision avoidance
Blind spot detection
Self-parking
Figure 1.
Electronic bumper
GENERAL DESCRIPTION
The AD8283 is designed for low cost, low power, compact size,
flexibility, and ease of use. It contains six channels of a low noise
preamplifier (LNA) with a programmable gain amplifier (PGA)
and an antialiasing filter (AAF) plus one direct-to-ADC
channel, all integrated with a single 12-bit analog-to-digital
converter (ADC).
Fabricated in an advanced CMOS process, the AD8283 is
available in a 10 mm × 10 mm, RoHS-compliant, 72-lead
LFCSP. It is specified over the automotive temperature range
of −40°C to +105°C.
Table 1. Related Devices
Part No.
Description
Each channel features a gain range of 16 dB to 34 dB in 6 dB
increments and an ADC with a conversion rate of up to 72 MSPS.
The combined input-referred noise voltage of the entire channel
is 3.5 nV/√Hz at maximum gain. The channel is optimized for
dynamic performance and low power in applications where a
small package size is critical.
AD8285
4-Channel LNA/PGA/AAF, pseudosimultaneous
channel sampling with ADC
4-Channel LNA/PGA/AAF, sequential channel
sampling with ADC
AD8284
ADA8282 4-Channel LNA/PGA
Rev. C
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Tel: 781.329.4700 ©2011–2015 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
AD8283
Data Sheet
TABLE OF CONTENTS
Features.....................................................................................1
Clock Jitter Considerations..................................................17
SDIO Pin .............................................................................17
SCLK Pin .............................................................................17
CS Pin..................................................................................17
RBIAS Pin............................................................................17
Voltage Reference................................................................17
Power and Ground Recommendations................................18
Exposed Paddle Thermal Heat Slug Recommendations......18
Serial Peripheral Interface (SPI) ..............................................19
Hardware Interface..............................................................19
Memory Map...........................................................................21
Reading the Memory Map Table..........................................21
Logic Levels.........................................................................21
Reserved Locations..............................................................21
Default Values......................................................................21
Application Diagrams..............................................................25
Outline Dimensions ................................................................27
Ordering Guide ...................................................................27
Automotive Products...........................................................27
Applications...............................................................................1
Functional Block Diagram.........................................................1
General Description ..................................................................1
Revision History........................................................................2
Specifications.............................................................................3
AC Specifications...................................................................3
Digital Specifications .............................................................5
Switching Specifications.........................................................6
Absolute Maximum Ratings......................................................7
ESD Caution..........................................................................7
Pin Configuration and Function Descriptions...........................8
Typical Performance Characteristics.......................................10
Theory of Operation................................................................14
Radar Receive Path AFE......................................................14
Channel Overview ...............................................................15
ADC.....................................................................................16
Clock Input Considerations.................................................16
Clock Duty Cycle Considerations........................................17
REVISION HISTORY
8/15—Rev. B to Rev. C
Changed AD951x/AD952x to AD9515/AD9520-0... Throughout
Added Table 1; Renumbered Sequentially .................................1
10/14—Rev. A to Rev. B
Changes to Addr. (Hex) 0x15, Table 8......................................23
Changes to Ordering Guide.....................................................27
11/13—Rev. 0 to Rev. A
Changed Maximum fSAMPLE from 80 MSPS to 72 MSPS
................................................................................. Throughout
Changed Clock Pulse Width High/Low (tEH/tEL) at 72 MSPS
from 6.25 ns to 6.94ns; Table 3...................................................6
Changes to Figure 25 ...............................................................14
Changes to Register Address 10 Bits[5:0] and Register
Address 0x12, Bit 3; Table 8 .....................................................23
Updated Outline Dimensions..................................................27
4/11—Revision0: Initial Version
Rev. C | Page 2 of 27
Data Sheet
AD8283
SPECIFICATIONS
AC SPECIFICATIONS
AVDD18x = 1.8 V, AVDD33x = 3.3 V, DVDD18x = 1.8 V, DVDD33x = 3.3 V, 1.024 V internal ADC reference, fIN = 2.5 MHz, fSAMPLE
=
72 MSPS, RS = 50 Ω, LNA + PGA gain = 34 dB, LPF cutoff = fSAMPLECH/4, full channel mode, 12-bit operation, temperature = −40°C to
+105°C, unless otherwise noted.
Table 2.
AD8283W
Parameter1
Conditions
Min
Typ
Max
Unit
ANALOG CHANNEL CHARACTERISTICS
LNA, PGA, and AAF channel
Gain
Gain Range
Gain Error
16/22/28/34
18
dB
dB
dB
−1.25
+1.25
Input VoltageRange
Channel gain =16 dB
0.25
V p-p
Channel gain = 22 dB
Channel gain = 28 dB
Channel gain = 34 dB
0.125
0.0625
0.03125
0.230
200
Input Resistance
200 Ω input impedance selected
200 kΩ input impedance selected
0.180
160
0.280
240
kΩ
Input Capacitance
22
pF
Input-ReferredVoltage Noise
Max gain at1 MHz
1.85
nV/√Hz
Min gain at 1 MHz
6.03
7.1
12.7
nV/√Hz
dB
dB
Noise Figure
Max gain, RS = 50 Ω, unterminated
Max Gain, RS=RIN = 50 Ω
Gain= 16 dB
Gain= 34 dB
−3 dB, programmable
Output Offset
−60
−250
+60
+250
LSB
LSB
MHz
%
AAF Low-Pass Filter Cutoff
1.0 to 12.0
5
AAF Low-PassFilter CutoffTole rance After filter autotune
−10
+10
AAF Attenuation in Stop Band
Third order elliptical filter
2× cutoff
30
dB
3× cutoff
40
dB
Group Delay Variation
Channel-to-Channel Phase Variation Frequencies up to −3 dB
¼ of −3 dB frequency
Filter set at 2 MHz
400
0.5
ns
−5
−1
+5
+1
Degrees
Degrees
dB
dB
dBm
dBc
Channel-to-Channel Gain Matching
Frequencies up to −3 dB
1/4 of −3 dB frequency
Relative to output
−0.5
−0.25
0.1
+0.5
+0.25
1 dB Compression
Crosstalk
POWER SUPPLY
AVDD18x
AVDD33x
DVDD18x
DVDD33x
IAVDD18
9.8
−70
−55
1.7
3.1
1.7
3.1
1.8
3.3
1.8
3.3
1.9
3.5
1.9
3.5
190
190
22
V
V
V
V
Full-channelmode
Full-channelmode
mA
mA
mA
mA
mW
IAVDD33
IDVDD18
IDVDD33
2
170
Total Power Dissipation – per
channel
Full-channelmode, no signal, typical
supply voltage × maximum supply
current; excludesoutputcurrent
Power-DownDissipation
5
mW
Power Supply RejectionRatio(PSRR)
Relative to input
1.6
mV/V
Rev. C | Page 3 of 27
AD8283
Data Sheet
AD8283W
Typ
Parameter1
Conditions
Min
Max
Unit
ADC
Resolution
Max Sample Rate
Signal-to-Noise Ratio (SNR)
12
72
68.5
66
Bits
MSPS
dB
fIN = 1 MHz
Signal-to-Noise and Distortion
(SINAD)
dB
SNRFS
68
dB
Differential Nonlinearity (DNL)
Integral Nonlinearity (INL)
Effective Number of Bits (ENOB)
ADC Output Characteristics
Maximum Cap Load
Guaranteed no missing codes
1
10
LSB
LSB
LSB
10.67
20
Per bit
pF
IDVDD33 Peak Current with Cap Load
Peak current per bit when driving a
20 pF load; can be programmedvia
the SPI port if required
40
25
mA
ADC REFERENCE
Output VoltageError
LoadRegulation
VREF = 1.024 V
At 1.0 mA, VREF = 1.024 V
mV
mV
kΩ
2
6
Input Resistance
FULL CHANNEL CHARACTERISTICS
LNA, PGA, AAF, and ADC
SNRFS
SINAD
SFDR
FIN = 1 MHz
Gain = 16 dB
Gain = 22 dB
Gain = 28 dB
Gain = 34 dB
68
68
68
66
dB
dB
dB
dB
FIN = 1 MHz
Gain = 16 dB
Gain = 22 dB
Gain = 28 dB
Gain = 34 dB
67
68
67
66
dB
dB
dB
dB
FIN = 1 MHz
Gain = 16 dB
Gain = 22 dB
Gain = 28 dB
Gain = 34 dB
68
74
74
73
dB
dB
dB
dB
Harmonic Distortion
Second Harmonic
FIN =1 MHz at −10 dBFS, gain = 16 dB
FIN =1 MHz at −10 dBFS, gain = 34 dB
FIN =1 MHz at −10 dBFS, gain = 16 dB
FIN =1 MHz at −10 dBFS, gain = 34 dB
FIN1 = 1 MHz, FIN2 = 1.1 MHz, −1 dBFS,
gain = 34 dB
−70
−70
−66
−75
−69
dBc
dBc
dBc
dBc
dBc
Third Harmonic
IM3 Distortion
Gain Response Time
600
200
ns
ns
Overdrive RecoveryTime
1 See the AN-835 Application Note, UnderstandingHighSpeed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed.
Rev. C | Page 4 of 27
Data Sheet
AD8283
DIGITAL SPECIFICATIONS
AVDD18x = 1.8 V, AVDD33 = 3.3 V, DVDD18 = 1.8 V, DVDD33 = 3.3 V, 1.024 V internal ADC reference, fIN = 2.5 MHz, fSAMPLE
=
72 MSPS, RS = 50 Ω, LNA + PGA gain = 34 dB, LPF cutoff = fSAMPLECH/4, full channel mode, 12-bit operation, temperature = −40°C to
+105°C, unless otherwise noted.
Table 3.
Parameter1
Temperature
Min
Typ
Max
Unit
CLOCK INPUTS (CLK+, CLK−)
Logic Compliance
CMOS/LVDS/LVPECL
Differential Input Voltage 2
Input Common-Mode Voltage
Input Resistance (Differential)
Input Capacitance
Full
250
mV p-p
Full
25°C
25°C
1.2
20
1.5
V
kΩ
pF
LOGIC INPUTS (PDWN, SCLK, AUX, MUXA, ZSEL)
Logic 1 Voltage
Logic 0 Voltage
Full
Full
25°C
25°C
1.2
1.2
3.6
0.3
V
V
kΩ
pF
Input Resistance
30
Input Capacitance
0.5
LOGIC INPUT (
)
CS
Logic 1 Voltage
Logic 0 Voltage
Full
Full
3.6
0.3
V
V
Input Resistance
Input Capacitance
25°C
25°C
70
0.5
kΩ
pF
LOGIC INPUT (SDIO)
Logic 1 Voltage
Logic 0 Voltage
Full
Full
1.2
0
DVDD33x + 0.3
0.3
V
V
Input Resistance
Input Capacitance
25°C
25°C
30
2
kΩ
pF
LOGIC OUTPUT (SDIO)3
Logic 1 Voltage (IOH = 800 μA)
Logic 0 Voltage (IOL = 50 μA)
LOGIC OUTPUT (D[11:0], DSYNC)
Logic 1 Voltage (IOH = 2 mA)
Logic 0 Voltage (IOL = 2 mA)
Full
Full
3.0
3.0
V
V
0.3
Full
Full
V
V
0.05
1 See the AN-835 Application Note, UnderstandingHighSpeed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed.
2 Specified for LVDS and LVPECL only.
3 Specified for 13 SDIO pins sharing the same connection.
Rev. C | Page 5 of 27
AD8283
Data Sheet
SWITCHING SPECIFICATIONS
AVDD18x = 1.8 V, AVDD33x = 3.3 V, DVDD18x = 1.8 V, DVDD33x = 3.3 V, 1.024 V internal ADC reference, fIN = 2.5 MHz, fSAMPLE
=
72 MSPS, RS = 50 Ω, LNA + PGA gain = 34 dB, LPF cutoff = fSAMPLECH/4, full channel mode, 12-bit operation, temperature = −40°C to
+105°C, unless otherwise noted.
Table 4.
Parameter1
Temperature
Min
Typ
Max
Unit
CLOCK
Clock Rate
Full
Full
Full
Full
Full
10
72
MSPS
ns
ns
ns
ns
Clock Pulse Width High (tEH) at 72 MSPS
Clock Pulse Width Low (tEL) at 72 MSPS
Clock Pulse Width High (tEH) at 40 MSPS
Clock Pulse Width Low (tEL) at 40 MSPS
OUTPUT PARAMETERS
6.94
6.94
12.5
12.5
Propagation Delay (tPD) at 72 MSPS
Rise Time (tR)
Fall Time (tF)
Data Set-Up Time (tDS) at 72 MSPS
Data Hold Time (tDH) at 72 MSPS
Data Set-Up Time (tDS) at 40 MSPS
Data Hold Time (tDH) at 40 MSPS
Pipeline Latency
Full
Full
Full
Full
Full
Full
Full
Full
1.5
2.5
1.9
1.2
10.0
4.0
22.5
4.0
7
5.0
ns
ns
ns
ns
ns
ns
ns
9.0
1.5
21.5
1.5
11.0
5.0
23.5
5.0
Clock cycles
1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed.
N
N –1
INAx
tEH
tEL
CLK–
CLK+
tDH
tDS
tPD
N – 7
N – 6
N – 5
N – 4
N – 3
N – 2
N – 1
N
D[11:0]
Figure 2. Timing Definitions for Switching Specifications
Rev. C | Page 6 of 27
Data Sheet
AD8283
ABSOLUTE MAXIMUM RATINGS
Stresses at or above those listed under Absolute Maximum
Table 5.
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
With
Respect To
Parameter
Electrical
AVDD18x
AVDD33x
DVDD18x
DVDD33x
Rating
GND
GND
GND
GND
GND
−0.3 V to +2.0 V
−0.3 V to +3.5 V
−0.3 V to +2.0 V
−0.3 V to +3.5 V
−0.3 V to +3.5 V
Analog Inputs
INx+, INx−
ESD CAUTION
Auxiliary Inputs
INADC+, INADC-
GND
GND
−0.3 V to +2.0 V
−0.3 V to +3.5 V
Digital Outputs
D[11:0], DSYNC, SDIO
CLK+, CLK−
PDWN, SCLK, , AUX,
CS
GND
GND
−0.3 V to +3.9 V
−0.3 V to +3.9 V
MUXA, ZSEL
RBIAS, VREF
GND
−0.3 V to +2.0 V
Environmental
OperatingTemperature
Range (Ambient)
Storage Temperature
Range (Ambient)
−40°C to +105°C
−65°C to +150°C
150°C
Maximum Junction
Temperature
Lead Temperature
(Soldering, 10 sec)
300°C
Rev. C | Page 7 of 27
AD8283
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
NC
DSYNC
PDWN
DVDD18
SCLK
SDIO
CS
AUX
MUXA
ZSEL 10
TEST1 11
TEST2 12
DVDD33SPI 13
AVDD18 14
AVDD33A 15
INA– 16
1
2
3
4
5
6
7
8
9
54 NC
PIN 1
INDICATOR
53 TEST4
52 DVDD18CLK
51 CLK+
50 CLK–
49 DVDD33CLK
48 AVDD33REF
47 VREF
46 RBIAS
45 BAND
44 APOUT
43 ANOUT
42 TEST3
41 AVDD18ADC
40 AVDD18
39 INADC+
38 INADC–
37 NC
AD8283
(TOP VIEW)
INA+ 17
NC 18
NOTES
1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN.
2. THE EXPOSED PADDLE SHOULD BE TIED TO ANALOG/DIGITAL GROUND PLANE.
Figure 3.
Table 6. Pin Function Descriptions
Pin No.
Name
Description
0
GND
Ground. Exposed paddle on the bottom side; should be tied to the analog/digital ground plane.
No Connection. Pin can be tied to any potential.
Data Out Synchronization.
Full Power-Down. Logic high overrides SPI and powers down the part, logic low allows selection through SPI.
1.8 V Digital Supply.
1
2
3
NC
DSYNC
PDWN
DVDD18
SCLK
4
5
Serial Clock.
6
SDIO
Serial Data Input/Output.
7
CS
Chip Select Bar.
8
AUX
Logic high forces to Channel ADC (INADC+/INADC−); AUX has a higher priority than MUXA.
Logic high forces to Channel A unless AUX is asserted.
Input Impedance Select. Logic high overrides SPI and sets it to 200 kΩ;logic low allows selection through SPI.
Pin should not be used; tie to ground.
9
MUXA
ZSEL
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
TEST1
TEST2
DVDD33SPI
AVDD18
AVDD33A
INA−
Pin should not be used; tie to ground.
3.3 V Digital Supply, SPI Port.
1.8 V Analog Supply.
3.3 V Analog Supply, Channel A.
Negative LNA Analog Input for Channel A.
Positive LNA Analog Input for Channel A.
No Connect. Pin can be tiedto any potential.
No Connect. Pin can be tiedto any potential.
No Connect. Pin can be tiedto any potential.
3.3 V Analog Supply, Channel B.
INA+
NC
NC
NC
AVDD33B
INB−
INB+
AVDD33C
INC−
INC+
Negative LNA Analog Input for Channel B.
Positive LNA Analog Input for Channel B.
3.3 V Analog Supply, Channel C.
Negative LNA Analog Input for Channel C.
Positive LNA Analog Input for Channel C.
Rev. C | Page 8 of 27
Data Sheet
AD8283
Pin No.
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
Name
AVDD33D
IND−
Description
3.3 V Analog Supply, Channel D.
Negative LNA Analog Input for Channel D.
Positive LNA Analog Input for Channel D.
3.3 V Analog Supply, Channel E.
Negative LNA Analog Input for Channel E.
Positive LNA Analog Input for Channel E.
3.3 V Analog Supply, Channel F.
Negative LNA Analog Input for Channel F.
Positive LNA Analog Input for Channel F.
No Connect, Pin can be tiedto any potential.
No Connect. Pin can be tiedto any potential.
Negative Analog Input for Alternate Channel F (ADC Only).
Positive Analog Input for Alternate Channel F (ADC Only).
1.8 V Analog Supply.
IND+
AVDD33E
INE−
INE+
AVDD33F
INF−
INF+
NC
NC
INADC−
INADC+
AVDD18
AVDD18ADC
TEST3
ANOUT
APOUT
BAND
RBIAS
VREF
1.8 V Analog Supply, ADC.
Pin should not be used; tie to ground.
Analog Outputs (Debug Purposes Only). Pinshould be floated.
Analog Outputs (Debug Purposes Only). Pinshould be floated.
Band Gap Voltage (Debug Purposes Only). Pinshould be floated.
External resistor to set the internal ADC core bias current.
Voltage Reference Input/Output.
3.3 V Analog Supply, References.
3.3 V Digital Supply, Clock.
AVDD33REF
DVDD33CLK
CLK−
Clock Input Complement.
Clock Input True.
1.8 V Digital Supply, Clock.
CLK+
DVDD18CLK
TEST4
NC
Pin should not be used; tie to ground.
No Connect. Pin can be tiedto any potential.
No Connect. Pin can be tied to any potential.
3.3 V Digital Supply, Output Driver.
ADC Data Out (MSB).
NC
DVDD33DRV
D11
D10
ADC Data Out.
ADC Data Out.
D9
D8
D7
D6
ADC Data Out.
ADC Data Out.
ADC Data Out.
D5
D4
D3
D2
ADC Data Out.
ADC Data Out.
ADC Data Out.
ADC Data Out.
D1
D0
NC
ADC Data Out.
ADC Data Out (LSB).
No Connect. Pin should be left open.
No Connect. Pin should be left open.
3.3 V Supply, Output Driver.
NC
DVDD33DRV
NC
No Connect. Pin can be tied to any potential.
Rev. C | Page 9 of 27
AD8283
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
VS = 3.3 V, 1.8 V, TA = 25°C, FS = 72 MSPS, RIN =200 kΩ, VREF = 1.0 V.
50
40
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
40
34dB
28dB
30
22dB
20
10
16dB
0
–10
–20
–30
–40
6
4
2
0
0.1
1
10
FREQUENCY (MHz)
100
33.50
33.66
33.82
33.98
34.14
34.30
34.46
33.58
33.74
33.90
34.06
34.22
34.38
(LSB)
Figure 4. Channel Gain vs. Frequency
Figure 7. Gain Error Histogram (Gain = 34 dB)
1.0
20
34dB
19
18
17
16
15
14
13
12
11
10
9
28dB
22dB
16dB
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
8
7
6
5
4
3
2
1
0
0
0.02 0.04 0.06 0.08 0.10 0.12 0.14 0.16 0.18 0.20 0.22 0.24
0.01 0.03 0.05 0.07 0.09 0.11 0.13 0.15 0.17 0.19 0.21 0.23 0.25
–40
–15
10
35
60
85
TEMPERATURE (°C)
(dB)
Figure 5. Gain Error vs. Temperature at All Gains
Figure 8. Channel-to-Channel Gain Matching (Gain = 16 dB)
40
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
10
9
8
7
6
5
4
3
2
1
0
6
4
2
0
0
0.02 0.04 0.06 0.08 0.10 0.12 0.14 0.16 0.18 0.20 0.22 0.24
0.01 0.03 0.05 0.07 0.09 0.11 0.13 0.15 0.17 0.19 0.21 0.23 0.25
16.00
16.16
16.32
16.48
16.64
16.8
16.96
16.08
16.24
16.4
16.56
16.72
16.88
(dB)
(dB)
Figure 6. Gain Error Histogram (Gain = 16 dB)
Figure 9. Channel-to-Channel Gain Matching (Gain = 34 dB)
Rev. C | Page 10 of 27
Data Sheet
AD8283
12000
10000
8000
6000
4000
2000
0
70
65
60
55
50
45
40
SNR
SINAD
–7 –6 –5 –4 –3 –2 –1
0
1
2
3
4
5
6
7
16
22
28
34
CODE
GAIN (dB)
Figure 10. Output Referred Noise Histogram (Gain = 16 dB)
Figure 13. SNR vs. Gain
7000
20
6000
5000
4000
3000
2000
1000
0
10
0
–10
–20
–30
–40
–50
12MHz
8MHz
4MHz
2MHz
1MHz
–7 –6 –5 –4 –3 –2 –1
0
1
2
3
4
5
6
7
0.1
1
10
100
CODE
FREQUENCY (Hz)
Figure 11. Output Referred Noise Histogram (Gain = 34 dB)
Figure 14. Filter Response
15
200
180
160
140
120
100
80
34dB
10
16dB
28dB
22dB
16dB
5
60
22dB
28dB
40
34dB
20
0
0.1
0
1
10
0.1
1
10
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 12. Short Circuit Input-Referred Noise vs. Frequency
Figure 15. Short-Circuit Output-Referred Noise vs. Frequency
Rev. C | Page 11 of 27
AD8283
Data Sheet
1000
900
800
700
600
500
400
300
200
100
1.5
1.0
1MHz
2MHz
4MHz
8MHz
12MHz
0.5
0
–0.5
–1.0
–1.5
0
0.1
1
10
FREQUENCY (MHz)
100
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
TIME (µs)
Figure 16. Group Delay vs. Frequency
Figure 19. Overdrive Recovery
–40
–45
–50
–55
–60
–65
–70
–75
SECOND –1dBFS
SECOND –10dBFS
THIRD –1dBFS
LEVEL
560mV
THIRD –10dBFS
TRIG HOLDOFF
1.5µs
MEAN(C2) 7.177mV
µ: 7.1773964m
m: 7177m M: 7.177m
σ: 0
SDO
MEAN(C2) 220mV
µ: 220m
m: 220m M: 220m
σ: 0
3
2
ANALOG
OUTPUT
FREQ(C2) 997.8kHz
µ: 997.75504k
m: 997.8k M: 997.8k
σ: 0
–80
0
1
2
3
4
5
6
7
CH2 500mV
Ω
M1µs 1.25GS/s
A CH2 560mV
800ps/pt
INPUT FREQUENCY (MHz)
CH3 1V
Figure 17. Harmonic Distortion vs. Frequency
Figure 20. Gain Step Response
500
450
400
350
300
250
200
150
100
50
200000
180000
160000
140000
120000
100000
80000
60000
40000
20000
0
30
25
20
15
10
5
34dB 50Ω TERMINATED
34dB UNTERMINATED
0
0.01
0
0.1
0.1
1
10
100
1
FREQUENCY (MHz)
10
FREQUENCY (MHz)
Figure 18. RIN vs. Frequency
Figure 21. Noise Figure vs. Frequency
Rev. C | Page 12 of 27
Data Sheet
AD8283
10
9
8
7
6
5
4
3
2
1
0
12
11
10
9
8
7
6
5
4
3
2
1
–60 –52 –44 –36 –28 –20 –12 –4
–56 –48 –40 –32 –24 –16 –8
4
12 20 28 36 44 52 60
8 16 24 32 40 48 56
0
–200 –160 –120
–80
–40
0
40
80
120
160
200
0
–180 –140 –100
–60
–20
20
60
100
140
180
(LSB)
(LSB)
Figure 22. Channel Offset Distribution (Gain = 16 dB)
Figure 23. Channel Offset Distribution (Gain = 34 dB)
Rev. C | Page 13 of 27
AD8283
Data Sheet
THEORY OF OPERATION
AAF cutoff characteristics, and ADC sample rate and
resolution.
RADAR RECEIVE PATH AFE
The primary application for the AD8283 is high-speed ramp,
frequency modulated, continuous wave radar (HSR-FMCW
radar). Figure 25 shows a simplified block diagram of an HSR-
FMCW radar system. The signal chain requires multiple
channels, each including a low noise amplifier (LNA), a
programmable gain amplifier (PGA), an antialiasing filter
(AAF), and an analog-to-digital converter (ADC). The AD8283
provides all of these key components in a single 10 × 10 LFCSP
package.
The AD8283 includes a multiplexer (mux) in front of the ADC
as a cost saving alternative to having an ADC for each channel.
The mux automatically switches between each active channel
after each ADC sample. The DSYNC output indicates when
Channel A data is at the ADC output, and data for each active
channel follows sequentially with each clock cycle.
The effective sample rate for each channel is reduced by a factor
equal to the number of active channels. The ADC resolution of
12 bits with up to 72 MSPS sampling satisfies the requirements
for most HSR-FMCW approaches.
The performance of each component is designed to meet the
demands of an HSR-FMCW radar system. Some examples of
these performance metrics are the LNA noise, PGA gain range,
REF.
OSCILLATOR
PA
VCO
CHIRP RAMP
GENERATOR
LNA
LNA
PGA
AAF
PGA
AAF
12-BIT
ADC
DSP
MUX
LNA
PGA
AAF
AD8283
ANTENNA
Figure 24. Radar System Overview
SDIO
SCLK
AD8283
SPI
MUX
DSYNC
D11:D0
INTERFACE
CONTROLLER
200Ω/
200kΩ
INx+
INx–
PIPELINE
ADC
PARALLEL
3.3V CMOS
MUX
LNA
22dB
PGA
AAF
–6dB,
0dB,
6dB,
12dB
THIRD-ORDER
ELLIPTICAL FILTER
12-BIT
72MSPS
Figure 25. Simplified Block Diagram of a Single Channel
Rev. C | Page 14 of 27
Data Sheet
AD8283
The antialiasing filter uses a combination of poles and zeros to
create a third-order elliptical filter. An elliptical filter is used to
achieve a sharp roll off after the cutoff frequency. The filter uses
on-chip tuning to trim the capacitors to set the desired cutoff
frequency. This tuning method reduces variations in the cutoff
frequency due to standard IC process tolerances of resistors
and capacitors. The default −3 dB low-pass filter cutoff is 1/3 or
1/4 the ADC sample clock rate. The cutoff can be scaled to 0.7,
0.8, 0.9, 1, 1.1, 1.2, or 1.3 times this frequency through the SPI.
CHANNEL OVERVIEW
Each channel contains an LNA, a PGA, and an AAF in the
signal path. The LNA input impedance can be either 200 Ω or
200 kΩ. The PGA has selectable gains that result in channel
gains ranging from 16 dB to 34 dB. The AAF has a three-pole
elliptical response with a selectable cutoff frequency. The mux
is synchronized with the ADC and automatically selects the
next active channel after the ADC acquires a sample.
The signal path is fully differential throughout to maximize
signal swing and reduce even-order distortion including the
LNA, which is designed to be driven from a differential signal
source.
Tuning is normally off to avoid changing the capacitor settings
during critical times. The tuning circuit is enabled and disabled
through the SPI. Initializing the tuning of the filter must be
performed after initial power-up and after reprogramming the
filter cutoff scaling or ADC sample rate. Occasional retuning
during an idle time is recommended to compensate for
temperature drift.
Low Noise Amplifier(LNA)
Good noise performance relies on a proprietary ultralow noise
LNA at the beginning of the signal chain, which minimizes the
noise contributions on the following PGA and AAF. The input
impedance can be either 200 Ω or 200 kΩ and isselected through
the SPI port or by the ZSEL pin.
A cut-off range of 1 MHz to 12 MHz is possible. An example
follows:
•
•
•
•
Four channels selected: A, B, C, and AUX
ADC clock: 30 MHz
Per channel sample rate = 30/4 = 7.5 MSPS
Default tuned cutoff frequency = 7.5/4 = 1.88 MHz
The LNA supports differential output voltages as high as 4.0 V p-p
with positive and negative excursions of 1.0 V from a common-
mode voltage of 1.5 V. With the output saturation level fixed,
the channel gain sets the maximum input signal before
saturation.
Muxand Mux Controller
Low value feedback resistors and the current-driving capability
of the output stage allow the LNA to achieve a low input-
referred noise voltage of 3.5 nV/√Hz at a channel gain of 34 dB.
The use of a fully differential topology and negative feedback
minimizes second-order distortion. Differential signaling
enables smaller swings at each output, further reducing third-
order distortion.
The mux is designed to automatically scan through each active
channel. The mux remains on each channel for one clockcycle,
then switches to the nextactive channel. The mux switching is
synchronized to the ADC sampling so that the mux switching
and channel settling time do not interfere with ADC sampling.
As indicated in Table 9, Register Address 0C, Flex Mux Control,
Channel A, is usually the first converted input. The one
exceptions occurs when Channel AUX is the sole input (see
Figure 26 for timing). Channel AUX is always forced to be the
last converted input. Unselected codes put the respective
channels (LNA, PGA, and Filter) in power-down mode unless
Register Address 0C, Bit 6, is set to 1. Figure 26 shows the
timing of the clock input and data/DSYNC outputs.
Recommendation
To achieve the best possible noise performance, it is important
to match the impedances seen by the positive and negative
inputs. Matching the impedances ensures that any common-
mode noise is rejected by the signal path.
AntialiasingFilter(AAF)
The filter that the signal reaches prior to the ADC is used to
band limit the signal for antialiasing.
Rev. C | Page 15 of 27
AD8283
Data Sheet
N
N + 1
INAx
CLK–
CLK+
XXXX
OUTA
tPD
OUTB
OUTC
OUTD
OUTE
OUTF
OUTA
OUTB
D[11:0]
N – 1
N
DSYNC
NOTES
tDS
tDH
1. FOR ABOVE CONFIGURATION REGISTER ADDRESS 0C SET TO 1010 (CHANNEL A, B, C, D, E AND F ENABLED).
2. DSYNC IS ALWAYS ALIGNED WITH CHANNEL A UNLESS CHANNEL A OR CHANNEL AUX IS THE ONLY CHANNEL SELECTED, IN WHICH CASE DSYNC IS NOT ACTIVE.
3. THERE IS A SEVEN CLOCK CYCLE LATENCY FROM SAMPLING A CHANNEL TO ITS DIGITAL DATA BEING PRESENT ON THE PARALLEL BUS PINS.
Figure 26. Data and DSYNC Timing
3.3V
ADC
®
MINI-CIRCUITS
ADT1-1WT, 1:1Z
The AD8283 uses a pipelined ADC architecture. The quantized
output from each stage is combined into a 12-bit result in the
digital correction logic. The pipelined architecture permits the
first stage to operate on a new input sample and the remaining
stages to operate on preceding samples. Sampling occurs on the
rising edge of the clock. The output staging block aligns the
data, corrects errors, and passes the data to the output buffers.
0.1µF
0.1µF
XFMR
OUT
CLK+
100Ω
ADC
AD8283
50Ω
0.1µF
VFAC3
CLK–
SCHOTTKY
DIODES:
HSM2812
0.1µF
Figure 27. Transformer-Coupled Differential Clock
If a low jitter clock is available, another option is to ac-couple a
differential PECL or LVDS signal to the sample clock input pins
as shown in and Figure 28 and Figure 29. The AD9515/
AD9520-0 family of clock drivers offers excellent jitter
performance.
CLOCK INPUT CONSIDERATIONS
For optimum performance, the AD8283 sample clock inputs
(CLK+ and CLK−) should be clocked with a differential signal.
This signal is typically ac-coupled into the CLK+ and CLK− pins
via a transformer or using capacitors. These pins are biased
internally and require no additional bias.
3.3V
*
50Ω
AD9515/AD9520-0
VFAC3
Figure 27 shows the preferred method for clocking the AD8283.
A low jitter clock source, such as the Valpey Fisher oscillator
VFAC3-BHL-50MHz, is converted from single ended to
differential using an RF transformer. The back-to-back Schottky
diodes across the secondary transformer limit clock excursions
into the AD8283 to approximately 0.8 V p-p differential. This
helps prevent the large voltage swings of the clock from feeding
through to other portions of the AD8283, and it preserves the
fast rise and fall times of the signal, which are critical to low
jitter performance.
0.1µF
0.1µF
0.1µF
OUT
CLK
PECL DRIVER
CLK
CLK+
ADC
AD8283
100Ω
0.1µF
CLK–
240Ω
240Ω
*
50Ω RESISTOR IS OPTIONAL.
Figure 28. Differential PECL Sample Clock
3.3V
*
50Ω
AD9515/AD9520-0
VFAC3
OUT
0.1µF
0.1µF
0.1µF
CLK
CLK+
ADC
AD8283
100Ω
LVDS DRIVER
CLK
0.1µF
CLK–
*
50Ω RESISTOR IS OPTIONAL.
Figure 29. Differential LVDS Sample Clock
Rev. C | Page 16 of 27
Data Sheet
AD8283
In some applications, it is acceptable to drive the sample clock
inputs with a single-ended CMOS signal. In such applications,
CLK+ should be driven directly from a CMOS gate, and the
CLK− pin should be bypassed to ground with a 0.1 μF capacitor
in parallel with a 39 kΩ resistor (see Figure 30). Although the
CLK+ input circuit supply is AVDD18, this input is designed to
withstand input voltages of up to 3.3 V, making the selection of
the drive logic voltage very flexible. The AD9515/AD9520-0
family of parts can be used to provide 3.3 V inputs (see Figure 31).
In this case, 39 kΩ is not needed.
CLOCK JITTER CONSIDERATIONS
High speed, high resolution ADCsare sensitive tothe quality of the
clock input. The degradation in SNR at a given input frequency (fA)
due only to aperture jitter (tJ) can be calculated by
SNR Degradation = 20 × log 10[1/2 × π × fA × tJ]
In this equation, the RMS aperture jitter represents the rootmean
square of all jitter sources, including the clockinput, analog input
signal, and ADC aperture jitter. IF undersampling applications
are particularly sensitive to jitter.
3.3V
The clock input should be treated as an analog signal in cases
where aperture jitter may affect the dynamic range of theAD8283.
Power supplies for clock drivers should be separated from the
ADC output driver supplies to avoid modulating the clock signal
with digital noise. Low jitter, crystal-controlled oscillators make
the best clock sources, such as the Valpey Fisher VFAC3 series.
If the clock is generated from another type of source (by gating,
dividing, or other methods), it should be retimed by the
original clock during the last step.
AD9515/AD9520-0
0.1µF
VFAC3
OUT
CLK
OPTIONAL
100Ω
0.1µF
*
1.8V
CMOS DRIVER
50Ω
CLK+
ADC
AD8283
CLK
0.1µF
CLK–
0.1µF
39kΩ
*
50Ω RESISTOR IS OPTIONAL.
Figure 30. Single-Ended 1.8 V CMOS Sample Clock
Refer to the AN-501 Application Note and the AN-756
Application Note for more in-depth information about how
jitter performance relates to ADCs (visit www.analog.com).
3.3V
AD9515/AD9520-0
0.1µF
VFAC3
OUT
CLK
OPTIONAL
100Ω
0.1µF
0.1µF
*
3.3V
CMOS DRIVER
50Ω
SDIO PIN
CLK+
The SDIO pin isrequired tooperate the SPI. It has an internal
30 kΩ pull-down resistorthat pullsthis pin low and is only 1.8 V
tolerant. If applications require that this pin be driven from a
3.3 V logic level, insert a 1 kΩ resistor in series with this pin to
limit the current.
ADC
AD8283
CLK
0.1µF
CLK–
*
50Ω RESISTOR IS OPTIONAL.
Figure 31. Single-Ended 3.3 V CMOS Sample Clock
SCLK PIN
CLOCK DUTY CYCLE CONSIDERATIONS
The SCLK pin is required to operate the SPI port interface. It has
an internal 30 kΩ pull-down resistor that pullsthis pin low and is
both 1.8 V and 3.3 V tolerant.
Typical high speed ADCs use both clock edges to generate a
variety of internal timing signals. As a result, these ADCs may
be sensitive to the clock duty cycle. Commonly, a 5% tolerance is
required on the clock duty cycle to maintain dynamic performance
characteristics. The AD8283 contains a duty cycle stabilizer (DCS)
that retimes the nonsampling edge, providing an internal clock
signal with a nominal 50% duty cycle. This allows a wide range
of clock input duty cycles without affecting the performance of
the AD8283.
PIN
CS
The CS pin is required to operate the SPI port interface. It hasan
internal 70 kΩ pull-up resistor that pulls thispin high and is both
1.8 V and 3.3 V tolerant.
RBIAS PIN
To set the internal core bias current of the ADC, place a resistor
nominally equal to 10.0 kΩ to ground at the RBIAS pin. Using
other than the recommended 10.0 kΩ resistorfor RBIAS
degrades the performance of the device. Therefore, it is imperative
that at leasta 1.0% tolerance on this resistor be used to achieve
consistent performance.
When the DCS ison, noise and distortion performance are nearly
flat for a wide range of duty cycles. However, some applications
may require the DCS function to be off. If so, keep in mind that
the dynamic range performance can be affected when operated in
this mode. See Table 9 for more details on using this feature.
The duty cycle stabilizer uses a delay-locked loop (DLL) to
create the nonsampling edge. As a result, any changes to the
sampling frequency require approximately eight clock cycles to
allow the DLL to acquire and lock to the new rate.
VOLTAGE REFERENCE
A stable and accurate 0.5 V voltage reference is built into the
AD8283. This is gained up internally by a factor of 2, setting
VREF to 1.0 V, which results in a full-scale differential input
span of 2.0 V p-p for the ADC. VREF is set internally by
default, but the VREF pin can be driven externally with a 1.0 V
Rev. C | Page 17 of 27
AD8283
Data Sheet
reference to achieve more accuracy. However, this device does
not support ADC full-scale ranges below 2.0 V p-p.
A single PC board ground plane should be sufficient when using
the AD8283. With proper decoupling and smart partitioning of
the PC board’s analog, digital, and clock sections, optimum
performance can be achieved easily.
When applying the decoupling capacitors to the VREF pin, use
ceramic low-ESRcapacitors. These capacitors should be close to
the reference pin and on the same layer of the PCB as
the AD8283. The VREF pin should have both a 0.1 µF capacitor
and a 1 µF capacitor connected in parallel to the analog ground.
These capacitor values are recommended for the ADC to
properly settle and acquire the next valid sample.
EXPOSED PADDLE THERMAL HEAT SLUG
RECOMMENDATIONS
It is required that the exposed paddle on the underside of the
device be connected to a quiet analog ground to achieve the
best electrical and thermal performance of the AD8283. An
exposed continuous copper plane on the PCB should mate to
the AD8283 exposed paddle, Pin 0. The copper plane should
have several vias to achieve the lowest possible resistive thermal
path for heat dissipation to flow through the bottom of the PCB.
These vias should be filled or plugged with nonconductive epoxy.
POWER AND GROUND RECOMMENDATIONS
When connecting power to the AD8283, it is recommended
that two separate 1.8 V supplies and two separate 3.3 V supplies
be used: one for analog 1.8 V (AVDD18x) and digital 1.8 V
(DVDD18x) and one for analog 3.3 V (AVDD33x) and digital
3.3 V (DVDD33x). If only one supply is available for both analog
and digital, for example, AVDD18x and DVDD18x, it should be
routed to the AVDD18x first and then tapped off and isolated
with a ferrite bead or a filter choke preceded by decoupling
capacitors for the DVDD18x. The same is true for the analog
and digital 3.3 V supplies. The user should employ several
decoupling capacitors on all supplies to cover both high and low
frequencies. These should be located close to the point of entry
at the PC board level and close to the parts, with minimal trace
lengths.
To maximize the coverage and adhesion between the device and
PCB, partition the continuous copper pad by overlaying a silk-
screen or solder maskto divide thisinto several uniform sections.
This ensuresseveral tie points between the two during the reflow
process. Using one continuous plane with no partitions only
guarantees one tie point between the AD8283 and PCB. For
more detailed information on packaging and for more PCB
layout examples, see the AN-772 Application Note.
Rev. C | Page 18 of 27
Data Sheet
AD8283
SERIAL PERIPHERAL INTERFACE (SPI)
The AD8283 serial port interface allows the user to configure
the signal chain for specific functions or operations through a
structured register space provided inside the chip. This offers
the user added flexibility and customization depending on the
application. Addresses are accessed via the serial port and can
be written to or read from via the port. Memory is organized
into bytes that can be further divided into fields, as documented
in the Memory Map section. Detailed operational information
can be found in the Analog Devices, Inc., AN-877 Application
Note, Interfacing to High Speed ADCs via SPI.
In addition to the operation modes, the SPI port can be
configured to operate in different manners. For applications
that do not require a control port, the CS line can be tied and
held high. This places the remainder of the SPI pins in their
secondary mode as defined in the SDIO Pin and SCLK Pin
sections. CS can also be tied low to enable 2-wire mode. When
CS is tied low, SCLK and SDIO are the only pins required for
communication. Although the device is synchronized during
power-up, caution must be exercised when using this mode to
ensure that the serial port remains synchronized with the CS
line. When operating in 2-wire mode, it is recommended to use
a 1-, 2-, or 3-byte transfer exclusively. Without an active CS
line, streaming mode can be entered but not exited.
There are three pins that define the serial port interface, or SPI.
They are the SCLK, SDIO, and CS pins. The SCLK (serial clock)
is used to synchronize the read and write data presented to the
device. The SDIO (serial data input/output) is a dual-purpose
pin that allows data to be sent to and read from the device’s
internal memory map registers. The CS (chip select bar) is an
In addition to word length, the instruction phase determines if
the serial frame is a read or write operation, allowing the serial
port to be used to both program the chip and read the contents
of the on-chip memory. If the instruction is a readback operation,
performing a readback causes the serial data input/output (SDIO)
pin to change direction from an input to an output at the
appropriate point in the serial frame.
active low control that enables or disables the read and write
cycles (see Table 7).
Table 7. Serial Port Pins
Pin
Function
Data can be sent in MSB- or LSB-first mode. MSB-first mode
is the default at power-up and can be changed by adjusting the
configuration register. For more information about this and
other features, see the AN-877 Application Note, Interfacing to
High Speed ADCs via SPI.
SCLK
Serial clock. The serial shift clock input. SCLK is used to
synchronize serial interface reads and writes.
SDIO
CS
Serial data input/output. A dual-purpose pin. The typical
role for this pin is as an input or output, depending on
the instruction sent and the relative position in the
timingframe.
HARDWARE INTERFACE
Chip select bar (active low). This control gates the read
and write cycles.
The pins described in Table 7 constitute the physical interface
between the user’s programming device and the serial port of
the AD8283. The SCLK and CS pins function as inputs when
using the SPI interface. The SDIO pin is bidirectional, functioning
as an input during write phasesand as an outputduring readback.
The falling edge of the CS in conjunction with the rising edge of
the SCLK determines the startof the framing sequence. During an
instruction phase, a 16-bitinstruction is transmitted, followed by
one or more data bytes, which is determined by Bit Field W0 and
Bit Field W1. An example of the serial timing and its definitions
can be found in Figure 32 and Table 8.
This interface is flexible enough to be controlled by either serial
PROMS or PIC microcontrollers. This provides the user with
an alternative method, other than a full SPI controller, for
programming the device (see the AN-812 Application Note).
In normal operation, CS is used to signal to the device that SPI
commands are to be received and processed. WhenCS is brought
low, the device processes SCLK and SDIO toprocessinstructions.
Normally, CS remains low until the communication cycle is
complete. However, if connected to a slow device, CS can be
brought high between bytes, allowing older microcontrollers
enough time to transfer data into shiftregisters. CS can be stalled
when transferring one, two, or three bytes of data. When W0 and
W1 are set to 11, the device enters streaming mode and continues
to process data, either reading or writing, until CS is taken high
to end the communication cycle. This allows complete memory
transfers without having to provide additional instructions.
Regardless of the mode, if CS is taken high in the middle of any
byte transfer, the SPI state machine is reset and the devicewaits
for a new instruction.
If the user chooses not to use the SPI interface, these pins serve
a dual function and are associated with secondary functions
when the CS is strapped to AVDD during device power-up. See
the SDIO Pin and SCLK Pin sections for details on which pin-
strappable functions are supported on the SPI pins.
Rev. C | Page 19 of 27
AD8283
Data Sheet
tDS
tHI
tCLK
tH
tS
tDH
tLO
CS
SCLK DON’T CARE
SDIO DON’T CARE
DON’T CARE
R/W
W1
W0
A12
A11
A10
A9
A8
A7
D5
D4
D3
D2
D1
D0
DON’T CARE
Figure 32. Serial Timing Details
Table 8. Serial Timing Definitions
Parameter
Minimum Timing (ns)
Description
tDS
5
2
40
5
Setup time between the data and the rising edge of SCLK
Hold time between the data and the rising edge of SCLK
Period of the clock
tDH
tCLK
tS
Setup time between CS and SCLK
tH
2
Hold time between CS and SCLK
tHI
tLO
tEN_SDIO
16
16
10
Minimum period that SCLK should be in a logic high state
Minimum period that SCLK should be in a logic low state
Minimum time for the SDIO pin to switch from an input to an output relative to the SCLK
falling edge (not shown in Figure 32).
tDIS_SDIO
10
Minimum time for the SDIO pin to switch from an output to an input relative to the SCLK
rising edge (not shown in Figure 32)
Rev. C | Page 20 of 27
Data Sheet
AD8283
MEMORY MAP
READING THE MEMORY MAP TABLE
LOGIC LEVELS
An explanation of various registers follows: “bit is set” is
synonymous with “bit is set to Logic 1” or “writing Logic 1 for
the bit.” Similarly, “clear a bit” is synonymous with “bit is set to
Logic 0” or “writing Logic 0 for the bit.
Each row in the memory map table has eight address locations.
The memory map is roughly divided into three sections: the
chip configuration registersmap (Address 0x00 and Address 0x01),
the device index and transfer registers map (Address 0x04 to
Address 0xFF), and the ADC channel functionsregisters map
(Address 0x08 to Address 0x2C).
RESERVED LOCATIONS
Undefined memory locations should not be written to except
when writing the default values suggested in this data sheet.
Addresses that have values marked as 0 should be considered
reserved and have a 0 written into theirregistersduring power-up.
The leftmost column of the memory map indicates the register
address number, and the default value is shown in the second
rightmost column. The Bit 7 (MSB) column is the start of the
default hexadecimal value given. For example, Address 0x09,
the clock register, has a default value of 0x01, meaning that Bit 7
= 0, Bit 6 = 0, Bit 5 = 0, Bit 4 = 0, Bit 3 = 0, Bit 2 = 0, Bit 1 = 0,
and Bit 0 = 1, or 0000 0001 in binary. This setting is the default
for the duty cycle stabilizer in the on condition. By writing a 0
to Bit 0 of this address followed by an 0x01 to the SW transfer
bit in Register 0xFF, the duty cycle stabilizer turns off. It is
important to follow each writing sequence with a write to the
SW transfer bit to update the SPI registers.
DEFAULT VALUES
After a reset, critical registers are automatically loaded with
default values. These values are indicated in Table 9, where an X
refers to an undefined feature.
Note that all registers except Register 0x00, Register 0x04,
Register 0x05, and Register 0xFF are buffered with a master
slave latch and require writing to the transfer bit. For more
information on this and other functions, consulttheAN-877
Application Note, Interfacing to High Speed ADCs via SPI.
Rev. C | Page 21 of 27
AD8283
Data Sheet
Table 9. AD8283 Memory Map Register
Addr.
(Hex)
Bit 7
(MSB)
Bit 0
(LSB)
Default Default Notes/
Value
Comments
Register Name
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Chip Configuration Registers
00
CHIP_PORT_CONFIG
0
LSB first
1 = on
Soft
reset
1
1
Soft
reset
LSB first
1 = on
0
0x18
The nibbles
should be
0 = off
(default)
1 = on
0 = off
(default)
1 = on
0 = off
(default)
0 = off
(default)
mirrored so
that LSB- or
MSB-first mode
is set correct
regardless of
shift mode.
01
CHIP_ID
Chip ID Bits[7:0]
(AD8283 = 0xA2, default)
Read
only
The default is a
unique chip ID,
specific to the
AD8283. This is
a read-only
register.
Device Index and Transfer Registers
04
05
FF
DEVICE_INDEX_2
DEVICE_INDEX_1
DEVICE_UPDATE
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Data
Data
0x0F
0x0F
0x00
Bits are set to
determine
which on-chip
device receives
the next write
command.
Channel Channel
F
1 = on
(default) (default)
E
1 = on
0 = off
0 = off
Data
Data
Data
Data
Bits are set to
determine
which on-chip
device receives
the next write
command.
Channel Channel
D
1 = on
(default) (default) (default) (default)
0 = off
Channel Channel
B
1 = on
C
A
1 = on
1 = on
0 = off
0 = off
0 = off
X
X
X
SW
transfer
Synchronously
transfers data
1 = on
from the
0 = off
(default)
master shift
register to the
slave.
Channel Functions Registers
08
GLOBAL_MODES
X
X
X
X
X
X
X
X
Internal power-
0x00
Determines the
power-down
mode (global).
down mode
00 = chip run
(default)
01 = full power-
down
11 = reset
09
0C
GLOBAL_CLOCK
X
X
X
X
X
X
X
X
Duty
0x01
0x00
Turns the
cycle
stabilizer
1 = on
(default)
0 = off
internal duty
cycle stabilizer
on and off
(global).
FLEX_MUX_CONTROL
Power-
down of
unused
Mux input active channels
0000 = A
0001 =
0010 = AB
0011 = A
0100 = ABC
0101 = AB
0110 = ABCD
0111 = ABC
1000 = ABCDE
Sets which mux
input channel(s)
are in use and
whether to
power down
unused
Aux
Aux
Aux
Aux
channels
0 = PD
(power-
down;
channels.
default)
1 =
power-on
1001 = ABCD Aux
1010 = ABCDEF
1011 = ABCDE Aux
Rev. C | Page 22 of 27
Data Sheet
AD8283
Addr.
Bit 7
Bit 0
Default Default Notes/
(Hex)
(MSB)
(LSB)
Value
Comments
Register Name
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
0D
FLEX_TEST_IO
User test mode
Reset PN Reset PN
0x00
When this
Output test mode—see Table 10
0000 = off (default)
0001 = midscale short
0010 = +FS short
0011 = −FS short
0100 = checkerboard output
0101 = PN sequence long
0110 = PN sequence short
0111 = one-/zero-word toggle
1000 = user input
00 = off (default)
01 = on, single
alternate
10 = on, single once
11 = on, alternate
once
long
gen
short
gen
register is set,
the test data is
placed on the
output pins in
place of
normal data.
(Local, except
for PN
1 = on
0 = off
1 = on
0 = off
(default) (default)
sequence.)
1001 = 1-/0-bit toggle
1010 = 1× sync
1011 = one bit high
1100 = mixed bit frequency (format
determined by the OUTPUT_MODE register)
0F
FLEX_CHANNEL_INPUT
Filter cutoff frequency control
0000 = 1.3 × 1/4 × fSA MPL EC H
0001 = 1.2 × 1/4 × fSA MPL EC H
0010 = 1.1 × 1/4 × fSA MPL EC H
0011 = 1.0 × 1/4 × fSA MPL EC H (default)
0100 = 0.9 × 1/4 × fSA MPL EC H
X
X
X
X
0x30
Low pass filter
cutoff (global).
fSAMPLECH = ADC
sample rate/
number of
active
0101 = 0.8 × 1/4 × fSA MPL EC H
0110 = 0.7 × 1/4 × fSA MPL EC H
0111 = N/A
channels.
Note that the
absolute range
is limited to
1 MHz to
1000 = 1.3 × 1/3 × fSA MPL EC H
1001 = 1.2 × 1/3 × fSA MPL EC H
1010 = 1.1 × 1/3 × fSA MPL EC H
1011 = 1.0 × 1/3 × fSA MPL EC H
1100 = 0.9 × 1/3 × fSA MPL EC H
1101 = 0.8 × 1/3 × fSA MPL EC H
1110 = 0.7 × 1/3 × fSA MPL EC H
1111 = N/A
12 MHz.
10
FLEX_OFFSET
X
X
6-bit LNA offset adjustment
00 0000 for LNA bias high
01 1111 for LNA mid-high
0x20
LNA force
offset
correction
(local).
10 0000 for LNA mid-low (default)
11 1111 for LNA bias low
11
12
FLEX_GAIN_1
X
X
X
X
X
X
X
010 = 16 dB(default)
0x00
0x09
Total LNA +
011 = 22 dB
100 = 28 dB
101 = 34 dB
PGA gain
adjustment
(local)
FLEX_BIAS_CURRENT
X
X
X
X
LNA bias
00 = high
LNA bias
current
01 = mid-high
(default)
adjustment
(global).
10 = mid-low
11 = low
14
15
FLEX_OUTPUT_MODE
FLEX_OUTPUT_ADJUST
X
X
X
X
X
X
X
X
1 =
output
invert
0 = offset binary
(default)
1 = twos comple-
ment (global)
0x00
0x0F
Configures the
outputs and
the format of
the data.
(local)
0 =
Typical output rise
time and fall time,
respectively
00 = 2.6 ns, 3.4 ns
01 = 1.1 ns, 1.6 ns
10 = 0.7 ns, 0.9 ns
11 = 0.7 ns, 0.7 ns
(default)
Typical output drive
strength
00 = 45 mA
01 = 30 mA
10 = 60 mA
11 = 60 mA
(default)
Used to adjust
output rise and
fall times and
select output
drive strength,
limiting the
noise added to
the channels
by output
enable
Data
Bits
[11:0]
1 =
disable
Data
Bits
[11:0]
switching.
Rev. C | Page 23 of 27
AD8283
Data Sheet
Addr.
Bit 7
Bit 0
Default Default Notes/
(Hex)
(MSB)
(LSB)
Value
Comments
Register Name
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
18
FLEX_VREF
X
0 =
X
X
X
X
00 = 0.625 V
01 = 0.750 V
10 = 0.875 V
0x03
Select internal
reference
internal
reference
1 =
external
reference
(recommended
default) or ex-
ternal reference
(global); adjust
internal refer-
ence.
11 = 1.024 V
(default)
19
1A
1B
1C
FLEX_USER_PATT1_LSB
B7
B6
B5
B4
B3
B2
B1
B9
B1
B9
B0
0x00
0x00
0x00
0x00
User-defined
pattern, 1 LSB.
FLEX_USER_PATT1_
MSB
B15
B7
B14
B6
B13
B5
B12
B4
B11
B3
B10
B2
B8
B0
B8
User-defined
pattern, 1 MSB.
FLEX_USER_PATT2_LSB
User-defined
pattern, 2 LSBs.
FLEX_USER_PATT2_
MSB
B15
B14
B13
B12
B11
B10
User-defined
pattern, 2
MSBs.
2B
FLEX_FILTER
CH_IN_IMP
X
X
Enable
X
X
X
X
0x00
automatic
low-pass
tuning
1 = on
(self-
clearing)
2C
X
X
X
0 =
0x00
Input imped-
200Ω
(default)
1 =
ance adjust-
ment (global).
200kΩ
Table 10. Flexible Output Test Modes
Output Test Mode
Subject to Data
Format Select
Bit Sequence
Pattern Name
Off (default)
Digital Output Word 1
N/A
Digital Output Word 2
0000
0001
N/A
Same
N/A
Yes
Yes
Yes
No
Yes
Yes
No
No
No
No
No
No
Midscale short
+Full-scale short
−Full-scale short
Checkerboardoutput
PN sequence long
PN sequence short
One-/zero-word toggle
User input
1000 0000 0000
1111 1111 1111
0000 0000 0000
1010 1010 1010
N/A
0010
0011
0100
Same
Same
0101 0101 0101
0101
0110
0111
N/A
N/A
N/A
1111 1111 1111
0000 0000 0000
1000
1001
1010
1011
Register 0x19 to Register 0x1A
1010 1010 1010
0000 0011 1111
Register 0x1Bto Register 0x1C
1-/0-bit toggle
1× sync
One bit high
N/A
N/A
N/A
N/A
1000 0000 0000
1100
Mixed bit frequency
1010 0011 0011
Rev. C | Page 24 of 27
Data Sheet
AD8283
APPLICATION DIAGRAMS
AVDD33REF
0.1µF
DVDD33SPI
0.1µF
DVDD18
0.1µF
AVDD18
0.1µF
3.3V
3.3V
1.8V
1.8V
AVDD33A
0.1µF
DVDD33CLK
0.1µF
AVDD18
0.1µF
DVDD18CLK
0.1µF
AVDD33B
0.1µF
DVDD33DRV
0.1µF
AVDD18ADC
0.1µF
AVDD33C
0.1µF
DVDD33DRV
0.1µF
AVDD33D
0.1µF
AVDD33E
0.1µF
AVDD33F
0.1µF
54
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
NC
NC
NC
TEST4
DVDD18CLK
CLK+
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
DSYNC
PDWN
DVDD18
SCLK
SDIO
CS
AUX
MUXA
ZSEL
TEST1
TEST2
DVDD33SPI
AVDD18
AVDD33A
INA–
DSYNC
PDWN
CLK+
CLK–
SCLK
CLK–
10kΩ
SDIO
DVDD33CLK
AVDD33REF
VREF
CS
AUX
MUXA
ZSEL
0.1µF
0.1µF
0.1µF
10kΩ
AD8283
(TOP VIEW)
RBIAS
BAND
APOUT
ANOUT
TEST3
1%
INADC+
AVDD18ADC
AVDD18
INADC+
INADC–
NC
INA–
0.1µF
0.1µF
INB–
INA+
NC
INADC–
0.1µF
INA+
INF+
0.1µF
0.1µF
0.1µF
0.1µF
INB+
INF–
INE–
IND–
0.1µF
0.1µF
0.1µF
0.1µF
INE+
IND+
INC–
0.1µF
INC+
0.1µF
NOTES
1. ALL CAPACITORS FOR SUPPLIES AND REFERENCES SHOULD BE PLACED CLOSE TO THE PART.
Figure 33. Differential Inputs
Rev. C | Page 25 of 27
AD8283
Data Sheet
AVDD33REF
0.1µF
DVDD33SPI
0.1µF
DVDD18
0.1µF
AVDD18
0.1µF
3.3V
3.3V
1.8V
1.8V
AVDD33A
0.1µF
DVDD33CLK
0.1µF
AVDD18
0.1µF
DVDD18CLK
0.1µF
AVDD33B
0.1µF
DVDD33DRV
0.1µF
AVDD18ADC
0.1µF
AVDD33C
0.1µF
DVDD33DRV
0.1µF
AVDD33D
0.1µF
AVDD33E
0.1µF
AVDD33F
0.1µF
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
54
NC
NC
NC
TEST4
DVDD18CLK
CLK+
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
DSYNC
PDWN
DVDD18
SCLK
SDIO
CS
AUX
MUXA
ZSEL
TEST1
TEST2
DVDD33SPI
AVDD18
AVDD33A
INA–
DSYNC
PDWN
CLK+
CLK–
SCLK
CLK–
10kΩ
SDIO
CS
AUX
MUXA
ZSEL
DVDD33CLK
AVDD33REF
VREF
0.1µF
0.1µF
0.1µF
10kΩ
AD8283
(TOP VIEW)
RBIAS
BAND
APOUT
ANOUT
TEST3
1%
INADC+
AVDD18ADC
AVDD18
INADC+
INADC–
NC
INA+
NC
R
0.1µF
INADC–
0.1µF
INA
0.1µF
INF
0.1µF
0.1µF
0.1µF
INB
INC
0.1µF
INE
IND
0.1µF
NOTES
1. RESISTOR R (INx– INPUTS) SHOULD MATCH THE OUTPUT IMPEDANCE OF THE INPUT DRIVER.
2. ALL CAPACITORS FOR SUPPLIES AND REFERENCES SHOULD BE PLACED CLOSE TO THE PART.
Figure 34. Single-Ended Inputs
Rev. C | Page 26 of 27
Data Sheet
AD8283
OUTLINE DIMENSIONS
10.10
10.00 SQ
9.90
0.60
0.42
0.24
0.30
0.23
0.18
0.60
0.42
0.24
PIN 1
INDICATOR
55
54
72
1
PIN 1
INDICATOR
9.85
0.50
BSC
9.75 SQ
9.65
8.60
8.50 SQ
8.40
EXPOSED
PAD
0.50
0.40
0.30
18
19
37
36
0.25 MIN
TOP VIEW
BOTTOM VIEW
8.50 REF
0.70
0.65
0.60
12° MAX
0.90
0.85
0.80
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.05 MAX
0.01 NOM
COPLANARITY
0.08
SECTION OF THIS DATA SHEET.
SEATING
PLANE
0.20 REF
COMPLIANT TO JEDEC STANDARDS MO-220-VNND-4
Figure 35. 72-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
10 mm × 10 mm Body, Very Thin Quad
(CP-72-5)
Dimensions shown in millimeters
ORDERING GUIDE
Model1, 2, 3
Temperature Range
−40°C to +105°C
−40°C to +105°C
Package Description
Package Option
AD8283WBCPZ-RL
AD8283WBCPZ
AD8283CP-EBZ
72-LeadLFCSP_VQ, 13”Tape and Reel
72-LeadLFCSP_VQ, Waffle Pack
Evaluation Board
CP-72-5
CP-72-5
1 Z = RoHS Compliant Part.
2 W = Qualified for Automotive Applications.
3 Compliant to JEDEC Standard MO-220-VNND-4.
AUTOMOTIVE PRODUCTS
The AD8283WBCPZ models are available with controlled manufacturing to support the quality and reliability requirements of
automotive applications. Note that these automotive models may have specifications thatdiffer from the commercial models; therefore,
designers should review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for
use in automotive applications. Contact your local Analog Devices account representative for specific product ordering information and
to obtain the specific Automotive Reliability reports for this model.
©2011–2015 Analog Devices, Inc. All rights reserved. Trademarksand
registered trademarks are the property of their respective owners.
D09795-0-8/15(C)
Rev. C | Page 27 of 27
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