ADMCF341-EVALKIT_技术文档

DashDSP^™28-Lead Flash Mixed-Signal DSP

with Enhanced Analog Front End

a

ADMCF341

Individual Enable and Disable for Each PWM Output

High-Frequency Chopping Mode for Transformer

FEATURES

20 MHz Fixed-Point DSP Core

Coupled Gate Drives

External PWMTRIP Pin

Single-Cycle Instruction Execution (50 ns)

ADSP-21xx Family Code Compatibility

Independent Computational Units

ALU, Multiplier/Accumulator, Barrel Shifter

Multifunction Instructions

Single-Cycle Context Switch

Powerful Program Sequencer

Zero Overhead Looping

Integrated 6-Channel ADC Subsystem

Three Bipolar I_SENSEInputs with Programmable

Sample-and-Hold Amplifier and Overcurrent Pro-

tection (Usable as Three Dedicated Analog Inputs)

Muxed Auxiliary Analog Inputs

Internal Voltage Reference (2.5 V)

Acquisition Synchronized to PWM Switching

Frequency

Conditional Instruction Execution

Two Independent Data Address Generators

Memory Conﬁguration

9-Pin Digital I/O Port

Bit Conﬁgurable as Input or Output

Change of State Interrupt Support

Two 16-Bit Auxiliary PWM Timers

Synthesized Analog Output

Programmable Frequency

0% to 100% Duty Cycle

Two Programmable Operational Modes

Independent Mode/Offset Mode

Motor Types

Permanent Magnet Synchronous Motors (PMSM)

Brushless DC Motors (BDCM)

512 ꢀ 16-Bit Data Memory RAM

512 ꢀ 24-Bit Program Memory RAM

4K ꢀ 24-Bit Program Memory ROM

4K ꢀ 24-Bit Program Flash Memory

Three Independent Flash Memory Sectors

3584 ꢀ 24-Bit, 256 ꢀ 24-Bit, 256 ꢀ 24-Bit

Low-Cost Pin-Compatible ROM Option

16-Bit Watchdog Timer

Programmable 16-Bit Internal Timer with Prescaler

Two Double Buffered Serial Ports with SPI Mode Support

Integrated Power-On Reset Function

Three-Phase 16-Bit PWM Generation Unit:

16-Bit Center-Based PWM Generator

Programmable PWM Pulsewidth

Edge Resolution to 50 ns

AC Induction Motors (ACIM)

APPLICATIONS

Refrigerator and Air Conditioner Compressor

Washing Machines

153 Hz Minimum Switching Frequency

Double/Single Duty Cycle Update Mode Control

Industrial Variable Speed Drives

HVAC

FUNCTIONAL BLOCK DIAGRAM

MOTOR CONTROL PERIPHERALS

MEMORY BLOCK

ADSP-21xx BASE

ARCHITECTURE

3

ADC SUBSYSTEM

3

PROGRAM PROGRAM

ROM

FLASH

4K x 24

I

AMP

SENSE

AND TRIP

DATA

4K x 24

ADDRESS

V

DATA

REF

6

PROGRAM

ANALOG

GENERATORS

PROGRAM

MEMORY

512 x 16

RAM

2.5V

INPUTS

16-BIT

THREE-

PHASE

PWM

SEQUENCER

512 x 24

DAG 1 DAG 2

SHA

TIMERS

PROGRAM MEMORY ADDRESS

DATA MEMORY ADDRESS

PROGRAM MEMORY DATA

DATA MEMORY DATA

ARITHMETIC UNITS

SHIFTER

SERIAL PORT

2 x 16-BIT

AUX

WATCH-

DOG

POR

TIMER

PIO

ALU MAC

SPORT 0

SPORT 1

PWM

TIMER

2

9

DashDSP is a trademark of Analog Devices, Inc.

7

REV. 0

MULTIPLEXED ON EXTERNAL PINS

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat

may result from its use. No license is granted by implication or otherwise

under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781/329-4700

Fax: 781/326-8703

www.analog.com

(V_DD= 5%, GND = 0 V. T_A= –40ꢁC to +85ꢁC. CLKIN = 10 MHz, unless

ADMCF341–SPECIFICATIONS ^{otherwise noted.)}

ANALOG-TO-DIGITAL CONVERTER

Parameter

Min

Typ

Max

Unit

Conditions/Comments

Signal Input

0.3

3.5

12

4

V

VAUX0, VAUX1, VAUX2

Resolution¹

Bits

mV

ns

mA

Linearity Error²

3

0

600

Zero Offset³

–32

–10

+7

Comparator Delay

ADC High Level Input Current²

ADC Low Level Input Current²

+10

V_IN= 3.5 V

V_IN= 0.0 V

NOTES

¹Resolution varies with PWM switching frequency (double update mode) 78.1 kHz = 8 bits, 4.9 kHz = 12 bits.

²2.44KHz sample frequency, VAUX0, VAUX1, VAUX2.

³Extrapolated point outside of operating range. 2.44KHz sample frequency.

Specifications subject to change without notice.

I_SENSEAMPLIFIER–TRIP

Parameter

Min

Typ

Max

Unit

Conditions/Comments

I_SENSESignal Operating Range

–400

–800

–2.6

+400

+800

–2.34

5.5

mV

%

Bits

V

%

dB

mA

kW

mV

ms

I

_SENSESignal Input Range

I_SENSEGain

–2.51

V_IN= –400 mV to +400 mV

I

_SENSEGain Channel Matching

_SENSEGain Stability¹

0.8

9

1.87

2.1

51

54

–40

–53

I_SENSELinearity²

8

1.68

I

_SENSEInternal Offset Voltage²

_SENSEInternal Offset Stability²

2.1

I_SENSESignal-to-Noise Ratio (SNRD)³

I

_SENSESignal-to-Noise Ratio Less Distortion

(SNR)³

I

_SENSETotal Harmonic Distortion³

_SENSEInput Current

–130

+10

V_IN= –400 mV to +400 mV

I_SENSEInput Resistance

TRIP Threshold Low

11.5

–690

+430

–430

+690

TRIP Threshold High

TRIP Minimum Pulsewidth⁴

5

NOTES

¹Variation of gain with V_DDand temperature.

²V_IN= –400 mV to +400 mV.

³f_IN= 1 kHz sine wave, V_IN= –400 mV to +400 mV, f_S= 4 kHz.

⁴High or low trip threshold.

CURRENT SOURCE¹

Parameter

Min

Typ

Max

Unit

Conditions/Comments

Programming Resolution

Tuned Current ²

3

109

Bits

mA

91

100

NOTES

¹For ADC calibration.

²0.3 V to 3.5 V I_CONSTvoltage.

–2–

REV. 0

ADMCF341

VOLTAGE REFERENCE

Parameter

Min

Typ

Max

Unit

Conditions/Comments

Voltage Level (V_REF

Drift

)

2.44

2.50

110

2.55

V

–40∞C to +85∞C

ppm/∞C

Speciﬁcations subject to change without notice.

POWER-ON RESET

Parameter

Min

Typ

Max

Unit

Conditions/Comments

Reset Threshold

Hysteresis

Reset Active Timeout Period

3.20

3.65

100

3.2*

4.10

V

mV

ms

*2¹⁶CLKOUT cycles.

Speciﬁcations subject to change without notice.

ELECTRICAL CHARACTERISTICS

Symbol

Parameter

Min

Typ

Max

Unit

Conditions/Comments

V_IL

V_IH

V_OL

V_OH

I_IL

I_IH

I_OZH

I_OZL

I_DD

Low Level Input Voltage

0.8

V

High Level Input Voltage

2

Low Level Output Voltage¹

Low Level Output Voltage²

High Level Output Voltage

0.4

0.8

I_OL= 2 mA

I_OH= 0.5 mA

V_IN= 0 V

4

–100

–10

V

Low Level Input Current RESET Pin³

Low Level Input Current

mA

V_IN= 0 V

High Level Input Current RESET Pin³

High Level Input Current⁴

30

100

10

V_IN= V_DD

V_IN= 0 V

High Level Input Current

High Level Three-State Leakage Current⁵

Low Level Three-State Leakage Current⁵

Supply Current (Idle)⁶

100

–10

55

135

V_DD= 5.25 V

Supply Current (Dynamic)⁶

NOTES

¹Output pins PIO0-PIO8, AH, AL, BH, BL, CH, CL.

²XTAL pin.

³Internal pull-up, RESET.

⁴Internal pull-down, PWMTRIP, PIO0-PIO8.

⁵Three stateable pins, DT1, RFS1, TFS1, SCLK1.

⁶Outputs not switching.

Speciﬁcations subject to change without notice.

REV. 0

–3–

ADMCF341

SPECIFICATIONS (continued)

FLASH MEMORY

Parameter

Min

Typ

Max

Unit

Conditions/Comments

Endurance

Data Retention

Program and Erase Operating Temperature

Read Operating Temperature

10,000

15

0

Cycles Cycle = Erase/Program/Verify

Years

∞C

85

+85

–40

Speciﬁcations subject to change without notice.

TIMING PARAMETERS

Parameter

Min

Max

Unit

Clock Signals

Signal t_CKis defined as 0.5 t_CKIN. The ADMCF341 uses an input clock with

a frequency equal to half the instruction rate; a 10 MHz input clock (which is

equivalent to 100 ns) yields a 50 ns processor cycle (equivalent to 20 MHz).

When t_CKvalues are within the range of 0.5 t_CKINperiod, they should be

substituted for all relevant timing parameters to obtain specification value as

in the following example:

t_CKH= 0.5 t_CK-10 ns = 0.5 ¥ 50 ns -10 ns = 15 ns

Timing Requirements:

t_CKIN

t_CKIL

t_CKIH

CLKIN Period

CLKIN Width Low

CLKIN Width High

100

20

150

20

ns

Switching Characteristics:

t_CKL

CLKOUT Width Low

0.5 t_CK– 10

0

ns

t_CKH

t_CKOH

CLKOUT Width High

CLKIN High to CLKOUT High

Control Signals

Switching Characteristics

t_RSP

RESET Width Low

5 t_CK

*

ns

PWM Shutdown Signals

Switching Characteristics

t_PWMTPWPWMTRIP Width Low

t_CK

*Applies after power-up sequence is complete.

Specifications subject to change without notice.

t_CKIN

t_CKIH

CLKIN

t_CKIL

t_CKOH

t_CKH

CLKOUT

t_CKL

Figure 1. Clock Signals

–4–

REV. 0

ADMCF341

TIMING PARAMETERS

Parameter

Min

Max

Unit

Serial Ports

Timing Requirements

t_SCK

t_SCS

t_SCH

t_SCP

SCLK Period

100

15

20

ns

DR/TFS/RFS Setup before SCLK Low

DR/TFS/RFS Hold after SCLK Low

SCLK_INWidth

40

Switching Characteristics

t_CC

CLKOUT High to SCLK_OUT

0.25 t_CK

0

0.25 t_CK+ 20

ns

t_SCDE

t_SCDV

t_RH

SCLK High to DT Enable

SCLK High to DT Valid

TFS/RFS_OUTHold after SCLK High

TFS/RFS_OUTDelay from SCLK High

DT Hold after SCLK High

SCLK High to DT Disable

TFS (Alt) to DT Enable

TFS (Alt) to DT Valid

RFS (Multichannel, Frame Delay Zero) to DT Valid

30

0

t_RD

t_SCDH

t_SCDD

t_TDE

t_TDV

t_RDV

25

30

Specifications subject to change without notice.

CLKOUT

SCLK

t_CC

t_SCK

t_SCP

t_SCSt_SCH

t_SCP

DR

RFS

TFS

IN

t_RD

t_RH

RFS

TFS

OUT

t_SCDD

t_SCDV

t_SCDH

t_SCDE

DT

t_TDE

t_TDV

TFS

(ALTERNATE

FRAME MODE)

t_RDV

RFS

(MULTICHANNEL MODE,

FRAME DELAY 0 [MFD = 0])

Figure 2. Serial Port Timing

REV. 0

–5–

ADMCF341

ABSOLUTE MAXIMUM RATINGS*

PIN FUNCTION DESCRIPTIONS

Supply Voltage (V_DD

) . . . . . . . . . . . . . . . . . . –0.3 V to +7.0 V

Mnemonic

Pin Type

Supply Voltage (AV_DD) . . . . . . . . . . . . . . . . . –0.3 V to +7.0 V

Input Voltage . . . . . . . . . . . . . . . . . . . . . –0.3 V to V_DD+0.3 V

Output Voltage Swing . . . . . . . . . . . . . . –0.3 V to V_DD+0.3 V

Operating Temperature Range (Ambient) . . . –40∞C to +85∞C

Storage Temperature Range . . . . . . . . . . . . –65∞C to +150∞C

Lead Temperature (5 sec) . . . . . . . . . . . . . . . . . . . . . . . 280∞C

1

2

3

4

5

6

7

8

PORTA6/DR1

PORTA5/(FL1/DT1)

PORTA4/(SCLK1/SCLK0)

PORTA3/TFS0

PORTA2/RFS0

PORTA1/DT0

PORTA0/DR0

CLKIN

I/O

I

O

SUP

I

*Stresses greater than those listed may cause permanent damage to the device.

These are stress ratings only; functional operation of the device at these or any

other conditions greater than those indicated in the operational sections of this

speciﬁcation is not implied. Exposure to absolute maximum rating conditions for

extended periods may affect device reliability.

9

XTAL

V_DD

PWMTRIP

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

I_SENSE

3

PIN CONFIGURATION

I

_SENSE2

_SENSE1

I

VAUX0

VAUX1

VAUX2

I_CONST

GND

RESET

CH

CL

BH

BL

AH

AL

1

2

3

4

PORTA6/DR1

PORTA5/(FL1/DT1)

PORTA4/(SCLK1/SCLK0)

PORTA3/TFS0

PORTA2/RFS0

PORTA1/DT0

28 PORTA7/(AUX1/PWMSYNC)

PORTA8/(AUX0/CLKOUT)

27

26

25

24

23

22

21

AL

AH

BL

BH

CL

CH

O

GND

I

O

5

6

ADMCF341

PORTA0/DR0

7

TOP VIEW

(Not to Scale)

CLKIN

8

XTAL

9

20 RESET

V

GND

19

10

DD

I

PWMTRIP 11

18

17

CONST

VAUX2

12

I

3

SENSE

PORTA8/(AUX0/CLKOUT)

PORTA7/(AUX1/PWMSYNC)

I/O

16 VAUX1

VAUX0

13

14

I

2

1

SENSE

15

SENSE

ORDERING GUIDE

Temperature

Range

Instruction

Rate

Package

Description

Package

Option

Model

ADMCF341BR

ADMCF341-EVALKIT

–40∞C to +85∞C

N/A

20 MHz

N/A

28-Lead Wide Body (SOIC)

Development Tool Kit

R-28

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily

accumulate on the human body and test equipment and can discharge without detection. Although the

ADMCF341 features proprietary ESD protection circuitry, permanent damage may occur on devices

subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended

to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

–6–

REV. 0

ADMCF341

GENERAL DESCRIPTION

to produce high accuracy PWM signals with minimal processor

overhead. The ADMCF341 also contains two 16-bit auxiliary

PWM timer outputs and nine lines of digital I/O.

The ADMCF341 is a low-cost, single-chip DSP-based control-

ler, suitable for permanent magnet synchronous motors, ac

induction motors, and brushless dc motors. The ADMCF341

integrates a 20 MHz, fixed-point DSP core with a complete set

of motor control and system peripherals that permits fast,

efficient development of motor controllers.

Because the ADMCF341 has a limited number of pins, functions

such as the auxiliary PWM timers and the serial communication

ports are multiplexed with the nine programmable digital input/

output (PIO) pins. The pin functions can be independently

selected to allow maximum flexibility for different applications.

The DSP core of the ADMCF341 is completely code-compatible

with the ADSP-21xx DSP family and combines three computa-

tional units, data address generators, and a program sequencer.

The computational units are an ALU, a multiplier/accumulator

(MAC), and a barrel shifter. There are special instructions for

bit manipulation, multiplication (ϫ squared), biased rounding,

and global interrupt masking. The system peripherals are the

power-on reset circuit (POR), the watchdog timer, and two

synchronous serial ports. The serial ports are configurable and

double buffered, with hardware support for UART, SCI, and

SPI port emulation. The ADMCF341 provides 512 ϫ 24-bit

program memory RAM, 4K ϫ 24-bit program memory ROM,

4K ϫ 24-bit program FLASH memory, and 512 ϫ 16-bit data

memory RAM. The user code can be stored and executed from

the flash memory. The program and data memory RAM can be

used for dynamic data storage or can be loaded through the

serial port from an external device as in other ADMCxxx family

parts. The program memory ROM contains a monitor function

as well as useful routines for erasing, programming, and verifying

the flash memory.

DSP CORE ARCHITECTURE OVERVIEW

Figure 3 is an overall block diagram of the DSP core of the

ADMCF341. The flexible architecture and comprehensive

instruction set allow the processor to perform multiple opera-

tions in parallel. In one processor cycle (50 ns with a 10 MHz

CLKIN) the DSP core can:

∑

Generate the next program address

Fetch the next instruction

Perform one or two data moves

Update one or two data address pointers

Perform a computational operation

This all takes place while the processor continues to:

∑

Receive and transmit through the serial ports

Decrement the interval timer

Generate three-phase PWM waveforms for a power inverter

Generate two signals using the 16-bit auxiliary PWM timers

Acquire four analog signals

The motor control peripherals of the ADMCF341 provide a

12-bit analog data acquisition system with six analog input

channels with three dedicated I_SENSEinputs (combining internal

amplification, sampling, and overcurrent PWM shutdown

features) and an internal voltage reference. In addition, a three-

phase, 16-bit, center-based PWM generation unit can be used

Decrement the watchdog timer

INSTRUCTION

REGISTER

FLASH

PROGRAM

MEMORY

4K ꢀ 24

PM ROM

DM RAM

4K ꢀ 24

512 ꢀ 16

DATA

ADDRESS

GENERATOR

#1

DATA

ADDRESS

GENERATOR

#2

PROGRAM

PM RAM

SEQUENCER

512 ꢀ 24

14

PMA BUS

DMA BUS

PMD BUS

DMD BUS

24

BUS

EXCHANGE

16

CONTROL

LOGIC

TIMER

INPUT REGS

ALU

INPUT REGS

SHIFTER

MAC

TRANSMIT REG

RECEIVE REG

COMPANDING

CIRCUITRY

OUTPUT REGS

16

SERIAL

PORT

R BUS

6

Figure 3. DSP Core Block Diagram

–7–

REV. 0

ADMCF341

The processor contains three independent computational units:

the arithmetic and logic unit (ALU), the multiplier/accumulator

(MAC), and the shifter. The computational units process 16-bit

data directly and have provisions to support multiprecision

computations. The ALU performs a standard set of arithmetic

and logic operations as well as provides support for division

primitives. The MAC performs single-cycle multiply, multiply/add,

and multiply/subtract operations with 40 bits of accumulation.

The shifter performs logical and arithmetic shifts, normalization,

denormalization, and derive-exponent operations. The shifter

can be used to efficiently implement numeric format control,

including floating-point representations. The internal result (R)

bus directly connects the computational units so that the output

of any unit may be the input of any unit on the next cycle.

modes of operation. Serial port 1 (SPORT1) is available with a

limited number of I/Os. It is mainly intended for codebooting to

serial ROMs (SROM) and support of the debugging tools.

SPORT0 and SPORT1 can generate an internal programmable

serial clock or accept an external serial clock.

A programmable interval counter is also included in the DSP

core and can be used to generate periodic interrupts. A 16-bit

count register (TCOUNT) is decremented every n processor

cycles, where n – 1 is a scaling value stored in the 8-bit TSCALE

register. When the value of the counter reaches zero, an inter-

rupt is generated, and the count register is reloaded from a

16-bit period register (TPERIOD).

The ADMCF341 instruction set provides flexible data moves

and multifunction (one or two data moves with a computation)

instructions. Each instruction is executed in a single 50 ns

processor cycle (for a 10 MHz CLKIN). The ADMCF341

assembly language uses an algebraic syntax for ease of coding

and readability. A comprehensive set of development tools

supports program development. For further information on the

DSP core, refer to the ADSP-2100 Family User’s Manual, Third

Edition, with particular reference to the ADSP-2171.

A powerful program sequencer and two dedicated data address

generators ensure efficient delivery of operands to these compu-

tational units. The sequencer supports conditional jumps and

subroutine calls and returns in a single cycle. With internal loop

counters and loop stacks, the ADMCF341 executes looped code

with zero overhead; no explicit jump instructions are required to

maintain the loop.

Two data address generators (DAGs) provide addresses for

simultaneous dual operand fetches from data memory and pro-

gram memory. Each DAG maintains and updates four address

pointers (I registers). Whenever the pointer is used to access

data (indirect addressing), it is post-modified by the value in

one of four modifications (M registers). A length value may be

associated with each pointer (L registers) to implement auto-

matic modulo addressing for circular buffers. The circular

buffering feature is also used by the serial ports for automatic

data transfers to and from on-chip memory. DAG1 generates

only data memory addresses and provides an optional bit-reversal

capability. DAG2 may generate either program or data memory

addresses but has no bit-reversal capability. Efficient data trans-

fer is achieved with the use of five internal buses:

SERIAL PORTS

The ADMCF341 incorporates two complete synchronous serial

ports (SPORT1 and SPORT0) for serial communication and

multiprocessor communication.

Following is a brief list of capabilities of the ADMCF341

SPORTs. Refer to the ADSP-2100 Family User’s Manual, Third

Edition, for further details.

∑

SPORTs are bidirectional and have a separate, double-buff-

ered transmit and receive section.

SPORTs use an external serial clock or generate their own

serial clock internally.

SPORTs have independent framing for the receive and

transmit sections. Sections run in a frameless mode or with

frame synchronization signals internally or externally gener-

ated. Frame synchronization signals are active high or

inverted, with either of two pulsewidths and timings.

∑

Program memory address (PMA) bus

Program memory data (PMD) bus

Data memory address (DMA) bus

Data memory data (DMD) bus

Result (R) bus

∑

SPORTs support serial data word lengths from 3 bits to

16 bits and provides optional A-law and m-law companding

according to ITU (formerly CCITT) recommendation

G.711.

Program memory can store both instructions and data, permit-

ting the ADMCF341 to fetch two operands in a single cycle—

one from program memory and one from data memory. The

ADMCF341 can fetch an operand from on-chip program

memory and the next instruction in the same cycle. The

ADMCF341 writes data from its 16-bit registers to the 24-bit

program memory using the PX register to provide the lower 8

bits. When it reads data (not instructions) from 24-bit program

memory to a 16-bit data register, the lower 8 bits are placed in

the PX register.

∑

SPORT receive and transmit sections can generate unique

interrupts on completing a data word transfer.

SPORTs can receive and transmit an entire circular buffer

of data with only one overhead cycle per data word. An

interrupt is generated after a data buffer transfer.

∑

SPORT0 has a multichannel interface to selectively receive

and transmit a 24-word, or 32-word, timedivision multi-

plexed, serial bitstream.

The ADMCF341 can respond to a number of distinct DSP

core and peripheral interrupts. The DSP interrupts comprise a

serial port receive interrupt, a serial port transmit interrupt, a

timer interrupt, and two software interrupts. Additionally, the

motor control peripherals include two PWM interrupts and a

PIO interrupt.

SPORT0 can be configured as an SPI port (master mode

only). The clock phase and polarity are programmable

through the MODECTRL register.

SPORT1 is the default port for program/data memory boot

loading and for development tools interface. The DT1/FL1

pin can be configured as SROM/E²PROM reset signal.

Serial port 0 (SPORT0) provides a complete synchronous serial

interface with optional companding in hardware and a wide

variety of framed and unframed data transmit and receive

–8–

REV. 0

ADMCF341

PIN FUNCTION DESCRIPTION

Table II. Program Memory Map

The ADMCF341 is available in a 28-lead SOIC package.

Table I describes the pins.

Memory

Type

Address Range

Function

Table I. Pin List

0x0000–0x002F

0x0030–0x01FF

0x0200–0x07FF

0x0800–0x17FF

0x1800–0x1FFF

0x2000–0x20FF

RAM

Internal Vector Table

User Program Memory

Reserved

Reserved Program Memory

Reserved

User Program Memory

Sector 0

User Program Memory

Sector 1

User Program Memory

Sector 2

Pin Group

Name

No. of Input/

Pins

Output Function

ROM

RESET

1

2

I

Processor Reset Input

SPORT1¹

I/O

Serial Port 1 Pins (DT1/FL1,

DR1, SCLK1/SCLK0²)

Serial Port 0 Pins (DT0, DR0

TFSO, SCLK1/SCLK0²)

Processor Clock Output

External Clock or Quartz

Crystal Connection Point

Digital I/O Port Pins

FLASH

SPORT0¹

5

I/O

0x2100–0x21FF

0x2200–0x2FFF

0x3000–0x3FFF

CLKOUT

CLKIN, XTAL

1¹

2

I/O

I, O

Reserved

PORTA0–

PORTA8¹

AUX0–AUX1¹

AH–CL

PWMTRIP

I_SENSE1–

9

I/O

Table III. Data Memory Map

Memory

2

6

1

3

O

I

Auxiliary PWM Outputs

PWM Outputs

PWM Trip Signal

I_SENSEInputs

Address Range

Type

Function

I

0x0000–0x1FFF

0x2000–0x20FF

0x2100–0x37FF

0x3800–0x39FF

0x3A00–0x3BFF

0x3C00–0x3FFF

Reserved

Memory Mapped Registers

Reserved

User Data Memory

Reserved

Memory Mapped Registers

I_SENSE

3

VAUX0–VAUX2

I_CONST

3

1

I

O

Auxiliary Analog Inputs

ADC Constant Current

Source

Power Supply

Ground

RAM

V_DD

GND

1

I

NOTES

¹Multiplexed pins, individually selectable through PORTA_SELECT

and PORTA_DATA registers.

FLASH MEMORY SUBSYSTEM

The ADMCF341 has 4K ϫ 24-bits of user-programmable,

nonvolatile flash memory. A flash programming utility is pro-

vided with the development tools, which perform the basic

device programming operations: erase, program, and verify.

²SCLK1/SCLK0 multiplexed signals. Selectable through MODECTRL

Register Bit 4.

INTERRUPT OVERVIEW

The flash memory array is portioned into three asymmetrically

sized sectors of 256 words, 256 words, and 3584 words, labeled

sector 0, sector 1, and sector 2, respectively. These sectors are

mapped into external program memory address space.

The ADMCF341 can respond to 18 different interrupt sources

with minimal overhead, seven of which are internal DSP core

interrupts and 11 from the motor control peripherals. The

seven DSP core interrupts are SPORT1 receive (or IRQ0) and

transmit (or IRQ1), SPORT0 receive and transmit, the internal

timer, and two software interrupts. The motor control periph-

eral interrupts are the nine programmable I/Os and two from

the PWM (PWMSYNC pulse and PWMTRIP). All motor

control interrupts are multiplexed into the DSP core through

the peripheral IRQ2 interrupt. The interrupts are internally

prioritized and individually maskable. A detailed description of the

entire interrupt system of the ADMCF341 is presented later,

following a more detailed description of each peripheral block.

Four flash memory interface registers are connected to the DSP.

These 16-bit registers are mapped into the register area of data

memory space. They are named flash memory control register

(FMCR), flash memory address register (FMAR), flash memory

data register low (FMDRL), and flash memory data register

high (FMDRH). These registers are diagrammed later in this

data sheet. They are used by the flash memory programming

utility. The user program may read these registers, but should

not modify them directly. The flash programming utility pro-

vides a complete interface to the flash memory.

MEMORY MAP

It should be noted that the core accesses flash memory through

an external memory interface that multiplexes the program

memory and data memory buses into a single external bus.

Therefore, if more than one external transfer must be made in

the same instruction, there will be at least an overhead cycle

required.

The ADMCF341 has two distinct memory types: program and

data. In general, program memory contains user code and coef-

ficients, while the data memory is used to store variables and

data during program execution. Three kinds of program

memory are provided on the ADMCF341: RAM, ROM, and

FLASH. The motor control peripherals are memory mapped

into a region of the data memory space starting at 0x2000. The

complete program and data memory maps are given in Tables II

and III, respectively.

REV. 0

–9–

ADMCF341

Special Flash Registers

22pF

CLKOUT

XTAL

The flash module has four nonvolatile 8-bit registers called

special flash registers (SFRs) that are accessible independent of

the main flash array, via the flash programming utility. These

registers are for general-purpose, nonvolatile storage. When

erased, the special flash registers contain all 0s. To read special

flash registers from the user program, call the read_reg routine

contained in ROM. Refer to the ADMCF34x DSP Motor Con-

troller Developers Reference Manual for an example.

10MHz

CLKIN

22pF

ADMCF341

RESET

Figure 4. Basic System Configuration

Clock Signals

Boot-from-Flash Code

A security feature is available in the form of a code that, when

set, causes the processor to execute the program in flash

memory at power-up or reset. In this mode, the flash program-

ming utility and debugger are unable to communicate with the

ADMCF341. Consequently, the contents of the flash memory

can be neither programmed nor read.

The ADMCF341 can be clocked either by a crystal or a TTL-

compatible clock signal. For normal operation, the CLKIN

input cannot be halted, changed during operation, or operated

below the specified minimum frequency. If an external clock is

used, it should be a TTL-compatible signal running at half the

instruction rate. The signal is connected to the CLKIN pin of

the ADMCF341. In this mode, with an external clock signal,

the XTAL pin must be left unconnected. The ADMCF341 uses

an input clock with a frequency equal to half the instruction

rate; a 10 MHz input clock yields a 50 ns processor cycle (which

is equivalent to 20 MHz). Normally, instructions are executed

in a single processor cycle. All device timing is relative to the

internal instruction rate, which is indicated by the CLKOUT

signal when enabled.

The boot-from-flash code may be set via the flash programming

utility, when the user’s program is thoroughly tested and loaded

into flash program memory at address 0x2200. The user’s program

must contain a mechanism for clearing the boot-from-flash code

if reprogramming the flash memory is desired. The only way to

clear boot-from-flash is from within the user program, by calling

the flash_init or auto_erase_reg routines that are included in the

ROM. The user program must be signaled in some way to call

the necessary routine to clear the boot-from-flash code. An

example would be to detect a high level on a PIO pin during

startup initialization and then call the flash_init or auto_erase_reg

routine. The flash_init routine will erase the entire user program

in flash memory before clearing the boot-from-flash code, thus

ensuring the security of the user program. If security is not a

concern, the auto_erase_reg routine can be used to clear the

boot-from-flash code while leaving the user program intact.

Because the ADMCF341 includes an on-chip oscillator feed-

back circuit, an external crystal may be used instead of a clock

source, as shown in Figure 4. The crystal should be connected

across the CLKIN and XTAL pins, with two capacitors as

shown in Figure 4. A parallel-resonant, fundamental frequency,

microprocessor grade crystal should be used. A clock output

signal (CLKOUT) is generated by the processor at the

processor’s cycle rate of twice the input frequency.

Refer to the ADMCF34x DSP Motor Controller Developer’s Refer-

ence Manual for further instructions and an example of using the

boot-from-flash code.

Reset

The ADMCF341 DSP core and peripherals must be correctly

reset when the device is powered up to assure proper unitiza-

tion. The ADMCF341 contains an integrated power-on-reset

(POR) circuit that provides a complete system reset on power-

up and power-down. The POR circuit monitors the voltage on

the ADMCF341 VDD pin and holds the DSP core and periph-

erals in reset while VDD is less than the threshold voltage level,

VRST. When this voltage is exceeded, the ADMCF341 is held

in reset for an additional 216 DSP clock cycles (T_RSTin Fig-

ure 5). During this time (T_RST), the supply voltage must reach

the recommended operating condition. On power-down, when

the voltage on the VDD pin falls below V_RST–V_HYST, the

ADMCF341 will be reset. Also, if the external RESET pin is

actively pulled low at any time after power-up, a complete hard-

ware reset of the ADMCF341 is initiated.

FLASH PROGRAM BOOT SEQUENCE

On power-up or reset, the processor begins instruction execu-

tion at address 0x0800 of internal program ROM. The ROM

monitor program that is located there checks the boot-from-

flash code. If that code is set, the processor jumps to location

0x2200 in external flash program memory, where it expects to

find the user’s application program.

If the boot-from-flash code is not set, the monitor attempts to

boot from an external device as described in the ADMCF34x

DSP Motor Controller Developers Reference Manual.

SYSTEM INTERFACE

Figure 4 shows a basic system configuration for the ADMCF341

with an external crystal.

V

RST

V

– V

HYST

RST

V

DD

T_RST

RESET

Figure 5. Power-On Reset Operation

–10–

REV. 0

ADMCF341

The ADMCF341 sets all internal stack pointers to the empty

stack condition, masks all interrupts, clears the MSTAT register,

and performs a full reset of all of the motor control peripherals.

Following a power-up, it is possible to initiate a DSP core and

motor control peripheral reset by pulling the RESET pin low.

The RESET signal must be the minimum pulsewidth specifica-

tion, t_RSP. Following the reset sequence, the DSP core starts

executing code from the internal PM ROM located at 0x0800.

PWM switching patterns for control of brushless dc motors

(BDCM), including electronically commutated motors (ECM).

The six PWM output signals consist of three high side drive

signals (AH, BH, and CH) and three low side drive signals

(AL, BL, and CL). The switching frequency, dead time, and

minimum pulsewidths of the generated PWM patterns are pro-

grammable using, respectively, the PWMTM, PWMDT, and

PWMPD registers. In addition, three registers (PWMCHA,

PWMCHB, and PWMCHC) control the duty cycles of the

three pairs of PWM signals.

DSP Control Registers

The DSP core has a system control register, SYSCNTL,

memory-mapped at DM (0x3FFF). SPORT1 must be configured

as a serial port by setting Bit 10. SPORT0 and SPORT1 are

enabled by setting Bit 11 and Bit 12.

Each of the six PWM output signals can be enabled or disabled

by separate output enable bits of the PWMSEG register. In

addition, three control bits of the PWMSEG register permit

crossover of the two signals of a PWM pair for easy control of

ECM or BDCM. In crossover mode, the high side PWM signals

are diverted to the complementary low side output and the low

side signals are diverted to the corresponding high side outputs.

The DSP core has a wait state control register, MEMWAIT,

memory-mapped at DM (0x3FFE). The default value of this

register is 0xFFFF. For proper operation of the ADMCF341,

this register must always contain the value 0x8000. This value

sets the minimum access time to the program memory.

In many applications, there is a need to provide an isolation

barrier in the gate-drive circuits that turn on the power devices

of the inverter. In general, there are two common isolation

techniques: optical isolation using optocouplers, and trans-

former isolation using pulse transformers. The PWM controller

of the ADMCF341 permits mixing of the output PWM signals

with a high-frequency chopping signal to permit an easy inter-

face to such pulse transformers. The features of this gate-drive

chopping mode can be controlled by the PWMGATE register.

There is an 8-bit value within the PWMGATE register that

directly controls the chopping frequency. In addition, high-

frequency chopping can be independently enabled for the high

side and the low side outputs using separate control bits in the

PWMGATE register.

The configurations of both the SYSCNTL and MEMWAIT regis-

ters of the ADMCF341 are shown at the end of the data sheet.

THREE-PHASE PWM CONTROLLER

Overview

The PWM generator block of the ADMCF341 is a flexible,

programmable three-phase PWM waveform generator that can

be programmed to generate the required switching patterns to

drive a three-phase voltage source inverter for ac induction

motors (ACIM) or permanent magnet synchronous motors

(PMSM). In addition, the PWM block contains special func-

tions that considerably simplify the generation of the required

PWM CONFIGURATION

REGISTERS

PWM DUTY CYCLE

REGISTERS

PWMTM (15...0)

PWMDT (9...0)

PWMCHA (15...0)

PWMCHB (15...0)

PWMCHC (15...0)

PWMPD (9...0)

PWMSYNCWT (7...0)

MODECTRL (6)

PWMSEG (8...0)

PWMGATE (9...0)

AH

AL

BH

BL

CH

CL

THREE-PHASE

OUTPUT

CONTROL

UNIT

GATE

DRIVE

UNIT

PWM TIMING

UNIT

SYNC

CLK

SYNC RESET

CLK

CLKOUT

PWMSYNC

TO INTERRUPT

CONTROLLER

PWMTRIP

OR

I

1

SENSE

PWMSWT (0)

PWM SHUTDOWN CONTROLLER

OVER-

CURRENT

TRIP

2

3

SENSE

ANALOG BLOCK

Figure 6. Overview of the PWM Controller of the ADMCF341

–11–

REV. 0

ADMCF341

The PWM generator is capable of operating in two distinct modes:

single update mode and double update mode. In single update

mode, the duty cycle values are programmable only once per

PWM period, so that the resultant PWM patterns are symmetrical

about the midpoint of the PWM period. In double update mode,

a second updating of the PWM duty cycle values is implemented

at the midpoint of the PWM period. In this mode, it is possible

to produce asymmetrical PWM patterns that produce lower

harmonic distortion in three-phase PWM inverters. This tech-

nique also permits the closed-loop controller to change the

average voltage applied to the machine winding at a faster rate,

allowing wider closed-loop bandwidths to be achieved. The

operating mode of the PWM block (single or double update

mode) is selected by a control bit in MODECTRL register.

The PWM controller is driven by a clock at the same frequency

as the DSP instruction rate, CLKOUT, and is capable of gener-

ating two interrupts to the DSP core. One interrupt is generated

on the occurrence of a PWMSYNC pulse, and the other is

generated on the occurrence of any PWM shutdown action.

Three-Phase Timing Unit

The 16-bit three-phase timing unit is the core of the PWM

controller and produces three pairs of pulsewidth modulated

signals with high resolution and minimal processor overhead.

There are four main configuration registers (PWMTM,

PWMDT, PWMPD, and PWMSYNCWT) that determine the

fundamental characteristics of the PWM outputs. In addition,

the operating mode of the PWM (single or double update

mode) is selected by bit 6 of the MODECTRL register. These

registers, in conjunction with the three 16-bit duty cycle regis-

ters (PWMCHA, PWMCHB and PWMCHC), control the

output of the three-phase timing unit.

The PWM generator of the ADMCF341 also provides an inter-

nal signal that synchronizes the PWM switching frequency to

the A/D operation. In single update mode, a PWMSYNC pulse

is produced at the start of each PWM period. In double update

mode, an additional PWMSYNC pulse is produced at the mid-

point of each PWM period. The width of the PWMSYNC pulse

is programmable through the PWMSYNCWT register.

PWM Switching Frequency: PWMTM Register

The PWM switching frequency is controlled by the PWM

period register, PWMTM. The fundamental timing unit of

the PWM controller is t_CK= 1/f_CLKOUT, where f_CLKOUTis the

CLKOUT frequency (DSP instruction rate). Therefore, for a

20 MHz CLKOUT, the fundamental time increment is 50 ns.

The value written to the PWMTM register is effectively the

number of t_CKclock increments in half a PWM period. The

required PWMTM value is a function of the desired PWM

switching frequency (f_PWM) and is given by:

The PWM signals produced by the ADMCF341 can be shut off

in a number of different ways. First, there is a dedicated asyn-

chronous PWM shutdown pin, PWMTRIP, which, when

brought LOW, instantaneously places all six PWM outputs in

the OFF state. In addition, PWM shutdown is initiated when

the voltage on any of the input pins (I_SENSE) exceeds the trip

thresholds (high or low) or the input is unconnected (floating).

Because these two hardware shutdown mechanisms are asyn-

chronous, and the associated PWM disable circuitry does not

use clocked logic, the PWM will shut down even if the DSP

clock is not running. The PWM system may also be shut down

from software by writing to the PWMSWT register.

f

CLKOUT

f

CLKIN

PWMTM =

=

2 ¥ f^PWM

PWM

Therefore, the PWM switching period, T_S, can be written as:

T_S= 2 ¥ PWMTM ¥ t_CK

Status information about the PWM system of the ADMCF341

is available to the user in the SYSSTAT register. In particular,

the state of PWMTRIP is available, as well as a status bit that

indicates whether the operation is in the first half or the second

half of the PWM period.

For example, for a 20 MHz CLKOUT and a desired PWM

switching frequency of 10 kHz (T_S= 100 ms), the correct value

to load into the PWMTM register is:

20 ¥10⁶

PWMTM =

= 1000 = 0x3E8

2 ¥10 ¥10³

A functional block diagram of the PWM controller is shown in

Figure 6. The generation of the six output PWM signals on pins

AH to CL is controlled by four important blocks:

The largest value that can be written to the 16-bit PWMTM

register is 0xFFFF = 65,535, which corresponds to a minimum

PWM switching frequency of:

∑

The three-phase PWM timing unit, which is the core of the

PWM controller, generates three pairs of complemented

and dead-time-adjusted center-based PWM signals.

20 ¥10⁶

f_PWM,min

=

= 153 Hz

2 ¥ 65,535

for a CLKOUT frequency of 20 MHz.

∑

The output control unit allows the redirection of the out-

puts of the three-phase timing unit for each channel to

either the high side or the low side output. In addition, the

output control unit allows individual enabling/disabling of

each of the six PWM output signals.

PWM Switching Dead Time: PWMDT Register

The second important PWM block parameter that must be

initialized is the switching dead time. This is a short delay time

introduced between turning off one PWM signal (e.g., AH) and

turning on its complementary signal (e.g., AL). This short time

delay is introduced to permit the power switch being turned off

to completely recover its blocking capability before the comple-

mentary switch is turned on. This time delay prevents a

potentially destructive short-circuit condition from developing

across the dc link capacitor of a typical voltage source inverter.

∑

The GATE drive unit provides the high chopping frequency

and its subsequent mixing with the PWM signals.

The PWM shutdown controller manages the three PWM

shutdown modes (via the PWMTRIP pin, the analog block,

or the PWMSWT register) and generates the correct

RESET signal for the timing unit.

–12–

REV. 0

ADMCF341

Dead time is controlled by the PWMDT register. The dead time

is inserted into the three pairs of PWM output signals. The dead

time, TD, is related to the value in the PWMDT register by:

operation in the first half of each PWM period (between the

rising edge of the original PWMSYNC pulse and the rising edge

of the new PWMSYNC pulse, which is introduced in double

update mode). Bit 3 of the SYSSTAT register is set during the

second half of each PWM period. If required, a user may deter-

mine the status of this bit during a PWMSYNC interrupt

service routine.

PWMDT

T_D= PWMDT ¥ 2 ¥ t_CK= 2 ¥

f_CLKOUT

Therefore, a PWMDT value of 0x00A (= 10), introduces a

1 ms delay between the turn-off of any PWM signal (for example,

AH) and the turn-on of its complementary signal (for example,

AL). The amount of the dead time can therefore be programmed

in increments of 2 t_CK(or 100 ns for a 20 MHz CLKOUT).

The PWMDT register is a 10-bit register. For a CLKOUT

rate of 20 MHz its maximum value of 0x3FF

The advantages of double update mode are that lower harmonic

voltages can be produced by the PWM process and wider

control bandwidths are possible. However, for a given PWM

switching frequency, the PWMSYNC pulses occur at twice the

rate in the double update mode. Because new duty cycle values

must be computed in each PWMSYNC interrupt service rou-

tine, there is a larger computational burden on the DSP in

double update mode.

(= 1023) corresponds to a maximum programmed dead time of:

T_{D max}= 1023¥ 2 ¥ t_CK

Width of the PWMSYNC Pulse: PWMSYNCWT Register

The PWM controller of the ADMCF341 produces an internal

PWM synchronization pulse at a rate equal to the PWM switching

frequency in single update mode and at twice the PWM fre-

quency in double update mode. This PWMSYNC synchronizes

the operation of the PWM unit with the A/D converter system.

The width of this PWMSYNC pulse is programmable by the

PWMSYNCWT register. The width of the PWMSYNC pulse,

T_PWMSYNC, is given by:

= 1023¥ 2 ¥ 50 ¥10^-9sec

= 102 ms

The dead time can be programmed to zero by writing 0 to the

PWMDT register.

PWM Operating Mode: MODECTRL and

SYSSTAT Registers

The PWM controller of the ADMCF341 can operate in two

distinct modes: single update mode and double update mode.

The operating mode of the PWM controller is determined by

the state of Bit 6 of the MODECTRL register. If this bit is

cleared, the PWM operates in the single update mode. Setting

Bit 6 places the PWM in the double update mode. By default,

following either a peripheral reset or power-on, Bit 6 of the

MODECTRL register is cleared. This means that the default

operating mode is single update mode.

T_PWMSYNC= t_CK¥(PWMSYNCWT +1)

which means that the width of the pulse is programmable from

t_CKto 256 t_CK(corresponding to 50 ns to 12.8 ms for a CLKOUT

rate of 20 MHz). Following a reset, the PWMSYNCWT

register contains 0x27 (= 39) so that the default PWMSYNC

width is 2.0 ms.

PWM Duty Cycles: PWMCHA, PWMCHB, PWMCHC

Registers

In single update mode, a single PWMSYNC pulse is produced

in each PWM period. The rising edge of this signal marks the

start of a new PWM cycle and is used to latch new values from

the PWM configuration registers (PWMTM, PWMDT, PWMPD,

and PWMSYNCWT) and the PWM duty cycle registers

(PWMCHA, PWMCHB, and PWMCHC) into the three-phase

timing unit. The PWMSEG register is also latched into the

output control unit on the rising edge of the PWMSYNC pulse.

In effect, this means that the parameters of the PWM signals

can be updated only once per PWM period at the start of each

cycle. Thus, the generated PWM patterns are symmetrical

about the midpoint of the switching period.

The duty cycles of the six PWM output signals are controlled

by the three duty cycle registers, PWMCHA, PWMCHB, and

PWMCHC. The integer value in the register PWMCHA con-

trols the duty cycle of the signals on AH and AL. PWMCHB

controls the duty cycle of the signals on BH and BL, and

PWMCHC controls the duty cycle of the signals on CH and

CL. The duty cycle registers are programmed in integer counts

of the fundamental time unit, t_CK, and define the desired on-time

of the high side PWM signal produced by the three-phase timing

unit over half the PWM period. The switching signals produced

by the three-phase timing unit are also adjusted to incorporate

the programmed dead time value in the PWMDT register.

In double update mode, there is an additional PWMSYNC

pulse produced at the midpoint of each PWM period. The

rising edge of this new PWMSYNC pulse is again used to latch

new values of the PWM configuration registers, duty cycle

registers, and the PWMSEG register. As a result, it is possible

to alter both the characteristics (switching frequency, dead time,

minimum pulsewidth, and PWMSYNC pulsewidth) and the

output duty cycles at the midpoint of each PWM cycle. Conse-

quently, it is possible to produce PWM switching patterns that

are no longer symmetrical about the midpoint of the period

(asymmetrical PWM patterns).

The PWM is center-based. This means that in single update

mode the resulting output waveforms are symmetrical and cen-

tered in the PWMSYNC period. Figure 7 presents a typical

PWM timing diagram illustrating the PWM-related registers

(PWMCHA, PWMTM, PWMDT, and PWMSYNCWT) con-

trol over the waveform timing in both half cycles of the PWM

period. The magnitude of each parameter in the timing diagram

is determined by multiplying the integer value in each register

by t_CK(typically 50 ns). It may be seen in the timing diagram

how dead time is incorporated into the waveforms by moving

the switching edges away from the original values set in the

PWMCHA register.

In double update mode, operation in the first half or the second

half of the PWM cycle is indicated by bit 3 of the SYSSTAT

register. In double update mode, this bit is cleared during

REV. 0

–13–

ADMCF341

PWMCHA PWMCHA

PWMCHA

2

1

AH

AL

2 ꢀ PWMDT

AL

1

2

PWMSYNCWT + 1

PWMSYNC

PWMSYNCWT + 1

1

PWMSYNCWT + 1

2

PWMSYNC

SYSSTAT (3)

PWMTM

1

PWMTM

2

Figure 7. Typical PWM Outputs of Three-Phase

Timing Unit in Single Update Mode

Figure 8. Typical PWM Outputs of Three-Phase

Timing Unit in Double Update Mode

Each switching edge is moved by an equal amount (PWMDT ϫ

t_CK) to preserve the symmetrical output patterns. The

PWMSYNC pulse, whose width is set by the PWMSYNCWT

register, is also shown. Bit 3 of the SYSSTAT register indicates

which half cycle is active. This can be useful in double update

mode, as will be discussed later.

In general, the on-times of the PWM signals in double update

mode are deﬁned by:

T_AH

=

(PWMCHA + PWMCHA₂-

1

PWMDT - PWMDT₂)¥T_CK

1

The resultant on-times of the PWM signals shown in Figure 7

may be written as:

T_AL

=

(PWMTM₁+ PWMTM₂- PWMCHA -

1

T_AH= 2 ¥(PWMCHA- PWMDT)¥ t_CK

PWMCHA₂- PWMDT - PWMDT₂)¥ t_CK

1

T_AL= 2 ¥(PWMTM - PWMCHA - PWMDT)¥ t_CK

T_AH

T_S

The corresponding duty cycles are:

d_AH

=

T_AH

T_S

PWMCHA- PWMDT

PWMCHA + PWMCHA₂

PWMTM₁+ PWMTM₂

PWMDT + PWMDT₂

PWMTM₁+ PWMTM₂

d_AH

=

1

-

PWMTM

T_ALPWMTM - PWMCHA - PWMDT

T_ALPWMTM₁+ PWMTM₂+ PWMCHA

d_AL

=

1

d_AL

=

-

T_S

PWMTM

T_S

PWMTM₁+ PWMTM₂

Obviously, negative values of T_AHand T_ALare not permitted

because the minimum permissible value is zero, corresponding

to a 0% duty cycle. In a similar fashion, the maximum value is

T_S, corresponding to a 100% duty cycle.

PWMCHA₂+ PWMDT + PWMCHA

1

PWMTM₁+ PWMTM₂

because for the completely general case in double update mode,

the switching period is given by:

The output signals from the timing unit for operation in double

update mode are shown in Figure 8. This illustrates a com-

pletely general case where the switching frequency, dead time,

and duty cycle are all changed in the second half of the PWM

period. Of course, the same value for any or all of these quanti-

ties could be used in both halves of the PWM cycle. However, it

can be seen that there is no guarantee that symmetrical PWM

signals will be produced by the timing unit in this double update

mode. Additionally, it is seen that the dead time is inserted into

the PWM signals in the same way as in single update mode.

T_S= (PWMTM₁+ PWMTM₂)¥ t_CK

Again, the values of T_AHand T_ALare constrained to lie between

zero and T_S.

PWM signals similar to those illustrated in Figure 7 and Figure 8

can be produced on the BH, BL, CH, and CL outputs by

programming the PWMCHB and PWMCHC registers in a

manner identical to that described for PWMCHA.

The PWM controller does not produce any PWM outputs until

all of the PWMTM, PWMCHA, PWMCHB, and PWMCHC

registers have been written to at least once. After these registers

have been written, the counters in the three-phase timing unit

are enabled. Writing to these registers also starts the main PWM

timer. If, during initialization, the PWMTM register is written

before the PWMCHA, PWMCHB, and PWMCHC registers,

the ﬁrst PWMSYNC pulse (and interrupt if enabled) will be

generated (1.5 ¥ t_CK¥ PWMTM) seconds after the initial write

to the PWMTM register in single update mode. In double up-

date mode, the ﬁrst PWMSYNC pulse will be generated (t_CK

PWMTM) seconds after the initial write to the PWMTM regis-

ter in single update mode.

¥

–14–

REV. 0

ADMCF341

Effective PWM Resolution

will remain OFF (0% duty cycle). Additionally, the AL signal

will be turned ON for the entire half period (100% duty cycle).

In single update mode, the same values of PWMCHA,

PWMCHB, and PWMCHC are used to deﬁne the on-times in

both half cycles of the PWM period. As a result, the effective

resolution of the PWM generation process is 2 t_CK(or 100 ns

for a 20 MHz CLKOUT), since incrementing one of the duty

cycle registers by one changes the resultant on-time of the asso-

ciated PWM signals by t_CKin each half period (or 2 t_CKfor the

full period).

Output Control Unit: PWMSEG Register

The operation of the output control unit is managed by the 9-bit

read/write PWMSEG register. This register sets two distinct

features of the output control unit that are directly useful in the

control of ECM or BDCM.

The PWMSEG register contains three crossover bits, one for

each pair of PWM outputs. Setting bit 8 of the PWMSEG regis-

ter enables the crossover mode for the AH/AL pair of PWM

signals; setting bit 7 enables crossover on the BH/BL pair of

PWM signals; and setting bit 6 enables crossover on the CH/CL

pair of PWM signals. If crossover mode is enabled for any pair

of PWM signals, the high side PWM signal from the timing unit

(for example, AH) is diverted to the associated low side output

of the output control unit so that the signal will ultimately

appear at the AL pin. Of course, the corresponding low side

output of the timing unit is also diverted to the complementary

high side output of the output control unit so that the signal

appears at pin AH. Following a reset, the three crossover bits

are cleared so that the crossover mode is disabled on all three

pairs of PWM signals.

In double update mode, improved resolution is possible since

different values of the duty cycle registers are used to deﬁne the

on-times in both the ﬁrst and second halves of the PWM period.

As a result, it is possible to adjust the on-time over the whole

period in increments of t_CK. This corresponds to an effective

PWM resolution of t_CKin double update mode (or 50 ns for a

20 MHz CLKOUT).

Table IV. Achievable PWM Resolution in Single and Double

Update Modes

Resolution Single Update Mode

(Bit) (kHz) PWM Frequency (kHz) PWM Frequency

Double Update Mode

8

9

10

11

12

39.1

19.5

9.8

4.9

2.4

78.4

39.1

19.5

9.8

The PWMSEG register also contains six bits (bits 0 to 5) that

can be used to individually enable or disable each of the six

PWM outputs. If the associated bit of the PWMSEG register is

set, the corresponding PWM output is disabled regardless of the

value of the corresponding duty cycle register. This PWM out-

put signal will remain in the OFF state as long as the

corresponding enable/disable bit of the PWMSEG register is

set. The PWM output enable function gates the crossover func-

tion. After a reset, all six enable bits of the PWMSEG register

are cleared, thereby enabling all PWM outputs by default.

4.9

Minimum Pulsewidth: PWMPD Register

In many power converter switching applications, it is desirable

to eliminate PWM switching pulses shorter than a certain width.

It takes a finite time to both turn on and turn off modern power

semiconductor devices. Therefore, if the width of any of the

PWM pulses is shorter than some minimum value, it may be

desirable to completely eliminate the PWM switching for that

particular cycle.

In a manner identical to the duty cycle registers, the PWMSEG

is latched on the rising edge of the PWMSYNC signal so that

changes to this register only become effective at the start of each

PWM cycle in single update mode. In double update mode, the

PWMSEG register can also be updated at the midpoint of the

PWM cycle.

The allowable minimum on-time for any of the six PWM out-

puts for half a PWM period that can be produced by the PWM

controller may be programmed using the PWMPD register. The

minimum on-time is programmed in increments of t_CKso that

the minimum on-time produced for any half PWM period,

T_MIN, is related to the value in the PWMPD register by:

In the control of an ECM, only two inverter legs are switched at

any time, and often the high side device in one leg must be

switched ON at the same time as the low side driver in a second

leg. Therefore, by programming identical duty cycles for two

PWM channels (for example, let PWMCHA = PWMCHB) and

setting bit 7 of the PWMSEG register to cross over the BH/BL

pair of PWM signals, it is possible to turn ON the high side

switch of phase A and the low side switch of phase B at the

same time. In the control of an ECM, one inverter leg (phase C

in this example) is disabled for a number of PWM cycles. This

disable may be implemented by disabling both the CH and CL

PWM outputs by setting bits 0 and 1 of the PWMSEG register.

This is illustrated in Figure 7, where it can be seen that both the

AH and BL signals are identical, because PWMCHA = PWM

CHB, and the crossover bit for phase B is set. In addition, the

other four signals (AL, BH, CH, and CL) have been disabled by

setting the appropriate enable/disable bits of the PWMSEG

register. For the situation illustrated in Figure 9, the appropriate

value for the PWMSEG register is 0x00A7. In ECM operation,

because each inverter leg is disabled for a certain period of time,

the PWMSEG register is changed based upon the position of

the rotor shaft (motor commutation).

T_MIN= PWMPD ¥ t_CK

A PWMPD value of 0x002 defines a permissible minimum

on-time of 100 ns for a 20 MHz CLKOUT.

In each half cycle of the PWM, the timing unit checks the on-

time of each of the six PWM signals. If any of the times is found

to be less than the value specified by the PWMPD register, the

corresponding PWM signal is turned OFF for the entire half

period, and its complementary signal is turned completely ON.

Consider the example where PWMTM = 200, PWMCHA = 5,

PWMDT = 3, and PWMPD = 10 with a CLKOUT of 20 MHz,

while operating in single update mode. For this case, the

PWM switching frequency is 50 kHz and the dead time is

300 ns. The minimum permissible on-time of any PWM signal

over one-half of any period is 500 ns. Clearly, for this example,

the dead-time adjusted on-time of the AH signal for one-half a

PWM period is (5–3) ¥ 50 ns = 100 ns. Because this is less than

the minimum permissible value, output AH of the timing unit

REV. 0

–15–

ADMCF341

PWMCHA = PWMCHB

PWMCHA

AH

2 ꢀ PWMDT

AH

AL

2 ꢀ PWMDT

2

ꢀ PWMDT

2

ꢀ PWMDT

AL

BH

BL

[4

ꢀ (GDCLK+1)]

PWMTM

Figure 10. Typical PWM Signals with High-

Frequency Gate Chopping Enabled on Both

High Side and Low Side Switches. (GDCLK Is

the Integer Equivalent of the Value in Bits 0

to 7 of the PWMGATE Register.)

CH

CL

PWMTM

Figure 9. An Example of PWM Signals Suitable for

ECM Control. PWMCHA = PWMCHB, BH/BL are a

Crossover Pair. AL, BH, CH, and CL Outputs are

Disabled. Operation Is in Single Update Mode.

PWM Shutdown

In the event of external fault conditions, it is essential that the

PWM system be instantaneously shut down. Two methods of

sensing a fault condition are provided by the ADMCF341. For

the ﬁrst method, a low level on the PWMTRIP pin initiates an

instantaneous, asynchronous (independent of DSP clock) shut-

down of the PWM controller. This places all six PWM outputs

in the OFF state, disables the PWMSYNC pulse and associated

interrupt signal, and generates a PWMTRIP interrupt signal.

The PWMTRIP pin has an internal pull-down resistor so that

even if the pin becomes disconnected, the PWM outputs will be

disabled. The state of the PWMTRIP pin can be read from Bit 0

of the SYSSTAT register.

Gate Drive Unit: PWMGATE Register

The gate drive unit of the PWM controller adds features that

simplify the design of isolated gate drive circuits for PWM

inverters. If a transformer-coupled power device gate drive

amplifier is used, the active PWM signal must be chopped at a

high frequency. The PWMGATE register allows the programming

of this high-frequency chopping mode. The chopped active

PWM signals may be required for the high side drivers only, for

the low side drivers only, or for both the high side and low side

switches. Therefore, independent control of this mode for both

high side and low side switches is included with two separate

control bits in the PWMGATE register.

The second method for detecting a fault condition is through

the I_SENSEpins of the analog block of the ADMCF341. When

the voltage at any of the I_SENSEpins exceeds the trip threshold

(high or low), or the I_SENSEpin is in high impedance (floating),

PWMTRIP will be internally pulled low. The negative edge of

the internal PWMTRIP will generate a shutdown in the same

manner as a negative edge on pin PWMTRIP.

Typical PWM output signals with high-frequency chopping

enabled on both high side and low side signals are shown in

Figure 10. Chopping of the high side PWM outputs (AH, BH

and CH) is enabled by setting Bit 8 of the PWMGATE register.

Chopping of the low side PWM outputs (AL, BL, and CL) is

enabled by setting Bit 9 of the PWMGATE register. The high

chopping frequency is controlled by the 8-bit word (GDCLK)

written to Bits 0 to 7 of the PWMGATE register. The period

and the frequency of this high-frequency carrier are:

It is possible through software to initiate a PWM shutdown by

writing to the 1-bit read/write PWMSWT register (0x2061).

Writing to this bit generates a PWM shutdown in a manner

identical to the PWMTRIP or I_SENSEpins. Following a PWM

shutdown, it is possible to determine if the shutdown was gener-

ated from hardware or software by reading the same PWMSWT

register. Reading this register also clears it.

T_CHOP= 4 ¥ GDCLK +1 ¥ t

(

)

[

]

CK

Restarting the PWM after a fault condition is detected requires

clearing the fault and reinitializing the PWM. Clearing the fault

requires PWMTRIP to return to a HIGH state and I_SENSEto

return to a voltage in the I_SENSEtrip level range. After the fault

has been cleared, the PWM can be restarted by writing to registers

PWMTM, PWMCHA, PWMCHB, and PWMCHC. After the

fault is cleared and the PWM registers are initialized, internal

timing of the three-phase timing unit will resume, and the new

duty cycle values will be latched on the next rising edge of

PWMSYNC.

f_CLKOUT

f_CHOP

=

4 ¥ GDCLK +1

(

)

[

]

The GDCLK value may range from 0 to 255, corresponding to

a programmable chopping frequency rate from 19.5 kHz to 5 MHz

for a 20 MHz CLKOUT rate. The gate drive features must

be programmed before operation of the PWM controller and

typically are not changed during normal operation of the PWM

controller. Following a reset, by default, all bits of the

PWMGATE register are cleared so that high-frequency chop-

ping is disabled.

PWM Registers

The conﬁguration of the PWM registers is described at the end

of the data sheet. The parameters of the PWM block are tabu-

lated in Table V.

–16–

REV. 0

ADMCF341

Table V. Fundamental Characteristics of PWM Generation Unit of ADMCF341

Parameter

Min

Typ

Max

Unit

16-BIT PWM TIMER

Counter Resolution

16

100

50

Bits

ns

ms

ns

ms

ns

Hz

ms

MHz

Edge Resolution (Single Update Mode)

Edge Resolution (Double Update Mode)

Programmable Dead Time Range

Programmable Dead Time Increments

Programmable Pulse Deletion Range

Programmable Pulse Deletion Increments

PWM Frequency Range

0

102

51

100

0

50

153¹

2.0

0.02

78,431²

12.8

5

PWMSYNC Pulsewidth (T_CRST

Gate Drive Chop Frequency Range

)

NOTES

¹153 Hz is calculated based on 16-bit resolution.

²78,431 Hz is calculated based on 8-bit resolution.

ADC Overview

I

_TRIM

CONST

REG <2:0>

The ADC of the ADMCF341 is based upon the single slope con-

version technique. This approach offers an inherently monotonic

conversion process within the noise and stability of its compo-

nents, and there will be no missing codes.

FILTER

MODECTRL REG

<09..10..11>

I

CONST

MODECTRL

REG <07>

VOLTAGE

CURRENT

CLK

The single slope technique has been adopted on the

ADMCF341 for four channels that are simultaneously con-

verted. Refer to Figure 11 for the functional schematic of the

ADC. The main inputs (I_SENSE1 to I_SENSE3) are connected to

the ADC converter through three front end blocks. Figure 15

shows the block diagram of a single front end block. Each front

end block has a bipolar current amplifier (gain = –2.5) designed

to acquire the voltage on a current-sensing resistor, whose volt-

age can be either positive or negative with respect to the power

supply ground rail.

CHANNEL1

I

1

SENSE

V1L

COMP

VOLTAGE

CURRENT

CHANNEL2

CHANNEL3

I

2

3

SENSE

V2L

V3L

COMP

VOLTAGE

CURRENT

SENSE

VAUX0 (V)

VAUX1 (V)

VAUX2 (V)

VAUX3 (V)

VAUX0

VAUX1

VAUX2

4-1

MULTIPLEXER

The fourth channel has been configured with a serially con-

nected 4-to-1 multiplexer. Table VI shows the multiplexer input

selection codes. One of these auxiliary multiplexed channels is

used to acquire the internal voltage reference (V_REF) for calibra-

tion purposes.

VAUXL

COMP

V

REF

MODECTRL REG <0..1>

I

CONST

ADC1

ADC2

ADC3

ADCAUX

CAPACITOR RESET

PWMSYNC (CONVST)

Table VI. ADC Auxiliary Channel Selection

MODECTRL (1) MODECTRL (0)

Figure 11. ADC Overview

Single Slope ADC Operations

Select

ADCMUX1

ADCMUX0

VAUX0

VAUX1

VAUX2

0

1

0

1

0

1

The ADC conversion process is done by comparing each ADC

input to a reference ramp voltage and timing the comparison of

the two signals. The actual conversion point is the time-point

intersection of the input voltage and the ramp voltage (VC), as

shown in Figure 12. This time is converted to counts by the 12-

bit ADC timer block and is stored in the ADC registers. The

ramp voltage used to perform the conversion is generated by

driving a fixed current into an off-chip capacitor, where the

capacitor voltage is:

Calibration (V_REF

)

V_C= (I C)¥ t

REV. 0

–17–

ADMCF341

Following reset, VC = 0 at t = 0. This reset and the start of the

conversion process are initiated by the PWMSYNC pulse, as

shown in Figure 12. The width of the PWMSYNC pulse is

controlled by the PWMSYNCWT register and should be pro-

grammed according to Figure 13 to ensure complete resetting.

ADC Resolution

The ADC is intrinsically linked to the PWM block through the

PWMSYNC pulse’s control of the ADC conversion process.

Because of this link, the effective resolution of the ADC is a

function of both the PWM switching frequency and the rate at

which the ADC counter timer is clocked. For a CLKOUT

period of t_CKand a PWM period of T_PWM, the maximum count

of the ADC is given by:

In order to compensate for IC process manufacturing tolerances

(and to adjust for capacitor tolerances), the current source of

the ADMCF341 is software-programmable. Using software to

set the magnitude of the ICONST current generator is accom-

plished by selecting one of eight steps over approximately 20%

current range.

Max Count = min (4095, (T_PWM-T_CRST)/2 t_CK

for MODECTRL Bit 7 = 0

Max Count = min (4095, (T_PWM-T_CRST)/t_CK

for MODECTRL Bit 7 = 1

)

V

C

V

CMAX

where T_PWMis equal to the PWM period if operating in single

update mode or equal to half that period if operating in

double update mode. For an assumed CLKOUT frequency

of 20 MHz and PWMSYNC pulsewidth of 2.0 ms, the effec-

tive resolution of the ADC block is tabulated for various

PWM switching frequencies in Table VII.

V1

T

VIL

Table VII. ADC Resolution Examples

T

CRST

T

– T

CRST

PWM

Frequency

(kHz)

MODECTRL[7] = 0

MODECTRL[7] = 1

Max Effective

Count Resolution

Max

Effective

Resolution

PWMSYNC

Count

2.4

4

4095

2480

1230

535

12

4095

2460

1070

760

12

COMPARATOR

OUTPUT

>11

>10

>9

12

8

>11

>10

>9

18

25

Figure 12. Analog Input Block Operation

380

>8

The ADC system consists of four comparators and a single

Programmable Current Source

timer, which may be clocked at either the DSP rate or half the

DSP rate, depending on the setting of the ADCCNT bit (bit 7)

of the MODECTRL register. When this bit is cleared, the timer

counts at a slower rate of CLKIN. When this bit is set, it counts

at CLKOUT or twice the rate of CLKIN. ADC1, ADC2,

ADC3, and ADCAUX are the registers that capture the conver-

sion times, which are the timer values when the associated

comparator trips.

The ADMCF341 has an internal current source that is used to

charge an external capacitor, generating the voltage ramp used

for conversion. The magnitude of the output of the current

source circuit is subject to manufacturing variations and can

vary from one device to the next. Therefore, the ADMCF341

includes a programmable current source whose output can

always be tuned to within 5% of the target 100 mA. A 3-bit

register, I_CONST_TRIM, allows the user to make this adjust-

ment. The output current is proportional to the value written to

the register: 0x0 produces the minimum output and 0x7 pro-

duces the maximum output. The default value of I_CONST_TRIM

after reset is 0x0.

200

150

100

50

Charging Capacitor Selection

The charging capacitor value is selected based on the sample

(PWM) frequency desired. A too-small capacitor value will re-

duce the available resolution of the ADC by having the ramp

voltage rise rapidly and convert too quickly, not utilizing all pos-

sible counts available in the PWM cycle. A too-large capacitor

may not convert in the available PWM cycle returning 0x000.

To select a charging capacitor use Figure 14. Select the sam-

pling frequency desired, determine if the current source is to be

tuned to a nominal 100 mA or left in the default (0x0 code) trim

state, then determine the proper charge capacitor off the appro-

priate curve.

0

2

4

6

8

10

CHARGING CAPACITOR – nF

Figure 13. PWMSYNCWT Program Value

–18–

REV. 0

ADMCF341

VOLTAGE (THIS IS NOT AVAILABLE EXTERNALLY ON THE ADMCF341)

100

10

1

TRIP

TRIP REF HIGH

TRIP REF LOW

(TO PWMTRIP FILTER)

OVERCURRENT

COMPARATOR

TUNED I

VxL

CONST

CURRENT

SHA

(TO ADC)

–2.5

PWMSYNC

CLOCKOUT

DEFAULT I

CONST

SHA

STATE

MACHINE

SHA TIMER

COUNTER

1

10

100

ADC CONVERSION

STATUS BIT

Figure 14. Timing Capacitor Selection

Analog Front End

The main analog inputs of the ADMCF341 (I_SENSE1 to I_SENSE3)

are connected to the ADC converter through three front end

blocks. Figure 15 shows the block diagram of a single analog

front end.

SHA TIMER

REGISTER

(ADC REGISTER)

MODECTRL REGISTER

CHANNEL SELECTION (I

/V)

SENSE

Figure 15. Analog Front End Block Diagram

1

2

3

4

5

6

7

8

9

10

11 12

CYCLE

N+4

N–1

N

N+1

N+2

N+3

N+5

PWMSYNC

VC

T

SAMPLE

T

SAMPLE

T

SAMPLE

SHA TIMER

COUNTER

T

SAMPLE

TRACK

H

SHA STATUS

X

T

H

T

H

T

H

I

INPUT

SENSE

S

DATA READY

SAMPLED ON

CYCLE N–2

DATA READY

SAMPLED ON

CYCLE N+4

DATA READY

SAMPLED ON

CYCLE N

DATA READY

SAMPLED ON

CYCLE N+2

INVALID

LSB = 1

INVALID

LSB = 1

ADC REGISTER

Figure 16. ADC Conversion Sequence of a Current Input

REV. 0

–19–

ADMCF341

Table VIII. Fundamental Characteristics of Auxiliary PWM Timers

Parameter

Test Conditions

Min

Typ

Max

Unit

Resolution

16

Bits

PWM Frequency

10 MHz CLKIN

0.152

MHz

Each analog front end has two analog inputs: voltage and cur-

rent. A 2-to-1 multiplexer selects which input will be converted;

the multiplexer selection is determined by the MODECTRL

register. Note that in the ADMCF341 only the current inputs

(I_SENSE) are externally available.

During the acquire phase (the PWMSYNC cycle during the

sampling of the input value) the conversion takes place. How-

ever, the value on the ADC registers is not considered valid.

This condition is signaled by the ADC by setting the LSB of the

ADC register to high.

The current input (I_SENSE) is amplified through a bipolar ampli-

fier (gain –2.5). There is an output offset that matches the

amplifier output signal range to the input signal range of the

A/D converter. The amplifier has built-in overcurrent and open-

circuit protection. The overcurrent protection shuts the PWM

Block when the voltage at any of the I_SENSEpins exceeds the trip

threshold (high or low). The open-circuit detection shuts the

PWM block when any of the I_SENSEinputs is in high impedance

(for example, the current sense resistor or transducer is discon-

nected). The shutdown signals generated by the amplifiers are

then OR-ed and filtered in order to avoid a spurious trip caused

by the switching of the power devices. The amplifier is followed

by a sample-and-hold amplifier (SHA). The SHA time is user-

programmable through the SHA timer register. The sampling

time is set as a delay from the rising edge of the PWMSYNC

signal and is calculated as:

On cycle N + 4, at the rising edge of the PWMSYNC signal (9),

the timer counter is reloaded with a value smaller than the

PWMSYNC pulsewidth. In this case the SHA samples within

the PWMSYNC pulsewidth and the conversion takes place in

the same PWMSYNC cycle [from (10) to (11)].

AUXILIARY PWM TIMERS

Overview

The ADMCF341 provides two variable frequency, variable duty

cycle, 16-bit, auxiliary PWM outputs that, when enabled, are

available at the AUX1 and AUX0 pins. These auxiliary PWM

outputs can be used to provide switching signals to other

circuits in typical motor control systems, such as power factor

corrected front end converters or other switching power con-

verters. Alternatively, by adding a suitable filter network, the

auxiliary PWM output signals can be used as simple single-bit

digital-to-analog converters as shown in Figure 17. The auxiliary

PWM system of the ADMCF341 can operate in two different

modes: independent mode and offset mode. The operating

mode of the auxiliary PWM system is controlled by Bit 8 of the

MODECTRL register. Setting Bit 8 of the MODECTRL regis-

ter places the auxiliary PWM system in the independent mode.

In this mode, the two auxiliary PWM generators are completely

independent and separate switching frequencies and duty cycles

may be programmed for each auxiliary PWM output. In this

mode, the 16-bit AUXTM0 register sets the switching frequency

of the signal at the AUX0 output pin. Similarly, the 16-bit

AUXTM1 register sets the switching frequency of the signal at

the AUX1 pin. The fundamental time increment for the auxiliary

PWM outputs is twice the DSP instruction rate (or 2 t_CK) and

the corresponding switching periods are given by:

T_SAMPLE= (SHA_CNT + 2)¥ t_CK

The SHA timer counter has a minimum reload value of 0x0003,

which ensures a minimum settling time of the SHA output in

case the user is programming the SHA timer register to a value

smaller than 0x0003. This means that the sampling time is

programmable from 5 t_CKto 65,535 t_CK(corresponding to 250 ns

to 3.28 ms for a CLKOUT rate of 20 MHz). The sampling time

is limited, however, to the rising edge of the following PWMSYNC

cycle. Each channel has an independent amplifier, SHA, and

SHA timing unit/state machine. Figure 16 shows a conversion

sequence of a single channel.

At the beginning of the cycle N (rising edge of PWMSYNC

signal (1), the timer counter is loaded with the value contained

in the SHA_CNT register. After the timer counter has been

reloaded, it starts counting down at the CLKOUT rate. In this

phase the SHA state-machine forces the SHA in TRACK

(sample) status.

T_{AUX 0}= 2 ¥ (AUXTM0 +1) ¥ t_CK

T_AUX1= 2 ¥ (AUXTM1+1) ¥ t_CK

Since the values in both AUXTM0 and AUXTM1 can range

from 0 to 0xFFFF, the achievable switching frequency of the

auxiliary PWM signals may range from 152.59 Hz to 10 MHz

for a CLKOUT frequency of 20 MHz. The on-time of the two

auxiliary PWM signals is programmed by the two 16-bit

AUXCH0 and AUXCH1 registers, according to:

When the counter reaches the value of 0x0000 (after the time

T

_SAMPLEfrom the rising edge of PWMSYNC), the SHA state-

machine forces the SHA in HOLD status.

The conversion of the sampled value is then taking place in the

cycle N + 1 [from (4) to (5)] in Figure 16 and the result of the

conversion is available on the ADC register at the cycle N + 2

[rising edge of PWMSYNC (5)].

T_ON, AUX0 = 2 ¥(AUXCH0)¥ t_CK

T

_ON, AUX1= 2 ¥(AUXCH1)¥ t_CK

On cycle N + 2, the reload value of the timer counter exceeds

the period of the PWMSYNC signal. In this case the SHA state-

machine forces the SHA in HOLD status at the rising edge of

PWMSYNC of the next cycle (7). The conversion then takes place

on cycle N + 3, and the conversion result is available on the ADC

register at the cycle N + 4 [rising edge of PWMSYNC (9)].

so that output duty cycles from 0% to 100% are possible. Duty

cycles of 100% are produced if the on-time value exceeds the

period value. Typical auxiliary PWM waveforms in independent

mode are shown in Figure 18a. When bit 8 of the MODECTRL

register is cleared, the auxiliary PWM channels are placed

–20–

REV. 0

ADMCF341

in offset mode. In offset mode, the switching frequency of the

two signals on the AUX0 and AUX1 pins are identical and

controlled by AUXTM0 in a manner similar to that previously

described for independent mode. In addition, the on-times of

both the AUX0 and AUX1 signals are controlled by the AUXCH0

and AUXCH1 registers as before.

2 ꢀ (AUXTM0 + 1)

2 ꢀ AUXCH0

AUX0

AUX1

2 ꢀ (AUXTM0 + 1)

In this mode, however, the AUXTM1 register defines the offset

time from the rising edge of the signal on the AUX0 pin to that

on the AUX1 pin according to:

2 ꢀ AUXCH1

2 ꢀ (AUXTM1 + 1)

T_OFFSET= 2 ¥(AUXTM1 +1)¥ t_CK

Figure 18b. Typical Auxiliary PWM Signals

(All Times in Increments of t_CK), Offset Mode

For correct operation in this mode, the value written to the

AUXTM1 register must be less than the value written to the

AUXTM0 register. Typical auxiliary PWM waveforms in offset

mode are shown in Figure 18b. Again, duty cycles from 0% to

100% are possible in this mode.

WATCHDOG TIMER

The ADMCF341 incorporates a watchdog timer that can

perform a full reset of the DSP and motor control peripherals

in the event of software error. The watchdog timer is enabled by

writing a timeout value to the 16-bit WDTIMER register. The

timeout value represents the number of CLKIN cycles required

for the watchdog timer to count down to zero. When the watchdog

timer reaches zero, a full DSP core and motor control peripheral

reset is performed. In addition, bit 1 of the SYSSTAT register is

set so that after a watchdog reset, the ADMCF341 can determine

that the reset was due to the timeout of the watchdog timer and

was not an external reset. Following a watchdog reset, bit 1 of

the SYSSTAT register may be cleared by writing zero to the

WDTIMER register. This clears the status bit but does not

enable the watchdog timer.

In both operating modes, the resolution of the auxiliary PWM

system is 16 bits only at the minimum switching frequency

(AUXTM0 = AUXTM1 = 65,535 in independent mode,

AUXTM0 = 65,535 in offset mode). Obviously, as the switch-

ing frequency is increased, the resolution is reduced.

Values can be written to the auxiliary PWM registers at any

time. However, new duty cycle values written to the AUXCH0

and AUXCH1 registers only become effective at the start of the

next cycle. Writing to the AUXTM0 or AUXTM1 registers

causes the internal timers to be reset to 0 and new PWM cycles

to begin. By default following a reset, bit 8 of the MODECTRL

register is cleared, thus enabling offset mode. In addition, the

registers AUXTM0 and AUXTM1 default to 0xFFFF, corre-

sponding to the minimum switching frequency and zero offset.

The on-time registers AUXCH0 and AUXCH1 default to

0x0000.

On reset, the watchdog timer is disabled and is only enabled

when the first timeout value is written to the WDTIMER

register. To prevent the watchdog timer from timing out, the

user must write to the WDTIMER register at regular intervals

(shorter than the programmed WDTIMER period value). On

all but the first write to WDTIMER, the particular value written

to the register is unimportant, since writing to WDTIMER

simply reloads the first value written to this register.

AUXPWM

R1

R2

C1

C2

PROGRAMMABLE DIGITAL INPUT/OUTPUT

The ADMCF341 has a nine-pin programmable digital input/

output (PIO) port (PORTA). The nine pins (PORTA0–

PORTA8) are multiplexed with other on-chip peripheral

functions, in accordance with Table IX. When configured as a

PIO, each of these nine pins can act as an input or output, or an

interrupt source.

R1 = R2 = 13kꢂ

C1 = C2 = 10nF

Figure 17. Auxiliary PWM Output Filter

Auxiliary PWM Interface, Registers, and Pins

The registers of the auxiliary PWM system are summarized at

the end of the data sheet.

The operating mode (PIO or alternate function) of pins PORTA0

to PORTA8 is controlled by the PORTA_SELECT register.

This 9-bit register has a bit for each input so that the mode of

each pin may be selected individually.

2 ꢀ (AUXTM0 + 1)

2 ꢀ AUXCH0

AUX0

Bit 0 of PORTA_SELECT controls the operation of the

PORTA0 pin, bit 1 controls the PORTA1 pin, etc. Setting the

appropriate bit in the PORTA_SELECT register causes the

corresponding pin to be configured for PIO functionality.

Clearing the bit selects the alternate mode of the corresponding

pin. Following power-on reset, all bits of PORTA_SELECT

are set such that PIO functionality is selected. The second

alternate function of PORTA7 is selected by bit 14 of the

PORTA_SELECT register. The second alternate function of

2 ꢀ (AUXTM1 + 1)

2 ꢀ AUXCH1

AUX1

2 ꢀ AUXCH1

Figure 18a. Typical Auxiliary PWM Signals

(All Times in Increments of t_CK), Independent

Mode

REV. 0

–21–

ADMCF341

Table IX. Port A Multiplexing

First Alternate Function (Peripheral)

PORTA Pin

Second Alternate Function (Peripheral)

PORTA8

PORTA7

PORTA6

PORTA5

PORTA4

PORTA3

PORTA2

PORTA1

PORTA0

AUX0 (Auxiliary PWM Output)

AUX1 (Auxiliary PWM Output)

DR1 (Data Receive SPORT1)

FL1 (Flag Out SPORT1)

SCLK1 (Serial Clock SPORT1)

TFS0 (Transmit Frame Sync SPORT0)

RFS0 (Receive Frame Sync SPORT0)

DT0 (Data Transmit SPORT0)

DR0 (Data Receive SPORT0)

CLKOUT (System CLOCK)

PWMSYNC (PWM)

None

DT1 (Data Transmit SPORT1)

SCLK0 (Serial Clock SPORT0)

None

PORTA8 is selected by bit 15 of the PORTA_SELECT

register.

the internal timer, and two software interrupts. The motor

control interrupts are the nine PORTA PIOs and two from the

PWM block (PWMSYNC pulse and PWMTRIP). All the on-chip

peripheral interrupts are multiplexed into the DSP core via the

peripheral IRQ2 interrupt. They are also internally prioritized

and individually maskable. The start address in the interrupt

vector table for the ADMCF341 interrupt sources is shown in

Table X. The interrupts are listed from highest to lowest prior-

ity. The PWMSYNC interrupt is triggered by a low-to-high

transition on the PWMSYNC pulse. The PWMTRIP interrupt

is triggered on a high-to-low transition on the PWMTRIP pin.

A PIO interrupt is detected on any change of state (high-to-low

or low-to-high) on the PIO lines.

The second alternate function of the PORTA4 and PORTA5

pins is selected by bit 4 of MODECTRL Register (SPORT1

mode: boot mode/UART mode).

Once PIO functionality has been selected for any or all of these

nine pins, the direction may be set by the 9-bit PORTA_DIR

register. Clearing any bit configures the corresponding PIO line

as an input, while setting the bit configures it as an output. By

default, following a reset all bits of PORTA_DIR are cleared,

configuring the PIO lines as inputs. The data of the PORTA0

to PORTA8 lines is controlled by the PORTA_DATA register.

These registers can be used to read data from those PIO lines

configured as inputs and write data to those configured as outputs.

Any of the nine pins that have been configured for PIO func-

tionality can be made to act as an interrupt source by setting

the appropriate bit of the PORTA_INTEN register. In order to

act as an interrupt source the pin must also be configured as an

input. An interrupt is generated upon a change of state (low-to-

high transition or high-to-low transition) on any input that has

been configured as an interrupt source. Following a change of

state event on any such input, the corresponding bit is set in the

PORTA_FLAG register and a common PIO interrupt is generated.

The entire interrupt control system of the ADMCF341 is con-

figured and controlled by the IFC, IMASK, and ICNTL

registers of the DSP core, the IRQFLAG register for the

PWMSYNC and PWMTRIP interrupts, and PORTA_FLAG

register for the PIO interrupts.

Table X. Interrupt Vector Addresses

Interrupt Source

Interrupt Vector Address

PWMTRIP

Peripheral Interrupt (IRQ2)

PWMSYNC

0x002C (Highest Priority)

0x0004

0x000C

Reading the PORTA_FLAG register permits determining the

interrupt source. Reading the PORTA_FLAG register automati-

cally clears all bits of the registers. Following power-on or reset,

all bits of PORTA_INTEN are cleared so that no interrupts are

enabled.

PIO

0x0008

Software Interrupt 1

Software Interrupt 0

SPORT0 Transmit Interrupt

SPORT0 Receive Interrupt

0x0018

0x001C

0x0010

0x0014

Each PIO line has an internal pull-down resistor so that follow-

ing power-on or reset all nine lines are configured as input PIOs

and will be read as logic lows if left unconnected.

SPORT1 Transmit Interrupt (or IRQ1) 0x0020

SPORT1 Receive Interrupt (or IRQ0) 0x0024

Timer

0x0028 (Lowest Priority)

PIO Registers

The configuration of all registers of the PIO system is shown at

the end of the data sheet.

Interrupt Masking

Interrupt masking (or disabling) is controlled by the IMASK

register of the DSP core. This register contains individual bits

that must be set to enable the various interrupt sources. If any

peripheral interrupt is to be enabled, the IRQ2 interrupt enable

bit (bit 9) of the IMASK register must be set. The configuration

of the IMASK register of the ADMCF341 is shown at the end

of the data sheet.

INTERRUPT CONTROL

The ADMCF341 can respond to 18 different interrupt sources

with minimal overhead. Seven of these interrupts are internal

DSP core interrupts and 11 are from the on-chip peripherals.

The seven DSP core interrupts are SPORT0 receive and

transmit, SPORT1 receive (or IRQ0) and transmit (or IRQ1),

–22–

REV. 0

ADMCF341

Interrupt Configuration

SYSTEM CONTROLLER

The IFC and ICNTL registers of the DSP core control and

configure the interrupt controller of the DSP core. The IFC

register is a 16-bit register that may be used to force and/or clear

any of the eight DSP interrupts. Bits 0 to 7 of the IFC register

may be used to clear the DSP interrupts while Bits 8 to 15 can

be used to force a corresponding interrupt. Writing to Bits 11

and 12 in IFC is the only way to create the two software inter-

rupts. The ICNTL register is used to configure the sensitivity

(edge- or level-) of the IRQ0, IRQ1, and IRQ2 interrupts and to

enable/disable interrupt nesting. Setting Bit 0 of ICNTL config-

ures the IRQ0 as edge-sensitive, while clearing the bit configures

it as level-sensitive. Bit 1 is used to configure the IRQ1 interrupt

and Bit 2 is used to configure the IRQ2 interrupt. It is recom-

mended that the IRQ2 interrupt always be configured as

level-sensitive as this ensures that no peripheral interrupts are

lost. Setting Bit 4 of the ICNTL register enables interrupt nesting.

The configuration of both IFC and ICNTL registers is shown at

the end of the data sheet.

The system controller block of the ADMCF341 performs the

following functions:

1. Manages the interface and data transfer between the DSP

core and the motor control peripherals.

2. Handles interrupts generated by the motor control periph-

erals and generates a DSP core interrupt signal IRQ2.

3. Controls the ADC multiplexer select lines.

4. Enables PWMTRIP and PWMSYNC interrupts.

5. Controls the multiplexing of the SPORT1 and SPORT0

pins.

6. Controls the PWM single/double update mode.

7. Controls the ADC conversion time modes and the SHA

timers.

8. Controls the auxiliary PWM operation mode.

9. Contains a status register (SYSSTAT) that indicates the

state of the PWMTRIP pin, the watchdog timer, and the

PWM timer.

INTERRUPT OPERATION

Following a reset, the ROM code on the ADMCF341 must

copy a default interrupt vector table into program memory

RAM from address 0x0000 to 0x002F. Since each interrupt

source has a dedicated four-word space in this vector table, it is

possible to code short interrupt service routines (ISR) in place.

Alternatively, it may be necessary to insert a JUMP instruction

to the appropriate start address of the ISR if the ISR requires

more memory. When an interrupt occurs, the program sequencer

ensures that there is no latency (beyond synchronization delay)

when processing unmasked interrupts. In the case of the timer,

SPORT0, SPORT1, and software interrupts, the interrupt

controller automatically jumps to the appropriate location in the

interrupt vector table. At this point, a JUMP instruction to the

appropriate ISR is required. Motor control peripheral interrupts

are slightly different. When a peripheral interrupt is detected,

a bit is set in the IRQFLAG register for PWMSYNC and

PWMTRIP or in the PORTA_FLAG register for a PIO inter-

rupt, and the IRQ2 line is pulled low until all pending interrupts

are acknowledged. The DSP software must determine the

source of the interrupts by reading the IRQFLAG register. If more

than one interrupt occurs simultaneously, the higher priority

interrupt service routine is executed. Reading the IRQFLAG

register clears the PWMTRIP and PWMSYNC bits and acknowl-

edges the interrupt, thus allowing further interrupts when the

ISR exits. A user’s PIO interrupt service routine must read the

PORTA_FLAG register to determine which PIO port is the

source of the interrupt. Reading register PORTA_FLAG clears

all bits in the registers and acknowledges the interrupt, thus

allowing further interrupts after the ISR exits. The configuration

of all these registers is shown at the end of the data sheet.

10. Performs a reset of the motor control peripherals and

control registers following a hardware, software, or watch-

dog initiated reset.

SPORT1 and SPORT0 Control

The ADMCF341 has two serial ports: SPORT0 and SPORT1.

SPORT1 is available with a limited number of pins and is mainly

intended as a secondary port for development tools interfacing

and/or code booting from, as well as external serial memory.

Figure 19 shows the internal multiplexing of the SPORT0 and

SPORT1 signals. SPORT0 is intended as a general-purpose

communication port. SPORT0 can support the following

operating modes: SPORT, UART, and SPI.

SPORT1 Configuration

There are two operating modes for SPORT1: boot mode and

UART mode. These modes are selectable through Bit 4 of the

MODECTRL register. With SPORT1 in boot mode, the

SPORT1 serial clock (SCLK1) is externally available through

the SCLK1/SCLK0 pin. The signal SCLK1 is used to drive the

external serial memory input clock.

The SPORT1 flag signal (FL1) is externally available through

the FL1/DT1 pin. This signal is used to drive the external serial

memory input reset.

With SPORT1 configured in UART mode, the SPORT0 serial

clock (SCLK0) is externally available through the SCLK1/

SCLK0 pin. The SPORT1 data transmit (DT1) is externally

available through the FL1/DT1 pin.

SPORT0 Configuration

SPORT0 can be configured in the following modes: SPORT

mode, UART mode, and SPI mode.

SPORT0 can be configured for UART mode. In this mode the

DR0 and RFS0 signals of the internal serial port are connected

together.

SPORT0 can be configured to operate as the master SPI inter-

face. The SPI mode is set through Bit 14 of the MODECTRL

register. When SPORT0 is configured as the SPI interface, the

SPORT I/O pins assume the configuration shown in Table XI.

REV. 0

–23–

ADMCF341

Table XI. SPORT0 Pin Assignment in SPI Mode

The slave select pin automatically generates the select signal

at each word transfer. This pin can also be used as a general-

purpose I/O during the SPI transfer without affecting the

SPORT operations.

SPORT I/O Signal

SPI Mode

SPI Mode I/O

DT0 (Data Transmit)

MOSI

Output

(Master Output/

Slave Input)

The SPI clock polarity and phase are configurable through

Bits 13 and 12 of the MODECTRL Register. The SPI transfer

using clock phase is shown in Figures 20 and 21.

DR0

MISO

Input

(Master Input/

Slave Output)

TFS0

SS

Output

(Slave Select)

RFS0

Unused

N/A

SCLK0

SCK

Output

(Serial Clock)

MODECTRL REGISTER (04)

SPORT1 BOOT MODE/UART MODE

DT1/FL1

DR1

DT1

FL1

TFS1

RFS1

DR1

DSP

CORE

SPORT1

SCLK1

SCLK1/SCLK0

DT1

FL1

TFS1

RFS1

DT0

DR0

TFS0

SPI

CONTROL

BLOCK

DSP

CORE

SPORT0

SCLK1

RFS0

MODECTRL REGISTER (15)

SPORT0 SPORT MODE/UART MODE

MODECTRL REGISTER (14..13..12)

SPORT0 SPI INTERFACE CONTROL

Figure 19. SPORT0 and SPORT1 Internal Multiplexing (Simplified Diagram)

–24–

REV. 0

ADMCF341

SCK CYCLE #

1

2

3

4

5

N

SCK (POLARITY = 0)

SCK (POLARITY = 1)

SS

MOSI

SEE NOTE 1

SEE NOTE 2

MSB

LSB

MOSO

NOTE

1. LSB OF PREVIOUSLY TRANSMITTED WORD

2. UNDEFINED

Figure 20. SPI Transfer Using Clock Phase CPHA = 0

SCK CYCLE #

1

2

3

4

5

N

SCK (POLARITY = 0)

SCK (POLARITY = 1)

SS

MOSI

SEE NOTE 1

SEE NOTE 2

MSB

LSB

MOSO

NOTES

1. LSB OF PREVIOUSLY TRANSMITTED WORD

2. UNDEFINED

Figure 21. SPI Transfer Using Clock Phase CPHA = 1

REV. 0

–25–

ADMCF341

Table XII. Peripheral Register Map

Bits Used

Address (hex)

Name

Function

0x2000

0x2001

0x2002

0x2003

0x2004

0x2005

0x2006

0x2007

ADC1

ADC2

ADC3

ADCAUX

PORTA_DIR

PORTA_DATA

PORTA_INTEN

PORTA_FLAG

PWMTM

[15 . . . 4]

[8 . . . 0]

[15 . . . 0]

[9 . . . 0]

[15 . . . 0]

[8 . . . 0]

[7 . . . 0]

ADC Results for I_SENSE1

ADC Results for I_SENSE2

ADC Results for I_SENSE3

ADC Results for VAUX

PA8 . . . PA0 Direction Setting

PA8 . . . PA0 Input/Output Data

PA8 . . . PA0 Interrupt Enable

PA8 . . . PA0 Interrupt Status

PWM Period

0x2008

0x2009

PWMDT

PWMPD

PWM Dead Time

0x200A

0x200B

0x200C

0x200D

0x200E

0x200F

0x2010

0x2011

0x2012

0x2013

0x2014

PWM Pulse Deletion Time

PWM Gate Drive Conﬁguration

PWM Channel A Pulsewidth

PWM Channel B Pulsewidth

PWM Channel C Pulsewidth

PWM Segment Select

AUX PWM Output 0

AUX PWM Output 1

Auxiliary PWM Frequency Value

Auxiliary PWM Frequency Value/Offset

Reserved

PWMGATE

PWMCHA

PWMCHB

PWMCHC

PWMSEG

AUXCH0

AUXCH1

AUXTM0

AUXTM1

0x2015

0x2016

0x2017

0x2018

MODECTRL

SYSSTAT

IRQFLAG

[8 . . . 0]

[3 . . . 0]

[1 . . . 0]

[15 . . . 0]

Mode Control Register

System Status

Interrupt Status

WDTIMER

Watchdog Timer

0x2019 . . . 48

0x2049

0x204A . . . 5F

0x2060

0x2061

Reserved

PA8 . . . PA0 Mode Select

Reserved

PWMSYNC Pulsewidth

PWM S/W Trip Bit

PORTA-SELECT

[8 . . . 0]

PWMSYNCWT

PWMSWT

[7 . . . 0]

[0]

0x2062 . . . 67

0x2068

0x2069

0x206A

0x206B

0x2070

Reserved

I_CONST_TRIM

Sample Hold Timer 1

Sample Hold Timer 2

Sample Hold Timer 3

Reserved

I_CONST_TRIM

SHA1_TM

SHA2_TM

SHA3_TM

[2 . . . 0]

[15 . . . 0]

0x2080

0x2081

0x2082

0x2083

FMCR

FMAR

FMDRH

FMDRL

[15 . . . 0]

[11 . . . 0]

[13 . . . 0]

[15 . . . 0]

Flash Memory Control Register

Flash Memory Address Register

Flash Memory Data Register High

Flash Memory Data Register Low

Reserved

0x2084 . . . FF

–26–

REV. 0

ADMCF341

Table XIII. DSP Core Registers

Bits

Address (hex)

Name

Function

0x3FFF

0x3FFE

0x3FFD

0x3FFC

0x3FFB

0x3FFA

0x3FF9

0x3FF8

0x3FF7

0x3FF6

0x3FF5

0x3FF4

0x3FF3

0x3FF2

0x3FF1

0x3FF0

0x3FEF

SYSCNTL

MEMWAIT

TPERIOD

TCOUNT

[15 . . . 0]

[7 . . . 0]

[15 . . . 0]

System Control Register

Memory Wait State Control Register

Interval Timer Period Register

Interval Timer Count Register

TSCALE

Interval Timer Scale Register

SPORT0_RX_WORDS1

SPORT0_RX_WORDS0

SPORT0_TX_WORDS1

SPORT0_TX_WORDS0

SPORT0_CTRL_REG

SPORT0_SCLKDIV

SPORT0_RFSDIV

SPORT0_AUTOBUF_CTRL

SPORT1_CTRL_REG

SPORT1_SCLKDIV

SPORT0 Multichannel Word 1 Receive

SPORT0 Multichannel Word 0 Receive

SPORT0 Multichannel Word 1 Transmit

SPORT0 Multichannel Word 0 Transmit

SPORT0 Control Register

SPORT0 Clock Divide Register

SPORT0 Receive Frame Sync Divide

SPORT0 Autobuffer Control Register

SPORT1 Control Register

SPORT1 Clock Divide Register

SPORT1 Receive Frame Sync Divide

SPORT1 Autobuffer Control Register

SPORT1_RFSDIV

SPORT1_AUTOBUF_CTRL

FLASH MEMORY CONTROL REGISTER

15 14 13 12 11 10

9

8

7

6

5

4

3

0

2

0

1

0

1

0

0x2080

BOOT Ϸ MEMORY Ϸ FLASH Ϸ CODE

FLASH MEMORY ADDRESS REGISTER

15 14 13 12

11 10

9

8

7

6

5

4

3

2

1

0

0x2081

ADDRESS 11 Ϸ 0

RESERVED

ALWAYS READ 0

FLASH MEMORY DATA REGISTER LOW (FMDRL)

15 14 13 12

11 10

9

8

7

6

5

4

3

2

1

0

0x2083

0

STATUS 5 Ϸ 0

DATA 7 Ϸ 0

RESERVED

ALWAYS READ 0

FLASH MEMORY DATA REGISTER HIGH (FMDRH)

15 14 13 12

11 10

9

8

7

6

5

4

3

2

0

1

0

0x2082

0

DATA 23 Ϸ 8

MOST SIGNIFICANT BIT IS ON THE LEFT. FOR EXAMPLE, DATA23 IS BIT 15 OF FMDRH.

Figure 22. Conﬁguration of Flash Memory Registers

Default bit values are shown; if no value is shown, the bit ﬁeld is undeﬁned at reset.

Reserved bits are shown on a gray ﬁeld—these bits should always be written as shown.

REV. 0

–27–

ADMCF341

PWMTM (R/W)

15 14 13 12

11 10

9

8

7

6

5

4

3

2

1

0

DM (0x 2008)

PWMTM

f_CLKOUT

f_PWM

=

2 ꢀ PWMTM

PWMDT (R/W)

15 14 13 12 11 10

9

8

7

0

6

0

5

0

4

3

0

2

1

0

DM (0x2009)

PWMDT

2 ꢀ PWMTM

f_CLKOUT

T

=

D

PWMSEG (R/W)

15 14 13 12

11 10

9

8

7

6

5

0

4

3

0

2

1

0

DM (0x200F)

0

A CHANNEL CROSSOVER

B CHANNEL CROSSOVER

CH OUTPUT DISABLE

CL OUTPUT DISABLE

BH OUTPUT DISABLE

0 = NO CROSSOVER

1 = CROSSOVER

C CHANNEL CROSSOVER

0 = ENABLE

1 = DISABLE

BL OUTPUT DISABLE

AH OUTPUT DISABLE

AL OUTPUT DISABLE

PWMSYNCWT (R/W)

1

15 14 13 12 11 10

9

8

0

7

0

6

0

5

1

4

3

0

2

0

1

0

1

DM (0x2060)

PWMSYNCWT

PWMSYNCWT + 1

f_CLKOUT

T

=

PWMSYNC, ON

PWMSWT (R/W)

15 14 13

12 11 10

9

8

7

0

6

0

5

0

4

3

0

2

1

0

DM (0x2061)

Figure 23. Conﬁguration of PWM Registers

Default bit values are shown; if no value is shown, the bit ﬁeld is undeﬁned at reset.

Reserved bits are shown on a gray ﬁeld—these bits should always be written as shown.

–28–

REV. 0

ADMCF341

PWMPD (R/W)

15 14 13 12

11 10

9

0

8

0

7

0

6

0

5

0

4

0

3

0

2

0

1

0

DM (0x200A)

PWMPD

0

PWMPD

f_CLKOUT

=

T

MIN

PWMGATE (R/W)

15 14 13 12

11 10

9

8

7

6

5

0

4

0

3

0

2

0

1

0

DM (0x200B)

GDCLK

0

GATE DRIVE CHOPPING FREQUENCY

f_CLKOUT

LOW SIDE GATE CHOPPING

HIGH SIDE GATE CHOPPING

0 = DISABLE

1 = ENABLE

=

f_CHOP

4 ꢀ (GDCLK + 1)

PWMCHA (R/W)

15 14 13 12

11 10

9

8

7

6

5

4

3

2

1

0

DM (0x200C)

PWM CHANNEL A

DUTY CYCLE

PWMCHB (R/W)

15 14 13 12

11 10

9

8

7

6

5

4

3

2

1

0

DM (0x200D)

PWM CHANNEL B

DUTY CYCLE

PWMCHC (R/W)

15

14 13 12

11 10

9

8

7

6

5

4

3

2

1

0

DM (0x200E)

PWM CHANNEL C

DUTY CYCLE

Figure 24. Conﬁguration of Additional PWM Registers

Default bit values are shown; if no value is shown, the bit ﬁeld is undeﬁned at reset.

Reserved bits are shown on a gray ﬁeld—these bits should always be written as shown.

REV. 0

–29–

ADMCF341

PORTA_DIR (R/W)

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

7

6

5

0

4

0

3

0

2

0

1

0

DM (0x2004)

0

0 = INPUT

PA0-PA8

1 = OUTPUT

PORTA_DATA (R/W)

15

0

14

13

12

11

0

10

0

9

0

8

7

6

5

4

3

2

0

1

0

DM (0x2005)

0

0 = LOW LEVEL

1 = HIGH LEVEL

PA0-PA8

PORTA_SELECT (R/W)

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

1

7

1

6

1

5

4

1

3

2

1

0

1

DM (0x2049)

1

0 = DR0

1 = PA0

0 = CLOCKOUT

1 = AUX0

0 = AUX0/CLOCKOUT

1 = PA8

0 = PWMSYNC

1 = AUX1

0 = DT0

1 = PA1

0 = AUX1/PWMSYNC

1 = PA7

0 = DR1

1 = PA6

0 = RFS0

1 = PA2

0 = DT1/FL1

1 = PA5

0 = TFS0

1 = PA3

0 = SCLK1/SCLK0

1 = PA4

Figure 25. Conﬁguration of PIO Registers

Default bit values are shown; if no value is shown, the bit ﬁeld is undeﬁned at reset.

Reserved bits are shown on a gray ﬁeld—these bits should always be written as shown.

–30–

REV. 0

ADMCF341

PORTA_INTEN (R/W)

15 14 13 12

11 10

9

0

8

0

7

0

6

0

5

0

4

0

3

0

2

0

1

0

DM (0x2006)

0

0 = INTERRUPT DISABLE

1 = INTERRUPT ENABLE

PORTA_FLAG (R/W)

15 14 13 12 11 10

9

8

7

6

5

4

0

3

0

2

0

1

0

DM (0x2007)

0

0 = INTERRUPT DISABLE

1 = INTERRUPT ENABLE

Figure 26. Conﬁguration of Additional PIO Registers

Default bit values are shown; if no value is shown, the bit ﬁeld is undeﬁned at reset. Reserved bits are shown on a gray ﬁeld—these

bits should always be written as shown.

AUXCH0 (R/W)

15 14 13 12

11 10

9

8

7

6

5

0

4

0

3

0

2

0

1

0

DM (0x2010)

T

= 2 ꢀ (AUXCH0) ꢀ t_CK

ON, AUX0

AUXCH1 (R/W)

15 14 13 12

11 10

9

8

7

6

5

0

4

3

0

2

0

1

0

DM (0x2011)

T

= 2 ꢀ (AUXCH1) ꢀ t_CK

ON, AUX1

AUXTM0 (R/W)

15 14 13 12

11 10

9

1

8

7

6

5

1

4

3

1

2

1

0

1

DM (0x2012)

AUX0 PERIOD = 2 ꢀ (AUXTM0 + 1) ꢀ t_CK

AUXTM1 (R/W)

15 14 13 12

11 10

9

1

8

7

6

5

1

4

1

3

1

2

1

0

1

DM (0x2013)

AUX1 PERIOD = 2 ꢀ (AUXTM1) ꢀ t_CK

OFFSET = 2 ꢀ (AUXTM1) ꢀ t_CK

Figure 27. Conﬁguration of Auxiliary PWM Register

Default bit values are shown; if no value is shown, the bit ﬁeld is undeﬁned at reset.

REV. 0

–31–

ADMCF341

ADC1 (R)

15 14 13 12

11 10

9

8

7

6

5

4

3

0

2

0

1

0

DM (0x2000)

0 = DATA READY

1 = NOT READY

CONVERSION

STATUS

ADC2 (R)

15 14 13 12

11 10

8

7

6

4

3

0

2

0

1

0

DM (0x2001)

0 = DATA READY

1 = NOT READY

CONVERSION

STATUS

ADC3 (R)

15 14 13 12

11 10

9

8

7

6

5

4

3

0

2

0

1

0

DM (0x2002)

0 = DATA READY

1 = NOT READY

CONVERSION

STATUS

ADCAUX (R)

15 14 13 12

11 10

8

7

3

0

2

0

1

0

DM (0x2003)

DM (0x2068)

I

_TRIM (R/W)

CONST

9

15 14 13 12

11 10

8

7

6

5

0

4

0

3

0

2

0

1

0

I

MIN = BITS 0 – 2 CLEARED.

MAX = BITS 0 – 2 SET.

CONST

I

SHA1_TM (R/W)

15

0

14

0

13

12

11

0

10

0

9

8

7

6

0

5

0

4

0

3

0

2

0

1

0

DM (0x2069)

0

SHA2 _TM (R/W)

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

0

7

0

6

0

5

0

4

0

3

0

2

0

1

0

DM (0x206A)

DM (0x206B)

SHA3 _TM (R/W)

15

0

14

0

13

0

12

0

11

0

10

0

9

8

7

6

0

5

0

4

0

3

0

2

0

1

0

Figure 28. Conﬁguration of ADC Registers

Default bit values are shown; if no value is shown, the bit ﬁeld is undeﬁned at reset.

Reserved bits are shown on a gray ﬁeld—these bits should always be written as shown.

–32–

REV. 0

ADMCF341

MODECTRL (R/W)

15 14 13 12

11 10

9

8

7

6

5

0

4

3

0

2

0

1

0

DM (0x2015)

0

ADC MUX CONTROL

00 VAUX0

SPORT 0

0 = SPORT MODE

1 = UART MODE

MODE SELECT

01 VAUX1

10 VAUX2

11 VREF

SPORT 0

0 = SPORT

PWMTRIP

INTERRUPT

0 = DISABLE

SPI MODE

1 = SPI MODE

1 = ENABLE

0 = STANDARD

1 = REVERSE

SPI CLOCK

POLARITY

PWMSYNC

INTERRUPT

0 = DISABLE

1 = ENABLE

0 = PHA0

1 = PHA1

SPI CLOCK

PHASE

0 = BOOT MODE

1 = UART MODE

SPORT1 MODE

SELECT

0 = I

SENSE

CHANNEL 3

SELECTION

ADC MUX

CONTROL

NOT USED IN ADMCF341

SET BIT TO ZERO

1 = VOLTAGE

0 = I

SENSE

CHANNEL 2

SELECTION

1 = VOLTAGE

PWM UPDATE

MODE SELECT

0 = SINGLE UPDATE MODE

1 = DOUBLE UPDATE MODE

0 = I

SENSE

CHANNEL 1

SELECTION

1 = VOLTAGE

0 = OFFSET MODE

AUX PWM

1 = INDEPENDENT MODE

MODE SELECT

0 = CLKIN RATE

ADC

1 = CLKOUT RATE

COUNTER

SYSSTAT (R)

15 14 13 12

11 10

9

0

8

7

6

0

5

0

4

0

3

2

1

0

DM (0x2016)

0

PWMTRIP

PIN STATUS

0 = LOW

1 = HIGH

0 = 1ST HALF OF PWM

CYCLE

0 = NORMAL

PWM TIMER

STATUS

WATCHDOG

STATUS

1 = WATCHDOG RESET

OCCURRED

1 = 2ND HALF OF PWM

CYCLE

IRQFLAG (R)

15 14 13 12

11 10

9

0

8

7

6

0

5

0

4

0

3

0

2

0

1

0

DM (0x2017)

0

PWMTRIP INTERRUPT

0 = NO INTERRUPT

1 = INTERRUPT

OCCURRED

PWMSYNC INTERRUPT

WDTIMER (W)

15 14 13 12

11 10

9

0

8

0

7

0

6

0

5

0

4

0

3

0

2

0

1

0

DM (0x2018)

0

Figure 29. Conﬁguration of Status/Control Registers

Default bit values are shown; if no value is shown, the bit ﬁeld is undeﬁned at reset.

Reserved bits are shown on a gray ﬁeld—these bits should always be written as shown.

REV. 0

–33–

ADMCF341

ICNTL

2

4

0

3

0

1

0

1

0

DSP REGISTER

0 = DISABLE

1 = ENABLE

INTERRUPT NESTING

IRQ0 SENSITIVITY

IRQ1 SENSITIVITY

IRQ2 SENSITIVITY

0 = LEVEL

1 = EDGE

IFC

15 14 13 12 11 10

9

0

8

7

0

6

0

5

0

4

0

3

0

2

0

1

0

DSP REGISTER

INTERRUPT CLEAR

INTERRUPT FORCE

IRQ2

TIMER

SPORT1 RECEIVE OR IRQ0

SPORT1 TRANSMIT OR IRQ1

SPORT0 TRANSMIT

SPORT0 RECEIVE

SOFTWARE 1

SOFTWARE 0

SOFTWARE 1

SOFTWARE 0

SPORT0 RECEIVE

SPORT0 TRANSMIT

SPORT1 TRANSMIT OR IRQ1

SPORT1 RECEIVE OR IRQ0

TIMER

IRQ2

IMASK (R/W)

15 14 13 12

11 10

9

0

8

7

6

5

0

4

3

0

2

1

0

DSP REGISTER

TIMER

PERIPHERAL (OR IRQ2)

SPORT1 RECEIVE

SPORT0 TRANSMIT

(OR IRQ0)

0 = DISABLE

(MASK)

D0I=SABLE

(MASK)

1 = ENABLE

SPORT0 RECEIVE

SPORT1 TRANSMIT

1 = ENABLE

(OR IRQ1)

SOFTWARE 1

SOFTWARE 0

Figure 30. Conﬁguration of Interrupt Control Registers

Default bit values are shown; if no value is shown, the bit ﬁeld is undeﬁned at reset.

Reserved bits are shown on a gray ﬁeld—these bits should always be written as shown.

–34–

REV. 0

ADMCF341

SYSCNTL (R/W)

15 14 13 12 11 10

9

8

7

6

5

1

4

1

3

1

2

1

0

1

DM (0x3FFF)

0

1

0

0 = DISABLED

1 = DISABLED

0 = FI, FO, IRQ0, IRQ1, SCLK

1 = SERIAL PORT

SPORT0 ENABLE

SPORT1 ENABLE

SPORT1 CONFIGURE

MEMWAIT (R/W)

0 = DISABLED

1 = ENABLED

15 14 13 12

11 10

9

8

7

6

5

1

4

1

3

1

2

1

0

1

DM (0x3FFE)

1

Figure 31. Conﬁguration of Registers

Default bit values are shown; if no value is shown, the bit ﬁeld is undeﬁned at reset.

Reserved bits are shown on a gray ﬁeld—these bits should always be written as shown.

REV. 0

–35–

ADMCF341

OUTLINE DIMENSIONS

Dimensions shown in mm and (inches).

28-Lead Wide-Body SOIC

(R-28)

18.10 (0.7125)

17.70 (0.6969)

28

1

15

7.60 (0.2992)

7.40 (0.2914)

10.65 (0.419)

10.00 (0.394)

14

PIN 1

2.65 (0.1043)

2.35 (0.0926)

0.75 (0.029)

0.25 (0.010)

ꢀ 45ꢁ

8ꢁ

0ꢁ

1.27

(0.0500)

BSC

0.51 (0.020) SEATING

0.30 (0.0118)

0.10 (0.0040)

1.27 (0.0500)

0.40 (0.016)

0.32 (0.0125)

0.23 (0.0091)

PLANE

0.33 (0.013)

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE

ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE

FOR USE IN DESIGN

–36–

REV. 0


型号：	ADMCF341-EVALKIT
厂家：	ADI
描述：	DashDSP⑩ 28-Lead Flash Mixed-Signal DSP with Enhanced Analog Front End DashDSP⑩ 28引脚闪存混合信号DSP增强型模拟前端闪存
文件：	总36页 (文件大小：1065K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADMCF341-EVALKIT [ADI]

相关型号：

ADMCF341BR

ADMOD79JQ

ADMP401-1

ADMP401-1ACEZ-RL

ADMP401-1ACEZ-RL7

ADMP401ACEZ

ADMP401ACEZ-RL

ADMP401ACEZ-RL7

ADMP404

ADMP404ACEZ

ADMP404ACEZ-RL

ADMP404ACEZ-RL7