ADSP-21MOD970-110 [ADI]
Multiport Internet Gateway Processor Solution; 多端的互联网网关处理器解决方案
| 型号： | ADSP-21MOD970-110 |
| 厂家： | 
ADI |
| 描述： | Multiport Internet Gateway Processor Solution |
| 文件： | 总6页 (文件大小：83K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Multiport Internet
Gateway Processor Solution
a
ADSP-21mod970-110
FEATURES
INTRODUCTION
High Density
The ADSP-21mod970-110 is a six-channel solution intended
for remote access server and remote access concentrator applica-
tions. It combines a highly integrated DSP processor with
downloadable software. All datapump and controller functions
are implemented on a single 1.45-square-inch chip. This modem
package allows the highest modem port density while achieving
the lowest power consumption in a software upgradable platform.
Implements Six Modem Channels in One Package
304-Ball PBGA with a 1.45 Square Inch (961 sq. mm.)
Footprint
ISDN B-Channel HDLC
DATA Modulations
CCITT V.90 (30 kbps–56 kbps)
K56Flex™ (30 kbps–56 kbps)
ITU-T V.34: 33600 Bits/s–2400 Bits/s
CCITT V.32bis: 14400 Bits/s–7200 Bits/s
CCITT V.32: 9600 Bits/s, 4800 Bits/s
CCITT V.23
CCITT V.22/V.22bis: 2400, 1200, 600 Bits/s
CCITT V.21: 300 Bits/s
Bell 212A: 1200 Bits/s
Bell 103: 300 Bits/s
Start-Up Procedures:
ITU-T V.8
Error Correction and Data Compression:
CCITT V.42 Error Correction (LAPM and MNP2-4)
CCITT V.42bis Data and MNP Class 5 Compression
FAX Modem
V.17/V.29/V.27ter/V.21 Channel 2
T.30 Protocol
The ADSP-21mod970-110 is designed for high-density systems
such as remote access servers, see Figure 1. Its high performance
DSP core, large on-chip SRAM, TDM serial port and 16-bit
DMA port provide efficient control and data communication
with minimal chip count. The modem software provides a num-
ber of data modulations, such as V.34, 56 kbps PCM and ISDN
with a software upgrade path to future standards and new appli-
cations, such as voice over network. The host interface allows
system access to modem statistics such as call progress, connect
speed and modulation parameters such as retrain count and
symbol rate.
ON-CHIP SRAM
The ADSP-21mod970-110 processor integrates 960K bytes
of on-chip memory. The modem datapump and controller
software, as well as data storage, are contained in the on-chip
SRAM. The SRAM cells are designed by Analog Devices. These
cells are optimized for high speed digital signal processing and
low power consumption. You can dynamically configure the
ADSP-21mod970-110 with software through the 16-bit DMA
interface.
V.120
V.110
PPP Asynchronous Framing Support (RFC 1662)
Low Power
80 mW per Channel Typical Active
Low Power and Sleep Modes
On-Chip DS0/DS1 Interface
Full Function DMA Port
No External Memory Required
3.3 V Supply
Fully Upgradable RAM-Based Architecture
Fast Download
DMA INTERFACE
The 16-bit internal DMA port (DMA Port) provides transpar-
ent, direct access to the on-chip RAM of the ADSP-21mod970-110
processor. This high speed access to on-chip memory simpli-
fies control and data communication and system debug. Use the
16-bit DMA interface to dynamically configure the ADSP-
21mod970-110 with software.
Full Image in 5 ms
High Speed 16-Bit Port Link Bus Provides Simple
Interface Between Host and Modem Pool
K56Flex is a trademark of Rockwell International and Lucent Technologies.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
World Wide Web Site: http://www.analog.com
© Analog Devices, Inc., 1999
ADSP-21mod970-110
DMA
ADSP-21mod970
SP0
DMA
ADSP-21mod970
SP0
DMA
ADSP-21mod970
SP0
DMA
ADSP-21mod970
SP0
PORT LINK
BUS
T1
E1
PRI
xDSL
ATM
HOST
ADSP-2183
FRAMER
DMA
ADSP-21mod970
SP0
DMA
ADSP-21mod970
SP0
DMA
ADSP-21mod970
SP0
DMA
ADSP-21mod970
SP0
LAN
OR
INTERNET
ADSP-21mod970 FUNCTIONS
HOST FUNCTIONS
MULTI-DSP CONTROL, OVERLAY MANAGEMENT
AND DATA TRANSFERS
V.34/56k MODEM
V.17 FAX
V.42, V.42bis, MNP2-5
DTMF DIALING
CALLER ID
HDLC PROTOCOL
Figure 1. ADSP-21mod970 Network Access System
SERIAL PORTS
Parallel Telco PCM Data Stream Architecture
The ADSP-21mod970-110 processor incorporates two complete
synchronous, double-buffered serial ports for serial communica-
tions. The serial ports interface directly to a time-division
multiplexed (TDM) 1544 kbps (T1) or 2048 kbps (E1) serial
stream, to an 8K sample/s data stream, or to an 8-bit companded
(64 kb/s) data stream (DS0). The serial ports operate under
modem software control.
The parallel Telco PCM data stream architecture, shown in
Figure 3, provides a single bus interface for all data and control.
In this architecture, the modem pool may have a remote Telco
interface that provides a parallel data stream of Telco PCM data
to the DSP through the DSP’s DMA Port. An arbitrary number
of DSPs can be connected, through the DMA Port, to a Host
that provides the parallel data stream.
Note: The number of parallel DSPs is limited only by the soft-
ware loading constraints on the Host.
SUPPORTED SYSTEM ARCHITECTURES
The ADSP-21mod970-110 Multiport Internet Gateway Proces-
sor supports two system architectures: serial Telco PCM TDM
data stream and parallel Telco PCM data stream. The two archi-
tectures are differentiated by the method of proving Telco PCM
data to the DSP Modem.
MEMORY
I/F
DMA
PORT
ADSP-21mod970
ADSP-21mod970
ADSP-21mod970
ADSP-21mod970
Serial Telco PCM TDM Data Stream Architecture
The serial Telco PCM TDM data stream architecture, shown in
Figure 2, is the most common architecture. In this architecture,
the modem pool may have a local Telco interface that provides
a serial TDM data stream of Telco PCM data to the DSP through
the DSP’s Serial Port. You can connect up to 24/32 DSPs,
through the Serial Port, to a 24-/32-channel serial TDM data
stream.
HOST
MEMORY
I/F
DMA
PORT
SERIAL
PORT
TELCO PCM
I/F
ADSP-21mod970
ADSP-21mod970
ADSP-21mod970
ADSP-21mod970
Figure 3. Parallel Telco PCM Data Stream Architecture
TELCO PCM
I/F
HOST
Figure 2. Serial Telco PCM TDM Data Stream Architecture
–2–
REV. 0
ADSP-21mod970-110
Table I. FIFO Example
SOFTWARE INTERFACE
Analog Devices provides sample C code for the software inter-
face to the ADSP-21mod970-110. The software interface en-
compasses the following four areas—download, control interface,
data interface and modem statistics.
BASE
Download
The DMA Port on the ADSP-21mod970-110 contains an auto-
incrementing address generator. The host writes the starting
address of the transfer and then writes the first word of data.
After the first write, the DMA address generator automatically
increments; the host writes the next data word and the DMA
transfers that word to the next location in ADSP-21mod970-
110 memory.
PD_PTR
INFO
INFO
INFO
INFO
The executable image contains code and data that must be
loaded into program and data memory. Program memory on the
ADSP-21mod970-110 is 24 bits wide, therefore two transfers
are used to load each word of program memory.
WR_PDR
BASE + SIZE
The host begins the download by asserting the RESET pin of
the ADSP-21mod970-110. The host then transfers all code and
data. All internal memory can be loaded in 5 ms.
Control Interface
Modem Statistics
The ADSP-21mod970-110 is controlled through two FIFOs in
DSP memory. The host sends a control event by writing to the
host-to-modem FIFO. The ADSP-21mod970-110 posts events to
the host by writing into the modem-to-host FIFO.
Several modem statistics can be gathered through the DMA
Port. These statistics include call status, modulation in use,
connect rate, transmit and receive data rate, symbol rate, retrain
count, rate renegotiation count and others. Table II and Table IV
contain a complete listing of available modem statistics.
Data Interface
All data transferred to and from the ADSP-21mod970-110
passes through word FIFOs located in internal memory on the
ADSP-21mod970-110. The FIFOs are accessed through a
control structure that contains a pointer to the start of the FIFO
in memory, the length of the FIFO in 16-bit words, a pointer to
the next address to be read, and a pointer to the next address to
be written. The transmit and receive FIFOs are 1024 bytes
deep. Example code providing primitives for accessing the byte-
FIFOs is available from Analog Devices. Table I shows an ex-
ample of a data FIFO.
Modem Configuration
The modem is configured by programming various parameters
through the DMA Port. Table III and Table V contain complete
lists of modem configuration parameters.
Table II. Shell Status
Reference #
Function
SS. 0
SS. 1
SS. 2
SS. 3
Product Number
Application Version
Application Type
Programmable Flag Data
Table III. Shell Parameters
Reference #
Function
SP. 0
SP. 1
SP. 2
SP. 3
SP. 4
SP. 5
Serial Port Tx Time Slot
Serial Port Rx Time Slot
Serial Port Configuration
Programmable Flag Control
Programmable Flag Data
Host Interrupt Count
REV. 0
–3–
ADSP-21mod970-110
Table IV. Modem Status
Table V. Modem Parameters
Reference # Function
Reference # Function
MS. 0
MS. 1
MS. 2
MS. 3
Data Modulation State
SNR MSE Measure
Rx Level dBm
Tx Level dBm
MP. 0
MP. 1
MP. 2
Omc Data Modulation Originate Enable
Dial Billing Delay Duration
Omc Data Modulation/Data Protocol
Maximum Start-Up Duration
Data Protocol Start Delay
MS. 4
Tx V.34 Symbol Rate
MP. 3
MS. 5
MS. 6
MS. 7
MS. 8
Rx V.34 Symbol Rate
Round Trip Delay
Telemetry Data Update
Constellation X
Constellation Y
Variable 2 X Pointer
Variable 2 Y Pointer
Variable 3 X Pointer
MP. 4
MP. 5
MP. 6
MP. 7
MP. 8
MP. 9
MP. 10
MP. 11
MP. 12
MP. 13
MP. 14
MP. 15
MP. 16
MP. 17
Data Protocol Allowed Mask
Data Protocol Preferred Mask
Data Protocol Auto-Select Mask
Data Protocol Compression Mask
Data Protocol Cmn Binary Enable
Data Protocol Cmn HDLC Enable
Data Protocol LAPM to Sync
Data Protocol MNP Block Mode Enable
Data Protocol MNP Data Compression Select
Data Protocol MNP Header Optimize Enable
Data Protocol MNP Maximum Data Size
Data Protocol MNP Service Class
Data Protocol Disconnect Management Mode
Data Protocol Disconnect Management
Duration
MS. 9
MS. 10
MS. 11
MS. 12
MS. 13
MS. 14
MS. 15
MS. 16
MS. 17
MS. 18
MS. 19
Variable 3 Y Pointer
Variable 4 X Pointer
Variable 4 Y Pointer
Data Modulation Monitor Retrain Local Count
Data Modulation Monitor Retrain Remote Count
Data Modulation Monitor Retrain Auto Count
Data Modulation Monitor Renegotiate Local
Count
Data Modulation Monitor Renegotiate Remote
Count
Data Modulation Monitor Renegotiate Auto
Count
Omc Carrier Family
MP. 18
MP. 19
MP. 20
MP. 21
MP. 22
MP. 23
MP. 24
Digital Data Modes
Pump Data Modes
Pump Tone Transmit Level
Pump Transmit Level
MS. 20
MS. 21
Pump V.34 Transmit Level
MS. 22
MS. 23
MS. 24
MS. 25
MS. 26
MS. 27
MS. 28
MS. 29
MS. 30
MS. 31
MS. 32
MS. 33
MS. 34
MS. 35
MS. 36
MS. 37
MS. 38
MS. 39
MS. 40
MS. 41
Data Modulation Carrier Detect Duration
Data Modulation Carrier Loss Disconnect
Timer Duration
Data Modulation Line Quality Monitor Mode
Data Modulation Options Mask
Data Modulation V.32 Rate Enable Mask
Data Modulation V.34 Data Rate Mask
V.PCM Maximum Power
V.PCM Reference Point
K56 RBS Maximum
K56 Tx Data Rate Maximum
K56 Tx Data Rate Minimum
DTE Interface Big Endian
Omc Disconnect Reason
Omc State
Omc Time
MP. 25
MP. 26
MP. 27
MP. 28
MP. 29
MP. 30
MP. 31
MP. 32
MP. 33
MP. 34
MP. 35
MP. 36
MP. 37
MP. 38
MP. 39
Omc Idle Time Start
Omc Data Protocol Time Start
Omc Initial Rx Data Rate
Omc Current Rx Data Rate
Omc Initial Tx Data Rate
Omc Current Tx Data Rate
Data Protocol
Data Protocol Compression
Data Protocol Rx HDLC Error Frame Count
Data Protocol Rx HDLC Frame Count
Data Protocol Tx HDLC Frame Count
Data Protocol Tx Data Frame Count
Data Protocol Tx Data Frame Retransmit Count
Data Protocol Rx Data Frame Count
Data Protocol Rx Data Frame Missing Count
Data Modulation Monitor Retrain Remote
Count
PPP Rx Mode Enable
PPP Tx Mode Enable
fP PPP Detect Enable
fP PPP Rx ACCM
fP PPP Tx ACCM
MS. 42
MS. 43
Data Protocol Call Tx Data Compressibility
Metric
Data Protocol Call Rx Data Compressibility
Metric
MS. 44
MS. 45
MS. 46
MS. 47
MS. 48
Data Protocol Call Tx Data Metric
Data Protocol Call Rx Data Metric
V.PCM Digital Attenuation
V.PCM Robbed Bit Mask
V.PCM Coding Law
–4–
REV. 0
ADSP-21mod970-110
ORDERING GUIDE
Package
Option
Part Number
Description
Processor Clock
Package Description
304 Plastic Ball Grid Array
ADSP-21mod970-110 with
Unit Software License
312 MIPS DSP with Modem
Software Unit License
26.0 MHz
BP-304
RELATED DOCUMENTS
For further information see the ADSP-21mod970 Multiport Internet Gateway Processor data sheet.
ESD SENSITIVITY
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the ADSP-21mod970-110 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precau-
tions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. 0
–5–
ADSP-21mod970-110
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
304-Plastic Ball Grid Array
(BP-304)
1.224 (31.10)
1.220 (31.00) SQ
1.217 (30.90)
0.050 (1.27)
BSC
23 22 21201918 17 16 15 14 13 12 11 10
9
8 7 6 5 4 3 2 1
A
B
C
D
E
F
G
H
J
K
L
M
N
1.104 (28.04)
1.100 (27.94)
1.096 (27.84)
TOP VIEW
BOTTOM VIEW
P
R
T
U
V
W
Y
AA
AB
AC
1.104 (28.04)
1.100 (27.94)
1.096 (27.84)
0.050 (1.27)
BSC
1.051 (26.70)
1.037 (26.35) SQ
1.024 (26.00)
DETAIL A
DETAIL A
0.100 (2.54)
0.092 (2.33)
0.083 (2.12)
0.048 (1.22)
0.046 (1.17)
0.044 (1.12)
0.024 (0.62)
0.022 (0.56)
0.020 (0.50)
NOTE
THE ACTUAL POSITION OF THE BALL POPULATION IS WITHIN 0.011 (0.30)
OF ITS IDEAL POSITION RELATIVE TO THE PACKAGE EDGES. THE
ACTUAL POSITION OF EACH BALL IS WITHIN 0.004 (0.10) OF ITS IDEAL
POSITION RELATIVE TO THE BALL POPULATION.
0.008 (0.20)
MAX
0.028 (0.70)
0.024 (0.60)
0.020 (0.50)
0.035 (0.90)
0.030 (0.75)
0.024 (0.60)
SEATING
PLANE
BALL DIAMETER
–6–
REV. 0
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