ADV7403KSTZ-1402_技术文档

12-Bit, Integrated, Multiformat SDTV/HDTV

Video Decoder and RGB Graphics Digitizer

ADV7403

GENERAL DESCRIPTION

FEATURES

Four Noise Shaped Video® 12-bit ADCs sampling up to

140 MHz (140 MHz speed grade only)

12 analog input channel mux

SCART fast blank support

Internal antialias filters

NTSC/PAL/SECAM color standards support

525p-/625p-component progressive scan support

720p-/1080i-component HDTV support

Digitizes RGB graphics up to 1280 × 1024 @ 75 Hz (SXGA)

(140 MHz speed grade only)

24-bit digital input port supports data from DVI/HDMI Rx IC

Any-to-any, 3 × 3 color-space conversion matrix

Industrial temperature range (−40°C to +85°C)

12-bit 4:4:4/10-/8-bit 4:2:2 DDR pixel output interface

Programmable interrupt request output pin

VBI data slicer (including teletext)

The ADV7403 is a high quality, single chip, multiformat video

decoder and graphics digitizer. This multiformat decoder

supports the conversion of PAL, NTSC, and SECAM standards

in the form of composite or S-video into a digital ITU-R BT.656

format. The ADV7403 also supports the decoding of a

component RGB/YPrPb video signal into a digital YCrCb or

RGB pixel output stream. The support for component video

includes standards such as 525i, 625i, 525p, 625p, 720p, 1080i,

1250i, and many other HD and SMPTE standards. Graphic

digitization is also supported by the ADV7403; it is capable of

digitizing RGB graphics signals from VGA to SXGA rates and

converting them into a digital RGB or YCrCb pixel output

stream. SCART and overlay functionality are enabled by the

ADV7403’s ability to simultaneously process CVBS and

standard definition RGB signals. The mixing of these signals is

controlled by the fast blank pin.

The ADV7403 contains two main processing sections. The first

is the standard definition processor (SDP), which processes all

PAL, NTSC, and SECAM signal types. The second is the

component processor (CP), which processes YPrPb and RGB

component formats, including RGB graphics. For more specific

descriptions of the ADV7403 features, see the Detailed

Functionality and Detailed Description sections.

APPLICATIONS

LCD/DLP™ rear projection HDTVs

PDP HDTVs

CRT HDTVs

LCD/DLP front projectors

LCD TV (HDTV ready)

HDTV STBs with PVR

Hard-disk-based video recorders

Multiformat scan converters

DVD recorders with progressive scan input support

AVR receiver

Rev. SpA

Information furnished by Analog Devices is believed to be accurate and reliable.

However, no responsibility is assumed by Analog Devices for its use, nor for any

infringements of patents or other rights of third parties that may result from its use.

Specifications subject to change without notice. No license is granted by implication

or otherwise under any patent or patent rights of Analog Devices. Trademarks and

registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.461.3113

www.analog.com

ADV7403

TABLE OF CONTENTS

Functional Block Diagram .............................................................. 3

CP Pixel Data Output Modes ................................................... 13

Composite and S-Video Processing......................................... 13

Component Video Processing.................................................. 14

RGB Graphics Processing ......................................................... 14

Digital Video Input Port............................................................ 14

General Features......................................................................... 14

Detailed Description...................................................................... 15

Analog Front End....................................................................... 15

Standard Definition Processor ................................................. 15

Component Processor ............................................................... 15

Pixel Input/Output Formatting .................................................... 17

Recommended External Loop Filter Components.................... 19

Typical Connection Diagram ....................................................... 20

Outline Dimensions....................................................................... 21

Ordering Guide .......................................................................... 21

Electrical Characteristics................................................................. 4

Video Specifications......................................................................... 6

Timing Characteristics..................................................................... 7

Analog Specifications....................................................................... 8

Absolute Maximum Ratings............................................................ 9

Stress Ratings ................................................................................ 9

Package Thermal Performance................................................... 9

Thermal Specifications ................................................................ 9

ESD Caution.................................................................................. 9

Pin Configuration and Function Descriptions........................... 10

Timing Diagrams............................................................................ 12

Detailed Functionality ................................................................... 13

Analog Front End....................................................................... 13

SDP Pixel Data Output Modes ................................................. 13

REVISION HISTORY

9/05—Rev. Sp0 to Rev. SpA

Deleted EDTV.....................................................................Universal

Added AVR Receiver to Applications Section.............................. 1

Change to Crystal Normal Frequency Typ Value in Table 3 ...... 7

Changes to Figure 2 ....................................................................... 10

Changes to Function Descriptions of Pin 37 and Pin 38 .......... 11

Change Pin 70 Type........................................................................ 11

Change to Crystal MHz Unit Value ............................................. 13

Added Pixel Input Information to Table 9 and Table 10........... 17

Changes to Figure 9........................................................................ 20

4/05—Revision Sp0: Initial Version

Rev. SpA | Page 2 of 24

ADV7403

FUNCTIONAL BLOCK DIAGRAM

OUTPUT FIFO AND FORMATTER

Figure 1.

Rev. SpA | Page 3 of 24

ADV7403

ELECTRICAL CHARACTERISTICS

@ AVDD = 3.15 V to 3.45 V, DVDD = 1.65 V to 2.0 V, DVDDIO = 3.0 V to 3.6 V, PVDD = 1.71 V to 1.89 V, nominal input range 1.6 V.

Operating temperature range, a otherwise noted.

Table 1.

Parameter^{1, 2, 3}

Symbol

Test Conditions

Min Typ

Max

Unit

STATIC PERFORMANCE^{4, 5}

Resolution (each ADC)

Integral Nonlinearity

Differential Nonlinearity

N

12

±±.ꢀ

Bits

LSB

INL

DNL

BSL at 27 MHz (at a 12-bit level)

BSL at 54 MHz (at a 12-bit level)

BSL at 74 MHz (at a 1ꢀ-bit level)

BSL at 11ꢀ MHz (at a 1ꢀ-bit level)

BSL at 135 MHz (at an ±-bit level)⁶

At 27 MHz (at a 12-bit level)

At 54 MHz (at a 12-bit level)

At 74 MHz (at a 1ꢀ-bit level)

At 11ꢀ MHz (at a 1ꢀ-bit level)

At 135 MHz (at an ±-bit level)⁶

±2.ꢀ

−2.ꢀ/+2.5

±1.ꢀ

−3.ꢀ/+3.ꢀ

±1.3

−ꢀ.7/+ꢀ.±5 −ꢀ.99/+2.5

−ꢀ.75/+ꢀ.9

±ꢀ.75

−ꢀ.7/+5.ꢀ

−ꢀ.±/+2.5

DIGITAL INPUTS

Input High Voltage⁷

Input Low Voltage^±

Input High Voltage

Input Low Voltage

Input Current

V_IH

V_IL

V_IH

V_IL

I_IN

2

V

μA

pF

ꢀ.±

HS_IN, VS_IN low trigger mode

Pins listed in Note 9

ꢀ.7

ꢀ.3

−6ꢀ

−1ꢀ

+6ꢀ

+1ꢀ

1ꢀ

All other input pins

Input Capacitance^1ꢀ

C_IN

DIGITAL OUTPUTS

Output High Voltage¹¹

Output Low Voltage¹¹

High Impedance Leakage Current

V_OH

V_OL

I_LEAK

ISOURCE = ꢀ.4 mA

ISINK = 3.2 mA

Pins listed in Note 12

All other output pins

2.4

V

μA

pF

ꢀ.4

6ꢀ

1ꢀ

2ꢀ

Output Capacitance^1ꢀ

POWER REQUIREMENTS^1ꢀ

Digital Core Power Supply

Digital I/O Power Supply

PLL Power Supply

C_OUT

DVDD

DVDDIO

PVDD

AVDD

IDVDD

1.65 1.±

3.ꢀ 3.3

2

V

3.6

1.±9

3.45

1.71 1.±

3.15 3.3

1ꢀ5

137

1ꢀ6

4

Analog Power Supply

Digital Core Supply Current

CVBS input sampling at 54 MHz

Graphics RGB sampling at 135 MHz

SCART RGB FB sampling at 54 MHz

CVBS input sampling at 54 MHz

Graphics RGB sampling at 135 MHz

CVBS input sampling at 54 MHz

Graphics RGB sampling at135 MHz

CVBS input sampling at 54 MHz

Graphics RGB sampling at 135 MHz

SCART RGB FB sampling at 54 MHz

mA

ms

Digital I/O Supply Current

PLL Supply Current

IDVDDIO

IPVDD

19

11

12

99

242

269

2.25

16

Analog Supply Current¹³

IAVDD

Power-Down Current

Green Mode Power-Down

Power-Up Time

IPWRDN

IPWRDNG Sync bypass function

TPWRUP

2ꢀ

¹The min/max specifications are guaranteed over this range.

²Temperature range T_MINto T_MAX: −4ꢀ°C to +±5°C (ꢀ°C to 7ꢀ°C temperature range for ADV74ꢀ3KSTZ-14ꢀ).

³All specifications obtained using programming scripts with the following sequence included: Addr ꢀxꢀE - data ꢀx±ꢀ, Addr ꢀx54 - data ꢀxꢀꢀ, Addr ꢀxꢀE - data ꢀxꢀꢀ.

Rev. SpA | Page 4 of 24

ADV7403

⁴All ADC linearity tests performed at input range of full scale − 12.5%, and at zero scale + 12.5%.

⁵Max INL and DNL specifications obtained with part configured for component video input.

⁶Specification for ADV74ꢀ3KSTZ-14ꢀ only.

⁷To obtain specified V_IHlevel on Pin 3±, Register ꢀx13 (wo) must be programmed with value ꢀxꢀ4. If Register ꢀx13 is programmed with value ꢀxꢀꢀ,

then V_IHon Pin 3± = 1.2 V.

^±To obtain specified V_ILlevel on Pin 3±, Register ꢀx13 (wo) must be programmed with value ꢀxꢀ4. If Register ꢀx13 is programmed with value ꢀxꢀꢀ,

then V_ILon Pin 3± = ꢀ.4 V.

⁹Pins 1, 2, 13, 14, 16, 19, 24, 29, 3ꢀ, 31, 32, 33, 34, 35, 45, 7±, 79, ±3, ±4, ±7, ±±, 95, 96, 97, 1ꢀꢀ.

^1ꢀGuaranteed by characterization.

11

V

OH

and V_OLlevels obtained using default drive strength value (ꢀxD5) in Register Subaddress ꢀxF4.

¹²Pins 3, 13, 14, 19, 24, 29, 3ꢀ, 31, 32, 33, 34, 45.

¹³Analog current measurements for CVBS made with ADCꢀ powered up only, For RGB, ADCꢀ, ADC1, and ADC2 powered up only, for SCART FB, all ADCs powered up.

Rev. SpA | Page 5 of 24

ADV7403

VIDEO SPECIFICATIONS

@ AVDD= 3.15 V to 3.45 V, DVDD = 1.65 V to 2.0 V, DVDDIO = 3.0 V to 3.6 V, PVDD = 1.71 V to 1.89 V. Operating temperature range,

unless otherwise noted.

Table 2.

Parameter^{1, 2, 3}

Symbol

Test Conditions

Min

Typ

Max

Unit

NONLINEAR SPECIFICATIONS

Differential Phase

Differential Gain

DP

DG

LNL

CVBS input, modulated 5 step

CVBS input, 5 step

ꢀ.4

degree

%

Luma Nonlinearity

NOISE SPECIFICATIONS

SNR Unweighted

Analog Front End Crosstalk

LOCK TIME SPECIFICATIONS

Horizontal Lock Range

Vertical Lock Range

Luma ramp

Luma flat field

61

64

65

6ꢀ

dB

−5

4ꢀ

+5

7ꢀ

%

Hz

F_SCSubcarrier Lock Range

Color Lock in Time

±1.3

6ꢀ

kHz

line

%

Sync Depth Range⁴

2ꢀ

5

2ꢀꢀ

Color Burst Range

%

Vertical Lock Time

2

1ꢀꢀ

field

line

Horizontal Lock Time

CHROMA SPECIFICATIONS

Hue Accuracy

Color Saturation Accuracy

Color AGC Range

HUE

CL_AC

1

degree

%

5

4ꢀꢀ

Chroma Amplitude Error

Chroma Phase Error

Chroma Luma Intermodulation

LUMA SPECIFICATIONS

Luma Brightness Accuracy

Luma Contrast Accuracy

ꢀ.4

ꢀ.3

ꢀ.1

%

degree

%

CVBS, 1 V input

1

%

¹The min/max specifications are guaranteed over this range.

²Temperature range T_MINto T_MAX: −4ꢀ°C to +±5°C (ꢀ°C to 7ꢀ°C temperature range for ADV74ꢀ3KSTZ-14ꢀ).

³Guaranteed by characterization.

⁴Nominal sync depth is 3ꢀꢀ mV at 1ꢀꢀ% sync depth range.

Rev. SpA | Page 6 of 24

ADV7403

TIMING CHARACTERISTICS

@ AVDD = 3.15 V to 3.45 V, DVDD = 1.65 V to 2.0 V, DVDDIO = 3.0 V to 3.6 V, PVDD = 1.71 V to 1.89 V. Operating temperature range,

unless otherwise noted.

Table 3.

Parameter^{1, 2, 3}

Symbol Test Conditions

Min

Typ

Max

Unit

SYSTEM CLOCK AND CRYSTAL

Crystal Nominal Frequency

Crystal Frequency Stability

Horizontal Sync Input Frequency

LLC1 Frequency Range⁴

I²C PORT⁵

2±.63636

MHz

ppm

kHz

±5ꢀ

11ꢀ

14ꢀ

14.±

12.±25

MHz

SCLK Frequency

4ꢀꢀ

kHz

μs

ns

μs

SCLK Min Pulse Width High

SCLK Min Pulse Width Low

Hold Time (Start Condition)

Setup Time (Start Condition)

SDA Setup Time

SCLK and SDA Rise Time

SCLK and SDA Fall Time

Setup Time for Stop Condition

RESET FEATURE

t₁

t₂

t₃

t₄

t₅

t₆

t₇

t_±

ꢀ.6

1.3

ꢀ.6

1ꢀꢀ

3ꢀꢀ

ꢀ.6

Reset Pulse Width

5

ms

CLOCK OUTPUTS

LLC1 Mark Space Ratio

t₉:t_1ꢀ

45:55

55:45 % duty

cycle

DATA and CONTROL OUTPUTS

Data Output Transition Time SDR (SDP)⁶

t₁₁

t₁₂

t₁₃

t₁₄

t₁₅

t₁₆

t₁₇

t_1±

Negative clock edge to start of

valid data

End of valid data to negative

clock edge

End of valid data to negative

clock edge

Negative clock edge to start of

valid data

Positive clock edge to end of

valid data

Positive clock edge to start of

valid data

Negative clock edge to end of

valid data

3.6

2.4

2.±

ꢀ.1

ns

Data Output Transition Time SDR (SDP)⁶

Data Output Transition Time SDR (CP)⁷

Data Output Transition Time DDR (CP)^{7, ±}

−4 + TLLC1/4

ꢀ.25 + TLLC1/4

−2.95 + TLLC1/4

−ꢀ.5 + TLLC1/4

Negative clock edge to start of

valid data

DATA and CONTROL INPUTS⁵

Input Setup Time (Digital Input Port)

t₁₉

t_2ꢀ

HS_IN, VS_IN

DE_IN, data inputs

HS_IN, VS_IN

9

2.2

7

ns

Input Hold Time (Digital Input Port)

DE_IN, data inputs

2

¹The min/max specifications are guaranteed over this range.

²Temperature range T_MINto T_MAX: −4ꢀ°C to +±5°C (ꢀ°C to 7ꢀ°C temperature range for ADV74ꢀ3KSTZ-14ꢀ).

³Guaranteed by characterization.

⁴Maximum LLC1 frequency is 11ꢀ MHz for ADV74ꢀ3BSTZ-11ꢀ.

⁵TTL input values are ꢀ V to 3 V, with rise/fall times ≥3 ns, measured between the 1ꢀ% and 9ꢀ% points.

⁶SDP timing figures obtained using default drive strength value (ꢀxD5) in register subaddress ꢀxF4.

⁷CP timing figures obtained using max drive strength value (ꢀxFF) in Register Subaddress ꢀxF4.

^±DDR timing specifications dependent on LLC1 output pixel clock; TLCC1/4 = 9.25 ns at LLC1 = 27 MHz.

Rev. SpA | Page 7 of 24

ADV7403

ANALOG SPECIFICATIONS

@ AVDD = 3.1.5 V to 3.45 V, DVDD = 1.65 V to 2.0 V, DVDDIO = 3.0 V to 3.6 V, PVDD = 1.71 V to 1.89 V. Operating temperature

range, unless otherwise noted. Recommended analog input video signal range: 0.5 V to 1.6V , typically 1 V p-p.

Table 4.

Parameter^{1, 2, 3}

Test Conditions

Min

Typ

Max

Unit

CLAMP CIRCUITRY

External Clamp Capacitor

Input Impedance⁴

Input Impedance of Pin 51 (FB)

CML

ꢀ.1

1ꢀ

2ꢀ

1.±6

μF

MΩ

kΩ

V

Clamps switched off

ADC Full-Scale Level

ADC Zero-Scale Level

ADC Dynamic Range

Clamp Level (When Locked)

CML + ꢀ.± V

CML − ꢀ.± V

1.6

CML − ꢀ.292 V

CML − ꢀ.4 V

CML − ꢀ.292 V

CML – ꢀ V

CML – ꢀ.3 V

CML − ꢀ.3 V

ꢀ.75

V

CVBS input

SCART RGB input (R, G, B signals)

S-Video input (Y signal)

S-Video input (C signal)

Component input (Y, Pr, Pb signals)

PC RGB input (R, G, B signals)

SDP only

V

Large Clamp Source Current

Large Clamp Sink Current

Fine Clamp Source Current

Fine Clamp Sink Current

mA

μA

ꢀ.9

17

¹The min/max specifications are guaranteed over this range.

²Temperature range T_MINto T_MAX:−4ꢀ°C to +±5°C (ꢀ°C to 7ꢀ°C temperature range for ADV74ꢀ3KSTZ-14ꢀ).

³Guaranteed by characterization.

⁴Except Pin 51 (FB).

Rev. SpA | Page ± of 24

ADV7403

ABSOLUTE MAXIMUM RATINGS

STRESS RATINGS

Table 5.

Parameter

Rating

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

AVDD to AGND

DVDD to DGND

PVDD to AGND

DVDDIO to DGND

DVDDIO to AVDD

PVDD to DVDD

DVDDIO to PVDD

DVDDIO to DVDD

AVDD to PVDD

AVDD to DVDD

Digital Inputs Voltage to

DGND

Digital Outputs Voltage to

DGND

Analog Inputs to AGND

Maximum Junction

4 V

2.2 V

4 V

−ꢀ.3 V to +ꢀ.3 V

−ꢀ.3 V to +2 V

DGND − ꢀ.3 V to DVDDIO+ ꢀ.3 V

PACKAGE THERMAL PERFORMANCE

To reduce power consumption when using the part the user is

advised to turn off any unused ADCs .

The junction temperature must always stay below the

maximum junction temperature (T_{J MAX}) of 125°C. This

equation shows how to calculate the junction temperature:

DGND − ꢀ.3 V to DVDDIO+ ꢀ.3 V

AGND − ꢀ.3 V to AVDD + ꢀ.3 V

T_J= T_{A Max}+ (θ_JA× W_Max

where:

_{A Max}= 85°C.

_JA= 30°C/W.

)

Temperature (T_{J MAX}

Storage Temperature Range

Infrared Reflow Soldering

(2ꢀ sec)

)

125°C

−65°C to +15ꢀ°C

T

θ

W

_Max= ((AVDD × IAVDD)+(DVDD × IDVDD)+ (DVDDIO ×

IDVDDIO) + (PVDD × IPVDD)).

26ꢀ°C

THERMAL SPECIFICATIONS

Table 6.

Thermal Characteristics

Symbol

θ_JC

θ_JA

Test Conditions

Typ

7

3ꢀ

Unit

°C/W

Junction-to-Case Thermal Resistance

Junction-to-Ambient Thermal Resistance

4-layer PCB with solid ground plane

4-layer PCB with solid ground plane (still air)

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4ꢀꢀꢀ V readily accumulate on the

human body and test equipment and can discharge without detection. Although this product features

proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy

electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance

degradation or loss of functionality.

Rev. SpA | Page 9 of 24

ADV7403

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

1

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

AIN12

AIN5

P32

PIN 1

2

P31

3

AIN11

AIN4

INT

4

CS/HS

5

AIN10

TEST0

CAPC2

CAPC1

BIAS

DGND

6

DVDDIO

7

P15

8

P14

9

P13

10

P12

AGND

CML

ADV7403

11

DGND

12

REFOUT

AVDD

CAPY2

CAPY1

AGND

TEST1

AIN3

DVDD

LQFP

TOP VIEW

(Not to Scale)

13

14

15

16

17

18

19

20

21

22

23

24

25

P29

P28

SFL/SYNC_OUT

SCLK2

DGND

DVDDIO

SDA2

P11

AIN9

AIN2

AIN8

P10

AIN1

P9

AIN7

P8

SOG

P27

FB

P7

Figure 2. Pin Configuration

Table 7. Pin Function Descriptions

Pin No.

5, 11, 17, 4ꢀ, ±9

49, 5ꢀ, 6ꢀ, 66

6, 1±

12, 39, 9ꢀ

63

47, 4±

51

54, 56, 5±, 72, 74,

76, 53, 55, 57, 71,

73, 75

Mnemonic

Type

Function

DGND

AGND

DVDDIO

DVDD

AVDD

PVDD

FB

AIN1 to AIN12

G

P

I

Digital Ground.

Analog Ground.

Digital I/O Supply Voltage (3.3 V).

Digital Core Supply Voltage (1.± V).

Analog Supply Voltage (3.3 V).

PLL Supply Voltage (1.± V).

Fast Switch Overlay Input. This pin switches between CVBS and RGB analog signals.

Analog Video Input Channels.

I

42, 41, 2±, 27, 26,

25, 23, 22, 1ꢀ, 9, ±,

7, 94, 93, 92, 91

44, 43, 21, 2ꢀ, 45,

34, 33, 32, 31, 3ꢀ,

29, 24, 14, 13

P2 to P9, P12 to P19

O

Video Pixel Output Port.

Video Pixel Input/Output Port.

Video Pixel Input Port.

Pꢀ to P1, P1ꢀ to P11, I/O

P2ꢀ to P21, P22 to

P25, P26 to P29

2, 1, 1ꢀꢀ, 97, 96,

95, ±±, ±7, ±4, ±3

P31 to P4ꢀ

I

Rev. SpA | Page 1ꢀ of 24

ADV7403

Pin No.

Mnemonic

Type

Function

3

INT

O

Interrupt. This pin can be active low or active high. When SDP/CP status bits change,

this pin triggers. The set of events that triggers an interrupt is under user control.

4

HS/CS

O

HS is a Horizontal Synchronization Output Signal (SDP and CP modes). CS is a Digital

Composite Synchronization Signal (and can be selected while in CP mode).

99

9±

VS

FIELD/DE

O

Vertical Synchronization Output Signal (SDP and CP modes).

FIELD is a Field Synchronization Output Signal (all interlaced video modes). This

pin also can be enabled as a Data Enable signal (DE) in CP mode to allow direct

connection to a HDMI/DVI Tx IC.

±1, 19

±2, 16

±ꢀ

SDA1, SDA2

SCLK1, SCLK2

ALSB

I/O

I²C Port Serial Data Input/Output Pins. SDA1 is the data line for the control port, and

SDA2 is the data line for the VBI readback port.

I²C Port Serial Clock Input (max clock rate of 4ꢀꢀ kHz). SCLK1 is the clock line for the

Control port and SCLK2 is the clock line for the VBI data readback port.

This pin selects the I²C address for the ADV74ꢀ3 control and VBI readback ports. ALSB

set to Logic ꢀ sets the address for a write to control port of ꢀx4ꢀ and the readback

address for the VBI port of ꢀx21. ALSB set to a logic high sets the address for a write to

control port of ꢀx42 and the readback address for the VBI port of ꢀx23.

I

7±

36

3±

37

RESET

LLC1

I

System Reset Input. Active low. A minimum low reset pulse width of 5 ms is required

to reset the ADV74ꢀ3 circuitry.

LLC1 is a line-locked output clock for the pixel data (range is 12.±25 MHz to 14ꢀ MHz

for ADV74ꢀ3KSTZ-14ꢀ; 12.±25 MHz to 11ꢀ MHz for ADV74ꢀ3BSTZ-11ꢀ.

Input Pin for 2±.63636 MHz crystal, or can be overdriven by an external 3.3 V,

2±.63636 MHz clock oscillator source to clock the ADV74ꢀ3.

This pin should be connected to the 2±.63636 MHz crystal or left as a no connect if an

external 3.3 V 2±.63636 MHz clock oscillator source is used to clock the ADV74ꢀ3. In

crystal mode the crystal must be a fundamental crystal.

O

I

XTAL

XTAL1

O

46

7ꢀ

59

15

ELPF

TESTꢀ

TEST1

SFL/SYNC_OUT

O

NC

O

The recommend external loop filter must be connected to this ELPF pin.

This pin should be left unconnected or alternaltely tie to AGND.

This pin should be left unconnected.

Subcarrier Frequency Lock (SFL). This pin contains a serial output stream, which can

be used to lock the subcarrier frequency when this decoder is connected to any

Analog Devices digital video encoder. SYNC_OUT is the sliced sync output signal

available only in CP mode.

O

64

65

61, 62

6±, 69

67

REFOUT

CML

CAPY1, CAPY2

CAPC1, CAPC2

BIAS

O

I

O

Internal Voltage Reference Output.

Common-Mode Level Pin (CML) for the internal ADCs.

ADC Capacitor Network.

External Bias Setting Pin. Connect the recommended resistor (1.35 kΩ) between pin

and ground.

±6

HS_IN/CS_IN

I

Can be configured in CP mode to be either a digital HS input signal or a digital CS

input signal used to extract timing in a 5-wire or 4-wire RGB mode.

±5

79

VS_IN

DE_IN

I

VS Input Signal. Used in CP mode for 5-wire timing mode.

Data Enable Input Signal. Used in 24-bit digital input port mode (for example,

processing 24-bit RGB data from a DVI Rx IC).

35

DCLK_IN

I

Clock Input Signal. Used in 24-bit digital input mode (for example, processing 24-bit

RGB data from a DVI Rx IC) and also in digital CVBS input mode.

52

77

SOG

SOY

I

Sync on Green Input. Used in embedded sync mode.

Sync on Luma Input. Used in embedded sync mode.

Rev. SpA | Page 11 of 24

ADV7403

TIMING DIAGRAMS

t₃

t₅

t₃

SDA1/SDA2

t₆

t₁

SCLK1/SCLK2

t₂

t₇

t₄

t₈

Figure 3. I²C Timing

t₉

t₁₀

LLC1

t₁₁

t₁₂

P0–P29, VS, HS,

FIELD/DE,

SFL/SYNC_OUT

Figure 4. Pixel Port and Control SDR Output Timing (SD Core)

t₉

t₁₀

LLC1

t₁₃

t₁₄

P0–P29, VS,

HS, FIELD/DE

Figure 5. Pixel Port and Control SDR Output Timing (CP Core)

LLC1

t₁₆

t₁₈

t₁₅

t₁₇

P6–P9,

P10–P19

Figure 6. Pixel Port and Control DDR Output Timing (CP Core)

DCLK_IN

t₂₀

t₉

t₁₀

HS_IN

VS_IN

DE_IN

CONTROL

INPUTS

P0–P1, P10–P11,

P20–P21, P22–P29,

P31–P32, P33–P40

t₁₉

Figure 7. Digital Input Port and Control Input Timing

Rev. SpA | Page 12 of 24

ADV7403

DETAILED FUNCTIONALITY

ANALOG FRONT END

•

Adaptive digital line length tracking (ADLLT™)

•

Four 140 MHz (ADV7403KSTZ-140), Noise Shaped Video,

12-bit ADCs enable true 10-bit video decoder

Proprietary architecture for locking to weak, noisy, and

unstable sources from VCRs and tuners

12 analog input channel mux enables multisource

connection without the requirement of an external mux

•

IF filter block compensates for high frequency luma

attenuation due to tuner SAW filter

Four current and voltage clamp control loops ensure any

dc offsets are removed from the video signal

•

Chroma transient improvement (CTI)

Luminance digital noise reduction (DNR)

SCART functionality and SD RGB overlay on CVBS

controlled by fast blank input

Color controls include hue, brightness, saturation, contrast,

and Cr and Cb offset controls

Four antialias filters to remove out of band noise on

standard definition input video signals.

•

Certified Macrovision copy protection detection on

composite and S-video for all worldwide formats

(PAL/NTSC/SECAM)

SDP PIXEL DATA OUTPUT MODES

•

8-/10-bit ITU-R BT.656 4:2:2 YCrCb with embedded time

codes and/or HS, VS, and FIELD

4× oversampling (54 MHz) for CVBS, S-video, and YUV

modes

16-/20-bit YCrCb with embedded time codes and/or HS,

VS, and FIELD

•

Line-locked clock output (LLC)

Letterbox detection supported

24-/30-bit YCrCb with embedded time codes and/or HS,

VS, and FIELD

Free-run output mode provides stable timing when no

video input is present

CP PIXEL DATA OUTPUT MODES

•

Single data rate (SDR) 8-/10-bit 4:2:2 YCrCb for 525i, 625i

•

Vertical blanking interval data processor

•

Single data rate (SDR) 16-/20-bit 4:2:2 YCrCb for all

standards

•

TeleText

Video Programming System (VPS)

Vertical Interval Time Codes (VITC)

•

Single data rate (SDR) 24-/30-bit 4:4:4 YCrCb/RGB for all

standards

Closed captioning (CC) and extended data service

(EDS)

Double data rate (DDR) 8-/10-bit 4:2:2 YCrCb for all

standards

•

Wide screen signaling (WSS)

Double data rate (DDR) 12-bit 4:4:4 YCrCb/RGB for all

standards

Copy generation management system (CGMS)

Gemstar™ 1×/2× electronic program guide compatible

COMPOSITE AND S-VIDEO PROCESSING

•

Support for NTSC (J, M, 4.43), PAL (B, D, I, G, H, M, N,

60) and SECAM B/D/G/K/L standards in the form of

CVBS and S-video

•

Clocked from a single 28.63636 MHz crystal

Subcarrier frequency lock (SFL) output for downstream

video encoder

•

Superadaptive 2D 5-line comb filters for NTSC and PAL

give superior chrominance and luminance separation for

composite video

•

Differential gain typically 0.4%

Differential phase typically 0.4°

•

Full automatic detection and autoswitching of all

worldwide standards (PAL/NTSC/SECAM)

Automatic gain control with white peak mode ensures

the video is always processed without loss of the video

processing range

Rev. SpA | Page 13 of 24

ADV7403

COMPONENT VIDEO PROCESSING

DIGITAL VIDEO INPUT PORT

•

Formats supported include 525i, 625i, 525p, 625p, 720p,

1080i, and many other HDTV formats

•

Supports raw 8-/10-bit CVBS data from digital tuner

•

Support for 24-bit RGB input data from DVI Rx chip,

output converted to YCrCb 4:2:2

Automatic adjustments include gain (contrast) and offset

(brightness); manual adjustment controls are also

supported

•

Support for 24-bit 4:4:4, 16-/20-bit 4:2:2 525i, 625i, 525p,

625p, 1080i, 720p, VGA to SXGA @ 60 Hz input data from

HDMI Rx chip, output converted to 16-bit 4:2:2 YCrCb

•

Support for analog component YPrPb/RGB video formats

with embedded sync or with separate HS, VS, or CS

GENERAL FEATURES

Any-to-any, 3 × 3 color space conversion matrix supports

YCrCb-to-RGB and RGB-to-YCrCb

•

HS, VS, and FIELD output signals with programmable

position, polarity, and width

Standard identification (STDI) enables system level

component format detection

•

Programmable interrupt request output pin,

SDP/CP status changes

, signals

INT

Synchronization source polarity detector (SSPD) deter-

mines the source and polarity of the synchronization

signals that accompany the input video

•

Supports two I²C host port interfaces (control and VBI)

Low power consumption: 1.8 V digital core, 3.3 V analog

and digital I/O, low power power-down mode, and green

PC mode

•

Certified Macrovision copy protection detection on

component formats (525i, 625i, 525p, and 625p)

•

Industrial temperature range (−40°C to +85°C)

(ADV7403BSTZ-110)

Free-run output mode provides stable timing when no

video input is present

•

140 MHz speed grade (ADV7403KST-140)

100-lead, 14 mm × 14 mm, Pb-free LQFP

Arbitrary pixel sampling support for nonstandard video

sources

RGB GRAPHICS PROCESSING

•

140 MSPS conversion rate supports RGB input resolutions

up to 1280 × 1024 @ 75 Hz (SXGA); (110 MSPS conversion

rate for ADV7403BSTZ-110)

•

Automatic or manual clamp and gain controls for graphics

modes

•

Contrast and brightness controls

32-phase DLL allows optimum pixel clock sampling

Automatic detection of sync source and polarity by SSPD

block

•

Standard identification is enabled by STDI block

RGB can be color space converted to YCrCb and

decimated to a 4:2:2 format for video centric backend

IC interfacing

•

Data enable (DE) output signal supplied for direct

connection to HDMI/DVI Tx IC

Arbitrary pixel sampling support for nonstandard video

sources

Rev. SpA | Page 14 of 24

ADV7403

DETAILED DESCRIPTION

The SDP has specific luminance and chrominance parameter

control for brightness, contrast, saturation, and hue.

ANALOG FRONT END

The ADV7403 analog front end comprises four Noise Shaped

Video, 12-bit ADCs that digitize the analog video signal before

applying it to the SDP or CP (See Table 8 for sampling rates).

The analog front end uses differential channels to each ADC to

ensure high performance in a mixed-signal application.

The ADV7403 implements a patented adaptive-digital-line-

length-tracking (ADLLT) algorithm to track varying video line

lengths from sources such as a VCR. ADLLT enables the

ADV7403 to track and decode poor quality video sources such as

VCRs, noisy sources from tuner outputs, VCD players, and

camcorders. The SDP also contains a chroma transient

The front end also includes a 12-channel input mux that enables

multiple video signals to be applied to the ADV7403. Current

and voltage clamps are positioned in front of each ADC to

ensure that the video signal remains within the range of the

converter. Fine clamping of the video signals is performed

downstream by digital fine clamping either in the CP or SDP.

improvement (CTI) processor. This processor increases the edge

rate on chroma transitions, resulting in a sharper video image.

The SDP can process a variety of VBI data services, such as

TeleText, closed captioning (CC), wide screen signaling (WSS),

video programming system (VPS), vertical interval time codes

(VITC), copy generation management system (CGMS), Gemstar

1×/2×, and extended data service (XDS). The ADV7403 SDP

section has a Macrovision 7.1 detection circuit that allows it to

detect Types I, II, and III protection levels. The decoder is also

fully robust to all Macrovision signal inputs.

Optional antialiasing filters are positioned in front of each

ADC. These filters can be used to band-limit standard

definition video signals, removing spurious, out-of-band noise.

The ADCs are configured to run in 4× oversampling mode

when decoding composite and S-video inputs; 2× oversampling

is performed for component 525i, 625i, 525p, and 625p sources.

All other video standards are 1× oversampled. Oversampling

the video signals reduces the cost and complexity of external

anti-aliasing filters with the benefit of an increased signal-to-

noise ratio (SNR).

COMPONENT PROCESSOR

The CP section is capable of decoding/digitizing a wide range of

component video formats in any color space. Component video

standards supported by the CP are 525i, 625i, 525p, 625p, 720p,

1080i, 1250i, VGA up to SXGA @ 75 Hz, (ADV7403KSTZ-140

only) and many other standards not listed here.

The ADV7403 can support simultaneous processing of CVBS

and RGB standard definition signals to enable SCART compat-

ibility and overlay functionality. A combination of CVBS and

RGB inputs can be mixed and output under control of I²C

registers and the fast blank pin.

The CP section of the ADV7403 contains an AGC block.

When no embedded sync is present, the video gain can be set

manually. The AGC section is followed by a digital clamp

circuit that ensures the video signal is clamped to the correct

blanking level. Automatic adjustments within the CP include

gain (contrast) and offset (brightness); manual adjustment

controls are also supported.

Table 8: Maximum ADC Sampling Rates

Model

Maximum ADC Sampling Rate

ADV74ꢀ3BSTZ-11ꢀ

ADV74ꢀ3KSTZ-14ꢀ

11ꢀ MHz

14ꢀMHz

A fully programmable any-to-any, 3 × 3 color space conversion

matrix is placed between the analog front end and the CP

section. This enables YPrPb-to-RGB and RGB-to-YCrCb

conversions. Many other standards of color space can be

implemented using the color space converter.

STANDARD DEFINITION PROCESSOR

The SDP section is capable of decoding a large selection of

baseband video signals in composite S-video and YUV

formats. The video standards supported by the SDP include

PAL B/D/I/G/H, PAL60, PAL M, PAL N, NTSC M/J, NTSC

4.43, and SECAM B/D/G/K/L. The ADV7403 can automatically

detect the video standard and process it accordingly.

The output section of the CP is highly flexible. It can be config-

ured in single data rate mode (SDR) with one data packet per

clock cycle or in a double data rate (DDR) mode where data is

presented on the rising and falling edges of the clock. In SDR

mode, a 16-/20-bit 4:2:2 or 24-/30-bit 4:4:4 output is possible. In

these modes, HS, VS, and FIELD/DE (where applicable) timing

reference signals are provided. In DDR mode, the ADV7403 can

be configured in an 8-/10-bit 4:2:2 YcrCb or 12-bit 4:4:4 RGB/

YcrCb pixel output interface with corresponding timing signals.

The SDP has a 5-line super adaptive 2-D comb filter that gives

superior chrominance and luminance separation when decod-

ing a composite video signal. This highly adaptive filter auto-

matically adjusts its processing mode according to video

standard and signal quality with no user intervention required.

The SDP has an IF filter block that compensates for attenuation

in the high frequency luma spectrum due to tuner SAW filter.

Rev. SpA | Page 15 of 24

ADV7403

VBI extraction of CGMS data is performed by the CP section

of the ADV7403 for interlaced, progressive, and high definition

scanning rates. The data extracted can be read back over the

I²C interface. For more detailed product information about the

ADV7403, contact your local ADI sales office or email

video.products@analog.com.

The ADV7403 is capable of supporting an external DVI/

HDMI receiver. The digital interface expects 24-bit 4:4:4 or

16-/20-bit 4:2:2 bit data (either graphics RGB or component

video YcrCb), accompanied by HS, VS, DE, and a fully

synchronous clock signal. The data is processed in the CP and

output as 16-bit 4:2:2 YcrCb data.

The CP section contains circuitry to enable the detection of

Macrovision encoded YPrPb signals for 525i, 625i, 525p, and

625p. It is designed to be fully robust when decoding these

types of signals.

Rev. SpA | Page 16 of 24

ADV7403

PIXEL INPUT/OUTPUT FORMATTING

Table 9. SDP, CP Pixel Input/Output Pin Map (P19 to P0)

Processor, Format,

Pixel Port Pins P[19:0]

11 10

and Mode

19 18 17 16 15 14 13 12

9

8

7

6

5

4

3

2

1

0

SDP

Video out, ±-bit,

4:2:2

YcrCb[7:ꢀ]_OUT

-

SDP

Video out, 1ꢀ-bit,

4:2:2

YcrCb[9:ꢀ] _OUT

Y[7:ꢀ]_OUT

-

Video out,

16-bit, 4:2:2

CrCb[7:ꢀ]_OUT

CrCb[9:ꢀ]_OUT

Cb[7:ꢀ]_OUT

Video out,

2ꢀ-bit, 4:2:2

Y[9:ꢀ]_OUT

Video out,

24-bit, 4:4:4

Y[7:ꢀ]_OUT

-

Video out,

Y[9:ꢀ]_OUT

Cb[9:ꢀ]_OUT

3ꢀ-bit, 4:4:4

SM-SDP Digital tuner

input[1]

Output choices are the same as video out 16-/2ꢀ-bit or pseudo ±-/1ꢀ-bit DDR

CP

±-bit, 4:2:2, DDR D7 D6 D5 D4 D3 D2 D1 Dꢀ

-

1ꢀ-bit, 4:2:2, DDR D9 D± D7 D6 D5 D4 D3 D2 D1 Dꢀ

-

12-bit, 4:4:4, RGB D7 D6 D5 D4 D3 D2 D1 Dꢀ

DDR

-

D11 D1ꢀ D9 D±

CP

Video out,

16-bit, 4:2:2

CHA[7:ꢀ]_OUT(for example, Y[7:ꢀ])

CHA[9:ꢀ]_OUT(for example, Y[9:ꢀ])

CHA[7:ꢀ]_OUT(for example, G[7:ꢀ])

CHA[9:ꢀ]_OUT(for example, G[9:ꢀ])

CHA[7:ꢀ]_OUT(for example, Y[7:ꢀ])

CHB/C[7:ꢀ]_OUT(for example, Cr/Cb[7:ꢀ])

CHB/C[9:ꢀ]_OUT(for example, Cr/Cb[9:ꢀ])

CHB[7:ꢀ]_OUT(for example, B[7:ꢀ])

-

CP

Video out,

2ꢀ-bit, 4:2:2

CP

Video out,

24-bit, 4:4:4

-

CP

Video out,

3ꢀ-bit, 4:4:4

CHB[9:ꢀ]_OUT(for example, B[9:ꢀ])

SM-CP

HDMI receiver

support, 24-bit,

4:4:4 input

R[5:4]_IN

CHB/C[7:ꢀ]_OUT(for example, Cr/Cb[7:ꢀ])

R[1:ꢀ]_IN

SM-CP

HDMI receiver

support 16-bit

pass-through

CHA[7:ꢀ]_OUT(for example, Y[7:ꢀ])

CHA[9:ꢀ]_OUT(for example, Y[9:ꢀ])

-

CHB/C[7:ꢀ]_OUT(for example, Cr/Cb[7:ꢀ])

CHB/C[9:ꢀ]_OUT(for example, Cr/Cb[9:ꢀ])

-

HDMI receiver

support, 2ꢀ-bit,

pass-through

Rev. SpA | Page 17 of 24

ADV7403

Table 10. SDP, CP Pixel Input/Output Pin Map (P40 to P20)

Processor, Format,

Pixel Port Pins P[40:31], P[29:20]

and Mode

40 39 38 37 36 35 34 33 32 31 29 28 27 26 25 24 23 22 21 20

SDP

Video out, ±-bit,

4:2:2

-

SDP

Video out, 1ꢀ-bit,

4:2:2

Video out, 16-bit,

4:2:2

Video out, 2ꢀ-bit,

4:2:2

Video out, 24-bit,

4:4:4

Cr[7:ꢀ]_OUT

Cr[9:ꢀ]_OUT

Video out, 3ꢀ-bit,

4:4:4

SM-SDP Digital tuner

input[1]

DCVBS[9:ꢀ]_IN

-

CP

±-bit, 4:2:2, DDR

-

CP

1ꢀ-bit, 4:2:2, DDR

-

CP

12-bit, 4:4:4, RGB

DDR

-

CP

Video out, 16-bit,

4:2:2

CP

Video out, 2ꢀ-bit,

4:2:2

CP

Video out, 24-bit,

4:4:4 input

CHC[7:ꢀ]_OUT(for example, R[7:ꢀ])

CHC[9:ꢀ]_OUT(for example, R[9:ꢀ])

B[7:ꢀ]_IN

CP

Video out, 3ꢀ-bit,

4:4:4 input

SM-CP

HDMI receiver

support, 24-bit,

4:4:4 input

G[7:ꢀ]_IN

R[7:6]_IN

R[3:2]_IN

SM-CP

HDMI receiver

support, 16-bit,

pass-through

CHA[7:ꢀ]_IN(for example, Y[7:ꢀ])

CHA[9:ꢀ]_IN(for example, Y[9:ꢀ])

-

CHB/C[7:ꢀ]_IN(for example, Cr/Cb[7:ꢀ])

CHB/C[9:ꢀ]_IN(for example, Cr/Cb[9:ꢀ])

-

HDMI receiver

support, 2ꢀ-bit,

pass-through

Rev. SpA | Page 1± of 24

ADV7403

RECOMMENDED EXTERNAL LOOP

FILTER COMPONENTS

The external loop filter components for the ELPF pin should

be placed as close as possible to the respective pins. Figure 8

shows the recommended component values.

PIN 46–ELPF

1.69kΩ

10nF

82nF

PVDD = 1.8V

Figure 8. ELPF Components

Rev. SpA | Page 19 of 24

ADV7403

TYPICAL CONNECTION DIAGRAM

D D D I O V

V S D S

1 8

6

8 9

4 0

1 1

D D D V

9 0

3 9

1 2

O

V S D S I

1 7

5

P V S S

5 0

D D A V

6 3

P V S S

4 9

D

P V D

4 8

4 7

V S A S

T E S T 0

6 0

6 6

7 0

Ω 7 k 2 .

Ω 5 6

Ω 7 5

Figure 9. ADV7403 Typical Connection Diagram

Rev. SpA | Page 2ꢀ of 24

ADV7403

OUTLINE DIMENSIONS

16.20

16.00 SQ

15.80

1.60 MAX

0.75

0.60

0.45

100

1

76

75

PIN 1

14.20

14.00 SQ

13.80

TOP VIEW

(PINS DOWN)

1.45

1.40

1.35

0.20

0.09

7°

3.5°

0°

25

51

50

0.15

0.05

26

SEATING

PLANE

0.08

0.27

0.22

0.17

COPLANARITY

VIEW A

0.50

BSC

LEAD PITCH

VIEW A

ROTATED 90° CCW

COMPLIANT TO JEDEC STANDARDS MS-026-BED

Figure 10. 100-Lead Low Profile Quad Flat Package [LQFP]

(ST-100)

Dimensions shown in millimeters

ORDERING GUIDE

Model¹

ADV7403BSTZ-110²

ADV7403KSTZ-140²

EVAL-ADV7403EBM

Temperature Range

−40°C to +85°C

0°C to 70°C

Package Description

Package Option

100-Lead Low Profile Quad Flat Package (LQFP)

Evaluation board

ST-100

¹The ADV7403 is a Pb-free, environmentally friendly product. It is manufactured using the most up-to-date materials and processes. The coating on the leads of each

device is 100% pure Sn electroplate. The device is suitable for Pb-free applications, and is able to withstand surface-mount soldering at up to 255°C ( 5°C). In addition,

it is backward-compatible with conventional SnPb soldering processes. This means that the electroplated Sn coating can be soldered with SnPb solder pastes at

conventional reflow temperatures of 220°C to 235°C.

²Z = Pb-free part.

Rev. SpA | Page 21 of 24

ADV7403

NOTES

Rev. SpA | Page 22 of 24

ADV7403

NOTES

Rev. SpA | Page 23 of 24

ADV7403

NOTES

Purchase of licensed I²C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I²C Patent

Rights to use these components in an I²C system, provided that the system conforms to the I²C Standard Specification as defined by Philips.

©

registered trademarks are the property of their respective owners.

D05431–0–9/05(SpA)

Rev. SpA | Page 24 of 24


型号：	ADV7403KSTZ-1402
厂家：	ADI
描述：	12-Bit, Integrated, Multiformat SDTV/HDTV Video Decoder and RGB Graphics Digitizer 12位，集成，多格式SDTV / HDTV视频解码器和RGB图形数字化仪解码器电视
文件：	总24页 (文件大小：461K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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