L9218A_技术文档

Data Sheet

November 2001

L9218A/G Low-Cost Line Interface

Features

Description

■ Basic forward battery only SLIC functionality at a

This general-purpose electronic subscriber loop

low cost

interface circuit (SLIC) is optimized for low cost, while

still providing a satisfactory set of features.

■ Pin compatible with Agere Systems Inc. L9219 and

L9217 SLIC

The L9218 is pin-for-pin compatible with the Agere

L9219 and L9217 SLICs.

■ Low active power (typical 138 mW during on-hook

transmission)

The L9218 requires a 5 V power supply and single

battery to operate. This is a forward battery only

device. Additionally, a low-power scan mode,

wherein all circuitry except the off-hook supervision is

shut down to conserve power, is available.

■ Low-power scan mode for low-power, on-hook

power dissipation (59 mW typical)

■ Minimal external components

■ Distortion-free, on-hook transmission

Via the logic inputs, a low or high current limit may be

selected. The low value is set via a single external

resistor, and the high value is 1.4 times the low value.

■ Convenient operating states:

— Forward battery low current limit

— Forward battery high current limit

— Low-power scan

Device overhead is fixed and is adequate for

3.14 dBm into 900 Ω of on-hook transmission.

— Disconnect (high impedance)

Both the loop supervision and ring trip supervision

functions are offered with user-controlled thresholds

via external resistors.

■ Adjustable supervision functions:

— Off-hook detector with hysteresis

— Ring trip detector

The L9218 is offered with a receive gain that is opti-

mized for interface to a first-generation type codec

(L9218A). It is also offered with a gain option that is

optimized for interface to a third- or fourth-generation

type codec (L9218G). In both cases, minimizing

external components required at this interface. In the

receive direction, the device may be dc-coupled to a

third-generation codec. No dc blocking capacitors

are needed.

■ Logic controlled high and low current limit

■ Two gain options to optimize the codec interface

■ Thermal protection with thermal shutdown indica-

tion

Data control is via a parallel data control scheme.

The device is available in a 28-pin PLCC package. It

is built by using a 90 V complementary bipolar

(CBIC) process.

Data Sheet

L9218A/G Low-Cost Line Interface

Contents

November 2001

Table of Contents

Page Figures

Page

Features ......................................................................1

Description...................................................................1

Pin Information ............................................................4

Functional Description.................................................6

Figure 15. Ring Trip Equivalent Circuit and

Equivalent Application ........................... 21

Figure 16. ac Equivalent Circuit.............................. 23

Figure 17. Interface Circuit Using First-

A

Absolute Maximum Ratings (at T = 25 °C) ................7

Generation Codec (±5 V Battery) .......... 26

Figure 18. Interface Circuit Using First-

Recommended Operating Conditions .........................7

Electrical Characteristics .............................................8

Ring Trip Requirements..........................................12

Test Configurations ...................................................13

Applications ...............................................................15

dc Applications....................................................... 19

Battery Feed.........................................................19

Current Limit.........................................................19

Overhead Voltage ............................................... 19

Loop Range..........................................................20

Off-Hook Detection...............................................20

Ring Trip Detection...............................................21

Longitudinal Balance.............................................. 21

ac Design............................................................... 22

Codec Types........................................................22

ac Interface Network ............................................22

Receive Interface .................................................22

Example 1: Real Termination (First-

Generation Codec (5 V Only Codec)..... 26

Tables

Page

Table 1.

Table 2.

Table 3.

Table 4.

Table 5.

Table 6.

Table 7.

Table 9.

Pin Descriptions ...................................... 4

Input State Coding .................................. 6

Supervision Coding ................................. 6

Power Supply .......................................... 8

2-Wire Port .............................................. 9

Analog Pin Characteristics .................... 10

ac Feed Characteristics ...................... 11

Parts List for Loop Start Application

Circuit Using T7504-Type Codec .......... 16

Table 10. 200 Ω + 680 Ω || 0.1 µF First-

Generation Codec Design Parameters . 17

Table 11. Parts List for Loop Start Application

Circuit Using T8536-Type Codec .......... 18

Generation Codec).............................................. 23

Example 2: Complex Termination (First-

Generation Codec)...............................................25

Power Derating ...................................................... 27

Pin-for-Pin Compatibility with L9217/L9219........... 27

PCB Layout Information ............................................27

Outline Diagram.........................................................28

28-Pin PLCC.......................................................... 28

Ordering Information..................................................29

Figures

Page

Figure 1. Functional Diagram...................................3

Figure 2. 28-Pin PLCC.............................................4

Figure 3. Ring Trip Circuits ....................................12

Figure 4. L9218 Basic Test Circuit.........................13

Figure 5. Metallic PSRR.........................................13

Figure 6. Longitudinal PSRR .................................13

Figure 7. Longitudinal Balance ..............................14

Figure 8. RFI Rejection..........................................14

Figure 9. Longitudinal Impedance..........................14

Figure 10. ac Gains..................................................14

Figure 11. Basic Loop Start Application

Circuit Using T7504-Type Codec............15

Figure 12. Basic Loop Start Application

Circuit Using T8536-Type Codec............17

Figure 13. Loop Current vs. Loop Voltage...............19

Figure 14. Off-Hook Detection Circuit......................20

2

Agere Systems Inc.

Data Sheet

November 2001

L9218A/G Low-Cost Line Interface

Description (continued)

POWER CONDITIONING AND REFERENCE

FORWARD AND REVERSE BATTERY

DCOUT

VTX

RECTIFIER

3

+

AX

–

β = 41 V/A

TG

TXI

AAC

VITR

–

PT

PR

A = 1

β = 9.66

+

TIP/RING

–

+

RCVN

RCVP

CURRENT

SENSE

A VERSION GAIN = 3.93

G VERSION GAIN = 1

+

A = –1

–

B0

BATTERY FEED

STATE CONTROL

B1

B2/NC

LOOP CLOSURE DETECTOR

+

–

LCTH

THERMAL

SHUTDOWN

TSD

+

–

RTSP

RTSN

NSTAT

RING TRIP DETECTOR

12-3557 (F).d

Figure 1. Functional Diagram

Agere Systems Inc.

3

Data Sheet

November 2001

L9218A/G Low-Cost Line Interface

Pin Information

4

3

2

1

28

27

26

5

6

25

24

23

22

21

20

19

VTX

RCVP

RCVN

LCTH

DCOUT

V^BAT

TXI

7

VITR

NSTAT

NC

8

28-PIN PLCC

9

PR

10

11

RTSP

RTSN

CF2

12

13

14

15

16

17

18

12-3552 (F)

Figure 2. 28-Pin PLCC

Table 1. Pin Descriptions

PLCC

Symbol Type

Description

PROG

I

1

I

Current-Limit Program Input. A resistor to DCOUT sets the dc current limit of

the device.

2

3

4

5

NC

—

I

No Connect.

CC

V

5 V Power Supply.

RCVP

Receive ac Signal Input (Noninverting). This high-impedance input controls

the ac differential voltage on tip and ring.

6

RCVN

I

Receive ac Signal Input (Inverting). This high-impedance input controls the

ac differential voltage on tip and ring.

4

Agere Systems Inc.

Data Sheet

November 2001

L9218A/G Low-Cost Line Interface

Pin Information (continued)

Table 1. Pin Descriptions (continued)

PLCC

Symbol Type

Description

7

LCTH

I

Loop Closure Threshold Input. Connect a resistor to VTX to set off-hook

threshold.

8

DCOUT

O

dc Output Voltage. This output is a voltage that is directly proportional to the

absolute value of the differential tip/ring current.

BAT

9

V

—

Battery Supply. Negative high-voltage power supply.

10

PR

I/O Protected Ring. The output of the ring driver amplifier and input to loop sens-

ing circuitry. Connect to the loop through overvoltage protection.

11

12

13

CF2

CF1

—

Filter Capacitor 2. Connect a 0.1 µF capacitor from this pin to AGND.

Filter Capacitor 1. Connect a 0.47 µF capacitor from this pin to pin CF2.

B2/NC

Dummy Pin. Used for exact pin-for-pin compatibility with L9219. There is no

physical connection to this pin, however, it may be connected to the B2 control

latch to get an exact PWB footprint match with L9219.

14

15

B1

B0

I

State Control Input. B0 and B1 determine the state of the SLIC. See Table 2.

Pin B1 has an internal pull-down.

State Control Input. B0 and B1 determine the state of the SLIC. See Table 2.

Pin B0 has an internal pull-down.

16

17

18

AGND

BGND

PT

—

Analog Signal Ground.

Battery Ground. Ground return for the battery supply.

I/O Protected Tip. The output of the tip driver amplifier and input to loop-sensing

circuitry. Connect to loop through overvoltage protection.

19

20

RTSN

RTSP

I

Ring Trip Sense Negative. Connect this pin to the ringing generator signal

through a high-value resistor.

Ring Trip Sense Positive. Connect this pin to the ring relay and the ringer

series resistor through a high-value resistor.

21

22

NC

—

O

No Connect.

NSTAT

Loop Detector Output/Ring Trip Detector Output. When low, this logic out-

put indicates that an off-hook condition exists or that ringing is tripped.

23

VITR

O

Transmit ac Output Voltage. This output is a voltage that is directly propor-

tional to the differential tip/ring current.

ac/dc Separation. Connect a 0.1 µF capacitor from this point to VTX.

24

25

TXI

—

O

VTX

Transmit ac/dc Output Voltage. This output is a voltage that is directly pro-

portional to the differential tip/ring current.

26

27

TG

—

O

Transmit Gain. Connect an 8.06 kΩ from TG to VTX to set the transmit gain of

the SLIC.

TSD

Thermal Shutdown. When high, this logic output indicates the device is in

thermal shutdown.

28

NC

—

No Connect.

Agere Systems Inc.

5

Data Sheet

November 2001

L9218A/G Low-Cost Line Interface

Functional Description

Table 2. Input State Coding

B0 B1

State/Definition

1

0

1

0

1

Powerup, Forward Battery. Normal talk and battery feed state. Pin PT is positive with respect to PR.

On-hook transmission is enabled. Low current limit is selected.

Powerup, Forward Battery. Normal talk and battery feed state. Pin PT is positive with respect to PR.

On-hook transmission is enabled. High current limit is selected.

Disconnect. The tip and ring amplifiers are turned off, and the SLIC goes to a high-impedance state

(>100 kΩ). Supervision outputs read on hook. Device will power up in this state.

Low-Power Scan. Except for off-hook detection, all circuits are shut down to conserve power. Pin PT

is positive with respect to pin PR. On-hook transmission is disabled.

Table 3. Supervision Coding

NSTAT

TSD

0 = Normal device operation.

1 = Device is in thermal shutdown.

0 = off-hook or ring trip.

1 = on-hook and no ring trip.

6

Agere Systems Inc.

Data Sheet

November 2001

L9218A/G Low-Cost Line Interface

A

Absolute Maximum Ratings (at T = 25 °C)

Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are abso-

lute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess

of those given in the operational sections of the data sheet. Exposure to absolute maximum ratings for extended

periods can adversely affect device reliability.

Parameter

Symbol

Min

—

Typ

—

Max

7.0

–75

7.0

—

Unit

V

CC

V

5 V Power Supply

Battery (talking) Supply

VBAT

—

V

Logic Input Voltage

–0.5

–7.0

150

—

V

Analog Input Voltage

—

V

J

Maximum Junction Temperature

Storage Temperature Range

Relative Humidity Range

T

—

°C

%

V

stg

T

–40

—

125

95

H

R

5

—

Ground Potential Difference (BGND to AGND)

PT or PR Fault Voltage (dc)

PT or PR Fault Voltage (10 x 1000 µs)

Current into Ring Trip Inputs

—

±3

—

VPT, VPR

IRTSP, IRTSN

VBAT – 5

VBAT – 15

—

3

V

—

15

V

±240

—

µA

Note: The IC can be damaged unless all ground connections are applied before, and removed after, all other connections. Furthermore, when

powering the device, the user must guarantee that no external potential creates a voltage on any pin of the device that exceeds the

device ratings. Some of the known examples of conditions that cause such potentials during powerup are the following:

1. An inductor connected to tip and ring can force an overvoltage on VBAT through the protection devices if the VBAT connection chatters.

2. Inductance in the VBAT lead could resonate with the VBAT filter capacitor to cause a destructive overvoltage.

Recommended Operating Conditions

Parameter

Min

–40

4.75

–24

Typ

—

Max

85

Unit

°C

V

Ambient Temperature

CC

V

Supply Voltage

5.0

–48

5.25

–70

BAT

Supply Voltage

V

Agere Systems Inc.

7

Data Sheet

November 2001

L9218A/G Low-Cost Line Interface

Electrical Characteristics

Minimum and maximum values are testing requirements in the temperature range of 25 °C to 85 °C and battery

range of –24 V to –70 V. These minimum and maximum values are guaranteed to –40 °C based on component

simulations and design verification of samples, but devices are not tested to –40 °C in production. The test circuit

shown in Figure 4 is used, unless otherwise noted. Positive currents flow into the device.

Typical values are characteristics of the device design at 25 °C based on engineering evaluations and are not part

CC

BAT

of the test requirements. Supply values used for typical characterization are V = 5.0 V, V

= –48 V, unless oth-

erwise noted.

Table 4. Power Supply

Parameter

Min

Typ

Max

Unit

Power Supply—Powerup, No Loop Current:

CC

I

—

4.6

–2.4

138

5.6

–2.7

158

mA

mW

BAT

I

BAT

(V

= –48 V)

BAT

Power Dissipation (V

= –48 V)

Power Supply—Scan, No Loop Current:

CC

I

—

2.8

–0.8

52

3.8

–1.0

67

mA

mW

BAT

I

BAT

(V

= –48 V)

BAT

Power Dissipation (V

= –48 V)

Power Supply—Disconnect, No Loop Current:

CC

I

—

1.6

–0.12

14

—

mA

mW

BAT

I

BAT

(V

= –48 V)

BAT

Power Dissipation (V

= –48 V)

Power Supply Rejection 500 Hz to 3 kHz

(See Figure 5 and Figure 6)¹:

30

40

—

dB

CC

V

BAT

V

Thermal Protection Shutdown (Tjc)³

150

165

—

°C

2, 3

JA

Thermal Resistance, Junction to Ambient (θ )

Natural Convection 2S2P Board

:

—

30

43

27

36

—

°C/W

Natural Convection 2S0P Board

Wind Tunnel 100 Linear Feet per Minute (LFPM) 2S2P Board

Wind Tunnel 100 Linear Feet per Minute (LFPM) 2S0P Board

1. This parameter is not tested in production. It is guaranteed by design and device characterization.

2. Careful thermal design as a function of maximum battery, loop length, maximum ambient temperature package thermal resistance, airflow,

PCB board layers, and other related parameters must ensure that thermal shutdown temperature is not exceeded under normal use condi-

tions.

3. Airflow, PCB board layers, and other factors can greatly affect this parameter.

8

Agere Systems Inc.

Data Sheet

November 2001

L9218A/G Low-Cost Line Interface

Electrical Characteristics (continued)

Table 5. 2-Wire Port

Parameter

Min

Typ

Max

Unit

—

Tip or Ring Drive Current = dc + Longitudinal + Signal

Currents

80

mA

—

Signal Current

15

mArms

Longitudinal Current Capability per Wire¹

15

8.5

dc Loop Current Limit²:

Allowed Range Including Tolerance³

15

—

±5

45

—

mA

%

LOOP

Accuracy (R

BAT

= –48 V)

= 100 Ω, V

Powerup Open Loop Voltage Levels:

Common-mode Voltage

BAT

—

V

/2

—

V

Differential Voltage VBAT = –48 V⁴(Gain = 2)

Differential Voltage VBAT = –48 V⁴(Gain = 7.86)

BAT

|V

+ 7.5| |V

+ 8.0| |V

+ 6.5| |V

+ 5.9|

BAT

Disconnect State:

Leakage

—

10

150

µA

LOOP

dc Feed Resistance (for I

below regulation level) (does

—

80

—

100

—

Ω

not include protection resistor)

Loop Resistance Range (–3.17 dBm overload into

900 Ω; not including protection):

LOOP

I

BAT

= 20 mA at V

= –48 V

1800

Ω

Longitudinal to Metallic Balance—IEEE^®Std. 455

(See Figure 7)⁵:

200 Hz to 3400 Hz

61

—

58

40

dB

Metallic to Longitudinal Balance (open loop):

200 Hz to 4 kHz

RFI Rejection (See Figure 8)³, 0.5 Vrms, 50 Ω Source,

30% AM Mod 1 kHz:

—

–55

—

–45

—

dBV

500 kHz to 100 MHz

1. The longitudinal current is independent of dc loop current.

2. Current-limit ILIM is programmed by a resistor, RPROG, from pin IPROG to DCOUT. ILIM is specified at the loop resistance where current limiting

begins (see Figure 13).

3. This parameter is not tested in production. It is guaranteed by design and device characterization.

4. Specification is reduced to |VBAT1 + 10.5 V| minimum when VBAT1 = –70 V at 85 °C.

5. Longitudinal balance of circuit card will depend on loop series protection resistor matching and magnitude. More information is available in

the Applications section of this document.

Agere Systems Inc.

9

Data Sheet

November 2001

L9218A/G Low-Cost Line Interface

Electrical Characteristics (continued)

Table 6. Analog Pin Characteristics

Parameter

Min

Typ

Max

Unit

Differential PT/PR Current Sense (DCOUT):

Gain (PT/PR to DCOUT)

121

–100

125

—

129

100

V/A

mV

LOOP

Offset Voltage at I

= 0

1

LCTH

Loop Closure Detector Threshold (R

= 22.1 kΩ) :

8.8

6.0

—

13.6

10.2

mA

On- to Off-hook Threshold (scan mode)

Off- to On-hook Threshold (active mode)

Ring Trip Comparator:

Input Offset Voltage²

Internal Voltage Source

Current at Input RTSP³

—

–9.1

I – 0.5

±10

–8.6

—

–8.1

I + 0.6

mV

V

µA

N

I

N

RCVN, RCVP:

Input Bias Current

Input Resistance

—

–0.2

1

–1

—

µA

MΩ

1. Loop closure threshold is programmed by resistor RLCTH from pin LCTH to pin DCOUT. The programming equation or relationship between

off-hook threshold and resistor value is different for active mode versus scan mode (see Applications section for more details).

2. This parameter is not tested in production. It is guaranteed by design and device characterization.

3. IN is the sourcing current at RTSN. Guaranteed if IN is within 5 µA to 30 µA.

10

Agere Systems Inc.

Data Sheet

November 2001

L9218A/G Low-Cost Line Interface

Electrical Characteristics (continued)

Table 7. ac Feed Characteristics

Parameter

ac Termination Impedance¹

Longitudinal Impedance at PT/PR²

Min

150

—

Typ

—

0

Max

1300

—

Unit

Ω

Total Harmonic Distortion—200 Hz to 4 kHz²:

—

0.3

1.0

%

Off-hook

On-hook

Transmit Gain, f = 1 kHz (PT/PR to VITR) (current limit)

–391

–403

–415

V/A

L9218A, Open Loop:

Receive + Gain, f = 1 kHz (RCVP to PT/PR)³

7.62

–7.62

7.86

–7.86

8.09

–8.09

—

Receive – Gain, f = 1 kHz (RCVN to PT/PR)³

L9218G, Open Loop:

Receive + Gain, f = 1 kHz (RCVP to PT/PR)⁴

Receive – Gain, f = 1 kHz (RCVN to PT/PR)⁴

1.94

–1.94

2.00

–2.00

2.06

–2.06

—

Gain vs. Frequency (transmit and receive)

(600 Ω termination; reference 1 kHz²):

200 Hz to 300 Hz

–1.00

–0.3

–3.0

—

0.0

–0.1

—

0.05

0.3

dB

300 Hz to 3.4 kHz

3.4 kHz to 16 kHz

16 kHz to 266 kHz

2.5

Gain vs. Level (transmit and receive)(reference 0 dBV²):

–55 dB to +3 dB

–0.05

0

0.05

dB

2-Wire Idle-channel Noise (600 Ω termination):

Psophometric²

C-message

3 kHz Flat²

—

–87

2

–77

12

dBmp

dBrnC

dBrn

10

20

Transmit Idle-channel Noise:

Psophometric²

—

–82

7

–77

12

dBmp

dBrnC

dBrn

C-message

3 kHz Flat²

15

20

1. With a first-generation codec, this parameter is set by external components. Any complex impedance R1 + R2 || C between 150 Ω and

1300 Ω can be synthesized. With a third-generation codec, this parameter is set by a codec or by a combination of a codec and an external

network.

2. This parameter is not tested in production. It is guaranteed by design and device characterization.

3. Use this gain option with a first-generation or third-generation codec.

4. Use this gain option with an Agere third-generation codec.

Agere Systems Inc.

11

Data Sheet

November 2001

L9218A/G Low-Cost Line Interface

Electrical Characteristics (continued)

Table 8. Logic Inputs and Outputs

All outputs are open collectors with internal, 30 kΩ pull-down resistor. Input pins have internal pull-down or some

way to power up in disconnect state.

Parameter

Symbol

Min

Typ

Max

Unit

Input Voltages:

IL

Low Level (permissible range)

High Level (permissible range)

V

–0.5

2.0

0.4

2.4

0.7

V

IH

CC

V

Input Currents:

Low Level (V = 5.25 V, V = 0.4 V)

CC

I

IL

I

0

+10

+4

+24

+10

+50

µA

CC

I

IH

High Level (V = 5.25 V, V = 2.4 V)

Output Voltages (open collector with internal pull-up resistor):

CC

OL

Low Level (V = 4.75 V, I = 200 µA)

V

0

2.4

0.2

—

0.4

V

CC

OH

CC

High Level (V = 4.75 V, I = –20 µA)

V

Ring Trip Requirements

8 µF

TIP

RING

■ Ringing signal:

— Voltage, minimum 35 Vrms, maximum 100 Vrms.

— Frequency, 17 Hz to 33 Hz.

— Crest factor, 1.2 to 1.6.

10 kΩ

■ Ring trip:

— ≤100 ms (typical).

2 µF

100 Ω

RING

■ Pretrip:

12-2572 (F).f

— The circuits in Figure 3 will not cause ring trip.

Figure 3. Ring Trip Circuits

12

Agere Systems Inc.

Data Sheet

November 2001

L9218A/G Low-Cost Line Interface

Test Configurations

V^BAT

0.1 µF

V^CC

0.1 µF

V^BAT

PT

BGND V^CCAGND

VITR

50 Ω

TIP

XMT

75 kΩ

R^LOOP

100 Ω/600 Ω

RCVN

RCVP

46 kΩ

L9218

SLIC

RCV

50 Ω

19.4 kΩ

RING

PR

DCOUT

I^PROG

8.06 kΩ

TG

43.2 kΩ

22.1 kΩ

2 MΩ

VTX

0.1 µF

TXI

LCTH

B0

B1

B2

RTSP

RTSN

NSTAT

TSD

402 Ω

274 kΩ

CF1

2 MΩ

0.47 µF

CF2

V^BAT

0.1 µF

2796 (F)

Figure 4. L9218 Basic Test Circuit

VBAT OR V^CC

VBAT OR VCC

100 Ω

4.7 µF

DISCONNECT

BYPASS CAPACITOR

DISCONNECT

BYPASS CAPACITOR

100 Ω

4.7 µF

VS

VBAT OR

VCC

VBAT OR

VCC

67.5 Ω

TIP

+

BASIC

TEST CIRCUIT

10 µF

BASIC

TEST CIRCUIT

900 Ω

VT/R

67.5 Ω

56.3 Ω

+

–

RING

VM

–

10 µF

VS

VT/R

VS

VM

PSRR = 20 log

12-2583 (F).b

12-2582 (F).b

Figure 6. Longitudinal PSRR

Figure 5. Metallic PSRR

Agere Systems Inc.

13

Data Sheet

November 2001

L9218A/G Low-Cost Line Interface

Test Configurations (continued)

ILONG

100 µF

TIP

+

VPT

–

TIP

VS

368 Ω

+

BASIC

TEST CIRCUIT

BASIC

TEST CIRCUIT

VM

–

ILONG

VPR

+

RING

100 µF

RING

VS

VM

∆ VPT

∆ ILONG

∆VPR

∆ ILONG

LONGITUDINAL BALANCE = 20 log

ZLONG =

OR

12-2584 (F).c

12-2585 (F).a

Figure 7. Longitudinal Balance

Figure 9. Longitudinal Impedance

0.01 µF

82.5 Ω

TIP

600 Ω

1

XMT

6, 7

2

50 Ω

VS

TIP

BASIC TEST

CIRCUIT

L7591

4

+

VBAT

BASIC

TEST CIRCUIT

600 Ω

VT/R

2.15 µF

RING

82.5 Ω

–

RCV

RING

®

HP 4935A

TIMS

VS

VS = 0.5 Vrms 30% AM 1 kHz modulation,

f = 500 kHz—1 MHz

device in powerup mode, 600 Ω termination.

VXMT

VT/R

GXMT =

VT/R

VRCV

GRCV =

Figure 8. RFI Rejection

12-2587 (F).e

Figure 10. ac Gains

14

Agere Systems Inc.

Data Sheet

November 2001

L9218A/G Low-Cost Line Interface

Applications

A basic loop start reference circuit, using bused ringing with the L9218 SLIC and the T7504 first-generation codec,

is shown in Figure 11. This circuit is designed for a 200 Ω + 680 Ω || 0.1 µF complex termination impedance and

transhybrid. Transmit gain is set at 0 dBm and receive gain is set at –7 dBm.

V^BAT

V^CC

C^BAT

0.1 µF

C^CC

0.1 µF

R^PROG

C^GS

R^GS

1

I^PROG

LCTH

9

4

2.37 kΩ

6.8 nF

35.7 kΩ

R^LCTH

26

25

V^BAT

V^CC

TG

7

8

R^GP1

8.06 kΩ

22.1 kΩ

VTX

R^X

C^B

158.0 kΩ

DCOUT

0.1 µF

R^T2

80.6 kΩ

GSX

DX

24

23

C^B1

0.47 µF

TXI

VITR

–

+

R^T1

R^HB1

R^PT

TIP

18

10

71.5 kΩ

357 k

Ω

PT

PCM

HIGHWAY

+2.4 V

50 Ω

R^RCV

137.0 kΩ

5

L9218

SLIC

RCVP

RCVN

DR

L7591

LCAS

EMR

C^B2

R^GP

30.1 kΩ

R^N1

FSX CONTROL

143.0 kΩ 0.47 µF

AND

CLOCK

FSR

MCLK

R^PR

VF^RO

RING

C^GN

0.1 nF

R^N2

PR

18.2 kΩ

6

50 Ω

R^TSP

2.94 MΩ

27

22

SUPERVISION

TSD

20

19

OUTPUTS

RTSP

RTSN

NSTAT

1/4 T7504

CODEC

C^RTS1

0.015 µF

R^TS1

402 Ω

B2/NC 13

B1 14

CONTROL

INPUTS

R^TSN

3.32 MΩ

B0 15

CF2

11

CF1

12

C^F1

0.47 µF

AGND BGND

16

17

V^RING

C^F2

0.1 µF

V^BAT

2797 (F).a

Figure 11. Basic Loop Start Application Circuit Using T7504-Type Codec

Table 9 shows the design parameters of the application circuit shown in Figure 11. Components that are adjusted

to program these values are also shown.

Table 9. 200 Ω + 680 Ω || 0.1 µF First-Generation Codec Design Parameters

Design Parameter

Loop Closure Threshold

Parameter Value

10 mA

Components Adjusted

LCTH

R

PROG

dc Loop Current Limit

2-wire Signal Overload Level

ac Termination Impedance

Hybrid Balance Line Impedance

Transmit Gain

20 mA

R

3.14 dBm

—

T1

GP

RCV, GP1, GS, GS

200 Ω + 680 Ω || 0.1 µF

0 dBm

R , R , R

R

C

HB1

R

T2

X, N1, N2,

N

R , R R

R

C

RCV

GP

, R , R

T1

Receive Gain

–7 dBm

R

Agere Systems Inc.

15

Data Sheet

November 2001

L9218A/G Low-Cost Line Interface

Applications (continued)

Table 10. Parts List for Loop Start Application Circuit Using T7504-Type Codec

Name

Integrated Circuits

SLIC

Value

Function

L9218

Subscriber loop interface circuit (SLIC).

Secondary protection.

Protector

Agere L7591

Ringing Relay

Codec

Agere L7581/2/3 or EMR

T7504

Switches ringing signals.

First-generation codec.

Overvoltage Protection

PT

R

50 Ω, Fusible

Protection resistor.

PR

R

Power Supply

BAT1

BAT

C

0.1 µF, 20%, 100 V

0.1 µF, 20%, 10 V

0.47 µF, 20%, 100 V

0.1 µF, 20%, 100 V

V

filter capacitor.

F2

CC

V

C

F1

C

With C , improves idle-channel noise.

F2

F1

C

With C , improves idle-channel noise.

dc Profile

PROG

R

35.7 kΩ, 1%, 1/16 W

Sets dc loop current limit.

ac Characteristics

B1

C

0.47 µF, 20%, 10 V

71.5 kΩ, 1%, 1/16 W

137 kΩ, 1%, 1/16 W

30.1 kΩ, 1%, 1/16 W

ac/dc separation capacitor.

B2

C

T1

GP

RCV

R

With R and R , sets ac termination impedance.

RCV

GP

T1

R

With R and R , sets receive gain.

GP

T1

RCV

R

With R and R , sets ac termination impedance

and receive gain.

T2

X

R

80.6 kΩ, 1%, 1/16 W

158 kΩ, 1%, 1/16 W

357 kΩ, 1%, 1/16 W

6.8 nF, 10%, 10 V

With R , sets transmit gain in codec.

X

T2

R

With R , sets transmit gain in codec.

HB1

R

Sets hybrid balance.

GS

C

With R , provides gain shaping for termination

impedance matching.

GS

R

2.37 kΩ, 1%, 1/16 W

With C , provides gain shaping for termination

impedance matching.

GP1

R

8.06 kΩ, 1%, 1/16 W

0.1 nF, 20%, 10 V

Sets transmit gain of SLIC.

N

N1

N2

C

With R and R high frequency compensation.

N1

N

N2

R

143 kΩ, 1%, 1/16 W

18.2 kΩ, 1%, 1/16 W

With C and R high frequency compensation.

N2

N1

N

R

With R and C high frequency compensation.

Supervision

LCTH

R

22.1 kΩ, 1%, 1/16 W

402 Ω, 5%, 2 W

Sets loop closure (off-hook) threshold.

Ringing source series resistor.

TS1

R

RTS1

TSN

TSP

C

0.015 µF, 20%, 10 V

3.32 MΩ, 1%, 1/16 W

2.94 MΩ, 1%, 1/16 W

With R , R , forms filter pole.

TSN

TSP

R

With R , sets threshold.

TSP

RTS1

With C

TSN

R

, R , sets threshold.

16

Agere Systems Inc.

Data Sheet

November 2001

L9218A/G Low-Cost Line Interface

Applications (continued)

A basic loop start reference circuit, using bused ringing with the L9218 SLIC and the T8536 third-generation codec,

is shown in Figure 12.

V^BAT

V^CC

C^BAT

0.1 µF

C^CC

0.1 µF

R^PROG

1

I^PROG

LCTH

9

4

35.7 kΩ

R^LCTH

V^BAT

V^CC

7

8

26

25

TG

R^GP1

22.1 kΩ

8.06 kΩ

VTX

DCOUT

C^B

0.1 µF

24

TXI

DX1

C^B1

0.1 µF

1/4 T8536

CODEC

R^CIN

20 MΩ

R^PT

DX2

DR1

DR2

TIP

PCM

18

10

23

5

PT

HIGHWAY

VITR

VF^XI

50 Ω

L9218

SLIC

RCVP

VF^ROP

VF^RON

SLIC0a

SLIC3a

SLIC2a

SLIC4a

L7591

6

LCAS

EMR

RCVN

NSTAT

B0

CONTROL

AND

CLOCK

FS

BCLK

V^DD

22

15

14

R^PR

RING

PR

50 Ω

R^TSP

2.94 MΩ

C^VDD

0.1 µF

20

19

B1

RTSP

RTSN

13 (OPTIONAL*)

DGND

C^RTS1

0.015 µF

R^TS1

510 Ω

B2/NC

R^TSN

3.4 MΩ

CF2

11

CF1

12

AGND BGND

16

17

C^F1

V^RING

0.47 µF

C^F2

0.1 µF

V^BAT

2798 (F).a

* Optional nonfunctional connection for exact footprint match with L9219.

Figure 12. Basic Loop Start Application Circuit Using T8536-Type Codec

Agere Systems Inc.

17

Data Sheet

November 2001

L9218A/G Low-Cost Line Interface

Applications (continued)

Table 11. Parts List for Loop Start Application Circuit Using T8536-Type Codec

Name

Integrated Circuits

SLIC

Value

Function

L9218

Subscriber loop interface circuit (SLIC).

Secondary protection.

Protector

Agere L7591

Ringing Relay

Codec

Agere L7581/2/3 or EMR

T8536

Switches ringing signals.

Third-generation codec.

Overvoltage Protection

PT

R

50 Ω, Fusible

Protection resistor.

PR

R

Power Supply

BAT1

BAT

C

0.1 µF, 20%, 100 V

0.1 µF, 20%, 10 V

0.47 µF, 20%, 100 V

0.1 µF, 20%, 100 V

V

filter capacitor.

F2

CC

V

C

F1

C

With C , improves idle-channel noise.

F2

F1

C

With C , improves idle-channel noise.

dc Profile

PROG

R

35.7 kΩ, 1%, 1/16 W

Sets dc loop current limit.

ac Characteristics

B3

C

0.1 µF, 20%, 10 V

8.06 kΩ, 1%, 1/16 W

20 MΩ, 5%, 1/16 W

ac/dc separation capacitor.

Sets transmit gain of SLIC.

dc bias.

GP1

R

CIN

R

Supervision

LCTH

R

22.1 kΩ, 1%, 1/16 W

510 Ω, 5%, 2 W

Sets loop closure (off-hook) threshold.

Ringing source series resistor.

TS1

R

RTS1

TSN

TSP

C

0.015 µF, 20%, 10 V

3.4 MΩ, 1%, 1/16 W

2.94 MΩ, 1%, 1/16 W

With R

and R , forms second 2 Hz filter pole.

TSN

TSP

R

With R , sets threshold.

TSP

TSN

R

With R , sets threshold.

18

Agere Systems Inc.

Data Sheet

November 2001

L9218A/G Low-Cost Line Interface

Starting from the on-hook condition and going through

to a short circuit, the curve passes through the follow-

ing two regions:

Applications (continued)

dc Applications

Region 1: On-hook and low-loop currents. The slope

corresponds to the dc resistance of the

Battery Feed

dc1

SLIC, R (70 Ω typical). The open circuit

voltage is the battery voltage minus the over-

The dc feed characteristic can be described by:

OH

head voltage of the device, V (6.5 V typi-

^BAT– OH

V

) × R

dc

L

( V

cal). These values are suitable for most

applications but can be adjusted if needed.

T/R

V

= ---------------------------------------------

L

P

R + 2R + R

Region 2: Current limit. The dc current is limited to a

starting value determined by external resis-

PROG

V

^BAT– OH

V

L

I = ---------------------------------

L

P

dc

R + 2R + R

tor R

, an internal current source, and

the gain from tip/ring to pin DCOUT.

where:

L

I = dc loop current.

T/R

V

= dc loop voltage.

Current Limit

|V^BAT| = battery voltage magnitude.

OH

V

= overhead voltage. This is the difference between

the battery voltage and the open loop tip/ring

voltage.

With the B0/B1 logic inputs set to 11 (low current limit),

current limit with a 100 Ω load is given by the following

equation:

L

R = loop resistance, not including protection resistors.

P

R = protection resistor value.

PROG

LIM

0.637 R

(kΩ) + 2 mA= I x (mA)

dc

R

= SLIC internal dc feed resistance.

The relationship between low current limit (B0 = 1,

B1 = 1) and high current limit (B0 = 1, B1 = 0) is

The design begins by drawing the desired dc template.

An example is shown in Figure 13.

ILIMIT(Low)

---------------------------------

= 0.7

ILIMIT(High)

50

40

Overhead Voltage

I^LIMONSET

I^LIMTESTED

In order to drive an on-hook ac signal, the SLIC must

set up the tip and ring voltage to a value less than the

battery voltage. The amount that the open loop voltage

is decreased relative to the battery is referred to as the

overhead voltage, expressed as the following equation:

1

30

20

12.5 kΩ

–1

Rdc1

10

0

OH

BAT

PT

PR

V

= |V | – (V – V )

Without this buffer voltage, amplifier saturation will

occur and the signal will be clipped. The L9218 is auto-

matically set at the factory to allow undistorted on-hook

transmission of a 3.14 dBm signal into a 900 Ω loop

impedance.

0

10

20

30

40

50

LOOP VOLTAGE (V)

12-3050 (F).i

Notes:

VBAT = –48 V.

ILIM = 22 mA.

Rdc1 = 115 Ω.

Figure 13. Loop Current vs. Loop Voltage

Agere Systems Inc.

19

Data Sheet

November 2001

L9218A/G Low-Cost Line Interface

Applications (continued)

dc Applications (continued)

Loop Range

The equation below can be rearranged to provide the loop range for a required loop current:

V

^BAT– OH

V

L

---------------------------- –

R =

2R R

^P– DC

L

I

Off-Hook Detection

The loop closure comparator has built-in longitudinal rejection, eliminating the need for an external 60 Hz filter. The

LCTH

loop closure detection threshold is set by resistor R

. The supervision output bit NSTAT is high in an on-hook

condition. The off-hook comparator goes low during an off-hook condition:

TR

LCTH

I

(mA) = 0.4167 R

(kΩ) – 1.9 mA ACTIVE off-hook to on-hook

(kΩ) + 2.7 mA SCAN on-hook to off-hook

TR

RP

TIP

0.125 V/mA

DCOUT

ITR

RL

+

–

RLCTH

RING

LCTH

RP

+

0.05 mA

NSTAT

–

12-2553 (F).f

Figure 14. Off-Hook Detection Circuit

20

Agere Systems Inc.

Data Sheet

November 2001

L9218A/G Low-Cost Line Interface

Applications (continued)

dc Applications (continued)

Ring Trip Detection

The ring trip circuit is a comparator that has a special input section optimized for this application. The equivalent

circuit is shown in Figure 15, along with its use in an application using unbalanced, battery-backed ringing.

PHONE

HOOK SWITCH

RLOOP

RTSP

+

RTSP

2.94 M

Ω

NSTAT

8.6 V

RC PHONE

I

P

= I

N

RS

C

0.015

RTS1

+

–

402 510

Ω/

Ω

F

µ

IN

VBAT

VRING

RTSN

–

RTSN

15 k

Ω

3.32 M 3.40 M

Ω/

Ω

2799 (F)

Figure 15. Ring Trip Equivalent Circuit and Equivalent Application

Ring trip detection threshold is given by the following equation:

[RTSN(MΩ) + 0.015 – RTSP(MΩ)] × [ V^BAT– 8.6] × 1000

-------------------------------------------------------------------------------------------------------------------------------------------------------------------------

(mA) =

TH

I

[RTSN(MΩ) + 0.015] × R^S

Longitudinal Balance

The SLIC is graded to certain longitudinal balance specifications. The numbers are guaranteed by testing (Figure

5 and Figure 8). However, for specific applications, the longitudinal balance may also be determined by termination

impedance, protection resistance, and especially by the mismatch between protection resistors at tip and ring. This

can be illustrated by the following equation:

(368 + RP) × (368 + ZT – RP)

-------------------------------------------------------------------------------------------

LB = 20 x log

where:

368 × (2 × [ZT – 2 × RP] × ∆ + ε⁾

LB: longitudinal balance.

RP: protection resistor value in Ω.

ZT: magnitude of the termination impedance in Ω.

ε: protection resistor mismatch in Ω.

∆: SLIC internal tip/ring sensing mismatch.

The ∆ can be calculated using the above equation with these exceptions: ε = 0, ZT = 600 Ω, RP = 100 Ω, and the

longitudinal balance specification on a specific code.

Now with ∆ available, the equation will predict the actual longitudinal balance for RP, ZT, and ε.

Be aware that ZT may vary with frequency for complex impedance applications.

Agere Systems Inc.

21

Data Sheet

November 2001

L9218A/G Low-Cost Line Interface

ac Interface Network

Applications (continued)

The ac interface network between the L9218 and the

codec will vary depending on the codec selected. With

a first-generation codec, the interface between the

L9218 and codec actually sets the ac parameters. With

a third-generation codec, all ac parameters are set dig-

itally, internal to the codec; thus, the interface between

the L9218 and this type of codec is designed to avoid

overload at the codec input in the transmit direction,

and to optimize signal-to-noise ratio (S/N) in the

receive direction.

ac Design

Codec Types

At this point in the design, the codec needs to be

selected. The interface network between the SLIC and

codec can then be designed. There are four key ac

design parameters. Termination impedance is the

impedance looking into the 2-wire port of the line card.

It is set to match the impedance of the telephone loop

in order to minimize echo return to the telephone set.

Transmit gain is measured from the 2-wire port to the

PCM highway, while receive gain is done from the PCM

highway to the transmit port. Finally, the hybrid balance

network cancels the unwanted amount of the receive

signal that appears at the transmit port.

Receive Interface

Because the design requirements are very different

with a first- or third-generation codec, the L9218 is

offered with two different receive gains. Each receive

gain was chosen to optimize, in terms of external com-

ponents required, the ac interface between the L9218

and the codec.

Below is a brief codec feature summary.

First-Generation Codecs. These perform the basic fil-

tering, A/D (transmit), D/A (receive), and µ-law/A-law

companding. They all have an op amp in front of the

A/D converter for transmit gain setting and hybrid bal-

ance (cancellation at the summing node). Depending

on the type, some have differential analog input stages,

differential analog output stages, 5 V only or ±5 V oper-

ation, and µ-law/A-law selectability. These are avail-

able in single and quad designs. This type of codec

requires continuous time analog filtering via external

resistor/capacitor networks to set the ac design param-

eters. An example of this type of codec is the Agere

T7504 quad 5 V only codec.

With a first-generation codec, the termination imped-

ance is set by providing gain shaping through a feed-

back network from the SLIC VITR output to the SLIC

RCVN/RCVP inputs. The L9218 provides a transcon-

ductance from T/R to VITR in the transmit direction and

a single-ended to differential gain in the receive direc-

tion from either RCVN or RCVP to T/R. Assuming a

short from VITR to RCVN or RCVP, the maximum

impedance that is seen looking into the SLIC is the

product of the SLIC transconductance times the SLIC

receive gain, plus the protection resistors. The various

specified termination impedance can range over the

voice band as low as 300 Ω up to over 1000 Ω. Thus, if

the SLIC gains are too low, it will be impossible to syn-

thesize the higher termination impedances. Further-

more, the termination that is achieved will be far less

than what is calculated by assuming a short for SLIC

output to SLIC input. In the receive direction, in order to

control echo, the gain is typically a loss, which requires

a loss network at the SLIC RCVN/RCVP inputs, which

will reduce the amount of gain that is available for ter-

mination impedance. For this reason, a high-gain SLIC

is required with a first-generation codec.

This type of codec tends to be the most economical in

terms of piece part price, but tends to require more

external components than a third-generation codec.

Furthermore, ac parameters are fixed by the external

R/C network, so software control of ac parameters is

difficult.

Third-Generation Codecs. This class of devices

includes all ac parameters set digitally under micropro-

cessor control. Depending on the device, it may or may

not have data control latches. Additional functionality

sometimes offered includes tone plant generation and

reception, TTX generation, test algorithms, and echo

cancellation. Again, this type of codec may be 5 V

only or ±5 V operation, single quad or 16-channel, and

µ-law/A-law or 16-bit linear coding selectable. Exam-

ples of this type of codec are the Agere T8535/6 (5 V

only, quad, standard features), T8533/4 (5 V only, quad

with echo-cancellation), and the T8531/36 (5 V only

16-channel with self-test).

22

Agere Systems Inc.

Data Sheet

November 2001

L9218A/G Low-Cost Line Interface

better the S/N. The problem is, if the codec is feeding a

high-gain SLIC, either an external resistor divider is

needed to knock the gain down to meet the TLP

requirements, or the codec is not operating near maxi-

mum signal levels, thus compromising the S/N.

Applications (continued)

ac Design (continued)

Receive Interface (continued)

It appears the solution is to have a SLIC with a low

gain, especially in the receive direction. This will allow

the codec to operate near its maximum output signal

(to optimize S/N), without an external resistor divider

(to minimize cost).

With a third-generation codec, the line card designer

has different concerns. To design the ac interface, the

designer must first decide upon all termination imped-

ance, hybrid balances, and transmission-level points

(TLP) requirements that the line card must meet. In the

transmit direction, the only concern is that the SLIC

does not provide a signal that is too hot and overloads

the codec input. Thus, for the highest TLP that is being

designed to, given the SLIC gain, the designer, as a

function of voice band frequency, must ensure that the

codec is not overloaded. With a given TLP and a given

SLIC gain (if the signal will cause a codec overload),

the designer must insert some sort of loss, typically a

resistor divider, between the SLIC output and codec

input.

Note also that some third-generation codecs require

the designer to provide an inherent resistive termina-

tion via external networks. The codec will then provide

gain shaping, as a function of frequency to meet the

return loss requirements. Further stability issues may

add external components or excessive ground plane

requirements to the design.

To meet the unique requirements of both types of

codecs, the L9218 offers two receive gain choices.

These receive gains are mask-programmable at the

factory and are offered as two different code variations.

For interface with a first-generation codec, the L9218A

is offered with a receive gain of 7.86. For interface with

a third-generation codec, the L9218G is offered with a

receive gain of 2. In either case, the transconductance

in the transmit direction, or the transmit gain is 403 Ω.

In the receive direction, the issue is to optimize S/N.

Again, the designer must consider all the considered

TLPs. The idea is, for all desired TLPs, to run the

codec at or as close as possible to its maximum output

signal, to optimize the S/N. Remember noise floor is

constant, so the hotter the signal from the codec, the

Example 1: Real Termination (First-Generation Codec)

ac equivalent circuits for real termination using a T7504 codec is shown in Figure 15.

RX

VGSX

–0.403 V/mA

RT2

VFXIN

VFXIP

–

+

VITR

RT1

RCVN

RHB1

2.4 V

–

V =

–

ZT/R

RP

TIP

A

AV = 1

RRCV

3.93

RCVP

VFR

+

IT/R

+

CURRENT

SENSE

VS

ZT

VT/R

RG

–

+

AV = –1

–

RP

RING

L9218 SLIC

1/4 T7504 CODEC

12-3581 (F).d

Figure 16. ac Equivalent Circuit

Agere Systems Inc.

23

Data Sheet

November 2001

L9218A/G Low-Cost Line Interface

Applications (continued)

ac Design (continued)

Example 1: Real Termination (First-Generation Codec) (continued)

The following design equations refer to the circuit in Figure 16. Use these to synthesize real termination imped-

ance.

Termination Impedance:

T ⁄ R

V

–I

--------------

ZT =

T ⁄ R

3168

P

ZT = 2R + ----------------------------------

T3

R

1 +

+

-------- -----------

GP

RCV

R

Receive Gain:

T ⁄ R

V

-------------

rcv

g

=

fr

V

7.86

rcv

-------------------------------------------------------------------------------------

RCV

R

Z

T

Z

T/R

--------------- --------------- ------------

1 +

+

T3

GP

R

Transmit Gain:

GSX

V

--------------

tx

g =

T ⁄ R

V

X

R

403

----------

x

----------

tx

g =

T6

Z

T

Hybrid Balance:

GSX

V

--------------

bal

h

= 20log

T ⁄ R

V

To optimize the hybrid balance, the sum of the currents at the VFX input of the codec op amp should be set to 0.

The following expressions assume the test network is the same as the termination impedance:

X

R

------------------------

HB

R

=

tx × rcv

g

X

R

-----------

bal

h

tx × rcv

g

= 20log

– g

HB

24

Agere Systems Inc.

Data Sheet

November 2001

L9218A/G Low-Cost Line Interface

Applications (continued)

ac Design (continued)

Example 2: Complex Termination (First-Generation Codec)

Below are design equations for complex termination (see Figure 17 and Figure 18).

T

T1

T2

T

Z = R + R || C

7.86

-----------

201.2

1

---------------------------------- -----------------

T1

T2

=

P

TGP

TGS

R

= 2R +

•

–

R

|| R

T3

N1

R

1 +

+

-------- -----------

--------

1 +

GP

RCV

N2

R

7.86

TGP

TGS

R

⁄ R

1

-----------

TGP

=

• ---------------------------------- + -----------------

R

|| R

201.2

T3

N1

R

1 +

+

-------- -----------

--------

1 +

GP

RCV

N2

R

2

N2

TGP

1

7.86

1

R

N1

1

R

TGP

1

T3

1

_TGP||

------

CT

---------------- ----------------------------------------------

---------- ------------------------------------

---------------------------------------------- ---------------------

–

TGS

•

R

+

(

R

N2)²

+ R

C

N1

CTG

TGS

T3

N1

201.2

R

+ R

R

1 + ----------- + ---------------

----------

1 +

GP

RCV

N2

R

X

TG

R

1

Z

---------- ---------------- ----------

tx

g =

T6

201.2

Z

T

7.86

1

----------------------------------------------- -----------------------

rcv =

×

g

h

RCV

T

R

Z

--------------- ---------------

-------------

1 +

+

1 +

T3

GP

T ⁄ R

R

Z

X

R

-----------

bal

tx × rcv

= 20log

– g

g

HB

R

where:

T/R

1

2

Z

= R + R || C

TG

TGP

TGS

G

= R

|| (R

+ C )

TGP

R

= 8.06 kΩ

1

R

-------

TGS

TGP

=

R

2

R

------------------------------------------

G

C =

x C

TGP(

1

2)

R

R + R

and

P

2R

N

N2

G

TGP

C R = ------------ C R

3168

TGS

R

(3168)

-------------

N1

N2

–

1

R

= R -----------------

TGP

P

2R

The equations above do not include the blocking capacitors.

Agere Systems Inc.

25

Data Sheet

November 2001

L9218A/G Low-Cost Line Interface

Applications (continued)

ac Design (continued)

Example 2: Complex Termination (First-Generation Codec) (continued)

RTGS

CGS

RX

RTGP = 8.06 kΩ

–IT/R

CB

201.2

R

T6

–

+

AX

AAC

CODEC

OP AMP

CN

RT3

RN1

RRCCVVNN

RRCCVVPP

CODEC

OUTPUT

DRIVE

AMP

RRCV

RGP

RN2

5-6401 (F).j

Figure 17. Interface Circuit Using First-Generation Codec (±5 V Battery)

RTGS

CG

RX

RTGP = 8.06 kΩ

–IT/R

201.2

RT6

–

+

AX

AAC

CB

CB1

CODEC

OP AMP

–2.4 V

CN

RT3

RN1

RCVN

RCVP

CODEC

RRCV

OUTPUT

DRIVE

AMP

CB2

RGP

RN2

5-6400 (F).n

Figure 18. Interface Circuit Using First-Generation Codec (5 V Only Codec)

26

Agere Systems Inc.

Data Sheet

November 2001

L9218A/G Low-Cost Line Interface

^{Loop power = (25 mA}• ^1.05)²•

Applications (continued)

(200 Ω + 100 Ω)

Power Derating

Loop power = 0.207 W

SLIC power = 1.523 W – 0.207 W = 1.28

SLIC power = 1.28 W < 1.51 W

Operating temperature range, maximum current limit,

maximum battery voltage, minimum dc loop, and pro-

tection resistor values will influence the overall thermal

performance. This section shows the relevant design

equations and considerations in evaluating the SLIC

thermal performance.

Thus, in this example, the thermal design ensures that

the SLIC will not enter the thermal shutdown state.

Consider the L9218 SLIC in a 28-pin PLCC package.

The still-air thermal resistance on a 2-layer board is

typically 43 °C/W.

Pin-for-Pin Compatibility with L9217/L9219

The L9218 is an exact pin-for-pin replacement for the

L9217/19. The one minor exception is L9217/19 has

three logic control inputs: B0, B1, and B2. The L9218

has only two logic control inputs, B0 and B1. B2 in the

L9217/19 is pin 13. Pin 13 in L9218 is NC, so a con-

nection between the controller and pin 13 will not affect

L9218 operation. This allows an exact footprint match

with L9217/19.

The SLIC will enter the thermal shutdown state at a

minimum of 150 °C. The thermal shutdown design

should ensure that the SLIC temperature does not

reach 150 °C under normal operating conditions.

Assume a maximum ambient operating temperature of

85 °C, a maximum current limit of 25 mA (including tol-

erance), and a maximum battery of –52 V. Further-

more, assume a (worst-case) minimum dc loop of

200 Ω, and that 50 Ω protection resistors are used at

both tip and ring.

PCB Layout Information

BAT

Make the leads to BGND and V

as wide as possible

TSD

AMBIENT(max)

1. T

– T

= allowed thermal rise.

for thermal and electrical reasons. Also, maximize the

amount of PCB copper in the area of (and specifically

on) the leads connected to this device for the lowest

operating temperature.

150 °C – 85 °C = 65 °C

2. Allowed thermal rise = package thermal

^impedance• ^{SLIC power dissipation.}

When powering the device, make certain that no exter-

nal potential creates a voltage on any pin of the device

that exceeds the device ratings. In this application,

some of the conditions that cause such potentials dur-

ing powerup are the following:

^{65 °C = 43 °C/W}• ^{SLIC power dissipation}

DISS

SLIC power dissipation (P

) = 1.51 W

Thus, if the total power dissipated in the SLIC is less

than 1.51 W, it will not enter the thermal shutdown

state. Total SLIC power is calculated as:

1. An inductor connected to PT and PR (this can force

BAT

an overvoltage on V

through the protection

DISS

•

Total P

= maximum battery maximum

BAT

devices if the V

connection chatters).

current limit (including effects of accuracy)

+ SLIC quiescent power

BAT

2. Inductance in the V

lead (this could resonate with

BAT

the V

filter capacitor to cause a destructive over-

Q

For the L9218, SLIC quiescent power (P ) is maximum

at 0.158 W. Thus,

voltage).

This device is normally used on a circuit card that is

subjected to hot plug-in, meaning the card is plugged

into a biased backplane connector. In order to prevent

damage to the IC, all ground connections must be

applied before, and removed after, all other connec-

tions.

DISS

•

Total P

= (–52 V [25 mA 1.05]) + 0.158 W

= 1.365 W + 0.158 W

= 1.523 W

The power dissipated in the SLIC is the total power dis-

sipation minus the power that is dissipated in the loop.

DISS

SLIC P

= total power – loop power

2

LIM

•

dcLOOP

P

Loop power = (I

)

(R

min + 2R )

Agere Systems Inc.

27

Data Sheet

November 2001

L9218A/G Low-Cost Line Interface

Outline Diagram

28-Pin PLCC

Dimensions are in millimeters.

12.446 ± 0.127

11.506 ± 0.076

PIN #1 IDENTIFIER

4

1

26

ZONE

25

5

11.506

± 0.076

12.446

± 0.127

11

19

12

18

4.572

MAX

SEATING PLANE

0.10

0.51 MIN

TYP

1.27 TYP

0.330/0.533

5-2608(F)

28

Agere Systems Inc.

Data Sheet

November 2001

L9218A/G Low-Cost Line Interface

Ordering Information

Device

Package

Comcode

LUCL9218AAR-D

28-Pin PLCC

(Dry Bag)

108558271

Gain of 12

LUCL9218AAR-DT

LUCL9218GAR-D

LUCL9218GAR-DT

28-Pin PLCC

(Tape and Reel, Dry Bag)

Gain of 12

108558289

108558156

108558164

28-Pin PLCC

(Dry Bag)

Gain of 2

28-Pin PLCC

(Tape and Reel, Dry Bag)

Gain of 2

Agere Systems Inc.

29

IEEE is a registered trademark of The Institute of Electrical and Electronics Engineers, Inc.

HP is a registered trademark of Hewlett-Packard Company.

For additional information, contact your Agere Systems Account Manager or the following:

INTERNET:

E-MAIL:

http://www.agere.com

docmaster@agere.com

N. AMERICA: Agere Systems Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, PA 18109-3286

1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106)

ASIA:

Agere Systems Hong Kong Ltd., Suites 3201 & 3210-12, 32/F, Tower 2, The Gateway, Harbour City, Kowloon

Tel. (852) 3129-2000, FAX (852) 3129-2020

CHINA: (86) 21-5047-1212 (Shanghai), (86) 10-6522-5566 (Beijing), (86) 755-695-7224 (Shenzhen)

JAPAN: (81) 3-5421-1600 (Tokyo), KOREA: (82) 2-767-1850 (Seoul), SINGAPORE: (65) 778-8833, TAIWAN: (886) 2-2725-5858 (Taipei)

Tel. (44) 7000 624624, FAX (44) 1344 488 045

EUROPE:

Agere Systems Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application.

November 2001

DS02-039ALC (Replaces DS01-318ALC)


型号：	L9218A
厂家：	AGERE SYSTEMS
描述：	Low-Cost Line Interface 低成本线接口
文件：	总30页 (文件大小：365K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

L9218A [AGERE]

相关型号：

L9219A

L9222

L9222-D

L9222D

L9222D013TR

L9222_04

L9230

L9230-DIE1

L9230DIE1

L924GD

L924HD

L924YD