HMMC-3102 [AGILENT]
DC - 16 GHz Packaged Divide-by-2 Prescaler; DC - 16 GHz的包装分频预分频器
| 型号： | HMMC-3102 |
| 厂家： | 
AGILENT TECHNOLOGIES, LTD. |
| 描述： | DC - 16 GHz Packaged Divide-by-2 Prescaler |
| 文件： | 总6页 (文件大小：379K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Agilent HMMC-3102
DC - 16 GHz Packaged
Divide-by-2 Prescaler
HMMC-3102-TR1 - 7" diameter reel/500 each
HMMC-3102-BLK - Bubble strip/10 each
Data Sheet
Features
• Wide Frequency Range:
0.2–16 GHz
• High Input Power
Sensitivity:
On-chip pre- and post-amps
-20 to +10 dBm (1–10 GHz)
-15 to +10 dBm (10–12 GHz)
-10 to +5 dBm (12–15 GHz)
• Pout: +6 dBm (0.99 Vp-p) will
drive ECL
• Low Phase Noise:
-153 dBc/Hz @ 100 kHz Offset
• (+) or (-) Single Supply Bias
with wide range:
4.5 to 6.5 V
• Differential I/0 with on-chip
Package Type:
Package Dimensions: 4.9 ´ 3.9 mm Typ.
Package Thickness:
Lead Pitch:
Lead Width:
8-lead SSOP Plastic
1.55 mm Typ.
1.25 mm Nom.
0.42 mm Nom.
50W matching
[1]
Absolute Maximum Ratings
(@ TA=25°C, unless otherwise indicated)
Symbol
Parameters/Conditions
Min.
Max.
Units
Description
V
Bias Supply Voltage
Bias Supply Voltage
+7
volts
volts
CC
The HMMC-3102 is a packaged
GaAs HBT MMIC prescaler
which offers DC to 16 GHz fre-
quency translation for use in
communications and EW sys-
tems incorporating high-frequen-
cy PLL oscillator circuits and
signal-path down conversion ap-
plications. The prescaler pro-
vides a large input power
VEE
-7
|VCC
VEE
-
Bias Supply Delta
+7
volts
|
VLogic
Logic Threshold Voltage
CW RF Input Power
VCC-1.5
VCC-1.2
+10
volts
dBm
P
in(CW)
VRFin
[2]
DC Input Voltage
(@ RFin or RFin Ports)
VCC ± 0.5
volts
T
Backside Operating Temp.
Storage Temperature
-40
-65
+85
°C
°C
BS
sensitivity window and low
phase noise.
T
+165
st
Maximum Assembly Temp.
(60 seconds max.)
T
310
°C
max
[1]
[2]
Operation in excess of any parameter limit (except T ) may cause permanent damage
BS
to the device.
5
MTTF >5´ 10 hours @ T <85°C. Operation in excess of maximum operating temper-
BS
ature (T ) will degrade MTTF.
BS
6-53
DC Specifications/Physical Properties
(TA = 25°C, VCC - VEE = 5.0 volts, unless otherwise listed)
Symbol
Parameters/Conditions
Operating bias supply difference[1]
Min.
Typ.
Max.
Units
VCC - VEE
|ICC| or |IEE| Bias supply current
4.5
68
5.0
80
6.5
92
volts
mA
VRFin(q)
Quiescent DC voltage appearing at all RF ports
VCC
volts
volts
VRFout(q)
VLogic
Nominal ECL Logic Level
(VLogic contact self-bias voltage, generated on-chip)
VCC - 1.45
VCC -1.35
VCC -1.25
[1]
Prescaler will operate over full specified supply voltage range. V or V not to exceed limits specified in Absolute Maximum Ratings
CC
EE
section.
RF Specifications
(TA = 25°C, Z0 = 50W, VCC - VEE = 5.0 volts)
Symbol
Parameters/Conditions
Min.
Typ.
Max.
Units
¦
Maximum input frequency of operation
16
18
GHz
in(max)
Minimum input frequency of operation[1]
¦
0.2
0.5
GHz
in(min)
(Pin = -10 dBm)
¦
Output Self-Oscillation Frequency[2]
@ DC, (Square-wave input)
3.4
GHz
dBm
dBm
dBm
dBm
dBm
Self-Osc.
-15
-15
-15
-10
-4
>-25
>-20
>-25
>-15
>-10
+10
+10
+10
+10
+4
@ ¦ in = 500 MHz, (Sine-wave input)
Pin
¦
¦
¦
in = 1 to 10 GHz
= 10 to 12 GHz
= 12 to 15 GHz
in
in
Small-Signal Input/Output Return Loss
(@¦ in< 12 GHz)
Small-Signal Reverse Isolation
(@¦ in< 12 GHz)
RL
S12
15
30
dB
dB
SSB Phase noise (@ Pin = 0 dBm, 100kHz offset
from a ¦ out = 1.2 GHz Carrier)
Input signal time variation @ zero-crossing
(¦ in = 10 GHz, Pin = -10 dBm)
Output transition time (10% to 90% rise/fall time)
@ ¦ out < 1 GHz
@ ¦ out = 2.5 GHz
@ ¦ out = 3.5 GHz
@ ¦ out <1 GHz
@ ¦ out = 2.5 GHz
j
-153
1
dBc/Hz
ps
N
Jitter
Tr or Tf
70
6
5.5
ps
4
3.5
0
dBm
dBm
dBm
volts
volts
volts
[3]
Pout
2.0
0.99
0.94
0.63
[4]
|Vout(p-p)
|
@ ¦ out = 3.5 GHz
¦
out power level appearing at RFin or RFin
-40
-47
dBm
dBm
(@ ¦ in 12 GHz, Unused RFout or RFout
unterminated)
PSpitback
¦
out power level appearing at RFin or RFin
(@ ¦ in = 12 GHz, Both RFout & RFout
terminated)
Power level of ¦ in appearing at RFout or RFout
(@ ¦ in = 12 GHz, Pin = 0 dBm, Referred to
Pin(¦ in))
Pfeedthru
-23
-25
dBc
dBc
Second harmonic distortion output level
(@ ¦ out = 3.0 GHz, Referred to Pout(¦ out))
H2
[1]
[2]
For sine-wave input signal. Prescaler will operate down to D.C. for square-wave input signal. Minimum divide frequency limited by input
slew-rate.
Prescaler can exhibit this output signal under bias in the absence of an RF input signal. This condition can be eliminated by use of the
Input DC offset technique described on page 3.
Fundamental of output square wave’s Fourier Series.
[3]
[4]
Square wave amplitude calculated from P
.
out
6-54
HMMC-3102/rev.3.3
For positive supply operation,
VCC pins are nominally biased at
any voltage in the +4.5 to +6.5 volt
range with pin 8 (VEE) grounded.
For negative bias operation VCC
pins are typically grounded and a
negative voltage between -4.5 to -
6.5 volts is applied to pin 8 (VEE).
nal to noise ratio is present at the
RF input lead, the prescaler will
operate and provide a divided
output equal the input frequency
divided by the divide modulus.
Under certain "ideal" conditions
where the input is well matched
at the right input frequency, the
component may "self-oscillate",
especially under small signal in-
put powers or with only noise
present at the input This "self-os-
cillation" will produce a undes-
ired output signal also known as
a false trigger. To prevent false
triggers or self-oscillation condi-
tions, apply a 20 to 100 mV DC
offset voltage between the RFin
and RFin ports. This prevents
noise or spurious low level sig-
nals from triggering the divider.
Applicat ions
The HMMC-3102 is designed for
use in high frequency communi-
cations, microwave instrumenta-
tion, and EW radar systems
where low phase-noise PLL con-
trol circuitry or broad-band fre-
quency translation is required.
AC-Coupling and DC-
Blocking
Operat ion
The device is designed to operate
when driven with either a single-
ended or differential sinusoidal
input signal over a 200 MHz to 16
GHz bandwidth. Below 200 MHz
the prescaler input is “slew-rate”
limited, requiring fast rising and
falling edge speeds to properly di-
vide. The device will operate at
frequencies down to DC when
driven with a square-wave.
All RF ports are DC connected
on-chip to the VCC contact
through on-chip 50W resistors.
Under any bias conditions where
VCC is not DC grounded the RF
ports should be AC coupled via
series capacitors mounted on the
PC-board at each RF port. Only
under bias conditions where VCC
is DC grounded (as is typical for
negative bias supply operation)
may the RF ports be direct cou-
pled to adjacent circuitry or in
some cases, such as level shifting
to subsequent stages. In the latter
case the package heat sink may
be "floated" and bias applied as
the difference between VCC and
Adding a 10KW resistor between
the unused RF input to a contact
point at the VEE potential will re-
sult in an offset of » 25mV be-
tween the RF inputs. Note
however, that the input sensitivi-
ty will be reduced slightly due to
the presence of this offset.
Due to the presence of an off-chip
RF-bypass capacitor inside the
package (connected to the VCC
contact on the device), and the
unique design of the device itself,
the component may be biased
from either a single positive or
single negative supply bias. The
backside of the package is not DC
connected to any DC bias point
on the device.
VEE
.
Assembly Not es
Input DC Offset
Independent of the bias applied
to the package, the backside of
If an RF signal with sufficient sig-
V
V
V
CC
CC
CC
IN
IN
OUT
OUT
÷
SOIC8 w/Backside GND
V
EE
Figure 1.
Simplified Schematic
HMMC-3102/rev.3.3
6-55
board contact area equal to or
greater than 2.67 x 1.65 mm
(0.105" x 0.065") with eight 0.020"
diameter plated-wall thermal vias
is recommended.
tors in successful GaAs MMIC
performance and reliability.
the package should always be
connected to both a good RF
ground plane and a good thermal
heat sinking region on the PC-
board to optimize performance.
For single-ended output opera-
tion the unused RF output lead
should be terminated into 50W to
a contact point at the VCC poten-
tial or to RF ground through a DC
blocking capacitor.
Agilent application note #54,
"GaAs MMIC ESD, Die Attach
and Bonding Guidelines" pro-
vides basic information on these
subjects.
.GaAs MMICs are ESD sensitive.
ESD preventive measures must
be employed in all aspects of
storage, handling, and assembly.
Additional References:
PN #18, "HBT Prescaler Evalua-
tion Board."
MMIC ESD precautions, handling
considerations, die attach and
bonding methods are critical fac-
Notes:
A minimum RF and thermal PC
• All dimensions in millimeters.
• Refer to JEDEC Outline MS-012 for
additional tolerances
SYMBOL
MIN.
MAX.
A
A1
B
C
D
E
1.35
0.0
1.75
.25
0.51
.025
5.00
4.00
0.33
0.19
4.80
3.80
e
1.27 BSC
H
L
a
5.80
0.40
0°
6.20
1.27
8°
• Exposed heat slug area on pkg bot-
tom = 2.67 ´ 1.65.
• Exposed heat sink on package bot-
tom must be soldered to PCB rf
ground plane.
Figure 2.
Package & Dimensions
V (+4.5 to +6.5 volts)
CC
~ 1 mf Monoblock
Capacitor
To operate component from a negative supply,
ground each V connection and supply V with
CC
EE
a negative voltage (-4.5 to -6.5v) bypassed to
ground with ~ 1 mf capacitor.
V
RFin
CC
V
RFout
CC
V
RFin
CC
V
EE
RFout
RFout should be terminated in 50W to ground. (DC
blocking capacitor required for positive bias
configuration.)
Exposed heat sink on package bottom must be
soldered to PCB rf ground plane.
Figure 3.
Assembly Diagram
(Single-Supply, positive-bias configuration shown)
6-56
HMMC-3102/rev.3.3
Supplemental Data:
(T =25°C)
A
(V -V =+5 volts, T =25°C)
CC EE
A
100
1
0.0
20
90
-0.2
10
80
-0.4
70
-0.6
0
60
-0.8
50
-1.0
-10
4
0
-1.2
-20
30
-1.4
2
0
-1.6
-30
10
0
-1.8
-2.0
-40
0
2
4
6
8
10 12 14 16 18 20
0
1
2
3
4
5
6
7
8
9
V - V (volts)
Input Frequency,
¦
(GHz)
in
CC EE
Figure 4.
Typical Input Sensitivity Window
Figure 5.
Typical Supply Current & V
Logic
vs. Supply Voltage
(Low Pout Mode, Tr=~ 70 pS,
Output Freq:882 MHz, TA = 25°C)
(V - V = +5 volts, TA=25°C)
CC EE
8
6
4
2
0
-2
-4
-6
-8
0
1
2
3
4
5
6
7
8
Output Frequency (GHz)
Period (200 pS / div.)
Figure 6.
Typical Output Voltage Waveform
Figure 7.
Typical Output Power vs.
Output Frequency, ¦ out (GHz)
P =0 dBm, Fcarrier=6.0 GHz
(V -V +5 volts, P =0 dBm,T =25°C)
in
CC EE
in
A
0
-3
-23
-10
-20
-30
-43
Unterminated RFout Port
-63
-40
-83
-50
-103
-123
-143
-163
-60
Both RFout Ports Terminated
-70
-80
-90
-100
0
2
4
6
8
10 12 14 16 18 20
1K
100
10
100K
10K
1M 10M
Input Frequency, ¦ in (GHz)
Offset From Carrier (Hz)
Figure 8.
Typical Phase Noise Performance
Figure 9.
Typical HMMC-3102
"Spitback" Power
HMMC-3102/rev.3.3
6-57
Device Orientation
Reel
Tape
User
Feed
Direction
Cover Tape
Tape Dimensions and Product Orientation
2.0 0.05
See Note 6
1.5+0.1/-0.0
4.0
See Note 1
A
0.30 0.05
1.75
R0.3 MAX.
5.5 0.05
See Note 6
12.0 0.3
Bo
Ao
R0.5 Typical
Ko
1.5 MIN
SECTION A-A
A
Ao = 6.4mm
Bo = 5.2 mm
Ko = 2.1 mm
8.0
Notes:
1. 10 sprocket hole pitch cumulative tolerance: 0.2mm.
2. Camber not to exceed 1mm in 100mm.
3. Material: Black Conductive Advantek Polystyrene.
4. Ao and Bo measured on a plane 0.3mm above the bottom of the
pocket.
5. Ko measured from a plane on the inside bottom of the pocket to the
top surface of the carrier.
6. Pocket position relative to sprocket hole measured as true position
of pocket, not pocket hole.
This dat a sheet cont ains a variet y of typical and guarant eed performance dat a. The informat ion supplied should not be int erpret ed as a com-
plet e list of circuit specificat ions. In t his dat a sheet t he t erm typica l refers t o t he 50t h percent ile performance. For addit ional informat ion
cont act your local Agilent Technologies sales represent at ive.
6-58
HMMC-3102/rev.3.3
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