INA-12063-BLK [AGILENT]
1.5 GHz Low Noise Self-Biased Transistor Amplifier; 1.5 GHz的低噪声自偏置晶体管放大器
| 型号： | INA-12063-BLK |
| 厂家： | 
AGILENT TECHNOLOGIES, LTD. |
| 描述： | 1.5 GHz Low Noise Self-Biased Transistor Amplifier |
| 文件： | 总24页 (文件大小：347K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
1.5 GHz Low Noise Self-Biased
Transistor Amplifier
Technical Data
INA-12063
Surface Mount Package
SOT-363 (SC-70)
Description
Features
Hewlett-Packard’s INA-12063 is a
Silicon monolithic self-biased
transistor amplifier that offers
excellent gain and noise figure for
applications to 1.5 GHz. Packaged
in an ultra-miniature SOT-363
package, it requires half the board
space of a SOT-143 package.
• Integrated, Active Bias
Circuit
• Single Positive Supply
Voltage (1.5 – 5V)
• Current Adjustable, 1 to
10mA
• 2 dB Noise Figure at
900 MHz
Pin Connections and
Package Marking
The INA-12063 is a unique RFIC
that combines the performance
flexibility of a discrete transistor
with the simplicity of using an
integrated circuit. Using a pat-
ented bias circuit, the perfor-
mance and operating current of
the INA-12063 can be adjusted
over the 1 to 10 mA range.
• 16 dB Gain at 900 MHz
25 dB Gain at 100 MHz
RF OUTPUT
I
1
6
and V
bias
C
Applications
GND 2 2
5 GND 1
• Amplifier Applications for
Cellular, Cordless, Special
Mobile Radio, PCS, ISM,
and Wireless LAN
RF INPUT 3
4 V
d
Note:
Applications
The INA-12063 is fabricated using
Package marking provides orientation
and identification.
HP’s 30 GHz f
ISOSAT™
MAX
Equivalent Circuit
(Simplified)
Silicon bipolar process which
uses nitride self-alignment
submicrometer lithography,
trench isolation, ion implantation,
gold metalization, and polyimide
intermetal dielectric and scratch
protection to achieve superior
performance, uniformity, and
reliability.
V
d
ACTIVE
BIAS
CIRCUIT
GND 2
I
bias
RF
OUTPUT
and V
RF
c
INPUT
RF
FEEDBACK
NETWORK
GND 1
6-116
5965-5365E
INA-12063 Absolute Maximum Ratings
Thermal Resistance[2]:
Absolute
Symbol
Parameter
Units
V
Maximum[1]
θj-c=170°C/W
Notes:
Vd
Vc
Supply Voltage, to Ground
Collector Voltage
7
1. Operation of this device above any
one of these limits may cause
permanent damage.
2. TC = 25°C (TC is defined to be the
temperature at the package pins
where contact is made to the
circuit board).
V
7
15
Ic
Collector Current
mA
dBm
°C
Pin
Tj
CW RF Input Power
Junction Temperature
Storage Temperature
13
150
TSTG
°C
-65to150
Electrical Specifications, TC = 25°C, Vd = 3 V, unless noted
Symbol
Parameters and Test Conditions
Units Min. Typ. Max. Std.Dev.[3]
GP
PowerGain(|S21|2)
Noise Figure
f=900MHz[1] dB
14.5
16
19
0.36
f=250MHz[2]
NF
P1dB
IP3
f=900MHz[1] dB
f=250MHz[2]
2.0
5.0
2.6
0.2
Output Power at 1 dB Gain Compression f=900MHz[1] dBm
f=250MHz[2]
0
-7
Third Order Intercept Point
f=900MHz[1] dBm
f=250MHz[2]
15
2
Idd
Device Current[4]
900MHzLNA[1] mA
250MHzIFAmp[2]
5
1.5
7
0.6
Notes:
1. See Test Circuit in Figure 32.
2. See Test Circuit in Figure 33.
3. Standard deviation number is based on measurement of at least 500 parts from three non-consecutive wafer lots during
the initial characterization of this product, and is intended to be used as an estimate for distribution of the typical
specification.
4. Idd is the total current into Pins 1, 4, and 6 of the device, i.e. Idd = Ic + Ibias + Id.
6-117
INA-12063 Typical Performance, 900 MHz LNA (900 MHz Test Circuit, see Figure 32)
TC = 25°C, ZO = 50 Ω, Vd = 3 V, IC = 5 mA, unless noted
20
15
10
5
0
0
-5
-5
-10
-10
0
-15
-20
-15
-20
-5
-10
0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9
0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9
0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9
FREQUENCY (GHz)
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 1. Gain vs. Frequency.
Figure 2. Input Return Loss vs.
Frequency.
Figure 3. Output Return Loss vs.
Frequency.
17.2
2.7
4
TA = +85°C
TA = +25°C
TA = –40°C
TA = +85°C
TA = +25°C
TA = –40°C
+85°C
16.8
3
2.45
16.4
2
16.0
15.6
2.2
1
0
+25°C
1.95
15.2
14.8
-1
-2
–40°C
1.7
1
1
2
3
4
5
2
3
4
5
1
2
3
4
5
V
(V)
V
(V)
V (V)
d
d
d
Figure 4. Gain at 900 MHz vs. Voltage
and Temperature.
Figure 5. Noise Figure at 900 MHz vs.
Voltage and Temperature.
Figure 6. Output P
at 900 MHz vs.
1dB
Voltage and Temperature.
10
9
6
3
TA = +85°C
TA = +25°C
TA = –40°C
8
6
4
2
0
0
-3
-6
0
1
2
3
4
5
2
4
6
8
10
V
(V)
DEVICE CURRENT (mA)
d
Figure 7. Supply Current vs. Voltage
and Temperature.
Figure 8. Output P1 dB at 900MHz vs.
Device Current for Vd = 3 V.
6-118
INA-12063 Typical Scattering Parameters[1], IC = 1.5 mA
TC = 25°C,ZO =50Ω,Vd = 3.0V
Freq.
GHz
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2.0
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
3.0
S11
Ang.
S21
Mag.
4.26
4.20
4.11
4.00
3.83
3.69
3.49
3.32
3.18
3.03
2.89
2.72
2.64
2.54
2.43
2.33
2.23
2.15
2.08
1.99
1.93
1.83
1.82
1.72
1.70
1.65
1.60
1.54
1.50
1.49
S12
Mag.
0.01
0.02
0.02
0.03
0.04
0.04
0.05
0.05
0.05
0.06
0.06
0.06
0.06
0.07
0.07
0.07
0.07
0.07
0.07
0.08
0.08
0.08
0.08
0.08
0.08
0.08
0.09
0.09
0.09
0.09
S22
Mag.
0.93
0.92
0.90
0.89
0.83
0.79
0.75
0.72
0.69
0.65
0.61
0.59
0.55
0.52
0.49
0.47
0.44
0.42
0.40
0.38
0.36
0.34
0.31
0.31
0.29
0.28
0.27
0.25
0.23
0.24
dB
12.6
12.5
12.3
12.0
11.7
11.3
10.9
10.4
10.1
9.6
9.2
8.7
8.4
8.1
7.7
7.3
7.0
6.6
6.4
6.0
5.7
5.3
5.2
4.7
4.6
4.3
4.1
3.7
3.5
3.5
Ang.
172
164
157
149
141
135
128
122
116
111
106
102
97
92
88
84
80
77
73
69
66
dB
Ang.
86
79
73
69
64
60
56
53
50
47
45
43
41
40
38
36
35
35
34
33
32
29
30
29
31
30
29
27
24
28
Mag.
0.99
0.99
0.98
0.96
0.94
0.93
0.91
0.89
0.87
0.86
0.84
0.83
0.82
0.81
0.80
0.79
0.78
0.77
0.77
0.76
0.75
0.74
0.74
0.73
0.73
0.73
0.72
0.71
0.70
0.71
Ang.
-3
-7
-8
-16
-24
-32
-38
-45
-52
-58
-64
-69
-74
-80
-84
-89
-94
-98
-103
-107
-112
-116
-120
-124
-129
-133
-137
-144
-149
-154
-156
-162
-42.2
-36.2
-32.8
-30.5
-29.1
-27.9
-26.8
-26.1
-25.5
-24.9
-24.5
-24.2
-23.9
-23.6
-23.3
-23.2
-22.9
-22.9
-22.5
-22.3
-22.1
-22.0
-21.9
-22.0
-21.7
-21.4
-21.0
-20.7
-20.9
-21.0
-10
-13
-16
-19
-21
-23
-26
-28
-30
-32
-34
-35
-37
-39
-40
-42
-44
-45
-47
-49
-51
-52
-54
-56
-58
-60
-61
-63
63
59
57
54
50
47
44
41
39
Note:
1. Reference plane per Figure 31 in Applications Information section.
30
25
20
15
10
Typical Noise Parameters@ 900 MHz, IC = 1.5 mA
Fmin (dB)
Γopt Mag.
Γopt Ang.
RN (Ω)
1.4
0.6
36
23
MSG
MAG
2
|S
|
21
5
0
0.1
0.9
1.7
2.5
FREQUENCY (GHz)
6-119
INA-12063 Typical Scattering Parameters[1], IC = 2.5 mA
TC = 25°C,ZO =50Ω,Vd = 3.0V
Freq.
GHz
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2.0
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
3.0
S11
Ang.
S21
Mag.
6.33
6.19
5.98
5.74
5.37
5.07
4.73
4.43
4.18
3.93
3.71
3.47
3.31
3.15
2.98
2.84
2.72
2.60
2.51
2.40
2.31
2.20
2.15
2.05
2.01
1.95
1.89
1.81
1.75
1.75
S12
Mag.
0.01
0.02
0.02
0.03
0.03
0.04
0.04
0.05
0.05
0.05
0.06
0.06
0.06
0.06
0.07
0.07
0.07
0.07
0.07
0.08
0.08
0.08
0.08
0.08
0.09
0.09
0.10
0.10
0.10
0.10
S22
Mag.
0.90
0.88
0.85
0.82
0.76
0.71
0.67
0.62
0.59
0.54
0.51
0.49
0.45
0.42
0.39
0.37
0.35
0.33
0.31
0.29
0.27
0.25
0.24
0.23
0.22
0.20
0.19
0.18
0.16
0.17
dB
16.0
15.8
15.5
15.2
14.6
14.1
13.5
12.9
12.4
11.9
11.4
10.8
10.4
10.0
9.5
9.1
8.7
8.3
8.0
7.6
7.3
6.8
6.6
Ang.
171
161
153
144
135
128
122
116
110
104
100
95
91
87
83
79
76
72
69
66
dB
Ang.
87
79
73
68
62
59
55
53
51
49
48
46
44
44
42
41
40
41
40
40
38
36
36
36
38
36
35
32
29
32
Mag.
0.99
0.98
0.96
0.94
0.91
0.90
0.87
0.85
0.83
0.82
0.80
0.79
0.77
0.76
0.76
0.74
0.73
0.73
0.72
0.72
0.72
0.71
0.70
0.69
0.69
0.69
0.68
0.68
0.66
0.68
Ang.
-4
-8
-10
-18
-27
-35
-42
-49
-56
-62
-67
-72
-76
-81
-84
-89
-93
-96
-100
-104
-108
-112
-115
-119
-122
-126
-131
-136
-142
-145
-146
-153
-42.2
-36.2
-33.2
-31.1
-29.6
-28.4
-27.5
-26.6
-26.1
-25.6
-25.1
-24.8
-24.5
-24.1
-23.6
-23.5
-23.3
-23.0
-22.5
-22.2
-22.0
-21.8
-21.6
-21.7
-21.2
-20.7
-20.4
-20.0
-20.2
-20.1
-11
-15
-18
-20
-23
-25
-27
-29
-30
-32
-34
-35
-37
-39
-40
-42
-43
-45
-47
-49
-50
-52
-53
-55
-57
-60
-60
-62
62
59
56
54
51
48
45
42
6.2
6.1
5.8
5.5
5.2
4.9
4.8
39
37
Note:
1. Reference plane per Figure 31 in Applications Information section.
30
25
20
15
10
Typical Noise Parameters@ 900 MHz, IC = 2.5 mA
Fmin (dB)
Γopt Mag.
Γopt Ang.
RN (Ω)
1.5
0.54
36
20
MSG
MAG
2
|S
|
21
5
0
0.1
0.9
1.7
2.5
FREQUENCY (GHz)
6-120
INA-12063 Typical Scattering Parameters[1], IC = 5 mA
TC = 25°C,ZO =50Ω,Vd = 3.0V
Freq.
GHz
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2.0
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
3.0
S11
Ang.
S21
Mag.
9.56
9.18
8.65
8.07
7.34
6.75
6.18
5.68
5.26
4.88
4.55
4.24
3.99
3.76
3.55
3.37
3.21
3.05
2.93
2.81
2.67
2.55
2.47
2.37
2.31
2.24
2.17
2.08
2.02
2.00
S12
Mag.
0.01
0.01
0.02
0.03
0.03
0.04
0.04
0.04
0.04
0.05
0.05
0.05
0.06
0.06
0.06
0.07
0.07
0.07
0.08
0.08
0.08
0.09
0.09
0.09
0.09
0.10
0.11
0.11
0.11
0.11
S22
Mag.
0.86
0.82
0.78
0.73
0.65
0.59
0.55
0.50
0.46
0.43
0.40
0.37
0.35
0.33
0.30
0.28
0.27
0.25
0.23
0.22
0.20
0.18
0.17
0.17
0.15
0.14
0.13
0.12
0.11
0.11
dB
19.6
19.3
18.7
18.1
17.3
16.6
15.8
15.1
14.4
13.8
13.2
12.6
12.0
11.5
11.0
10.5
10.1
9.7
9.3
9.0
8.5
8.1
7.8
7.5
7.3
7.0
Ang.
168
157
146
137
128
120
114
108
103
97
93
89
85
81
78
75
71
68
64
61
58
56
53
51
48
45
42
39
37
35
dB
Ang.
79
73
71
68
62
61
59
56
55
52
52
52
51
50
48
48
47
48
46
45
43
41
41
41
42
40
39
36
33
35
Mag.
0.98
0.96
0.93
0.90
0.86
0.85
0.82
0.80
0.78
0.77
0.74
0.74
0.72
0.72
0.71
0.70
0.69
0.69
0.69
0.68
0.67
0.67
0.66
0.66
0.65
0.66
0.64
0.63
0.62
0.64
Ang.
-5
-11
-22
-31
-40
-46
-53
-59
-64
-68
-72
-76
-79
-81
-85
-87
-90
-94
-42.2
-36.8
-33.8
-31.7
-30.4
-28.7
-28.0
-27.2
-26.9
-26.3
-25.8
-25.3
-24.8
-24.3
-23.9
-23.5
-23.2
-22.9
-22.2
-22.0
-21.6
-21.3
-21.1
-20.8
-20.5
-20.0
-19.6
-19.3
-19.3
-19.3
-10
-13
-17
-20
-22
-24
-26
-27
-29
-30
-32
-34
-35
-36
-38
-39
-41
-42
-44
-45
-48
-50
-51
-53
-55
-56
-59
-59
-61
-95
-99
-101
-104
-104
-107
-109
-114
-118
-123
-125
-126
-133
6.7
6.4
6.1
6.0
Note:
1. Reference plane per Figure 31 in Applications Information section.
30
Typical Noise Parameters@ 900 MHz, IC = 5 mA
Fmin (dB)
Γopt Mag.
Γopt Ang.
RN (Ω)
25
20
15
10
1.8
0.41
38
16
MSG
MAG
2
|S
|
21
5
0
0.1
0.9
1.7
2.5
FREQUENCY (GHz)
6-121
INA-12063 Typical Scattering Parameters[1], IC = 8 mA
TC = 25°C,ZO =50Ω,Vd = 3.0V
Freq.
GHz
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2.0
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
3.0
S11
Ang.
S21
Mag.
12.97
12.17
11.10
10.06
8.89
8.00
7.20
6.56
6.02
5.53
5.08
4.72
4.40
4.18
3.86
3.71
3.48
3.34
3.14
3.01
2.89
2.77
2.68
2.59
2.51
2.42
2.32
2.25
2.17
2.18
S12
Mag.
0.01
0.01
0.02
0.02
0.03
0.03
0.04
0.04
0.05
0.05
0.05
0.05
0.06
0.06
0.07
0.07
0.07
0.07
0.08
0.08
0.09
0.09
0.09
0.09
0.10
0.11
0.11
0.12
0.12
0.12
S22
Mag.
0.80
0.76
0.69
0.63
0.55
0.50
0.45
0.41
0.37
0.34
0.32
0.30
0.28
0.26
0.24
0.23
0.21
0.20
0.19
0.17
0.17
0.15
0.14
0.14
0.13
0.12
0.11
0.10
0.10
0.09
dB
22.3
21.7
20.9
20.1
19.0
18.1
17.1
16.3
15.6
14.9
14.1
13.5
12.9
12.4
11.7
11.4
10.8
10.5
9.9
Ang.
166
152
141
130
121
114
107
102
97
92
88
84
81
77
74
71
68
65
62
59
56
53
51
48
47
43
40
37
36
dB
Ang.
73
72
75
69
64
64
59
59
58
58
57
56
55
53
53
52
52
51
50
48
47
44
43
43
43
42
41
38
34
35
Mag.
0.98
0.94
0.90
0.86
0.83
0.80
0.77
0.76
0.73
0.71
0.71
0.70
0.69
0.68
0.67
0.65
0.66
0.66
0.67
0.66
0.64
0.63
0.64
0.64
0.63
0.61
0.61
0.61
0.58
0.61
Ang.
-5
-13
-24
-35
-44
-49
-55
-59
-64
-67
-69
-72
-76
-76
-79
-82
-81
-84
-85
-89
-88
-91
-91
-93
-94
-98
-102
-103
-107
-101
-110
-41.9
-37.4
-33.9
-32.2
-30.6
-29.6
-28.9
-28.0
-26.9
-26.5
-25.9
-25.4
-24.7
-24.1
-23.5
-23.4
-22.8
-22.7
-22.0
-21.5
-21.2
-21.0
-20.6
-20.4
-19.9
-19.5
-19.0
-18.6
-18.7
-18.7
-11
-15
-18
-21
-23
-24
-25
-26
-29
-30
-31
-33
-34
-36
-38
-39
-41
-42
-44
-45
-47
-49
-49
-51
-53
-56
-58
-60
-60
9.6
9.2
8.8
8.6
8.3
8.0
7.7
7.3
7.1
6.7
6.8
34
Note:
1. Reference plane per Figure 31 in Applications Information section.
30
25
20
15
10
Typical Noise Parameters@ 900 MHz, IC = 8 mA
Fmin (dB)
Γopt Mag.
Γopt Ang.
RN (Ω)
2.0
0.30
41
15
MSG
MAG
2
|S
21
|
5
0
0.1
0.9
1.7
2.5
FREQUENCY (GHz)
6-122
configuration is of the type often
implemented in discrete transis-
tor designs for the purpose of
improving stability and bringing
the optimum noise match at the
input of the transistor closer to
50 Ω. The result is that for many
applications, a simple, series
inductor is often all that is needed
to adequately match the input of
theINA-12063to50Ω.
Description
INA-12063 Applications
Information
The active bias circuit solves
three problems normally encoun-
tered with traditional approaches
for biasing discrete transistors.
First, as an active bias circuit, the
emitter of the RF transistor is DC
grounded. This permits the
collector current to be controlled
without the need for resistors
and/or bypass capacitors in the
emitter that may degrade RF
performance.
Introduction
The INA-12063 is a unique RFIC
configuration that combines the
performance flexibility of a
discrete transistor with the
simplicity of using an integrated
circuit.
The INA-12063 is an integrated
circuit that combines three
In contrast to amplifiers that use
resistive feedback to achieve
broadband 50 Ω input and output
matches, the INA-12063 leaves
the designer with the flexibility of
optimizing performance for a
particular frequency band. For
example, frequency selective
input and output impedance
matching circuits can be used to
tune for optimum NF, maximum
output power, low input VSWR,
or to tailor the passband response
to eliminate undesirable gain
responses.
functions: (1) a silicon bipolar RF
transistor, (2) an RF feedback
Second, the internal bias circuit
greatly simplifies the design tasks
commonly associated with bias-
ing transistors, such as accurately
regulating the collector current,
allowing for variations in h
making a non-intrusive DC
connection to the base of the
[1]
network, and (3) a patented
bias regulation circuit. A simpli-
fied schematic diagram of the
INA-12063 is shown in Figure 9.
The result is a versatile gain stage
that can be operated from a single
+1.5 to +5 volt power supply with
the device current set by the user.
,
FE
transistor, and stabilizing current
over temperature.
The INA-12063 is designed for use
in battery powered equipment
demanding high performance
with low supply voltages and
minimal current drain. Typical
applications for the INA-12063
include low noise RF amplifiers,
IF amplifiers, gain and buffer
stages through 2 GHz. The
INA-12063 is an excellent choice
for use in cellular and cordless
telephones, PCS, W/LAN’s, RF
modems and other commercial
wireless equipment.
And, third, the integrated bias
circuit eliminates the cost, parts
count, and associated PCB space
required for as many as 8 addi-
tional DC components.
Setting the Bias Current
The integrated, active bias circuit
is a 10:1 current mirror. The
current mirror forces the collec-
tor current in the RF transistor to
be approximately 10 times the
The integrated bias control circuit
is very easy to use. For most
applications, the collector current
for the RF transistor can be set
with a single resistor.
current supplied to the I
pin.
bias
In normal use, a voltage between
+1.5and+5volts,isappliedto
The geometry of the integrated
RF transistor is designed to
provide an excellent balance
between low noise figure, high
gain, and good dynamic range
while retaining practical imped-
ance matching levels. The operat-
ing current is typically in the 1 to
10 mA range.
both the V and V terminals of
d
c
V
d
the INA-12063. Although normally
connected to the same supply
voltage, it is not necessary that
ACTIVE
BIAS
CIRCUIT
GND 2
I
bias
RF
both V and V be at the same
d
c
TRANSISTOR
RF
OUTPUT
and V
voltage.
RF
c
INPUT
RF
The collector current of the RF
transistor is then set by injecting
a small control current into the
FEEDBACK
NETWORK
TheintegratedRFfeedback
contains an inductive element in
the emitter circuit of the RF
transistor. This series feedback
GND 1
I
pin that is approximately
bias
Figure 9. INA-12063 Schematic.
1/10 of the desired collector
current.
1 U.S.PatentNumber5436595
6-123
While there are any number of
means of supplying the I
control current, the simplest way
is to merely place a resistor
The following “10-step” program
is suggested as the design se-
quence:
Step 2. Choose Bias
Conditions
The second step of the design
process is to choose the bias
conditions, i.e., the RF transistor
bias
between the V and I
termi-
1. Determine performance goals.
2. Select the bias condition.
3. Choose PCB material.
4. Check stability.
5. Determine required DC
connections.
6. Design the input impedance
matching network.
7. Design the output impedance
matching network.
d
bias
nals, shown as “R ” in
operating voltage (V ) and
bias
c
Figure 10. R
will be suffi-
current (I ). The bias conditions
bias
c
ciently high to act as a current
are chosen at this step in the
design sequence since many of
the RF design characteristics
(e.g., S-parameters and noise
parameters) are dependent on
current and/or voltage.
source. The value for R
calculated as follows:
is
bias
V – 0.8
d
R
= 10
(1)
bias
(
)
I
c
where V is the device voltage, I
d
c
is the desired collector current,
8. Layout the printed circuit
board.
9. Computer optimization and
performance verification.
10. Fabricate, assemble, and test.
The choice of bias voltage is often
preemptive as it is normally fixed
by available system resources,
such as a battery voltage or
system power supply. The
INA-12063 will operate from
supply voltages from 1.5 to
5 volts,with+3voltsconsidered
to be the typical operating
voltage.
and R
is the value of the bias
bias
determining resistor. For ex-
ample, for a desired collector
current of 1.5 mA and a power
supply of 2.7 volts, the value of
R
bias
would be 12.7 KΩ.
Each of these steps in the design
sequence will now be discussed
in the following sections.
PowerDown
A power-down function for the
INA-12063 can be conveniently
implemented by switching the
Step 1. Establish Performance
Goals
Although noise figure and gain
are somewhat insensitive to
device voltage as an independent
variable, some increase in output
power can be realized with higher
device voltages.
The first step in the design of an
INA-12063 amplifier stage is to
establish performance goals. It
may be necessary to consider
performance tradeoffs between
some amplifier parameters, such
as Noise Figure, Input VSWR,
Gain, Output Power, Output
VSWR, Stability, and DC power
consumption.
I
current. This method has the
bias
advantage of switching only a
very small current since I is
bias
typically only a fraction of a mA.
V
d
SUPPLY
R
bias
VOLTAGE
The bias current has the greatest
effect on RF performance and the
following tradeoffs should be
considered:
GND 2
ACTIVE
BIAS
CIRCUIT
BIAS
ISOLATION
I
bias
V
c
RF
TRANSISTOR
RF OUTPUT
I
c
RF
INPUT
RF
FEEDBACK
CIRCUIT
Some of these parameters are
counterposed, for example,
increased output power requires
greater DC power consumption.
The tradeoff decisions may
require consideration of the
choice of DC bias which is
discussed in the next section. The
final design will often be a
balance between system-critical
performance and those param-
eters of lesser significance.
Noise Figure increases with
device current. The data in the
Typical Noise Parameter tables
GND 1
shows an increase in F
of from
min
Figure 10. Single-Resistor Bias
Circuit.
1.4 dB at 1.5 mA of bias current to
2.0 dB at 8 mA.
Amplifier Application
Guidelines
2
Gain–Transducergain,|S | ,
21
increases significantly in propor-
tion to device current.
This section describes the general
approach for designing amplifiers
using the INA-12063. This is a
generic design approach and is
applicable for most low noise RF
or IF amplifiers or for general
purpose gain and buffer stages.
Output Power – One of the
benefits of increased device
current is greater output power. A
typical increase in current from
1.5 to 8 mA results in a corre-
6-124
sponding increase in P
-5.2 dBmto+4.6dBm.Thedata
sheet curve in Figure 8 character-
of
can result in performance degra-
dation or reduced stability.
Pin 5 of the package is the critical
connection for “RF” grounding. A
typical RF path to ground con-
sists of a short length of transmis-
sion line terminated in one or
more ground vias. (The length of
the PCB pad between the
INA-12063 ground pin and the
ground should be modeled as a
microstripline (“MLIN” in Touch-
stone), and the plated through
ground holes as “VIA” elements.)
1dB
izes the P
- I tradeoff.
c
Dielectric loss is not a significant
factor for the moderate frequency
ranges over which the INA-12063
is normally used. Low loss, low
dielectric constant “microwave”
type materials are usually
1dB
Impedance Match – While it is
not a parameter per se, the
degree of difficulty of impedance
match may also be a consider-
ation in the selection of bias
current. Generally, the higher the
device current, the less “severe”
reserved for applications
demanding the very lowest noise
figures (minimum circuit loss)
and/or for frequencies above
2 GHz.
the impedance match, i.e., Γ
,
opt
Γ
, Γ are all closer to 50 Ω.
ms ml
When evaluating stability, it is a
good practice to calculate K and
B1 over the full frequency range
for which S-parameters are
available. The reason for this is
that even though K and B1 may
indicate stability over the fre-
quency band of interest, the
Step 3. Selection of PCB
Material
If the selection of PCB material
has not been preordained by
other factors (e.g., system stan-
dards) then it should be chosen at
this stage of the design process.
The printed circuit board material
is chosen at this step since it will
have an effect on the next step of
the stability analysis and on the
subsequent design of the imped-
ance matching networks.
An overall good choice for most
low cost wireless applications
using devices such as the
INA-12063 is a fiberglass-epoxy
material such as FR-4 or G-10
with a thickness in the range of
0.020to0.031inches.
possibility exists for a circuit to
oscillate at frequencies that are
far outside of the band of interest.
Step 4. Stability Analysis
A stability analysis is the next
step in the design process. The
purpose of this step is to examine
the circuit’s tendency to oscillate.
A linear CAD program, such as
Hewlett-Packard’sTouchstone
should be used to calculate the
stability factor, K, and stability
measure, B1. The factors K and
B1 are both derived from the
S-parameters for the INA-12063 at
the previously established bias
voltage and current. The condi-
tions for unconditional stability
are:
While unconditional stability
requires a positive, non-zero
value of B1, most of the following
stability analysis will focus on the
K factor since the value of K
indicates the degree of stability.
What should the minimum value
of K be to ensure stability? While
K=1.001isstable, somemarginis
prudent to allow for component
tolerances, temperature effects,
and manufacturing variations.
Typical rules of thumb suggest
that K should be at least 1.2 to
1.5.
Key factors to consider in the
selection of board material are
dielectric constant, RF loss
characteristics, board thickness,
and cost.
The dielectric constant and board
thickness together contribute to
the physical geometry of the
circuit, an important consider-
ation for miniaturization. Higher
dielectric constant material
enables the construction of more
compact circuits since the
K>1andB1>0
While a simple analysis based
only on the S-parameters is often
adequate at this point, a slightly
more rigorous analysis is recom-
mended that includes the para-
sitic elements in the device’s path
to ground. At this stage in the
design, a reasonable estimation
(guess) of this electrical path and
the construction of the ground
vias are adequate. For the
There are three possible cases
resulting from the CAD analysis:
physical dimensions of transmis-
sion lines are smaller.
• Case 1 – K>1 over the entire
frequency range.
• Case 2 – K>1 within the band
of interest and K<1 for some
frequencies outside of the
band of interest.
In addition to transmission line
widths, PCB board thickness also
influences the quality of ground
vias. Ground vias in excessively
thick PCBs result in high induc-
tance paths to ground. For some
active devices, poor grounding
• Case 3 – K<1 within the band
of interest.
INA-12063, bear in mind that
6-125
If the CAD analysis indicates
there is a potential instability
issue (K < 1 and/or B1 ≤ 0 for any
frequency) as in Case 2 or Case 3
above, then some stability
lossless feedback technique is not
suggested for most INA-12063
amplifier applications since this
method adds considerable design
complexity as well as additional
parts count and board space to
the circuit.
into the device may preclude the
use of the series configuration.
Shunt resistance is usually the
most straightforward solution to
implement since it can be easily
bypassed to ground with a
capacitor without disturbing the
bias.
countermeasures will be needed.
There are four basic techniques
for handling potential instability:
(d) Resistive loading. Resistive
loading can be used at either the
input or output of the INA-12063
to create an unconditionally
stable amplifier. This is the brute-
force method of ensuring stabil-
ity. It is fairly fail-safe and is also
the simplest to implement. The
addition of a resistive element to
either the amplifier input or
output creates RF loss which
manifests itself as lower gain plus
either increased NF (if the
For gain or buffer stages requir-
ing maximum output power, the
loading is applied to the amplifier
input. If the performance goal is
low noise figure, the resistive
loading is implemented on the
output side of the INA-12063 as
shown in Figure 11.
(a) Live with it. If the source and
load impedances that will be
presented to the amplifier are
well defined, the finesse
approach of using stability circles
may be used. Stability circles
(calculated by a program such as
Touchstone) are plotted on a
Smith chart and define regions of
loads that could cause a circuit to
oscillate. An amplifier is safe
from oscillation if the expected
amplifier terminations lie well
outside of the unstable regions on
both the input and output imped-
ance planes. Since the possibility
of oscillation could exist at any
frequency for which the
RF
INPUT
RF
OUTPUT
INA-12063
STABILIZING
RESISTOR
resistance is added to the input)
or lower output power (if the
resistance is placed at the
output.)
Figure 11. Shunt Stabilizing Resistor
for LNA.
In keeping with the goals of low
cost (i.e., circuit simplicity), the
resistive loading method is the
technique suggested for produc-
ing an unconditionally stable
amplifier for most applications of
theINA-12063.
A simple manual optimization
may be used to determine a
starting value for the stabilizing
resistor. By adding a shunt
resistor to the output of the
INA-12063 in the circuit file used
in the previous stability analysis,
K may be observed while adjust-
ing the value of the resistor. The
shunt resistor should be the
highest value that will adequately
stabilize the circuit.
INA-12063hasgain, stability
circles must be checked at
frequencies over a wide
frequency range when this
method is used.
(b) Resistive feedback. The use of
resistive feedback is often used to
create stable, wideband, amplifi-
ers. While effective in stabilizing
active devices, this method will
not be considered here since a
significant penalty is often paid in
degraded NF, less gain, and
lowered output power
The resistive loading can be
applied in either series or shunt
and can be added to either the
input or output of the amplifier.
The choice of series or shunt
resistive load may be dictated by
whether the real part of the
output impedance of the amplifier
device is greater or less than
50 Ω. The logical choice is to use
a shunt resistor when the ampli-
fierimpedanceis>50 Ωanda
series resistor for the case of
>50 Ω.Thistechniquewillbring
the overall impedance closer to
50 Ω, thussimplifyingthematch.
In some cases, excessive voltage
drop across the stabilizing
The three possible cases resulting
from the stability analysis will
now be considered.
performance.
Case 1 (K>1 over the entire
frequency range) is always the
hoped for situation since it is the
easiest to deal with. If K is greater
than unity by a comfortable
margin, then no further action is
needed at this point.
(c) Lossless feedback. Reactive
feedback elements can also be
used to stabilize amplifiers. The
INA-12063alreadyincorporates
one type of reactive feedback in
the emitter of the RF transistor,
with a resulting improvement in
stability. Further use of the
resistor due to the DC current
6-126
Case 2 (K>1 within the band of
interest; K<1 for some frequen-
cies outside of the band of
interest ) is the next simplest case
to handle. Since K>1 in the band
of interest, little or no perfor-
mance tradeoffs may be needed
to make the amplifier uncondi-
tionally stable.
One of the advantages of the
active bias circuit in the
Γ
can be calculated using the
opt
same CAD circuit file used in the
stability analysis in Step 4 above.
This method is slightly more
accurate since it takes the
feedback effects of device
grounding and stabilization
components into account.
INA-12063 is that there is no need
for an external DC bias connec-
tion to the RF Input. If desired,
the input may be connected
directly to matching networks
using a series capacitor as the
first element.
If the design goal is to obtain
By using R-C or R-L combina-
tions, frequency selective resis-
tive loading can be applied only
over the frequency range for
which K < 1 in order to stabilize
the amplifier without adversely
affecting in-band performance.
Pins 4 and 6 are connected to the
supply voltage and Pins 2 and 5
are DC grounded. Pins 1 and 4
should be bypassed to ground. A
high value resistor from Pin 1 to
Pin 6 is a simple and convenient
method for setting the device
operating current. Pin 3, has an
internal voltage present and is
normally connected to a DC
blocking capacitor. The only DC
connection which could affect RF
performance is that of applying
the supply voltage to the RF
Output pin.
maximum power transfer (maxi-
mum gain/minimum input VSWR),
then the input of the INA-12063 is
matched to Γ . Γ is the source
ms ms
impedance resulting from the
simultaneous conjugate match of
the input and output of the
device. Since Γ is only defined
ms
Case 3 (K<1 in the band of inter-
est) requires tradeoffs in NF or
output power to achieve an uncon-
ditionally stable amplifier stage.
for devices/circuits with K > 1,
the CAD circuit file from design
Step 4, including any stabilizing
resistors, is used to calculate Γ
.
ms
The INA-12063 typically falls into
either Case 2 or Case 3, depending
on the bias current, circuit ground-
ing, and frequency band of interest.
For most communication systems
operating over relatively small
bandwidths, a single frequency
match approach is usually
adequate. As a general rule, the
selection of high pass networks
for the input (and output) match-
ing circuits is desirable to reduce
excess gain at low frequencies.
Step 6. Designing the Input
Match
In all cases, a final check of
The input impedance match is
generally designed to achieve
either of two goals, either lowest
noise figure or maximum power
transfer. The maximum power
transfer match provides maxi-
mum gain and corresponds to
minimum VSWR. In some cases,
noise circles in combination with
constant gain circles are used to
design an intermediate match
point to achieve a compromise in
performance between low noise
figure and low input VSWR.
stability should be done in the
analysis of the completed ampli-
fier design. This is done as part of
Step 9 in the design sequence.
As a final note in the choice of the
input matching structure, the use
of a series C element is possible
at the input of the INA-12063
since the internal bias circuit
obviates the need for an external
DC connection to the input.
Step 5. DC Connections
The DC connections to the
INA-12063 are considerations in
the next two steps in which the
input and output impedance
matching networks are chosen.
The goal is economy of compo-
nents by integrating as many of
the DC connections into the
matching circuits as practical.
For example the use of a series C
in an impedance matching
network could double as a DC
blocking capacitor. Or, a shunt L
can be used to apply the required
supply voltage to the output of
theINA-12063.
The choice of using either lumped
element or distributed (transmis-
sion line) matching elements is
mainly dictated by size and
frequency constraints as well as
by cost considerations. While
distributed elements are “free”
since they are etched onto the
PCB, they usually use more board
space than an equivalent lumped
element (chip) component.
If the design goal is to obtain
lowest NF, the input of the
INA-12063 is matched to the
conjugate of Γ . Γ is the
opt opt
reflection coefficient of the
source termination that results in
F
, the lowest possible device
min
noise figure. Γ design data are
opt
found in the tables of Typical
Noise Parameters. Alternatively
6-127
Before proceeding to the next
step, circuit stability and out-of-
band gain should be re-checked.
Step 8. RF Layout
This layout shows the direct
grounding of Pin 5 (the device RF
ground) which should be con-
nected to ground through as short
a path as practical, unless addi-
tional shunt feedback is desired.
Capacitive bypasses should be
placed on the DC connections at
Pins 1 and 4 to prevent possible
feedback and/or oscillation in the
active bias circuit. Multiple vias
are used to ensure good RF
grounding.
Up to this point, we have com-
pleted the RF electrical design,
the choice of circuit board
material, and the DC circuit. The
next step is to lay out the printed
circuit board. While the layout is
not critical, some precautions
should be considered.
Step 7. Designing the Output
Match
The output of the INA-12063 is
normally matched for maximum
power transfer (maximum gain
and lowest output VSWR.)
Maximum power transfer occurs
when the output is matched to
A recommended PCB pad layout
for the miniature SOT-363 (SC-70)
package used by the INA-12063 is
shown in Figure 12 (dimensions
are in inches). This layout pro-
vides ample allowance for pack-
age placement by automated
the conjugate of Γ . Γ is
ml ml
computed from the same CAD
circuit file as used for determin-
It is recommended that the PCB
pads for the two ground pins not
be connected together. Each
ground pin should have its own
separate path to ground, other-
wise, unintentional feedback
could lead to potential instability
in the RF transistor or internal
bias circuit.
ing Γ in the design of the input
ms
matching network in the previous
step. A typical LNA is matched
assembly equipment without
for Γ at the input and Γ at the
adding parasitics that could impair
the high frequency RF perfor-
mance of the INA-12063. The
layout is shown with a footprint of
a SOT-363 package superimposed
on the PCB pads for reference.
opt
ml
output.
Note: The small signal match for
maximum power transfer should
not be confused with matching
the output of the INA-12063 for
the highest output power. As
output power is increased, the
device becomes nonlinear
Step 9. Final CAD Analysis
and Optimization
0.026
Following the completion of the
amplifier electrical design and
layout, it is advisable to do a final
CAD analysis and circuit optimi-
zation. The analysis at this point
will take into account such things
as component parasitics (e.g.,
series L in chip caps), actual
transmission line dimensions and
interconnections, effects of
ground vias, etc.
resulting in a shift away from the
0.075
Γ
match. While various load
ml
pull types of measurements exist
to determine the optimum
0.035
impedance match for maximum
output power under nonlinear
conditions, these tests are fairly
tedious and an empirical tuning
approach is often more expedient
0.016
Figure 12. PCB Pad Layout for
INA-12063 Package
(dimensions in inches).
to arrive at a solution. The Γ
ml
Starting with the package pad
layout in Figure 12, an RF layout
similar to the one in Figure 13 is
suggested as a starting point for
theINA-12063amplifier.
match may be used as a starting
point in tuning for maximum
output power.
The circuit should be analyzed
over the full range of the provided
S-parameters to re-verify amplifier
stability and ensure well-behaved
out-of-band performance. With
the full circuit parasitics and
losses taken into account, it may
be necessary to adjust the value
of the shunt stabilizing resistor.
The same comments regarding
single frequency match, high pass
networks, and lumped vs. distrib-
uted elements referred to in the
input matching step above are
applicable to the output matching
circuit.
3
4
1
6
The results of this final analysis
and optimization are then used to
make final adjustments to compo-
nent values and the PCB layout as
Once again, out-of-band gain and
stability should be checked.
Figure 13. RF Layout.
6-128
well as to ensure that the perfor-
mance goals in Step 1 will be met.
Optimize:
Minimize output VSWR
Minimize DC power
Accept:
Results of this step:
PCBMaterial:0.031-inchFR-4
Step 10. Build and Test
The final step is to fabricate
circuit boards and assemble
amplifiers for testing and verifica-
tion of performance. Some
adjustment in component values
and transmission lines may be
done at this step to allow for
imperfections in the computer
simulation. This completes the
amplifier design.
4. Evaluate stability. Stability
factor is calculated from the set
of S-parameters closest to the
chosen bias condition, which in
this example is 3 volts and
2.5 mA. For the required accuracy
in the stability analysis, a short
length of transmission line
(0.030-inchlong,0.015-inchwide)
is added to connect the RF
ground pin (Pin 5) of the
Gain
Input VSWR
2. Select bias conditions. For
this example, the supply voltage
is constrained by an assumed
battery supply of 3 volts, leaving
device current as the only remain-
ing bias variable. The current is
selected based on output power
INA-12063toa0.025-inchdiam-
eter ground via.
900 MHz LNA Design Example
As an application example, the
design of a low noise amplifier
stage for 900 MHz using the
INA-12063 will be described. This
amplifier design would be repre-
sentative for use in many low-
cost, battery power receiver
applications such as LNAs for
cellular telephones or 900 MHz
ISM/spread spectrum systems.
which is driven by the IP require-
3
ment. The table of Electrical
Specifications provides a starting
point. Using the typical gain of
16 dB and a difference of 15 dB
Hewlett-Packard’sTouchstone
CAD program was used to
calculate the stability factor (K),
stability measure (B1), and gain
over the full S-parameter fre-
quency range of 0.1 to 3.1 GHz.
The results show a value of K<1
at 900 MHz, corresponding the
“Case 3” situation described in
the stability discussion in design
Step 4 above. To preserve NF,
the stabilizing resistor, R1, shown
in Figure 14, was added from the
output of the INA-12063 to
ground. Since the real part of the
output impedance of the INA-12
is>50 Ω, aresistorintheshunt
configuration is used to move the
overall impedance closer to 50 Ω.
between the output IP and P
,
3
1dB
the design goal of an input 3rd
order intercept point of -10 dBm
is translated to a 1-dB com-
pressed output power require-
ment of -9 dBm. Figure 8 indi-
cates a current of 2.5 mA will
This example will follow the
above design sequence.
meet this P
requirement with
1dB
adequate design margin.
1. Performance goals. As a
receiver front end stage, the
primary design goals for this
example amplifier are: (1) noise
figure less than 2 dB, and, (2) a
Results of this step:
Bias: 3 volts, 2.5 mA
3. Choose PCB material. FR-4
with a thickness of 0.031 inches is
chosen as the printed circuit
board material. FR-4 meets the
requirement of low cost while
providing acceptable low loss
performance at 900 MHz.
input 3rd order intercept (IP )
3
point of at least -10 dBm. Second-
ary goals are low output VSWR
and minimum DC current drain.
The resulting input VSWR and
stage gain will be accepted. Low
cost is always a design goal.
RF
INPUT
RF
OUTPUT
INA-12063
GND 1
(PIN 5)
R1
A thickness of 0.031 inches is
suitable for the miniaturization of
microstriplines and thin enough
to allow for low inductance
ground vias. With a relative
W = 0.015
L = 0.030
Results of this step:
Constrain:
NF≤ 2dB
0.025" DIA.
GROUND VIA
InputIP ≥ -10dBm
dielectric constant (ε ) of 4.8, the
3
r
Low cost
width of a 50 Ω microstripline on
0.031inchFR-4is0.056inches,
which is a convenient size for
mounting chip components.
Figure 14. Stabilizing Resistor on
Output.
6-129
The Touchstone circuit file for
this step is shown in Figure 15.
lowered to 290 Ω. This value
resulted in a K > 1 over the full
frequency range at a trade-off in
gain of 1.7 dB. (The stability
measure criteria, B1 > 0, was also
verified.)
6. Design of the input imped-
ance matching network.
Commensurate with the primary
design objective of low noise
figure, the 50 Ω input to the
DIM
FREQ GHZ
RES OH
LNG IN
CKT
amplifier stage will be matched to
the conjugate of Γ . The value
opt
Results of this step:
of Γ , 0.53 +36°, is found in
MSUB ER=4.8 H=0.031
T=0.001RHO=1RGH=0
opt
the table of Typical Noise Param-
eters for a bias current of 2.5 mA.
(Alternatively, a slightly more
A 290 Ω shunt resistor was added
to the output of the INA-12063 for
stability.
S2P
MLIN 3
1
2
4
0
3
TYP25B.S2P
W=0.015 L=0.030
D1=0.025
VIA
RES
DEF2P
TERM
Z0 = 50
OUT
4
accurate Γ could also have
opt
D2=0.025H=0.031
T=0.001
2
been calculated using the CAD
circuit file in Figure 15, which
includes the RF ground parasitics
and stabilizing resistor.) The
5. Allow for DC connections.
The required DC connections to
be made to this example amplifier
are: +3 volts to the RF Output
0
1
R=600 ! R1
2 INA12
conjugate of Γ , 0.53 −36°, is
opt
and V terminals (Pins 4 & 6), a
d
plotted on the Smith chart as
Point A in Figure 17. Since Point
A is not sufficiently close to the
R=1 or G=1 circles on the Smith
chart, a single series or shunt
element will not provide an exact
match. (For less critical NF
performance, a simple series
inductor would be adequate for
the input match.) A two-element
matching network will therefore
be required.
INA12
INA12
K
B1
suitable bias current into I
(Pin 1), and Pins 2 and 5 to
bias
INA12 DB[S21]
INA12 DB[GMAX]
INA12 MAG[GMN]
INA12 ANG[GMN]
INA12 MAG[GM2]
INA12 ANG[GM2]
ground. The RF Input (Pin 3) and
RF Output should have blocking
capacitors if the amplifier is to be
cascaded with stages that do not
have a DC open circuit.
!
!
!
!
FREQ
SWEEP 0.1 3.1
0.1
To set the INA-12063 operating
currentto2.5mA, a9.1 K Ω
resistor will be connected be-
tween the +3 volt supply and the
Figure 15. CAD File for Stability
Analysis and Conjugate Match.
The value of the shunt resistor,
R1, is varied while observing the
resulting K. While a 600 Ω resistor
is found to stabilize the circuit at
900MHz(K=1.46),therestill
exists a possibility of oscillation
at 100 MHz with the worst case
value of K = 0.72. There are two
options at this point: (a) lower
the value of the shunt resistor,
which trades additional stability
for circuit gain and output power,
or (b) use a frequency selective
circuit to resistive load the device
only at lower frequencies.
I
pin. The DC schematic for
bias
Impedances in this region of the
Smith chart can be matched to
50 Ω by either of two possible L-C
combinations, either a shunt
C-series L or a shunt L-series C.
Normally, the shunt L-series C
would be a good choice since its
high pass filter characteristic
would help roll off excess low
end gain. However, a DC blocking
capacitor would be required
between the INA-12063 and the
matching network. Placing
the LNA is shown in Figure 16.
Figure 16. 900 MHz LNA DC
Schematic.
Results of this step:
extraneous components within
matching network is usually not
recommended. The shunt C-series
L network is therefore chosen as
the input matching topology.
The DC connections were identi-
fied and will be considered in
choosing the input & output
matching circuits.
In the interest of circuit simplicity
(meeting the objective of low
cost) the shunt resistor value was
6-130
1
7. Design of the output
Results of this step:
0.5
impedance matching network.
Using the circuit file from step 4
(Figure 15), Touchstone was used
to calculate the load impedance
2
The output circuit is:
C (50 Ω)
B
A (Γ *)
opt
0.59 pF
0.2
RF
L1
Input
C1
RF
OUTPUT
Γ
(0.62 +35°)oftheINA-12063
ml
11.2 nH
1
C
2
0.2
0.5
to achieve maximum power
transfer. The conjugate of Γ ,
Γ * (0.62 -35°), is plotted as
ml
ml
A
Figure 20. Output Circuit.
-0.2
Point A on the Smith chart in
Figure19.
B
The circuit values from this step
and from Step 6 will be used as a
starting point to be refined in
Step 9 when the circuit is ex-
panded to take practical intercon-
nections and parasitics into
account.
-2
1
-0.5
0.5
-1
2
Figure 17. Input Impedance Match.
B
0.2
As shown in Figure 17, a shunt
capacitor of 0.59 pF will move
1
2
0.2
0.5
Γ
* at Point A to a position on
opt
8. PCB Layout. The results of
the preceding steps and the PCB
layout guidelines in design Step 8
were used to draft the circuit
board layout shown in Figure 21.
Since parasitic effects are mini-
mal, the current source resistor,
R2, can be conveniently placed
directly from the RF output to the
C
the unit conductance circle (G=1)
at Point B. A 11.2 nH series
inductor then completes the
match to 50 Ω by moving the
impedance at Point B to the
center of the chart.
A (Γ *)
B
C (50 Ω)
ml
A
-0.2
RF
Output
C2
L2
-2
-0.5
-1
Figure 19. Output Impedance Match.
The value of the shunt capacitor
is small enough that a short
I
connection. A bypass capaci-
bias
The two possible L-C networks
that can be used to match Γml* to
50 Ω are either a shunt C-series L
or a shunt L-series C circuit. By
choosing the shunt L-series C
circuit, two of the DC consider-
ations from Step 5 can be satis-
fied: the shunt L can be bypassed
and used to apply the +3 volt
length of open-circuit transmis-
sion line could be used in place of
the lumped element capacitor.
This saves the expense of a chip
component with the tradeoff of a
small amount of additional circuit
board space. A 0.20-inch length of
open-circuit 50 Ω line is one
choice that would be equivalent
to the 0.59 pF shunt capacitor.
The input matching circuit is
shown in Figure 19.
tor is added to the shunt stabiliz-
ing resistor, R1 and matching
inductor, L2, on the output. A DC
blocking capacitor, C1, is in-
cluded at the input to complete
the amplifier.
supply to the RF output terminal,
and the series C will serve double
duty as the DC blocking capacitor.
Referring again to Figure 19, a
shunt inductance of 10.8 nH
Results of this step:
The input circuit is:
11.2 nH
moves Γ * at Point A to Point B
ml
which is on the G1 circle of the
Smith chart. The addition of
1.9 pFofseriescapacitance
RF
Figure 21. PCB Layout of 900 MHz
LNA.
INPUT
0.59 pF
completes the impedance trans-
formation to Point C at the center
of the chart. The output matching
circuit is shown in Figure 20.
Figure 18. Input Circuit.
Results of this step:
PCB layout completed.
6-131
9. Final CAD simulation and
optimization. With reference to
Figure 21 the CAD circuit file
from step 4 is embellished to
include the effects of component
mounting pads, lengths of trans-
mission lines used to intercon-
nect components, ground vias,
bypass and blocking capacitors,
etc. (Since 900 MHz is a fairly
moderate frequency, extremely
fine detail is not required.)
A final simulation using optimized
component values predicted
performance of the amplifier at
900 MHz to be:
10. Assemble and test. A
circuit based on the PCB layout
was assembled using components
with standard values that were
closest to those resulting from
the circuit optimization.
NF=1.6dB
Gain=13.4dB
MAG=14.1dB
InputRL=8.4dB
Output RL = 31 dB
The test results compared well
with the computer simulations
from the previous step. For this
particular circuit, it was deter-
mined experimentally that less
shunt capacitance was required at
the input than predicted by the
CAD analysis. As a result, the
shunt, open circuit stub near Pin 3
was shortened to tune the circuit
for minimum noise figure. The
final LNA is shown in Figure 23.
Results of this step:
Optimization of circuit and
verification of performance goals.
Using the previous element
values for the matching circuits
as a starting point, Touchstone
was used to optimize the circuit
for noise figure and output match,
which were the primary design
goals from Step 1. The input and
output matching elements were
used as variables for the optimi-
zation. Following the optimiza-
tion, the value of the stabilizing
resistor, R1, was also reviewed
and it was found that an increase
to 330 Ω was sufficient to make
K>1 over the entire frequency
range of the S-parameters. The
Touchstone circuit file for the
complete amplifier is shown in
Appendix A and the simulation
results in Appendix B.
The schematic for the complete
INA-12063 amplifier circuit is
shown in Figure 22.
Figure 23. Completed 900 MHz LNA.
6-132
20
15
10
5
Actual, measured test results are
shown in Figures 24 through 28.
Output power for 1 dB of gain
Hints and Troubleshooting
• Oscillation
Even though a design may be
unconditionally stable (K > 1 and
B1 > 0) over its full frequency
range, other possibilities exist
that may cause an amplifier
compression (P ) at 900 MHz
1dB
was measured as -4.6 dBm.
20
circuit to oscillate. One thing to
look for, is oscillation in bias
circuits. It is important to capaci-
tively bypass the connections to
active bias circuits to ensure
stable operation. In multistage
circuits, feedback through bias
lines can also lead to oscillation.
0
15
-5
100
500
900
1300
1700 2100
10
5
FREQUENCY (MHz)
Figure 27. Measured Gain of Example
900 MHz LNA for Extended Frequency.
0
0
800
850
900
950
1000
Components of insufficient
quality for the frequency range of
the amplifier can sometimes lead
to instability. Also, component
values that are chosen to be much
higher in value than is appropri-
ate for the application can
present a problem. In both of
these cases, the components may
have reactive parasitics that make
their impedances very different
than expected. Chip capacitors
may have excessive inductance,
or chip inductors can exhibit
resonances at unexpected
Input
FREQUENCY (MHz)
-5
Figure 24. Measured Gain of Example
900 MHz LNA.
Output
-10
4
-15
-20
3
100
500
900
1300
1700 2100
2
1
0
FREQUENCY (MHz)
Figure 28. Measured Input and Output
Return Loss of Example 900 MHz LNA
for Extended Frequency.
Results of this step:
800
850
900
950
1000
frequencies.
A prototype circuit was built and
performance goals verified by
measurement. The following
900 MHz data was measured on
the example LNA:
FREQUENCY (MHz)
Figure 25. Measured Noise Figure of
Example 900 MHz LNA.
In systems with high gain cas-
cades, another possible feedback
path that could lead to oscillation
is radiation. Feedback via radia-
tion is most frequently encoun-
tered in situations where a large
cavity housing is used in combi-
nation with multiple gain stages.
One solution to minimizing
radiation feedback is to design
the housing so that it is well
below its equivalent waveguide
cutoff frequency. Another solu-
tion is to use shielding to parti-
tion the gain.
0
-5
Input
NF=1.9dB
Gain=14.7dB
-10
-15
P
(output)=-4.6dBm
1dB
Output
Input Return Loss = 9.6 dB
(InputVSWR=2.0:1)
Output Return Loss = 20.4 dB
(OutputVSWR=1.2:1)
DC Power = 8 mW
-20
-25
-30
-35
800
850
900
950
1000
(3 volts, 2.55 mA)
FREQUENCY (MHz)
Figure 26. Measured Input and
Output Return Loss of Example
900 MHzLNA.
6-133
The INA-12063 is has been
qualified to the time-temperature
profile shown in Figure 29. This
profile is representative of an IR
reflow type of surface mount
assembly process.
board and components should be
exposed only to the minimum
temperatures and times neces-
sary to achieve a uniform reflow
of solder.
• A Note on Supply Line
Bypassing
When multiple bypass capacitors
are used throughout the power
supply lines in a wireless system,
consideration should be given to
potential resonances. It is impor-
tant to ensure that the capacitors,
when combined with additional
parasitic L’s and C’s on the circuit
board, do not form resonant
circuits. The addition of a small
value resistor in the bias supply
line between bypass capacitors
will often “de-Q” the bias circuit
and eliminate resonance effects.
Statistical Parameters
After ramping up from room
temperature, the circuit board
with components attached to it
(held in place with solder paste)
passes through one or more
preheat zones. The preheat zones
increase the temperature of the
board and components to prevent
thermal shock and begin evapo-
rating solvents from the solder
paste. The reflow zone briefly
elevates the temperature suffi-
ciently to produce a reflow of the
solder.
Several categories of parameters
appear within this data sheet.
Parameters may be described
with values that are either
minimum or maximum, “typical,”
or standard deviations.
The values for parameters are
based on comprehensive product
characterization data, in which
automated measurements are
made on of a minimum of 500
parts taken from 3 non-consecu-
tive process lots of semiconduc-
tor wafers. The data derived from
product characterization tends to
be normally distributed, e.g., fits
the standard bell curve.
SMT Assembly
Reliable assembly of surface
mount components is a complex
process that involves many
material, process, and equipment
factors, including: method of
heating (e.g., IR or vapor phase
reflow, wave soldering, etc.)
circuit board material, conductor
thickness and pattern, type of
solder alloy, and the thermal
conductivity and thermal mass of
components. Components with a
low mass, such as the SOT-363
package, will reach solder reflow
temperatures faster than those
with a greater mass.
The rates of change of tempera-
ture for the ramp-up and cool-
down zones are chosen to be low
enough to not cause deformation
of the board or damage to compo-
nents due to thermal shock. The
maximum temperature in the
Parameters considered to be the
most important to system perfor-
mance are bounded by minimum
or maximum values. For the
reflow zone (T
) should not
MAX
exceed235°C.
INA-12063, theseparametersare:
2
PowerGain(|S | ),NoiseFigure
21
These parameters are typical for
a surface mount assembly
process for the INA-12063. As a
general guideline, the circuit
(NF), and Device Current. Each
of these guaranteed parameters is
100%tested.
Values for most of the parameters
in the table of Electrical Specifi-
cations that are described by
typical data are the mathematical
mean (µ), of the normal distribu-
tion taken from the characteriza-
tion data. For parameters where
measurements or mathematical
averaging may not be practical,
such as S-parameters or Noise
Parameters and the performance
curves, the data represents a
nominal part taken from the
center of the characterization
distribution. Typical values are
intended to be used as a basis for
electrical design.
250
200
TMAX
150
Reflow
Zone
100
Preheat
Zone
Cool Down
Zone
50
0
0
60
120
180
240
300
TIME (seconds)
Figure 29. Surface Mount Assembly Profile.
6-134
To assist designers in optimizing
not only the immediate circuit
using the INA-12063, but to also
optimize and evaluate trade-offs
that affect a complete wireless
system,thestandarddeviation
(σ) is provided for many of the
Electrical Specifications param-
eters (at 25°C) in addition to the
mean. The standard deviation is a
measure of the variability about
the mean. It will be recalled that a
normal distribution is completely
described by the mean and
discharges. Electrostatic charges
as high as several thousand volts
(which readily accumulate on the
human body and on test equip-
ment) can discharge without
detection and may result in
degradation in performance,
reliability, or failure.
REFERENCE
PLANES
TEST CIRCUIT
Figure 31. Phase Reference Planes.
Test Circuits
Electronic devices may be
subjected to ESD damage in any
of the following areas:
The test circuit shown in Fig-
ure 32isusedfor100%testingof
the guaranteed RF and DC
parameters that are shown in the
Table of Electrical Specifications.
• Storage and handling
• Inspection and testing
• Assembly
standard deviation.
1 nF
+3 V
Standard statistics tables or
calculations provide the probabil-
ity of a parameter falling between
any two values, usually symmetri-
cally located about the mean.
Referring to Figure 30 for ex-
ample, the probability of a
parameter being between ± 1σ is
68.3%;between± 2σ is95.4%;and
between± 3σ is99.7%.
• In-circuit use
5.6 kΩ
+3 V
1 nF
RF
INPUT
The INA-12063 is a ESD Class 1
device. Therefore, proper ESD
precautions are recommended
when handling, inspecting,
testing, assembling, and using
these devices to avoid damage.
8.2 nH
1 2 500 Ω
8.2 nH
RF
+3 V
OUTPUT
2.2 pF
10 nF
100 pF
Figure 32. 900 MHz Test Circuit.
The in-use aspect of potential
ESD damage is sometimes over-
looked. One such example of
possible damage is in the use of
an ESD sensitive device as the
front-end LNA stage in personal
communication equipment, such
as cellular telephones, PCS, or RF
modems.
The test circuits in Figures 32 and
33 were used to generate the
characterization data and perfor-
mance curves for 900 MHz and
250MHz.
68%
95%
99%
1 nF
+3 V
16 kΩ
+3 V
1 nF
RF
INPUT
-3σ -2σ -1σ Mean +1σ +2σ +3σ
(µ), typ
180 nH
Parameter Value
1 2 330 Ω
The input to receiver LNAs are
frequently connected to external
antennas that are subject to
human contact and exposure to
other potentially damaging levels
of ESD. If this type of condition
exists, some type of circuit
protection may be needed. One
simple method of preventing ESD
damage is to add a DC return
path (e.g., a shunt inductor) to
the input of the receiver. This
type of protection may be inte-
grated into other parts of the
receiver front end, such as in a
T/R switch, filter, or the input
matching network to the LNA.
150 Ω
39 nH
RF
OUTPUT
5.6 pF
Figure 30. Normal Distribution.
+3 V
5.6 pF
Phase Reference Planes
10 nF
100 pF
The positions of the reference
planes used to specify S-param-
eters and Noise Parameters for
the INA-12063 are shown in
Figure 31. As seen in the illustra-
tion, the reference planes are
located at the point where the
package leads contact the test
circuit.
Figure 33. 250 MHz Test Circuit.
Electrostatic Sensitivity
RFICs are electro-
static discharge
(ESD) sensitive
devices. Although the
INA-12063 is robust in design,
permanent damage may occur to
these devices if they are sub-
jected to high energy electrostatic
6-135
Appendix A - Touchstone Circuit File.
! Hewlett-PackardCMCD
!
!
Bob Myers
20 Sept 1996
! HPTouchstonecircuitfile
! INA-12063SingleStageLNA
!
!
fc = 900 MHz, Vc = 3.0 V, Ic = 2.5 mA
Input Matched for NF
DIM
FREQ GHZ
RES OH
CAP PF
IND NH
LNG IN
ANG DEG
VAR
!Inputmatch
L1#
A1#
C1#
0
0
0
12.6477
0.201808
0.636904
20
0.4
10
! Length of MLOC
!
!Outputmatch
L2#
C2#
0
0
9.25249
2.56665
20
10
CKT
MSUB ER=4.8 H=0.031 T=0.001 RHO=1 RGH=0
MLIN
CAP
MLIN
IND
MLOC
CAP
MLIN
S2P
RES
MLIN
VIA
MLIN
RES
1
2
3
4
5
5
5
6
7
8
9
7
2
3
4
5
W=0.056 L=0.300
C=300
! Input DC block
W=0.056 L=0.100
L^L1
! L1 in Input match
! Z1 in Input match
!AlternateshuntC
W=0.04 L^A1
0 C^C1
6
7
0
9
0
10
12
!
W=0.04
C:\SPARA\A120633B.S2P
R=9100 !R1biasresistor
W=0.020 L=0.035 ! Z2 in RF ground
D1=0.025 D2=0.025 H=0.031 T=0.0015 W=0.04
L=0.020
8
W=0.06
R=330
L=0.100
10
!R2StabilizingR
! L2 in Output match
! Bypass C
MLIN 10 11 W=0.056 L=0.065
IND 11 12 L^L2
MLIN 11 15 W=0.056 L=0.050
CAP 12 13 C=300
MLIN 13 14 W=0.050 L=0.020
VIA
CAP
14
15
0
16
D1=0.025 D2=0.025 H=0.031 T=0.001 W=0.04
C^C2
! C2 in Output match
MLIN 16 17 W=0.056 L=0.300
DEF2P
1
17
INA12
TERM
Z0 = 50
OUT
INA12
NF
GR3
GR1
GR2
GR2
INA12 DB[S21]
INA12 DB[S11]
INA12 DB[S22]
INA12 DB[GMAX] GR1
6-136
INA12
INA12
K
B1
! Stability factor (K > 1)
! Stability Measure (B1 > 0)
FREQ
SWEEP 0.1 3.1 0.02
GRID
FREQ 0.8
FREQ 0.1
1.0
3.1
20
-40
4
0.05
0.1
5
10
1
!
GR1
GR2
GR3
0
0
0
!Gain
!Returnloss
! NF
OPT
FREQ
INA12 NF<1.6
INA12 DB[S22]<-20 1
0.85
0.95
5
Appendix B – Touchstone Output File.
FREQ
GHZ
NF
INA12
DB[S21]
INA12
DB[S11]
INA12
DB[S22] DB[GMAX]
K
B1
INA12
INA12
INA12
INA12
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2.0
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
3.0
3.1
11.178
9.706
8.725
7.627
6.366
4.929
3.388
2.048
1.588
2.490
4.284
6.292
8.193
-43.253
-13.998
-4.922
1.602
-0.913
-1.070
-1.429
-1.843
-2.947
-4.674
-7.101
-8.450
-7.910
-6.677
-5.483
-4.459
-3.727
-3.076
-2.611
-2.221
-1.900
-1.646
-1.440
-1.265
-1.124
-1.011
-0.912
-0.815
-0.737
-0.672
-0.615
-0.566
-0.523
-0.475
-0.442
0.000
-0.005
-0.027
-0.111
-0.418
-1.404
-4.424
-11.782
-35.279
-14.634
-11.002
-8.998
-7.952
-7.141
-6.578
-6.221
-5.875
-5.602
-5.414
-5.222
-5.024
-4.905
-4.871
-4.736
-4.665
-4.546
-4.528
-4.345
-4.338
-4.171
-4.077
5.717
22.248
22.535
21.559
18.878
17.490
16.155
15.081
14.143
13.285
12.521
11.836
11.221
10.708
10.169
9.663
9.243
8.885
8.558
8.233
7.924
7.498
7.307
7.002
109.193
1.404
1.094
1.071
1.295
1.414
1.569
1.656
1.813
1.926
2.018
2.122
2.230
2.259
2.287
2.369
2.416
2.370
2.317
2.288
2.279
2.344
2.285
2.299
2.116
2.039
1.978
1.975
2.103
1.889
1.760
0.000
0.002
0.010
0.036
0.108
0.287
0.634
0.957
1.104
1.161
1.198
1.223
1.237
1.248
1.249
1.256
1.254
1.252
1.252
1.247
1.236
1.231
1.237
1.229
1.228
1.217
1.220
1.195
1.198
1.177
1.164
6.760
11.048
13.713
14.210
13.289
11.823
10.309
8.776
7.440
6.113
4.870
3.720
9.918
11.469
12.868
14.146
15.317
16.402
17.415
18.367
19.264
20.112
20.927
21.700
22.446
23.162
23.861
24.530
25.179
25.811
2.647
1.637
0.728
-0.174
-1.007
-1.850
-2.453
-3.275
-3.842
-4.446
-5.015
-5.656
-6.216
-6.619
-7.041
6.926
6.747
6.521
6.252
5.870
6.107
6.024
Results of computer simulation of optimized 900 MHz LNA.
1
U.S.PatentNumber5436595
6-137
INA-12063 Part Number Ordering Information
Part Number
Devices per Container
Container
INA-12063-TR1
3000
7" reel
tape strip in
antistatic bag
INA-12063-BLK
100
Package Dimensions
Outline 63 (SOT-363/SC-70)
1.30 (0.051)
REF.
2.20 (0.087)
2.00 (0.079)
1.35 (0.053)
1.15 (0.045)
0.650 BSC (0.025)
0.425 (0.017)
TYP.
2.20 (0.087)
1.80 (0.071)
0.10 (0.004)
0.00 (0.00)
0.30 REF.
1.00 (0.039)
0.80 (0.031)
0.20 (0.008)
0.10 (0.004)
10°
0.30 (0.012)
0.10 (0.004)
0.25 (0.010)
0.15 (0.006)
DIMENSIONS ARE IN MILLIMETERS (INCHES)
6-138
Device Orientation
TOP VIEW
4 mm
END VIEW
REEL
8 mm
12
12
12
12
CARRIER
TAPE
USER
FEED
DIRECTION
COVER TAPE
Tape Dimensions and Product Orientation
For Outline 63
P
P
D
2
P
0
E
F
W
C
D
1
t
(CARRIER TAPE THICKNESS)
T (COVER TAPE THICKNESS)
t
1
K
8° MAX.
5° MAX.
0
A
B
0
0
DESCRIPTION
SYMBOL
SIZE (mm)
SIZE (INCHES)
CAVITY
LENGTH
WIDTH
DEPTH
PITCH
A
B
K
P
D
2.24 ± 0.10
2.34 ± 0.10
1.22 ± 0.10
4.00 ± 0.10
1.00 + 0.25
0.088 ± 0.004
0.092 ± 0.004
0.048 ± 0.004
0.157 ± 0.004
0.039 + 0.010
0
0
0
F
y
d
BOTTOM HOLE DIAMETER
1
0
A
4
PERFORATION
DIAMETER
PITCH
POSITION
D
P
E
1.55 ± 0.05
4.00 ± 0.10
1.75 ± 0.10
0.061 ± 0.002
0.157 ± 0.004
0.069 ± 0.004
F
J
CARRIER TAPE WIDTH
THICKNESS
W
8.00 ± 0.30
0.315 ± 0.012
t
0.255 ± 0.013 0.010 ± 0.0005
5.4 ± 0.10 0.205 ± 0.004
0.062 ± 0.001 0.0025 ± 0.00004
1
COVER TAPE
WIDTH
TAPE THICKNESS
C
E
T
t
DISTANCE
CAVITY TO PERFORATION
(WIDTH DIRECTION)
F
3.50 ± 0.05
0.138 ± 0.002
D
C
CAVITY TO PERFORATION
(LENGTH DIRECTION)
P
2
2.00 ± 0.05
0.079 ± 0.002
P
6-139
相关型号：
INA-34063-BLK
Wide Band Low Power Amplifier, 100MHz Min, 3000MHz Max, BIPolar, SOT-363, 6 PIN
AGILENT
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