AKD4555 [AKM]
Low Power & Small Package 20bit ΔΣ CODEC; 低功耗和小封装20位ツヒCODEC
| 型号： | AKD4555 |
| 厂家： | 
ASAHI KASEI MICROSYSTEMS |
| 描述： | Low Power & Small Package 20bit ΔΣ CODEC |
| 文件： | 总17页 (文件大小：192K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ASAHI KASEI
[AK4555]
AK4555
∆Σ
Low Power & Small Package 20bit
CODEC
GENERAL DESCRIPTION
The AK4555 is a low voltage 20bit A/D & D/A converter for portable digital audio system. In the AK4555,
the loss of accuracy form clock jitter is also improved by using SCF techniques for on-chip post filter.
Analog signal input/output of the AK4555 are single-ended, therefore, any external filters are not required.
The AK4555 is suitable for portable digital audio system, as the AK4555 is low power dissipation and a
small package.
FEATURES
HPF for DC-offset cancel (fc=3.4Hz)
Single-ended ADC
- S/(N+D): 80dB@VDD=2.5V
- Dynamic Range, S/N: 89dB@VDD=2.5V
Single-ended DAC
- Digital de-emphasis for 32kHz, 44.1kHz, 48kHz sampling
- S/(N+D): 85dB@VDD=2.5V
- Dynamic Range, S/N: 92dB@VDD=2.5V
Audio I/F format: MSB First, 2’s Compliment
- ADC, DAC: I2S
Input/Output Voltage: 0.6 x VDD (=1.5Vpp@VDD=2.5V)
High Jitter Tolerance
Sampling Rate: 8kHz to 50kHz
Master Clock: 256fs/384fs/512fs/768fs (fs=8kHz to 50kHz)
1024fs (fs=8kHz to 25kHz)
Power Supply: 1.6 to 3.6V
Low Power Supply Current: 8.6mA
Ta = −40 to 85°C
Very Small Package: 16pin TSSOP
VDD
VSS
Clock
Divider
MCLK
∆Σ
Decimation
Filter
AINL
AINR
Modulator
LRCK
SCLK
∆Σ
Decimation
Filter
Modulator
SDTO
SDTI
Serial I/O
Interface
VCOM
Common Voltage
DEM0
DEM1
∆Σ
Modulator
8X
AOUTL
LPF
Interpolator
PWDAN
PWADN
∆Σ
Modulator
8X
AOUTR
LPF
Interpolator
MS0363-E-01
2005/08
- 1 -
ASAHI KASEI
[AK4555]
Ordering Guide
AK4555VT
AKD4555
−40 ∼ +85°C
16pin TSSOP (0.65mm pitch)
Evaluation Board for AK4555
Pin Layout
AOUTR
AOUTL
PWDAN
PWADN
VCOM
AINR
AINL
1
2
3
16
15
14
13
12
11
10
9
VSS
4
Top
View
VDD
5
SCLK
MCLK
DEM0
DEM1
SDTO
6
7
8
LRCK
SDTI
Comparison with AK4550 and AK4554
Item
AK4550
AK4554
AK4555
Power Supply Voltage
Å
2.3 ∼ 3.6V
ADC:
justified
1.6 ∼ 3.6V
MSB ADC:
16bit
16bit
MSB
Audio I/F Format
justified
I2S
DAC: 16bit LSB justified DAC: 16bit LSB justified
VCOM pin
0.45 x VDD
82dB
100kΩ
0.5 x VDD
80dB
70kΩ
Å
Å
Å
ADC S/(N+D) (typ)
ADC Input Resistance (typ)
Power Supply Current (typ)
AD+DA
10mA
5.6mA
5.6mA
8mA
4mA
4.4mA
Å
Å
Å
AD
DA
DAC Digital Filter
Stopband Attenuation (min)
Passband Ripple (max)
Group Delay
43dB
±0.06dB
14.8/fs
54dB
±0.02dB
19.0/fs
Å
Å
Å
256fs/384fs/512fs/768fs
(fs=8∼50kHz)
1024fs (fs=8∼25kHz)
MCLK
256fs/384fs/512fs
Å
External Circuit
VCOM pin
Å
Å
4.7µF + 0.1µF
RC filter is needed.
0.1µF
RC filter is on-chip.
AINL, AINR pins
MS0363-E-01
2005/08
- 2 -
ASAHI KASEI
No. Pin Name
[AK4555]
PIN/FUNCTION
I/O Function
1
2
3
4
5
6
7
8
9
VCOM
AINR
AINL
VSS
O
I
I
-
-
I
I
O
I
Common Voltage Output Pin, 0.5 x VDD
Rch Analog Input Pin
Lch Analog Input Pin
Ground Pin
Power Supply Pin
De-emphasis Control Pin
De-emphasis Control Pin
Audio Serial Data Output Pin
Audio Serial Data Input Pin
VDD
DEM0
DEM1
SDTO
SDTI
10 LRCK
11 MCLK
12 SCLK
I
I
I
Input/Output Channel Clock Pin
Master Clock Input Pin
Audio Serial Data Clock Pin
ADC Power-Down & Reset Mode Pin
“L”: Power down. ADC should always be reset upon power-up.
DAC Power-Down & Reset Mode Pin
“L”: Power down. DAC should always be reset upon power-up.
Lch Analog Output Pin
13 PWADN
14 PWDAN
I
I
15 AOUTL
16 AOUTR
O
O
Rch Analog Output Pin
Note: All input pins except analog input pins (AINR and AINL) should not be left floating.
Handling of Unused Pin
The unused I/O pins should be processed appropriately as below.
Classification
Analog
Pin Name
AINR, AINL, AOUTL, AOUTR
SDTO
SDTI
Setting
These pins should be open.
This pin should be open.
This pin should be connected to VSS.
Digital
MS0363-E-01
2005/08
- 3 -
ASAHI KASEI
[AK4555]
ABSOLUTE MAXIMUM RATINGS
(VSS=0V; Note 1)
Power Supply
Input Current (any pins except for supplies)
Input Voltage
Parameter
Symbol
VDD
IIN
VIN
Ta
min
−0.3
-
−0.3
−40
−65
max
4.6
±10
Units
V
mA
V
°C
°C
VDD+0.3
Ambient Temperature (power applied)
Storage Temperature
85
150
Tstg
Note 1. All voltages with respect to ground.
WARNING: Operation at or beyond these limits may results in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS
(VSS=0V; Note 1)
Parameter
Symbol
min
typ
max
Units
Power Supply
VDD
1.6
2.5
3.6
V
Note 1. All voltages with respect to ground.
*AKM assumes no responsibility for the usage beyond the conditions in this datasheet.
MS0363-E-01
2005/08
- 4 -
ASAHI KASEI
[AK4555]
ANALOG CHARACTERISTICS
(Ta=25°C; VDD=2.5V; fs=44.1kHz; Signal Frequency=1kHz; SCLK=64fs; Measurement frequency=20Hz ∼ 20kHz;
unless otherwise specified)
Parameter
min
typ
max
Units
ADC Analog Input Characteristics: (Note 2)
Resolution
-
70
82
82
80
-
1.35
40
-
-
80
89
89
95
0.2
1.50
70
20
-
-
-
-
0.5
1.65
-
Bits
dB
dB
dB
dB
S/(N+D)
D-Range
S/N
Interchannel Isolation
Interchannel Gain Mismatch
Input Voltage
(−0.5dB Input)
(−60dB Input, A-weighted)
(A-weighted)
dB
(Note 3)
(Note 4)
Vpp
kΩ
dB
Input Resistance
Power Supply Rejection
45
-
DAC Analog Output Characteristics:
Resolution
S/(N+D)
D-Range
S/N
Interchannel Isolation
Interchannel Gain Mismatch
Output Voltage
Load Resistance
Load Capacitance
Power Supply Rejection
-
75
86
86
80
-
1.35
10
-
-
20
-
-
-
-
0.5
1.65
-
30
-
Bits
dB
dB
dB
dB
dB
Vpp
kΩ
pF
85
92
92
95
0.2
1.5
-
(−60dB Output, A-weighted)
(A-weighted)
(Note 3)
(Note 4)
-
50
-
dB
Power Supplies
Power Supply Current
AD+DA
AD
DA
PWADN= “H”, PWDAN= “H”
PWADN= “H”, PWDAN= “L”
PWADN= “L”, PWDAN= “H”
-
-
-
-
8
4
4.4
10
13
-
-
mA
mA
mA
µA
Power down (Note 5) PWADN= “L”, PWDAN= “L”
Power Consumption
50
AD+DA
AD
DA
PWADN= “H”, PWDAN= “H”
PWADN= “H”, PWDAN= “L”
PWADN= “L”, PWDAN= “H”
-
-
-
-
20
10
11
25
32.5
-
-
mW
mW
mW
µW
Power down (Note 5) PWADN= “L”, PWDAN= “L”
125
Note 2. The offset of ADC is removed by internal HPF.
Note 3. Input/Output of ADC and DAC scales with VDD voltage. 0.6 x VDD(typ).
Note 4. PSR is applied to VDD with 1kHz, 50mV. No signal is input to AINL/R pins and “0” data is input to SDTI pin.
Note 5. In case of power-down mode, all digital input including clocks pins (MCLK, SCLK and LRCK) are held to VDD
or VSS. PWADN and PWDAN pins are held to VSS.
MS0363-E-01
2005/08
- 5 -
ASAHI KASEI
[AK4555]
FILTER CHARACTERISTICS
(Ta=25°C; VDD=1.6 ∼ 3.6V; fs=44.1kHz; DEM1 pin = “L”, DEM0 pin = “H”)
Parameter
Symbol
min
typ
max
Units
ADC Digital Filter (Decimation LPF):
Passband
(Note 6)
PB
0
-
-
-
17.4
-
-
-
kHz
kHz
kHz
kHz
dB
dB
1/fs
µs
±0.1dB
−1.0dB
−3.0dB
20.0
21.1
-
-
-
Stopband
SB
PR
SA
GD
∆GD
25.7
Passband Ripple
Stopband Attenuation
Group Delay
-
65
-
±0.1
-
-
-
(Note 7)
17.0
0
Group Delay Distortion
-
ADC Digital Filter (HPF):
Frequency Response (Note 6)
FR
-
-
-
3.4
10
22
-
-
-
Hz
Hz
Hz
−3dB
−0.5dB
−0.1dB
DAC Digital Filter:
Passband
(Note 6)
PB
0
-
20.0
-
-
±0.02
-
-
kHz
kHz
kHz
dB
dB
1/fs
±0.05dB
−6.0dB
-
24.1
-
54
-
22.05
-
-
-
Stopband
SB
PR
SA
GD
Passband Ripple
Stopband Attenuation
Group Delay
(Note 7)
19.0
DAC Digital Filter + Analog Filter:
Frequency Response
FR
-
-
dB
0 ∼ 20.0kHz
±0.5
Note 6. The passband and stopband frequencies scale with fs (sampling frequency). For examples, PB=20.0kHz(@ADC:
−1.0dB, DAC: −0.1dB) are 0.454 x fs.
Note 7. This is the calculated delay time caused by digital filtering. This time is measured from the input of analog signal
to setting the 20 bit data of both channels on input register to the output register of ADC. This time also includes
group delay of HPF. For DAC, this time is from setting the 20 bit data of both channels on input register to the
output of analog signal.
DC CHARACTERISTICS
(Ta=25°C; VDD=1.6 ∼ 3.6V)
Parameter
High-Level Input Voltage
Symbol
VIH
VIH
VIL
min
70%VDD
80%VDD
typ
max
-
-
30%VDD
20%VDD
-
Units
V
V
V
V
V
V
µA
2.2V≤VDD≤3.6V
1.6V≤VDD<2.2V
2.2V≤VDD≤3.6V
1.6V≤VDD<2.2V
(Iout= −20µA)
-
-
-
-
-
-
-
Low-Level Input Voltage
-
-
VIL
High-Level Output Voltage
Low-Level Output Voltage
Input Leakage Current
VOH
VOL
Iin
VDD−0.1
(Iout= 20µA)
-
-
0.1
±10
MS0363-E-01
2005/08
- 6 -
ASAHI KASEI
[AK4555]
SWITCHING CHARACTERISTICS
(Ta=25°C; VDD=1.6 ∼ 3.6V; CL=20pF)
Parameter
Symbol
min
typ
max
Units
Master Clock Timing
Frequency
256fs/384fs/512fs/768fs
1024fs
fCLK
fCLK
dCLK
2.048
2.048
40
-
-
-
38.4
25.6
60
MHz
MHz
%
Duty Cycle
LRCK Timing
Frequency
fs
Duty
8
45
44.1
-
50
55
kHz
%
Duty Cycle
Serial Interface Timing
SCLK Period
tSCK
tSCK
tSCKL
tSCKH
tLRS
tSLR
tDSS
tSDH
tSDS
1/(96fs)
312.5
130
130
50
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
80
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
(8kHz ≤ fs ≤ 33kHz)
(33kHz < fs ≤ 50kHz)
SCLK Pulse Width Low
Pulse Width High
LRCK Edge to SCLK “↑”
SCLK “↑” to LRCK Edge
SCLK “↓” to SDTO
SDTI Hold Time
(Note 8)
(Note 8)
50
-
50
50
SDTI Setup Time
-
Reset Timing
PWADN or PWDAN Pulse Width
(Note 9)
tPW
tPWV
150
-
-
-
-
ns
1/fs
2081
PWADN “↑” to SDTO Valid
Note 8. SCLK rising edge must not occur at the same time as LRCK edge.
Note 9. These cycles are the number of LRCK rising from PWADN rising.
MS0363-E-01
2005/08
- 7 -
ASAHI KASEI
[AK4555]
Timing Diagram
1/fCLK
VIH
VIL
MCLK
tCLKH
tCLKL
dCLK = tCLKH x fCLK x 100
= tCLKL x fCLK x 100
1/fs
VIH
LRCK
VIL
tLRH
tLRL
Duty = tLRH x fs x 100
= tLRL x fs x 100
tSCK
VIH
VIL
SCLK
tSCKH
tSCKL
Figure 1. Clock Timing
VIH
LRCK
SCLK
SDTO
VIL
tSLR
tLRS
VIH
VIL
tDSS
50%VD
tSDS
tSDH
VIH
VIL
SDTI
Figure 2. Serial Interface Timing
tPW
PWDAN
VIL
tPW
VIH
VIL
PWADN
SDTO
tPWV
50%VD
Figure 3. Reset & Initialize Timing
MS0363-E-01
2005/08
- 8 -
ASAHI KASEI
[AK4555]
OPERATION OVERVIEW
System Clock Input
The AK4555 can be input MCLK=256fs, 384fs, 512fs, 768fs or 1024fs (fs is equal to or lower than 25kHz when MCLK
is 1024fs). The input clock applied to the MCLK pin as internal master clock is divided into 256fs automatically. When
MCLK is 1024fs, oversampling rate of D/A converter is automatically changed from 128fs to 256fs. The relationship
between the external clock applied to the MCLK input and the desired sample rate is defined in Table 1. The LRCK clock
input should be synchronized with MCLK. The phase between these clocks does not matter. *fs is sampling frequency.
When the synchronization is out of phase by changing the clock frequencies during normal operation, the AK4555 may
occur click noise. In case of DAC, click noise is avoided by setting the inputs to “0”.
All external clocks(MCLK, SCLK and LRCK) must be present unless PWADN=PWDAN= “L”. If these clocks are not
provided, the AK4555 may draw excess current and may not possibly operate properly because the device utilizes
dynamic refreshed logic internally.
fs
MCLK
512fs
SCLK
256fs
384fs
768fs
1024fs
32fs
64fs
8.0kHz
16.0kHz
32.0kHz
2.0480MHz
4.0960MHz
3.0720MHz
6.1440MHz
4.0960MHz
8.1920MHz 12.2880MHz 16.3840MHz
6.1440MHz
8.1920MHz
0.2560MHz
0.5120MHz
1.0240MHz
1.4112MHz
1.5360MHz
0.512MHz
1.024MHz
2.048MHz
2.822MHz
3.072MHz
8.1920MHz 12.2880MHz 16.3840MHz 24.5760MHz
N/A
N/A
N/A
44.1kHz 11.2896MHz 16.9344MHz 22.5792MHz 33.8688MHz
48.0kHz 12.2880MHz 18.4320MHz 24.5760MHz 36.8640MHz
Table 1. System Clock Example
For low sampling rates, outband noise causes S/N of DAC to degrade. S/N is improved by setting MCLK to 1024fs. Table
2 shows S/N of DAC output.
fs
MCLK
256fs/384fs/512fs/768fs
1024fs
S/N(fs=8kHz, A-weighted)
84dB
90dB
8kHz ∼ 50kHz
8kHz ∼ 25kHz
Table 2. Relationship among fs, MCLK frequency and S/N of DAC
MS0363-E-01
2005/08
- 9 -
ASAHI KASEI
[AK4555]
Audio Serial Interface Format
Data is shifted in/out the SDTI/SDTO pins using SCLK and LRCK inputs. The data is MSB first, 2’s compliment. The
following formats are also valid when SCLK is 64fs: 16-bit data followed by four zeros and 18-bit data followed by two
zeros.
LRCK
0
1
2
3
16
17
18
19
20 21
30
31
0
1
2
3
16
17
18
19
20 21
30
31
0
1
SCLK(64fs
SDTO(o)
19 18
15 14
17 16
19 18
4
0
2
4
3
2
1
0
19 18
15 14
17 16
19 18
4
0
2
4
3
2
1
0
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Don’t Care
SDTI(i)
16bit
1
3
0
2
1
3
0
2
SDTI(i)
18bit
1
0
1
0
SDTI(i)
20bit
0
1
2
3
8
9
10
11
12
13 14
15
0
1
2
3
8
9
10
11
12
13 14
15
0
1
SCLK(32fs)
SDTO(o)
0
0
15 14
15 14
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
0
0
15 14
15 14
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
0
0
SDTI(i)
Lch Data
Figure 4. Audio Interface Timing
Rch Data
De-emphasis filter
The DAC of AK4555 includes the digital de-emphasis filter (tc=50/15µs) by IIR filter. This filter corresponds to three
frequencies (32kHz, 44.1kHz and 48kHz). The de-emphasis filter selected by DEM0 and DEM1 pins is enabled for input
audio data. The de-emphasis is also disabled at DEM1 pin = “L” and DEM0 pin = “H”.
DEM1 pin
DEM0 pin
Mode
44.1kHz
OFF
48kHz
32kHz
L
L
H
H
L
H
L
H
Table 3. De-emphasis filter control
Digital High Pass Filter
The AK4555 has a Digital High Pass Filter (HPF) for DC-offset cancel. The cut-off frequency of the HPF is 3.4Hz at
fs=44.1kHz and the frequency response at 20Hz is −0.12dB. It also scales with the sampling frequency (fs).
MS0363-E-01
2005/08
- 10 -
ASAHI KASEI
[AK4555]
Power-down & Reset
The ADC and DAC of AK4555 are placed in the power-down mode by bringing each power down pin, PWADN,
PWDAN = “L” independently and each digital filter is also reset at the same time. These resets should always be done
after power-up. In case of the ADC, an anlog initialization cycle starts after exiting the power-down mode. Therefore, the
output data, SDTO becomes available after 2081 cycles of LRCK clock. This initialization cycle does not affect the DAC
operation. Figure 5 shows the power-up sequence when the ADC is powered up before the DAC power-up.
PWADN
2081/fs
ADC Internal
State
Normal Operation
Power-down
Init Cycle
Normal Operation
PWDAN
DAC Internal
State
Normal Operation
GD
Normal Operation
Power-down
GD
ADC In
(Analog)
ADC Out
(Digital)
Idle Noise
Idle Noise
“0”data
DAC In
(Digital)
“0”data
GD
GD
DAC Out
(Analog)
Clock In
MCLK,LRCK,SCLK
The clocks may be stopped.
Mute ON
External
Mute
Figure 5. Power-up Sequence
MS0363-E-01
2005/08
- 11 -
ASAHI KASEI
[AK4555]
SYSTEM DESIGN
Figure 6 shows the system connection diagram. An evaluation board[AKD4555] is available which demonstrates
application circuit, optimum layout, power supply arrangements and measurement results.
0.1u
Rch In
+
1
2
3
4
5
6
7
8
VCOM
AINR
AINL
AOUTR 16
AOUTL 15
Lch In
+
Reset
Reset
PWDAN
PWADN
14
13
AK4555
Analog Supply
1.6 ∼ 3.6V
VSS
10u
0.1u
+
Top View
VDD
SCLK 12
MCLK 11
LRCK 10
DEM0
DEM1
SDTO
Controller
SDTI
9
Analog Ground
System Ground
Mode
Control
Figure 6. System Connection Diagram Example
Notes:
- When AOUT drives some capacitive load, some resistor should be added in series between AOUT and capacitive
load.
MS0363-E-01
2005/08
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ASAHI KASEI
[AK4555]
1. Grounding and Power Supply Decoupling
VDD and VSS are supplied from analog supply and should be separated from system digital supply. Decoupling
capacitors should be as near to the AK4555 as possible, with the small value ceramic capacitor being nearest.
2. Voltage Reference
The input to VDD voltage sets the analog input/output range. A 0.1µF ceramic capacitor is connected to VDD and VSS
pins, normally. VCOM is a signal ground of this chip. A 0.1µF ceramic capacitor attached to VCOM pin eliminates the
effects of high frequency noise. No load current may be drawn from VCOM pin. All signals, especially clock, should be
kept away from the VDD and VCOM pins in order to avoid unwanted coupling into the AK4555.
3. Analog Inputs
ADC inputs are single-ended and internally biased to VCOM. The input signal range scales with the supply voltage and
nominally 0.6xVDD Vpp(typ). The ADC output data format is 2’s compliment.
The AK4555 samples the analog inputs at 64fs. The digital filter rejects noise above the stop band except for multiples of
64fs. The AK4555 includes an anti-aliasing filter (RC filter) to attenuate a noise around 64fs.
4. Analog Outputs
The analog outputs are also single-ended and centered around the VCOM voltage. The output signal range scales with the
supply voltage and nominally 0.6xVDD Vpp(typ). The DAC input data format is 2’s compliment. The output voltage is a
positive full scale for 7FFFFH(@20bit) and a negative full scale for 80000H(@20bit). The ideal output is VCOM voltage
for 00000H(@20bit). If the noise generated by the delta-sigma modulator beyond the audio band would be the problem,
the attenuation by external filter is required.
DC offsets on analog outputs are eliminated by AC coupling since DAC outputs have DC offsets of a few mV.
MS0363-E-01
2005/08
- 13 -
ASAHI KASEI
[AK4555]
Layout Pattern Example
AK4555 requires careful attention to power supply and grounding arrangements to optimize performance.
(Please refer to AKD4555 Evaluation Board layout pattern.)
1. VDD pin should be supplied from analog power supply on system, and VSS pin should be connected to analog
ground on system. The AK4555 is placed on the analog ground plane, and near the analog ground and digital ground
split. And analog and digital ground planes should be only connected at one point. The connection point should be
near to the AK4555.
2. VDD pin should be distributed from the point with low impedance of regulator etc.
3. The series resistors are prevent on the clock lines to reduce overshoot and undershoot. To avoid digital noise
coupling to analog circuit in the AK4555, a 10pF ceramic capacitor on MCLK pin is connected with digital ground.
4. 0.1µF ceramic capacitors of VDD-VSS pins and VCOM-VSS pins should be located as close to the AK4555 as
possible. And these lines should be the shortest connection to pins.
0.1u
+
Rch In
AOUTR
AOUTL
VCOM
AINR
AINL
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
+
Lch In
AK4555 PWDAN
Analog Supply
1.6 ∼ 3.6V
Reset &Power-down
Controller
PWADN
VSS
51
+
Top View
VDD
SCLK
MCLK
LRCK
SDTI
10u 0.1u
51
10P
51
DEM0
DEM1
SDTO
Analog Ground
Digital Ground
51
51
Mode Control
Figure 7. Layout Pattern Example
MS0363-E-01
2005/08
- 14 -
ASAHI KASEI
[AK4555]
PACKAGE
16pin TSSOP (Unit: mm)
*5.0 0.1
1.05 0.05
±
±
16
9
A
8
1
0.22 0.1
±
0.65
0.17 0.05
±
0.13 M
Detail A
0.1 0.1
±
Seating Plane
0.10
NOTE: Dimension "*" does not include mold flash.
0-10
°
Package & Lead frame material
Package molding compound:
Lead frame material:
Epoxy
Cu
Lead frame surface treatment:
Solder (Pb free) plate
MS0363-E-01
2005/08
- 15 -
ASAHI KASEI
[AK4555]
MARKING
AKM
4555VT
XXYYY
1) Pin #1 indication
2) Date Code : XXYYY (5 digits)
XX: Lot#
YYY: Date Code
3) Marketing Code : 4555VT
4) Asahi Kasei Logo
Revision History
Date (YY/MM/DD) Revision Reason
Page
7
Contents
04/11/24
05/08/08
00
01
First Edition
Spec Change
Switching Characteristics
tSCK(min): 312.5ns Æ 1/(96fs) or 312.5ns
MS0363-E-01
2005/08
- 16 -
ASAHI KASEI
[AK4555]
IMPORTANT NOTICE
• These products and their specifications are subject to change without notice. Before considering
any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or
authorized distributor concerning their current status.
• AKM assumes no liability for infringement of any patent, intellectual property, or other right in the
application or use of any information contained herein.
• Any export of these products, or devices or systems containing them, may require an export license
or other official approval under the law and regulations of the country of export pertaining to customs
and tariffs, currency exchange, or strategic materials.
• AKM products are neither intended nor authorized for use as critical components in any safety, life
support, or other hazard related device or system, and AKM assumes no responsibility relating to
any such use, except with the express written consent of the Representative Director of AKM. As
used here:
(a) A hazard related device or system is one designed or intended for life support or maintenance of
safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its
failure to function or perform may reasonably be expected to result in loss of life or in significant
injury or damage to person or property.
(b) A critical component is one whose failure to function or perform may reasonably be expected to
result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or
system containing it, and which must therefore meet very high standards of performance and
reliability.
• It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or
otherwise places the product with a third party to notify that party in advance of the above content
and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability
for and hold AKM harmless from any and all claims arising from the use of said product in the
absence of such notification.
MS0363-E-01
2005/08
- 17 -
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