AKD4671-B [AKM]
stereo CODEC with built-in Microphone-Amplifier; 立体声编解码器，内置麦克风放大器
| 型号： | AKD4671-B |
| 厂家： | 
ASAHI KASEI MICROSYSTEMS |
| 描述： | stereo CODEC with built-in Microphone-Amplifier |
| 文件： | 总51页 (文件大小：1089K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
[AKD4671-B]
Evaluation board Rev.0 for AK4671
GENERAL DESCRIPTION
AKD4671 is an evaluation board for the AK4671, stereo CODEC with built-in Microphone-Amplifier,
Receiver-Amplifier and Headphone-Amplifier.
The AKD4671 can evaluate A/D converter and D/A converter separately in addition to loopback mode
(A/D → D/A). The AKD4671-B also has the digital audio interface and can achieve the interface with
digital audio systems via opt-connector.
Ordering guide
AKD4671 --- Evaluation board for AK4671
(Cable for connecting with printer port of IBM-AT,compatible PC and control
software are packed with this. This control software does not support Windows NT.)
FUNCTION
• DIT/DIR with optical input/output
• 10pin Header for Digital Audio I/F, PCM I/F (Baseband, Bluetooth)
• BNC connector for an external clock input
• 10pin Header for serial control mode
REG
TVDD3
DVDD
PVDD SAVDD AVDD
TVDD2
3.3 V
REG
Opt Out
Opt In
TX
RX
AK4114
DIR
DIT
MIC
Jack
LIN1/RIN1
LIN2/3/4
Digital Audio I/F
10Pin Header
RIN2/3/4
SAIN1/2/3
SAIN3
Control I/F
10Pin Header
AK4671
LOUT1/2/3
ROUT1/2/3
Control I/F
SAR ADC
10Pin Header
HP
Jack
VSS2
VSS4
Baseband I/F
10Pin Header
VSS1
VSS3
4212
HP
Bluetooth I/F
10Pin Header
SPK_L
Jack
AK4212
GND
SPK_R
Jack
Figure 1. AKD4671-B Block Diagram
* Circuit diagram and PCB layout are attached at the end of this manual
<KM089000>
2007 / 05
- 1 -
[AKD4671-B]
Evaluation Board Manual
Operation sequence
1) Set up the power supply lines.
(1-1) In case of using the regulator.
Set up the jumper pins.
JP18
SVDD
SEL
JP20
JP22
JP24
JP26
JP27
JP29
JP31
VCC
SEL
JP7
VCC2
SEL
JP
AVDD SAVDD PVDD
SEL
DVDD TVDD2 TVDD3
SEL
SEL
SEL
SEL
SEL
State
Short
Short
Short
Short
Short
Short
Short
Short
Short
Set up the power supply lines.
[REG] (red)
= 5.0V
: for regulator (3.3V output : AK4671 , Logic)
[D3V] (orange)
[AGND] (black)
[DGND] (black)
= 2.7 ∼ 3.6V : for AK4114 and logic (typ. 3.3V)
= 0V
= 0V
: for analog ground
: for logic ground
(1-2) In case of using the power supply connectors.
Set up the jumper pins.
JP18
SVDD
SEL
JP20
JP22
JP24
JP26
JP27
JP29
JP31
VCC
SEL
JP7
VCC2
SEL
JP
AVDD SAVDD PVDD
SEL
DVDD TVDD2 TVDD3
SEL
SEL
SEL
SEL
SEL
State
Open
Open
Open
Open
Open
Open
Open
Open
Open
Set up the power supply lines.
[SVDD] (orange) = 3.0 ~ 5.5V : for SVDD of AK4212 (typ. 3.6V)
[AVDD] (orange) = 2.2 ~ 3.6V : for AVDD of AK4671 (typ. 3.3V)
[SAVDD] (orange) = 2.2 ~ 3.6V : for SAVDD of AK4671 (typ. 3.3V)
[PVDD] (orange)
= 2.2 ∼ 3.6V : for PVDD of AK4671 (typ. 3.3V)
[DVDD] (orange) = 1.6 ∼ 3.6V : for DVDD of AK4671 (typ. 3.3V)
[TVDD2] (orange) = 1.6 ∼ 3.6V : for TVDD2 of AK4671 (typ. 3.3V)
[TVDD3] (orange) = 1.6 ∼ 3.6V : for TVDD3 of AK4671 (typ. 3.3V)
[VCC] (orange)
[VCC2] (orange)
[D3V] (orange)
[AGND] (black)
[DGND] (black)
= 1.6 ∼ 3.6V : for logic (typ. 3.3V : the voltage same as DVDD)
= 1.6 ∼ 3.6V : for logic (typ. 3.3V : the voltage same as TVDD2 and TVDD3)
= 2.7 ∼ 3.6V : for AK4114 and logic (typ. 3.3V)
= 0V
= 0V
: for analog ground
: for logic ground
* Each supply line should be distributed from the power supply unit.
2) Set up the evaluation mode, jumper pins and DIP switches. (See the followings.)
3) Power on.
The AK4671 and AK4114 should be reset once bringing SW1 (DIR) and SW2 (PDN) “L” upon power-up.
<KM089000>
2007 / 05
- 2 -
[AKD4671-B]
Evaluation mode
1. Audio I/F evaluation mode
In case of AK4671 evaluation using AK4114, it is necessary to correspond to audio interface format for
AK4671 and AK4114. About AK4671’s audio interface format, refer to datasheet of AK4671. About
AK4114’s audio interface format, refer to Table 2 on page 19.
The AK4114 operates at fs of 32kHz or more. If the fs is slower than 32kHz, please use other mode.
In addition, MCLK of AK4114 supports 256fs and 512fs. When evaluate it in a condition except this, please
use other modes
(1) External Slave Mode
(1-1) Evaluation of A/D using DIT of AK4114
(1-2) Evaluation of D/A using DIR of AK4114
(1-3) Evaluation of Loop-back using AK4114 <default>
(1-4) Evaluation of Loop-back that master clock is fed externally, BICK and LRCK are divided with a
board
(1-5) All interface signals including master clock are fed externally
(2) External Master Mode
(2-1) Evaluation of A/D using DIT of AK4114
(2-2) Evaluation of D/A using DIR of AK4114
(2-3) Evaluation of Loop-back using AK4114
(2-4) All interface signals including master clock are fed externally
(3) PLL Slave Mode
(3-1) PLL Reference Clock : MCKI pin
(3-1-1) Evaluation of A/D using DIT of AK4114
(3-1-2) Evaluation of Loop-back using AK4114
(3-1-3) All interface signals including master clock are fed externally
(3-2) PLL Reference Clock : BICK or LRCK pin
(3-2-1) Evaluation of A/D using DIT of AK4114
(3-2-2) Evaluation of D/A using DIR of AK4114
(3-2-3) Evaluation of Loop-back using AK4114
(3-2-4) All interface signals including master clock are fed externally
(4) PLL Master Mode
(4-1) Evaluation of A/D using DIT of AK4114
(4-2) Evaluation of Loop-back
(4-3) All interface signals including master clock are fed externally
<KM089000>
2007 / 05
- 3 -
[AKD4671-B]
(1) External Slave Mode
When PMPLL bit is “0”, the AK4671 becomes EXT mode. Master clock is input from MCKI pin, the internal PLL
circuit is not operated. This mode is compatible with I/F of the normal audio CODEC. The clocks required to
operate are MCKI (256fs, 384fs, 512fs, 768fs or 1024fs), LRCK (fs) and BICK (≥32fs). The master clock (MCKI)
should be synchronized with LRCK. The phase between these clocks does not matter. The input frequency of MCKI
is selected by FS1-0 bits.
AK4671
MCKO
DSP or μP
256fs, 384fs, 512fs,
768fs or 1024fs
MCKI
BICK
LRCK
MCLK
BCLK
LRCK
≥ 32fs
1fs
SDTI
SDTO
SDTI
SDTO
(1-1) Evaluation of A/D using DIT of AK4114
X2 (X’tal) and PORT2 (DIT) are used. Nothing should be connected to PORT1 (DIR) and PORT4 (DSP).
The jumper pins should be set as the following.
JP48
M/S
JP46
4114_MCKI
JP36
MCLK
JP33
BICK_SEL
JP38
LRCK_SEL
JP35
PHASE
DIR
EXT
Master Slave
DIR 4040
THR
INV
DIR 4040
(1-2) Evaluation of D/A using DIR of AK4114
PORT1 (DIR) is used. Nothing should be connected to PORT2 (DIT) and PORT4 (DSP).
The jumper pins should be set as the following.
JP48
M/S
JP36
MCLK
JP33
BICK_SEL
JP38
LRCK_SEL
JP51
SDTI_SEL
JP35
PHASE
DIR
EXT
Master Slave
DIR 4040
DIR 4040 DIR ADC THR
INV
<KM089000>
2007 / 05
- 4 -
[AKD4671-B]
(1-3) Evaluation of Loop-back using AK4114 <default>
X2 (X’tal) is used. Nothing should be connected to PORT1 (DIR), PORT2 (DIT) and PORT4 (DSP).
The jumper pins should be set as the following.
JP48
M/S
JP46
4114_MCKI
JP36
MCLK
JP33
BICK_SEL
JP38
LRCK_SEL
JP51
SDTI_SEL
JP35
PHASE
DIR
EXT
Master
Slave
DIR 4040
DIR 4040 DIR
ADC THR
INV
(1-4) Evaluation of Loop-back where master clock is fed externally, BICK and LRCK are generated by
on-board divider.
J12 (EXT) is used . MCLK is supplied from J12 (EXT). BICK and LRCK are generated by 74HC4040 on
AKD4671-B.
Nothing should be connected to PORT1 (DIR), PORT2 (DIT) and PORT4 (DSP).
The jumper pins should be set as the following.
JP48
M/S
JP36
MCLK
JP33
BICK_SEL
JP38
LRCK_SEL
JP51
SDTI_SEL
JP39
EXT
DIR
EXT
Master Slave
DIR 4040 DIR ADC
DIR 4040
When a termination (51Ω) is unnecessary, please set JP39 (EXT) open.
JP32 (MKFS), JP34 (BCFS), and JP37 (LRCK) should be set according to the frequency of MCLK, BICK and
LRCK.
Follows are setting examples in MCLK=256fs , BICK=64fs and LRCK=1fs.
When MCLK=384fs or 768fs, JP32, JP34, and JP37 should be set to “384” side.
.
JP34
JP37
JP32
BCFS
LRCK
MKFS
64fs-384
32fs-384
64fs
fs-384
fs
256fs
512fs
1024fs
384/768fs
32fs
MCKO
(1-5) All interface signals including master clock are fed externally
PORT4 (DSP) is used. Nothing should be connected to PORT1 (DIR) and PORT2 (DIT).
The jumper pins should be set as the following.
JP36
MCLK
JP33
BICK_SEL
JP38
LRCK_SEL
JP51
SDTI_SEL
JP48
M/S
DIR
EXT
DIR 4040
DIR 4040 DIR ADC Maste Slave
<KM089000>
2007 / 05
- 5 -
[AKD4671-B]
(2) External Master Mode
The AK4671 becomes EXT Master Mode by setting PMPLL bit = “0” and M/S bit = “1”. Master clock can be input
via MCKI pin, without using on-chip PLL circuit. The clock required to operate is MCKI (256fs, 384fs, 512fs,
768fs or 1024fs). The input frequency of MCKI is selected by FS1-0 bits.
AK4671
MCKO
DSP or μP
256fs, 384fs, 512fs,
768fs or 1024fs
MCKI
BICK
LRCK
MCLK
BCLK
LRCK
32fs or 64fs
1fs
SDTI
SDTO
SDTI
SDTO
(2-1) Evaluation of A/D using DIT of AK4114
X2 (X’tal) and PORT2 (DIT) are used. Nothing should be connected to PORT1 (DIR) and PORT4 (DSP).
In Master Mode, BICK and LRCK of AK4671 should be input to AK4114. Please refer to Table 2 on page 19.
The jumper pins should be set as the following.
JP46
4114_MCKI
JP48
M/S
JP36
MCLK
JP33
BICK_SEL
JP38
LRCK_SEL
JP35
PHASE
DIR
EXT
Master Slave
DIR 4040
THR
INV
DIR 4040
(2-2) Evaluation of D/A using DIR of AK4114
PORT1 (DIR) is used. Nothing should be connected to PORT2 (DIT) and PORT4 (DSP).
In Master Mode, BICK and LRCK of AK4671 should be input to AK4114. Please refer to Table 2 on page 19.
The jumper pins should be set as the following.
JP48
M/S
JP36
MCLK
JP33
BICK_SEL
JP38
LRCK_SEL
JP51
SDTI_SEL
JP35
PHASE
DIR
EXT
Master Slave
INV
DIR 4040
DIR 4040 DIR ADC THR
<KM089000>
2007 / 05
- 6 -
[AKD4671-B]
(2-3) Evaluation of Loop-back using AK4114
X’tal (X2) is used. Nothing should be connected to PORT1 (DIR), PORT2 (DIT) and PORT4 (DSP).
The jumper pins should be set as the following.
JP36
MCLK
JP33
BICK_SEL
JP38
LRCK_SEL
JP51
SDTI_SEL
JP35
PHASE
DIR
EXT
DIR 4040
DIR 4040 DIR
ADC THR
INV
(2-4) All interface signals including master clock are fed externally
PORT4 (DSP) is used. Nothing should be connected to PORT1 (DIR) and PORT2 (DIT).
The jumper pins should be set as the following.
JP36
MCLK
JP33
BICK_SEL
JP38
LRCK_SEL
JP51
SDTI_SEL
JP48
M/S
DIR
EXT
DIR 4040
DIR 4040 DIR ADC Master Slave
<KM089000>
2007 / 05
- 7 -
[AKD4671-B]
(3) PLL Slave Mode
A reference clock of PLL is selected among the input clocks to MCKI, BICK or LRCK pin. The required clock to
the AK4671 is generated by an internal PLL circuit. Input frequency is selected by PLL3-0 bits.
BICK and LRCK inputs should be synchronized with MCKO output. The phase between MCKO and LRCK dose
not matter. MCKO pin outputs the frequency selected by PS1-0 bits and the output is enabled by MCKO bit.
Sampling frequency can be selected by FS3-0 bits.
(3-1) PLL Reference Clock : MCKI pin
11.2896MHz, 12MHz, 12.288MHz, 13MHz,
13.5MHz, 19.2MHz, 24MHz, 26MHz,
27MHz
AK4671
DSP or μP
MCKI
256fs/128fs/64fs/32fs
MCLK
BCLK
LRCK
MCKO
BICK
≥ 32fs
1fs
LRCK
SDTI
SDTO
SDTI
SDTO
(3-1-1) Evaluation of A/D using DIT of AK4114
J12 (EXT) and PORT2 (DIT) are used. Nothing should be connected to PORT1 (DIR) and PORT4 (DSP).
X’tal oscillator should be removed from X2.
The jumper pins should be set as the following.
JP35
PHASE
JP7
MCKO
JP46
4114_MCKI
JP36
MCLK
JP33
BICK_SEL
JP38
LRCK_SEL
JP39
EXT
DIR
EXT
THR
INV
DIR 4040
DIR 4040
JP48
M/S
Master
Slave
When a termination (51Ω) is unnecessary, please set JP39 (EXT) to open.
<KM089000>
2007 / 05
- 8 -
[AKD4671-B]
(3-1-2) Evaluation of Loop-back using AK4114
J12 (EXT) is used. Nothing should be connected to PORT1 (DIR), PORT2 (DIT) and PORT4 (DSP).
X’tal oscillator should be removed from X2.
The jumper pins should be set as the following.
JP51
SDTI_SEL
JP35
PHASE
JP46
4114_MCKI
JP36
MCLK
JP33
BICK_SEL
JP38
LRCK_SEL
JP39
EXT
DIR
EXT
DIR ADC
THR
INV
DIR 4040
DIR 4040
JP48
M/S
JP7
MCKO
Slave
Master
When a termination (51Ω) is unnecessary, please set JP39 (EXT) open.
(3-1-3) All interface signals including master clock are fed externally
PORT4 (DSP) is used. Nothing should be connected to PORT1 (DIR) and PORT2 (DIT).
The jumper pins should be set as the following.
JP51
SDTI_SEL
JP35
PHASE
JP46
4114_MCKI
JP36
MCLK
JP33
BICK_SEL
JP38
LRCK_SEL
JP39
EXT
DIR
EXT
DIR ADC
THR
INV
DIR 4040
DIR 4040
JP48
M/S
Master
Slave
<KM089000>
2007 / 05
- 9 -
[AKD4671-B]
(3-2) PLL Reference Clock : BICK or LRCK pin
AK4671
MCKO
MCKI
DSP or μP
32fs or 64fs
1fs
BCLK
LRCK
BICK
LRCK
SDTI
SDTO
SDTI
SDTO
(PLL Reference Clock: BICK pin)
AK4671
MCKO
DSP or μP
MCKI
BICK
LRCK
≥ 32fs
BCLK
LRCK
1fs
SDTI
SDTO
SDTI
SDTO
(PLL Reference Clock: LRCK pin)
(3-2-1) Evaluation of A/D using DIT of AK4114
X2 (X’tal) and PORT2 (DIT) are used. Nothing should be connected to PORT1 (DIR) and PORT4 (DSP).
The jumper pins should be set as the following.
JP48
M/S
JP35
PHASE
JP46
4114_MCKI
JP36
MCLK
JP33
BICK_SEL
JP38
LRCK_SEL
JP39
EXT
DIR
EXT
Master Slave
THR
INV
DIR 4040
DIR 4040
<KM089000>
2007 / 05
- 10 -
[AKD4671-B]
(3-2-2) Evaluation of D/A using DIR of AK4114
PORT1 (DIR) is used. Nothing should be connected to PORT2 (DIT) and PORT4 (DSP).
The jumper pins should be set as the following.
JP51
SDTI_SEL
JP35
PHASE
JP46
4114_MCKI
JP36
MCLK
JP33
BICK_SEL
JP38
LRCK_SEL
JP39
EXT
DIR
EXT
DIR ADC
THR
INV
DIR 4040
DIR 4040
JP48
M/S
Master
Slave
(3-2-3) Evaluation of Loop-back using AK4114
X2 (X’tal) is used. Nothing should be connected to PORT1 (DIR), PORT2 (DIT) and PORT4 (DSP).
The jumper pins should be set as the following.
JP51
SDTI_SEL
JP35
PHASE
JP46
4114_MCKI
JP36
MCLK
JP33
BICK_SEL
JP38
LRCK_SEL
JP39
EXT
DIR
EXT
DIR ADC
THR
INV
DIR 4040
DIR 4040
JP48
M/S
Master
Slave
(3-2-4) All interface signals including master clock are fed externally
PORT4 (DSP) is used. Nothing should be connected to PORT1 (DIR) and PORT2 (DIT).
The jumper pins should be set as the following.
JP51
SDTI_SEL
JP35
PHASE
JP46
4114_MCKI
JP36
MCLK
JP33
BICK_SEL
JP38
LRCK_SEL
JP39
EXT
DIR
EXT
DIR ADC
THR
INV
DIR 4040
DIR 4040
JP48
M/S
Master
Slave
<KM089000>
2007 / 05
- 11 -
[AKD4671-B]
(4) PLL Master Mode
When an external clock (11.2896MHz, 12MHz, 12.288MHz, 13MHz, 13.5MHz, 19.2MHz, 24MHz, 26MHz or
27MHz) is input to MCKI pin, the MCKO, BICK and LRCK clocks are generated by an internal PLL circuit. The
MCKO output frequency is selected by PS1-0 bits and the output is enabled by MCKO bit. The BICK output
frequency is selected between 32fs or 64fs, by BCKO bit.
11.2896MHz, 12MHz, 12.288MHz, 13MHz,
13.5MHz, 19.2MHz, 24MHz, 26MHz,
27MHz
AK4671
DSP or μP
MCKI
256fs/128fs/64fs/32fs
MCLK
BCLK
LRCK
MCKO
BICK
32fs, 64fs
1fs
LRCK
SDTI
SDTO
SDTI
SDTO
(4-1) Evaluation of A/D using DIT of AK4114
J12 (EXT) and PORT2 (DIT) are used. Nothing should be connected to PORT1 (DIR) and PORT4 (DSP).
X’tal oscillator should be removed from X2.
In Master Mode, BICK and LRCK of AK4671 should be input to AK4114. Please refer to Table 2 on page 19.
The jumper pins should be set as the following.
JP7
MCKO
JP35
PHASE
JP46
4114_MCKI
JP36
MCLK
JP33
BICK_SEL
JP38
LRCK_SEL
JP39
EXT
DIR
EXT
THR
INV
DIR 4040
DIR 4040
JP48
M/S
Master
Slave
When a termination (51Ω) is unnecessary, please set JP39 (EXT) open.
<KM089000>
2007 / 05
- 12 -
[AKD4671-B]
(4-2) Evaluation of Loop-back
J12 (EXT) is used. Nothing should be connected to PORT1 (DIR), PORT2 (DIT) and PORT4 (DSP).
X’tal oscillator should be removed from X2.
The jumper pins should be set as the following.
JP51
SDTI_SEL
JP35
PHASE
JP46
4114_MCKI
JP36
MCLK
JP33
BICK_SEL
JP38
LRCK_SEL
JP39
EXT
DIR
EXT
DIR ADC
THR
INV
DIR 4040
DIR 4040
JP48
M/S
Master
Slave
When a termination (51Ω) is unnecessary, please set JP39 (EXT) open.
(4-3) All interface signals including master clock are fed externally
PORT4 (DSP) is used. Nothing should be connected to PORT1 (DIR) and PORT2 (DIT).
The jumper pins should be set as the following.
JP51
SDTI_SEL
JP35
PHASE
JP46
4114_MCKI
JP36
MCLK
JP33
BICK_SEL
JP38
LRCK_SEL
JP39
EXT
DIR
EXT
DIR ADC
THR
INV
DIR 4040
DIR 4040
JP48
M/S
Master
Slave
<KM089000>
2007 / 05
- 13 -
[AKD4671-B]
2. PCM I/F evaluation mode
A reference clock of PLLBT is selected among the input clocks to SYNCA, BICKA, SYNCB or BICKB pin.
The required clock to PCM I/F is generated by an internal PLLBT circuit. PLLBT circuit is powered up by
PMPCM bit. Input frequency is selected by PLLBT2-0 bits. BCKO2 bit select the output clock frequency of
BICKA or BICKB pin.
AK4671 does not support master mode for both PCM I/F A and B nor slave mode
for both PCM I/F A and B. When PMPCM bit is “0”, SYNCA, BICKA, SYNCB and BICKB pins are Hi-Z.
(1) PLLBT reference clock: SYNCA or BICKA pin
(1-1) SYNCA and BICKA are fed from on-board clock generator.
(1-2) SYNCA and BICKA are fed externally via PORT3 (Baseband Module).
(2) PLLBT reference clock: SYNCB or BICKB pin
(2-1) SYNCB and BICKB are fed from on-board clock generator.
(2-2) SYNCB and BICKB are fed externally via PORT6 (Bluetooth Module).
<KM089000>
2007 / 05
- 14 -
[AKD4671-B]
(1) PLLBT reference clock: SYNCA or BICKA pin
The PLLBT circuit generates the required clock for PCM I/F from SYNCA or BICKA. Generated clocks are output
via SYNCB and BICKB pins.
AK4671
Baseband Module
1fs2
SYNCA
SYNC
≥ 16fs2
BICK
SDTI
SDTO
BICKA
SDTOA
SDTIA
Bluetooth Module
1fs2
SYNC
SYNCB
16fs2 or 32fs2
BICK
SDTI
SDTO
BICKB
SDTOB
SDTIB
(PLLBT Reference Clock: SYNCA or BICKA pin)
(1-1) SYNCA and BICKA are fed from on-board clock generator.
X1 (X’tal), PORT3 (Baseband Module) and PORT6 (Bluetooth Module) are used.
The jumper pins should be set as the following.
Please set JP42 (BCFS2) to the required frequency. Follows are setting in BICKA=32fs.
When clocks are supplied from J13 (EXT1) without using X1, JP41 (MCLK2) should be set to “EXT1”.
JP49
PLLBT
JP42
BCFS2
JP41
MCLK2
JP43
BICK2_SEL
JP45
LRCK2_SEL
JP40
XTE
256fs2
128fs2
64fs2
32fs2
16fs2
XTL
EXT1
BICKA BICKB
BICKA BICKB
LRCKA LRCKB
JP61
SDTIB
JP65
SYNCB
JP60
SDTIA
JP63
SYNCA
JP64
BICKB
JP62
BICKA
<KM089000>
2007 / 05
- 15 -
[AKD4671-B]
JP47 (BICKA PHASE) is jumper which decides polarity of BICKA, “THR” or “INV” should be selected
according to the PCM I/F format.
JP54 (BICKB PHASE) should be set to “THR”.
JP47
BICKA PHASE
JP54
BICKB PHASE
THR
INV
THR
INV
In case of loop-back “SDTOA → SDTIA” and “SDTOB → SDTIB”, please set JP50 (SDTOA LOOP) and
JP55 (SDTOB LOOP) short.
JP50
SDTOA LOOP
JP55
SDTOB LOOP
(1-2) SYNCA and BICKA are fed externally via PORT3 (Baseband Module).
PORT3 (Baseband Module) and PORT6 (Bluetooth Module) are used.
SYNCA and BICKA should be supplied from PORT3.
The jumper pins should be set as the following.
JP49
PLLBT
JP41
MCLK2
JP43
BICK2_SEL
JP45
LRCK2_SEL
JP40
XTE
XTL
EXT1
BICKA BICKB
BICKA BICKB
LRCKA LRCKB
JP47 (BICKA PHASE) is jumper which decides polarity of BICKA, “THR” or “INV” should be selected
according to the PCM I/F format.
JP54 (BICKB PHASE) should be set to “THR”.
JP47
BICKA PHASE
JP54
BICKB PHASE
THR
INV
THR
INV
<KM089000>
2007 / 05
- 16 -
[AKD4671-B]
(2) PLLBT reference clock: SYNCB or BICKB pin
The PLLBT circuit generates the required clock for PCM I/F from SYNCB or BICKB. Generated clocks are output
via SYNCA and BICKA pins.
AK4671
Baseband Module
1fs2
SYNCA
SYNC
16fs2 or 32fs2
BICK
SDTI
SDTO
BICKA
SDTOA
SDTIA
Bluetooth Module
1fs2
SYNC
SYNCB
≥ 16fs2
BICK
SDTI
SDTO
BICKB
SDTOB
SDTIB
(PLLBT Reference Clock: SYNCB or BICKB pin)
(2-1) SYNCB and BICKB are fed from on-board clock generator.
X1 (X’tal), PORT3 (Baseband Module) and PORT6 (Bluetooth Module) are used.
The jumper pins should be set as the following.
Please set JP42 (BCFS2) to the required frequency. Follows are setting in BICKB=32fs.
When clocks are supplied from J13 (EXT1) without using X1, JP41 (MCLK2) should be set to “EXT1”.
JP49
PLLBT
JP42
BCFS2
JP41
MCLK2
JP43
BICK2_SEL
JP45
LRCK2_SEL
JP40
XTE
256fs2
128fs2
64fs2
32fs2
16fs2
XTL
EXT1
BICKA BICKB
BICKA BICKB
LRCKA LRCKB
JP61
SDTIB
JP65
SYNCB
JP60
SDTIA
JP63
SYNCA
JP64
BICKB
JP62
BICKA
<KM089000>
2007 / 05
- 17 -
[AKD4671-B]
JP54 (BICKB PHASE) is jumper which decides polarity of BICKB, “THR” or “INV” should be selected
according to the PCM I/F format.
JP47 (BICKA PHASE) should be set to “THR”.
JP47
BICKA PHASE
JP54
BICKB PHASE
THR
INV
THR
INV
In case of loop-back “SDTOA → SDTIA” and “SDTOB → SDTIB”, please set JP50 (SDTOA LOOP) and
JP55 (SDTOB LOOP) short.
JP50
SDTOA LOOP
JP55
SDTOB LOOP
(2-2) SYNCB and BICKB are fed externally via PORT6 (Bluetooth Module).
PORT3 (Baseband Module) and PORT6 (Bluetooth Module) are used.
Please supply SYNCB and BICKB from PORT6.
The jumper pins should be set as the following.
JP49
PLLBT
JP41
MCLK2
JP43
BICK2_SEL
JP45
LRCK2_SEL
JP40
XTE
XTL
EXT1
BICKA BICKB
BICKA BICKB
LRCKA LRCKB
JP54 (BICKB PHASE) is jumper which decides polarity of BICKB, “THR” or “INV” should be selected
according to the PCM I/F format.
JP47 (BICKA PHASE) should be set to “THR”.
JP47
BICKA PHASE
JP54
BICKB PHASE
THR
INV
THR
INV
<KM089000>
2007 / 05
- 18 -
[AKD4671-B]
DIP Switch set up
[S1] (SW DIP-6): Mode setting for AK4671 and AK4114.
No.
1
2
3
4
Name
DIF2
DIF1
ON (“H”)
OFF (“L”)
Default
ON
OFF
OFF
OFF
OFF
ON
AK4114 Audio Format Setting
See Table 2
DIF0
OCKS1
CAD0
I2C
AK4114 Master Clock Setting : See Table 3
AK4671 Control Mode Setting
See Table 4
5
6
Table 1. Mode Setting for AK4671 and AK4114
DIF2 DIF1 DIF0
DAUX
SDTO
LRCK
BICK
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
24bit, Left justified
24bit, Left justified
24bit, Left justified
24bit, Left justified
24bit, Left justified
24bit, I2S
16bit, Right justified H/L
18bit, Right justified H/L
20bit, Right justified H/L
24bit, Right justified H/L
O
O
O
O
O
O
I
64fs
64fs
64fs
64fs
64fs
64fs
64-128fs
64-128fs
O
O
O
O
O
O
I
24bit, Left justified
H/L
L/H
H/L
L/H
Default
24bit, I2S
24bit, Left justified
24bit, Left justified
24bit, I2S
24bit, I2S
I
I
Table 2. Setting for AK4114 Audio Interface Format
OCKS1
MCKO1
256fs
512fs
X’tal
256fs
512fs
Default
0
1
Table 3. Setting for AK4114 Master Clock
<KM089000>
2007 / 05
- 19 -
[AKD4671-B]
Other jumper pins set up
Sub Board
[JP1] (RIN2) : RIN2 input.
GND :
In case of full-differential input.
MPWR :
OPEN :
MIC-power is supplied to RIN2.
MIC-power is not supplied to RIN2. <Default>
[JP2] (LIN1) : LIN1 input.
SHORT :
OPEN :
MIC-power is supplied to LIN1.
MIC-power is not supplied to LIN1. <Default>
[JP3] (LIN2) : LIN2 input.
SHORT :
OPEN :
MIC-power is supplied to LIN2.
MIC-power is not supplied to LIN2. <Default>
[JP4] (RIN1) : RIN1 input.
GND :
In case of full-differential input.
MPWR :
OPEN :
MIC-power is supplied to RIN1.
MIC-power is not supplied to RIN1. <Default>
[JP5] (PVDD) : PVDD of AK4212 power supply.
SHORT :
OPEN :
PVDD is supplied from “PVDD” jack. <Default>
PVDD is not supplied from “PVDD” jack
[JP6] (PDN) : PDN of AK4212.
SHORT :
OPEN :
PDN is supplied from SW2 (PDN). <Default>
PDN is not supplied from SW2 (PDN).
[JP7] (MCKO) : MCKO output.
SHORT :
OPEN :
When AK4671 outputs MCKO. <Default>
When AK4671 does not output MCKO.
[JP8] (SDA) : SDA of AK4212.
SHORT :
OPEN :
SDA is supplied from PORT5 (CTRL). <Default>
SDA is not supplied from PORT5 (CTRL).
[JP9] (SCL) : SCL of AK4212.
SHORT :
OPEN :
SCL is supplied from PORT5 (CTRL). <Default>
SCL is not supplied from PORT5 (CTRL).
[JP10] (TVDD) : TVDD of AK4212 power supply.
SHORT :
OPEN :
TVDD is supplied from “DVDD” jack. <Default>
TVDD is not supplied from “DVDD” jack
[JP11] (AVDD) : AVDD of AK4212 power supply.
SHORT :
OPEN :
AVDD is supplied from “AVDD” jack. <Default>
AVDD is not supplied from “AVDD” jack
[JP12] (U2 RIN1) : RIN1 of AK4212 input
SHORT :
OPEN :
RIN1 is supplied from ROUT2. <Default>
RIN1 is not supplied from ROUT2.
[JP13] (U2 LIN1) : LIN1 of AK4212.
SHORT :
OPEN :
LIN1 is supplied from LOUT2. <Default>
LIN1 is not supplied from LOUT2.
<KM089000>
2007 / 05
- 20 -
[AKD4671-B]
[JP14] (U2 SPRIN) : SPRIN of AK4212.
SHORT :
OPEN :
SPRIN is supplied from ROUT3. <Default>
SPRIN is not supplied from ROUT3.
[JP15] (U2 SPLIN) : SPLIN of AK4212.
SHORT :
OPEN :
SPLIN is supplied from LOUT3. <Default>
SPLIN is not supplied from LOUT3.
Main Board
[JP30] (GND) : AGND and DGND.
SHORT:
OPEN :
Common. <Default>
Separated.
[JP46] (4114_MCKI) : MCKI of AK4114.
SHORT:
OPEN :
MCKO of AK4671.
X’tal (X2). <Default>
[JP56] (D3V) : Power supply of PORT7
SHORT :
OPEN :
It is supplied from “D3V” jack.
It is not supplied from “D3V” jack. <Default>
[JP57] (I2C PIN) : AK4671 I2C input.
I2C :
MCLK2 :
It is supplied from S1 (I2C). <Default>
It is supplied from MCLK2.
<KM089000>
2007 / 05
- 21 -
[AKD4671-B]
The function of the toggle SW
[SW2] (PDN) : Power down of AK4671. Keep “H” during normal operation.
[SW1] (DIR) : Power down of AK4114. Keep “H” during normal operation.
Keep “L” when AK4114 is not used.
Indication for LED
[LED1] (ERF) : Monitor INT0 pin of the AK4114. LED turns on when some error has occurred to AK4114.
Serial Control
The AK4671 can be controlled via the printer port (parallel port) of IBM-AT compatible PC. Connect PORT5
(CTRL) with PC by 10 wire flat cable packed with the AKD4671.Table 4 shows switch and jumper settings for
serial control. I2C Mode should be selected in Table 4.
Note) When evaluate it in SAR-ADC of AK4671, 4-WIRE Mode should be selected in Table 4.
PORT5
CSN
Connect
CCLK/SCL
PC
CDTI/SDA AKD4671
CDTO/SDA
10 wire
flat cable Connector
Figure 2. Connect of 10 wire flat cable
10pin
10pin
Header
Mode
S1 (DIP SW)
JP52
CTRL_SEL
4-WIRE
JP53
CTRL_SEL2
4-WIRE
I2C
OFF
ON
CAD0
OFF
OFF
ON
4-WIRE
CAD0=0
CAD0=1
Default
I2C
I2C
I2C
ON
Table 4. Serial Control Setting
<KM089000>
2007 / 05
- 22 -
[AKD4671-B]
Analog Input/Output Circuits
(1) Input Circuits
(1-1) LIN1/RIN1, LIN2/RIN2, LIN3/RIN3 and LIN4/RIN4 Input Circuit
J2
1
LIN1
RIN1
2
3
LIN1/RIN1
LIN2
LIN3
JP23
C50
1u
R39
(short)
J5
LIN
LIN2
LIN3
LIN4
2
3
4
5
1
LIN_SEL
JP25
LIN4
RIN2
C53
1u
R42
(short)
J7
RIN
RIN2
RIN3
RIN4
2
3
4
5
1
RIN3
RIN4
RIN_SEL
Figure 3. LIN1/RIN1, LIN2/RIN2, LIN3/RIN3 and LIN4/RIN4 Input Circuit
LIN2/RIN2, LIN3/RIN3 and LIN4/RIN4 share J5/J7.
JP23 (LIN_SEL) and JP25 (RIN_SEL) select each path.
(1-2) SAIN1, SAIN2 and SAIN3 Input Circuit
SAIN1
JP28
J9
SAIN
SAIN1
SAIN2
SAIN3
2
3
4
5
1
SAIN2
SAIN3
SAIN_SEL
J11
SAIN3
2
3
4
5
1
Figure 4. SAIN1, SAIN2 and SAIN3 Input Circuit
SAIN1, SAIN2 and SAIN3 share J9.
JP28 (SAIN_SEL) select each path.
<KM089000>
2007 / 05
- 23 -
[AKD4671-B]
(2) Output Circuits
(2-1) LOUT1/ROUT1, LOUT2/ROUT2 and LOUT3/ROUT3 Output Circuit
JP16
R32
LOUT3
LOUT2
LOUT1
J1
LOUT
LOUT3
LOUT2
LOUT1
220
1
2
3
4
5
C44
1u
R33
20k
LOUT_SEL
JP17
HPL JACK
R34
(short)
C45
100u
R35
16
J3
1
JP58
L_16ohm
2
3
HP
JP19
HPR JACK
R37
(short)
C47
100u
R36
16
JP59
R_16ohm
JP21
R38
220
ROUT3
ROUT2
ROUT1
J4
ROUT3
ROUT
1
2
ROUT2
ROUT1
3
4
5
C49
1u
R40
20k
ROUT_SEL
Figure 5. LOUT1/ROUT1, LOUT2/ROUT2 and LOUT3/ROUT3 Output Circuit
LOUT1/ROUT1, LOUT2/ROUT2 and LOUT3/ROUT3 share J1/J4.
JP16 (LOUT_SEL) and JP21 (ROUT_SEL) select each path.
(2-2) Headphone of AK4212 Output Circuit
JP13 (U2LIN1) and JP12 (U2RIN1) on sub board should be shorted, and LOUT2S and ROUT2S signal should
be input to Headphone-Amp block of AK4212.
JP13
U2LIN1
JP12
U2RIN1
R43
HPL
HPR
J10
(short)
1
R44
2
3
(short)
4212 HP
Figure 6. Headphone of AK4212 Output Circuit
<KM089000>
2007 / 05
- 24 -
[AKD4671-B]
(2-3) Speaker of AK4212 Output Circuit
JP15 (U2SPLIN) and JP14 (U2SPRIN) on sub board should be shorted, and LOUT3 and ROUT3 signal
should be input to Speaker-Amp block of AK4212.
JP15
U2SPLIN
JP14
U2SPRIN
LOUTP
LOUTN
ROUTP
ROUTN
J6
1
2
3
SPK_L
J8
1
2
3
SPK_R
Figure 7. Speaker of AK4212 Output Circuit
* AKM assumes no responsibility for the trouble when using the above circuit examples.
<KM089000>
2007 / 05
- 25 -
[AKD4671-B]
Control Software Manual
Set-up of evaluation board and control software
1. Set up the AKD4671-B according to previous term.
2. Connect IBM-AT compatible PC with AKD4671-B by 10-line type flat cable (packed with AKD4671-B). Take
care of the direction of 10pin header. (Please install the driver in the CD-ROM when this control software is used
on Windows 2000/XP. Please refer “Installation Manual of Control Software Driver by AKM device control
software”. In case of Windows95/98/ME, this installation is not needed. This control software does not operate
on Windows NT.)
3. Insert the CD-ROM labeled “AKD4671-B Evaluation Kit” into the CD-ROM drive.
4. Access the CD-ROM drive and double-click the icon of “AKD4671.exe” and “AKD4212 .exe” to set up the
control program. In case of evaluation using AK4212, “AKD4212 .exe” is necessary.
5. Then please evaluate according to the follows.
Operation flow
Keep the following flow.
1. Set up the control program according to explanation above.
2. Click “Port Reset” button.
3. Click “Write default” button
Explanation of each buttons
[Port Reset] :
[Write default] :
[All Write] :
[Function1] :
[Function2] :
[Function3] :
[Function4] :
[Function5]:
Set up the USB interface board (AKDUSBIF-A) .
Initialize the register of AK4671.
Write all registers that is currently displayed.
Dialog to write data by keyboard operation.
Dialog to write data by keyboard operation.
The sequence of register setting can be set and executed.
The sequence that is created on [Function3] can be assigned to buttons and executed.
The register setting that is created by [SAVE] function on main window can be assigned to
buttons and executed.
[SAVE] :
[OPEN] :
[Write] :
Save the current register setting.
Write the saved values to all register.
Dialog to write data by mouse operation.
[Filter] :
[5 Band EQ] :
Set Programmable Filter (FIL1, FIL3, EQ) of AK4671 easily.
Set 5Band Equalizer of AK4671 easily.
Indication of data
Input data is indicated on the register map. Red letter indicates “H” or “1” and blue one indicates “L” or “0”. Blank
is the part that is not defined in the datasheet.
<KM089000>
2007 / 05
- 26 -
[AKD4671-B]
Explanation of each dialog
1. [Write Dialog] : Dialog to write data by mouse operation
There are dialogs corresponding to each register.
Click the [Write] button corresponding to each register to set up the dialog. If you check the check box, data
becomes “H” or “1”. If not, “L” or “0”.
If you want to write the input data to AK4671, click [OK] button. If not, click [Cancel] button.
2. [Function1 Dialog] : Dialog to write data by keyboard operation
Address Box: Input registers address in 2 figures of hexadecimal.
Data Box:
Input registers data in 2 figures of hexadecimal.
If you want to write the input data to AK4671, click [OK] button. If not, click [Cancel] button.
3. [Function2 Dialog] : Dialog to evaluate DATT
Address Box:
Start Data Box:
End Data Box:
Interval Box:
Step Box:
Input registers address in 2 figures of hexadecimal.
Input starts data in 2 figures of hexadecimal.
Input end data in 2 figures of hexadecimal.
Data is written to AK4671 by this interval.
Data changes by this step.
Mode Select Box:
If you check this check box, data reaches end data, and returns to start data.
[Example] Start Data = 00, End Data = 09
Data flow: 00 01 02 03 04 05 06 07 08 09 09 08 07 06 05 04 03 02 01 00
If you do not check this check box, data reaches end data, but does not return to start data.
[Example] Start Data = 00, End Data = 09
Data flow: 00 01 02 03 04 05 06 07 08 09
If you want to write the input data to AK4671, click [OK] button. If not, click [Cancel] button.
<KM089000>
2007 / 05
- 27 -
[AKD4671-B]
4. [Save] and [Open]
4-1. [Save]
Save the current register setting data. The extension of file name is “akr”.
<Operation flow>
(1) Click [Save] Button.
(2) Set the file name and push [Save] Button. The extension of file name is “akr”.
4-2. [Open]
The register setting data saved by [Save] is written to AK4671. The file type is the same as [Save].
<Operation flow>
(1) Click [Open] Button.
(2) Select the file (*.akr) and Click [Open] Button.
<KM089000>
2007 / 05
- 28 -
[AKD4671-B]
5. [Function3 Dialog]
The sequence of register setting can be set and executed.
(1) Click [F3] Button.
(2) Set the control sequence.
Set the address, Data and Interval time. Set “-1” to the address of the step where the sequence should be
paused.
(3) Click [Start] button. Then this sequence is executed.
The sequence is paused at the step of Interval="-1". Click [START] button, the sequence restarts from the paused
step.
This sequence can be saved and opened by [Save] and [Open] button on the Function3 window. The extension of file
name is “aks”.
Figure 8. Window of [F3]
<KM089000>
2007 / 05
- 29 -
[AKD4671-B]
6. [Function4 Dialog]
The sequence that is created on [Function3] can be assigned to buttons and executed. When [F4] button is clicked,
the window as shown in Figure 9. opens.
Figure 9. [F4] window
<KM089000>
2007 / 05
- 30 -
[AKD4671-B]
6-1. [OPEN] buttons on left side and [START] buttons
(1) Click [OPEN] button and select the sequence file (*.aks).
The sequence file name is displayed as shown in Figure 10.
Figure 10. [F4] window (2)
(2) Click [START] button, then the sequence is executed.
6-2. [SAVE] and [OPEN] buttons on right side
[SAVE] : The sequence file names can assign be saved. The file name is *.ak4.
[OPEN] : The sequence file names assign that are saved in *.ak4 are loaded.
6-3. Note
(1) This function doesn't support the pause function of sequence function.
(2) All files need to be in same folder used by [SAVE] and [OPEN] function on right side.
(3) When the sequence is changed in [Function3], the file should be loaded again in order to reflect the change.
<KM089000>
2007 / 05
- 31 -
[AKD4671-B]
7. [Function5 Dialog]
The register setting that is created by [SAVE] function on main window can be assigned to buttons and executed.
When [F5] button is clicked, the following window as shown in Figure 11.opens.
Figure 11. [F5] window
7-1. [OPEN] buttons on left side and [WRITE] button
(1) Click [OPEN] button and select the register setting file (*.akr).
The register setting file name is displayed as shown in Figure 12.
(2) Click [WRITE] button, then the register setting is executed.
<KM089000>
2007 / 05
- 32 -
[AKD4671-B]
Figure 12. [F5] windows(2)
7-2. [SAVE] and [OPEN] buttons on right side
[SAVE] : The register setting file names assign can be saved. The file name is *.ak5.
[OPEN] : The register setting file names assign that are saved in *.ak5 are loaded.
7-3. Note
(1) All files need to be in same folder used by [SAVE] and [OPEN] function on right side.
(2) When the register setting is changed by [Save] Button in main window, the file should be loaded again in order to
reflect the change.
<KM089000>
2007 / 05
- 33 -
[AKD4671-B]
8. [Filter Dialog]
This dialog can easily set the AK4671’s programmable filter.
A calculation of a coefficient of Digital Programmable Filter such as HPF,EQ filter ,a write to a register and check
frequency response.
Window to show to Figure 13 opens when push a [Filter] button .
Figure 13. [Filter] window
<KM089000>
2007 / 05
- 34 -
[AKD4671-B]
8-1. Setting of a parameter
(1) Please set a parameter of each Filter.
Item
Contents
Sampling frequency (fs)
Setting range
7350Hz ≤ fs ≤ 48000Hz
Sampling Rate
FIL3
Cut Off Frequency
Stereo separation emphasis filter cut off fs/10000 ≤ Cut Off Frequency ≤
frequency
(0.497 * fs)
Filter type
Gain
Type of stereo separation emphasis filter
Gain of stereo separation emphasis filter
LPF or HPF
–10dB ≤ Gain ≤ 0dB
HPF
Cut Off Frequency
High pass filter cut off frequency
Low pass filter cut off frequency
fs/10000 ≤ Cut Off Frequency
≤ (0.497 * fs)
LPF
Cut Off Frequency
fs/20 ≤ Cut Off Frequency ≤
(0.497 * fs)
EQ for Gain Compensation (EQ0)
Pole Frequency
Pole Frequency
Zero-point Frequency
Gain
fs/10000 ≤ Pole Frequency ≤
(0.497 * fs)
fs/10000 ≤ Zero-point Frequency
≤ (0.497 * fs)
Zero-point Frequency
Gain
0dB ≤ Gain ≤ +12dB
5 Band Equalizer
EQ1-5 Center Frequency
EQ1-5 Center Frequency
0Hz ≤ Center Frequency < (0.497
* fs)
EQ1-5 Band Width
EQ1-5 Gain
EQ1-5 Band Width
EQ1-5 Gain
(
Note 1)
1Hz ≤ Band Width < (0.497 * fs)
-1≤ Gain < 3
(
Note 2)
Note 1. Bandwidth where the gain gap is 3dB compared with center frequency.
Note 2. When a gain is smaller than "0", EQ becomes a notch filter.
(2) Please set ON/OFF of Filter with check buttons of “FIL3”, “EQ0”, “LPF”, “HPF”, “HPFAD”, “EQ1”, “EQ2”,
“EQ3”, “EQ4”, “EQ5”. When the button is checked, Filter becomes ON. When “Notch Filter Auto Correction”
is checked, automatic compensation is executed for center frequency of notch filter.
(“Cf. 8-4. automatic compensation for center frequency of a notch filter”)
Figure14. Filter ON/OFF setting button
<KM089000>
2007 / 05
- 35 -
[AKD4671-B]
8-2. A calculation of a register
A register setting values are displayed when [Register Setting] button is clicked. When any value is set to out of
range, error message is displayed, and a calculation of register setting is not executed.
Figure15. A register setting calculation result
In the following cases, a register set values are updated.
(1) When [Register Setting] button was pushed.
(2) When [Frequency Response] button was pushed.
(3) When [UpDate] button was pushed on a frequency characteristic indication window.
(4) When set ON/OFF of a check button “Notch Filter Auto Correction”
<KM089000>
2007 / 05
- 36 -
[AKD4671-B]
8-3.Indication of a frequency characteristic
A frequency characteristic is displayed when [Frequency Response] button is clicked. The register values are
updated at the same time.
If "Frequency Range" is changed, and [UpDate] button is clicked, indication of a frequency characteristic is
updated.
Figure16. A frequency characteristic indication result
In the following cases, a register set values are updated.
(1) When [Register Setting] button was pushed.
(2) When [Frequency Response] button was pushed.
(3) When [UpDate] button was pushed on a frequency characteristic indication window.
(4) When set ON/OFF of a check button “Notch Filter Auto Correction”
8-4. Automatic compensation for center frequency of a notch filter
When a gain of 5 band Equalizer is set to "-1", Equalizer becomes a notch filter. When center frequency of several
notch filters are near frequency each other, center frequency error occurs (Figure 17).
When "Notch Filter Auto Correction" button is checked, automatic compensation is executed for center frequency
of a notch filter.
Register setting and frequency characteristics are displayed after automatic compensation (Figure18).
This automatic compensation is available for EqualizerBand where a gain is set to "-1".
(Note) When distance among center frequencies is smaller than band width, there is a possibility that automatic
compensation does not operate normally. Please confirm a compensation result by indication of a frequency
characteristic.
<KM089000>
2007 / 05
- 37 -
[AKD4671-B]
Setting of center frequency: 4400Hz, 5000Hz, 5400Hz / Band Width : 200Hz(3 band common)
Figure17. When there is no compensation of center frequency
Setting of center frequency: 4400Hz, 5000Hz, 5400Hz / Band Width : 200Hz(3 band common)
Figure18. When there is compensation of center frequency
<KM089000>
2007 / 05
- 38 -
[AKD4671-B]
9. [5 Band EQ Dialog]
This dialog can easily set the AK4671’s 5-Band Equalizer.
Figure 19. [5 Band EQ] window
When the check box of “5 Band EQ” is checked, 5-Band Equalizer is ON (EQ bit = ”1”).
When the slide button is changed, its value is written to the internal register immediately.
<KM089000>
2007 / 05
- 39 -
[AKD4671-B]
Revision History
Date
Manual
Board
Reason
Contents
(YY/MM/DD)
Revision
Revision
First
Edition
07/05/15
KM089000
0
IMPORTANT NOTICE
• These products and their specifications are subject to change without notice. Before considering any
use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized
distributor concerning their current status.
• AKM assumes no liability for infringement of any patent, intellectual property, or other right in the
application or use of any information contained herein.
• Any export of these products, or devices or systems containing them, may require an export license
or other official approval under the law and regulations of the country of export pertaining to customs
and tariffs, currency exchange, or strategic materials.
• AKM products are neither intended nor authorized for use as critical components in any safety, life
support, or other hazard related device or system, and AKM assumes no responsibility relating to
any such use, except with the express written consent of the Representative Director of AKM. As
used here:
(a) A hazard related device or system is one designed or intended for life support or maintenance of
safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its
failure to function or perform may reasonably be expected to result in loss of life or in significant
injury or damage to person or property.
(b) A critical component is one whose failure to function or perform may reasonably be expected to
result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or
system containing it, and which must therefore meet very high standards of performance and
reliability.
• It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or
otherwise places the product with a third party to notify that party in advance of the above content
and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability
for and hold AKM harmless from any and all claims arising from the use of said product in the
absence of such notification.
<KM089000>
2007 / 05
- 40 -
A
B
C
D
E
4670_TVDD2
4670_PVDD
SAIN1 SAIN2 SAIN3
LIN1 RIN1 LIN2 RIN2 LIN3 RIN3 LIN4 RIN4
4670_AVDD
80pin_4
CN4
TP9
TP10 TP11
TP1
TP2
TP3
TP4
TP5
TP6
TP7
TP8
SAIN1 SAIN2 SAIN3
LIN1 RIN1 LIN2 RIN2 LIN3 RIN3 LIN4 RIN4
JP1
RIN2
AVDD
GND
E
D
C
B
A
E
D
C
B
A
R1
MPWR
CN3
R2
2.2k
SPLIN
JP3LIN2
JP2LIN1
TP18
JP4
RIN1
LOUT3
R3
2.2k
GND
LOUT3
ROUT3
LOUT2
ROUT2
LOUT1
ROUT1
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
TP19
ROUT3
MPWR
R4
2.2k
TP16
LOUT2
2.2k
TP45
VSS1 AVDD
TP46
SPRIN
TP15
ROUT2
TP40
MPWR
TP12
LOUT1
TP13
ROUT1
R5
open
C2
1u
C3
1u
C39
10u
U1
C36
0.1u
TP21
HPR
MDT
TP41
TP34
TEST
HPR
HPL
CN1
A1
A9
MDT
TEST
1
2
TP23
HPL
B1
C1
C2
D1
D2
E1
E2
F2
F1
G2
G1
H1
J1
B9
C9
C8
MPWR
SAIN3
SAIN2
SAIN1
SAVDD
VSS3
LOUT2
ROUT2
MUTET
VCOM
VCOC
C7
JP5
TP24
SAVDD
TP22
MUTET
PVDD
C10
4670_SAVDD
3
10u
C8 C9
C6
1u
PDN
JP6
4
TP44
VCOM
PDN
2.2u 0.1u
2.2u
C35
D9 0.1u
2.2u
C38
+
U2
5
TP43
VCOC
R16
D8
17
18
19
20
21
22
23
24
8
7
6
5
4
3
2
1
6
TP26
VSS3
LIN4/IN4-
RIN3/IN3+
LIN3/IN3-
VREF
PDN
CDTI/SDA
CCLK/SCL
TVDD
+
C12
10u
C13
0.1u
TP20
VCOCBT
51
R18
E9
JP8
VCOCBT
PVDD
R19
220k
SDA
7
TP27
+
TP25
LOUTN
4670_TVDD3
4670_SDTOB
C17
10u
C16
0.1u
TP14
PVDD
R6
10k
R27
10k
SDA
JP9
TVDD3
51
R20
AK4671
E8
LOUTN
LOUTP
TVDD3
SDTOB
SYNCB
BICKB
SDTIB
SDTI
SCL
8
+
C5
0.1u
C4
10u
TP17
VSS2
C1
4.7n
C40
4.7n
51
SCL
TP59
C14
+
C15
0.1u
R13
SDTOB
F9
F8
G9
H9
G8
J8
JP10
VSS2
2.2u
9
TP29
LOUTP
DVDD
AVDD
51
C20
0.1u
C21
10u
TP58
+
TP28
TVDD2
C18
0.1u
C19
10u
TVDD
SYNCB
+
R12
51
AK4212
TVDD2
SDTOA
SYNCA
BICKA
SDTIA
4670_SYNCB
4670_BICKB
4670_SDTIB
10
11
12
13
14
15
16
17
18
19
20
RIN2/IN2+
LIN2/IN2-
RIN1/IN1+
LIN1/IN1-
AVSS
TP61
+
C22
0.1u
C23
10u
BICKB
R11
51
JP11
AVDD
TP60
TP32
AVDD
SDTIB
SPRIN
R14
51
JP12
80pin_3
SPRIN
U2 RIN1
JP13
C26
0.22u
MIXR
TP31
GPO1
U2 LIN1
C27
0.22u
TP39
SDTI
R26
51
GPO1
4670_SDTI
4670_SDTO
TP35
SDTO
TP38
R25
51
SPLIN
C31
0.1u
TP48
LRCK
R23
51
TP33
GPO2
4670_LRCK
4670_BICK
C24
TP49
BICK
R21
51
C33
10u
0.1u
C25
R28
51
R29
51
TP42
MCKI
R30
51
R17
R24
C11
(open)
JP15
C34
4670_MCKI
4670_MCKO
TP37
DVDD
SPLIN
TP36
51
R15
U2 SPLIN
0.015u
MCKO
10u
JP7
R31
51
1k
TP30
VSS4
51
MCKO
R7 R9 R10 R8
C37
0.033u
51
51
51
51
PDN
SCL
SDA
JP14
R22
1k
C28
0.015u
SPRIN
80pin_1
U2 SPRIN
DVDD
TP51 TP50
PDN I2C
TP55 TP52 TP53 TP54
CDTO CSN CCLK CDTI
TP62 TP64 TP63 TP65
SDTIA BICKA SYNCASDTOA
TP56
ROUTN
TP57
ROUTP
TP47
SVDD
C29
0.033u
CN2
Title
AKD4671-B
Size
A2
Document
Rev
0
NumberAK4671
4670_PDN
4670_I2C
CSN/CAD0
CDTI/SDA 4670_DVDD
4670_SDTIA 4670_SYNCA
4670_BICKA 4670_SDTOA
ROUTN
SVDD
ROUTP
4670_CDTO CCLK/SCL
Date:
Sheet
of
5
Wednesday, April 04, 2007
1
A
B
C
D
E
A
B
C
D
E
T1
TA48033F
E
D
C
B
A
E
D
C
B
A
REG1
1
IN
OUT
T45_RED
+
C41
0.1u
C42
0.1u
C43
47u
JP16
LOUT_SEL
R34
LOUT3
LOUT2
LOUT1
R32
220
J1
LOUT
LOUT3
LOUT2
LOUT1
AGND1
1
1
2
T45_BK
3
4
5
C44
1u
R33
20k
J2
1
LIN1
RIN1
2
3
L1
JP18
(short)
SVDD_SEL
JP17
HPL JACK (short)
C45
100u
R35
16
LIN1/RIN1
SVDD1
1
2
1
2
2
2
SVDD
J3
T45_OR
1
+
+
+
+
C46
47u
JP58
L_16ohm
2
3
JP20
AVDD_SEL
HP
LIN2
LIN3
LIN4
L2
JP23
JP19
R37
C47
100u
R36
16
AVDD1
1
1
J5
C50
1u
R39
HPR JACK (short)
4670_AVDD
4670_SAVDD
4670_PVDD
LIN2
LIN3
LIN4
LIN
(short)
T45_OR
(short)
2
3
4
5
1
C48
47u
JP59
R_16ohm
JP21
LIN_SEL
ROUT3
R38
220
J4
ROUT3
ROUT
JP22
SAVDD_SEL
ROUT2
1
2
3
4
5
ROUT2
ROUT1
L3
SAVDD1
1
1
ROUT1
C49
1u
R40
20k
ROUT_SEL
T45_OR
(short)
C51
47u
JP24
PVDD_SEL
L4
PVDD1
1
1
RIN2
RIN3
RIN4
JP25
T45_OR
(short)
J7
RIN
C53
1u
R42
(short)
RIN2
RIN3
RIN4
C52
47u
LOUTP
2
3
4
5
1
R41
10
RIN_SEL
J6
1
JP26
DVDD_SEL
2
3
LOUTN
ROUTP
ROUTN
L5
DVDD1
1
1
2
2
2
4670_DVDD
4670_TVDD2
4670_TVDD3
SPK_L
J8
T45_OR
(short)
+
+
+
C54
47u
1
2
3
SAIN1
SAIN2
SAIN3
JP27
TVDD2_SEL
JP28
L6
J9
SAIN1
SAIN2
SAIN3
TVDD2
1
1
SAIN
1
SPK_R
2
3
4
5
T45_OR
(short)
C55
47u
SAIN_SEL
JP29
TVDD3_SEL
L7
TVDD3
1
1
T45_OR
(short)
C56
47u
J11
SAIN3
1
2
3
4
5
R43
HPL
JP30
GND
(short)
R44
J10
1
JP31
VCC_SEL
L8
VCC1
VCC2
1
1
2
2
3
HPR
VCC
T45_OR
(short)
(short)
+
C57
47u
4212 HP
JP66
VCC2_SEL
L11
2
1
1
VCC2
T45_OR
(short)
+
C96
47u
L9
D3V1
1
1
2
D3V
T45_OR
(short)
+
C58
47u
DGND1
1
T45_BK
Title
Size
AKD4671-B
Document
Rev
0
NumbPer ower Supply, I/O
A2
Date:
Sheet
of
Wednesday, April 04, 2007
E
2
5
A
B
C
D
A
B
C
D
E
E
D
C
B
A
E
D
C
B
A
D3V
EXT_MCLK
EXT_BICK
EXT_LRCK
4114_BICK
JP32
JP33
DIR
BICK_SEL
4114_MCKO
JP34
256fs
512fs
THR
64fs-384
32fs-384
64fs
10
11
9
7
6
5
3
2
4
13
12
14
15
1
CLK
RST
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
1024fs
4040
JP35
384/768fs
MCKO
JP36
1
2
3
4
5
6
13
12
11
10
9
INV PHASE
1CLR 2CLR
32fs
J12
EXT
MCLK
1D
2D
2CK
2PR
2Q
DIR
1CK
1PR
1Q
2
3
4
5
1
MKFS
BCFS
fs-384
EXT
4040
R45
51
8
LED1
ERF
1Q
2Q
16
C60
0.1u
8
JP37
fs LRCK
VD
14
JP38
DIR LRCK_SEL
Vcc
Q10
Q11
C59
JP39
EXT
0.1u
DGND Q12
7
R46
1k
GND
U4 74HC4040
U3 74AC74
1
8
9
10
11
12
13
1A
2
4Y
4A
5Y
5A
6Y
6A
1Y
3
4114_INT0
4114_PDN
2A
4
4114_LRCK
3
4
5
6
14
13
12
11
15
A
B
C
D
QA
QB
QC
QD
Carry
2Y
5
3A
6
3Y
14
R47
10k
D1
Vcc
MCKO
10
7
2
9
1
HSU119
ENT
ENP
CLK
16
8
7
GND
Vcc
C62
0.1u
C61
0.1u
U6 74HC14
LOAD
CLR GND
L
H
SW1
DIR
C63
0.1u
U5 74AC163
VCC
U7
74HCU04
1
2
3
4
5
6
8
9
10
11
12
13
1A
1Y
2A
2Y
3A
3Y
4Y
4A
5Y
5A
6Y
6A
4670_PDN
C64
0.1u
14
7
R48
10k
D2
Vcc
HSU119
GND
C65
0.1u
U8 74HC14
L
H
SW2
PDN
C66
0.1u
4.096MHz
X1
1
2
R49
1M
JP40
XTE
C67
5p
C68
5p
EXT_MCLK2
D3V
JP41
MCLK2
JP42
J13
EXT1
XTL
512fs2
10
11
9
7
6
5
3
2
4
13
12
14
15
1
256fs2
CLK
RST
Q1
Q2
Q3
128fs2
64fs2
32fs2
16fs2
BICKA
BICKB
EXT_BICKA
EXT_BICKB
EXT1
Q4
R50
51
Q5
Q6
Q7
Q8
Q9
Q10
Q11
JP43
BCFS2
BICK2_SEL
JP44
EXT1
16
1fs2
VD
C69
0.1u
8
DGND Q12
U9 74HC4040
LRCKA
LRCKB
EXT_LRCKA
EXT_LRCKB
JP45
LRCK2_SEL
Title
Size
AKD4671-B
Document Number
Rev
0
A2
CLOCK
Date:
Sheet
of
Wednesday, April 04, 2007
3
5
A
B
C
D
E
A
B
C
D
E
D3V
PORT1
E
D
C
B
A
E
D
C
B
A
L10(short)
1 2
C70
0.1u
3
VCC
C71
0.1u
2
1
GND
OUT
TORX141
R51
470
C72 10u
C73
0.1u
C74
R52
18k
VCC
0.47u
U10
1
2 3 4 5 6
H
S1
SW DIP-6
1
2
36
35
34
33
32
31
30
29
28
27
26
25
IPS0
NC
INT0
OCKS0
OCKS1
CM1
4114_INT0
------OFF------
L
3
DIF0
TEST2
DIF1
NC
4
CAD0
I2C
5
CM0
6
PDN
4114_PDN
MCKO
RP1 47k
AK4114
C75 5p
C76 5p
7
JP46 4114_MCKI
DIF2
IPS1
P/SN
XTL0
XTL1
VIN
XTI
X2
11.2896MHz
8
XTO
9
DAUX
MCKO2
BICK
DAUX
10
11
12
4114_BICK
4114_SDTO
SDTO
C77
0.1u
C78
0.1u
4114_LRCK
4114_MCKO
C79
10u
C80
10u
PORT2
3
2
IN
VCC
C81
0.1u
1
GND
TOTX141
Title
Size
AKD4671-B
Document Number
Rev
0
A3
DIR/DIT
Date:
Sheet
of
Wednesday, April 04, 2007
4
5
A
B
C
D
E
A
B
C
D
E
VCC2
THR
EXT_BICKA
JP47
INV BICKA PHASE
VCC
D3V
U12
U11
JP62
BICKA
3
4
21
20
19
18
17
16
15
14
A1
A2
A3
A4
A5
A6
A7
A8
B1
B2
B3
B4
B5
B6
B7
B8
4670_BICKA
4670_SYNCA
3
4
21
20
19
18
17
16
15
14
EXT_LRCK
EXT_BICK
A1
A2
A3
A4
A5
A6
A7
A8
B1
B2
B3
B4
B5
B6
B7
B8
4670_LRCK
4670_BICK
EXT_LRCKA
5
JP63
SYNCA
E
D
C
B
A
5
E
D
C
B
A
6
6
7
7
7
6
5
4
3
2
1
7
R53
10k
7
6
5
4
3
2
1
7
6
5
4
3
2
1
PORT3
8
6
5
4
3
2
1
8
MCLK2
BICKA
LRCKA
SDTIA
VCC
GND
GND
1
3
5
7
9
2
4
6
8
9
EXT_MCLK2
9
10
PORT4
10
SDTOA
10
MCLK
BICK
LRCK
SDTI
VCC
GND
GND
1
3
5
7
9
2
4
6
8
RP4 47k
RP5 47k
RP2 47k
RP3 47k
R54
10k
Baseband
2
1
22
24
23
DIR
OE
VCCB
VCCB
2
22
24
23
DIR
OE
VCCB
VCCB
SDTO
10
D3V
VCCA
1
C83
0.1u
11
C82
0.1u
11
VCCA
DSP
C85
0.1u
GND
GND
C84
0.1u
GND
GND
12
13
GND
12
13
JP49
PLLBT
GND
SDTOA1
JP48
M/S
JP50
SDTOA LOOP
SDTIA
74AVC8T245
74AVC8T245
VCC
U13
3
4
21
20
19
18
17
16
15
14
A1
A2
A3
A4
A5
A6
A7
A8
B1
B2
B3
B4
B5
B6
B7
B8
4670_SDTO
DAUX
5
I2C
6
D3V
I2C
4670_I2C
MCLK2
7
JP51
JP57
8
ADC
DIR
SDTI_SEL
I2C PIN
9
VCC
MCKO
4670_MCKO
U14
1
2
3
4
5
6
8
9
10
11
12
13
4114_SDTO
1A
1Y
2A
2Y
3A
3Y
4Y
4A
5Y
5A
6Y
6A
10
3
4
21
20
19
18
17
16
15
14
A1
A2
A3
A4
A5
A6
A7
A8
B1
B2
B3
B4
B5
B6
B7
B8
4670_SDTI
4670_MCKI
2
1
22
24
23
DIR
OE
VCCB
VCCB
5
14
EXT_MCLK
D3V
Vcc
D3V
VCCA
6
C86
0.1u
7
GND
7
11
12
C88
0.1u
C87
0.1u
EXT_MCLK2
GND
GND
U15 74HC14
8
13
GND
CSN/CAD0
CCLK/SCL
9
4-WIRE (CDTO)
74AVC8T245
I2C (CAD0)
4-WIRE
10
CAD0
4670_CDTO
JP52
CTRL_SEL
I2C (ACK)
JP53
2
22
24
23
CTRL_SEL2
DIR
OE
1
C89
0.1u
11
VCCA
VCCB
VCCB
GND
R55
10k
R56
10k
R57
10k
C90
0.1u
GND
GND
12
13
PORT5
CSN
10
8
6
4
2
9
7
5
3
1
R58
R59
R60
470
470
470
CCLK/SCI
74AVC8T245
CDTI/SDA
CDTO/SDA(ACK)
VCC2
CTRL
U16
R61
1k
INV
EXT_BICKB
1
3
5
9
11
13
2
4
6
8
10
12
JP54
1A
2A
3A
4A
5A
6A
1Y
2Y
3Y
4Y
5Y
6Y
CDTI/SDA
THR BICKB PHASE
U17
JP64
BICKB
3
4
21
20
19
18
17
16
15
14
A1
A2
A3
A4
A5
A6
A7
A8
B1
B2
B3
B4
B5
B6
B7
B8
4670_BICKB
4670_SYNCB
EXT_LRCKB
14
C91
0.1u
7
Vcc
5
JP65
SYNCB
VCC2
6
GND
U18
7
74LVC07
7
6
5
4
3
2
1
7
6
5
4
3
2
1
PORT6
8
JP61
PORT7
MCLK2
1
3
5
7
9
2
4
6
GND
GND
9
SDTIB
EXT_MCLK2
BICKB
LRCKB
SDTIB
VCC
4
5
2
6
7
3
13
12
15
11
10
14
16
9
SDTIB
SDTIA
1A1
1B1
1B2
4670_SDTIB
4670_SDTIA
DOUT10
9
7
5
3
1
10
8
6
4
8
10
DIN
CSN
SCLK
SDTOB
RP6 47k
RP7 47k
1A2
VCCIO
2
R62
10k
Bluetooth
JP60
SDTIA
2
22
24
23
DIR
OE
CTRL SAR ADC
1
C92
0.1u
11
1DIR
2A1
1OE
2B1
D3V
VCCA
VCCB
VCCB
C93
0.1u
GND
GND
JP56
D3V
SDTOB1
4670_SDTOB
4670_SDTOA
12
13
GND
D3V
SDTOA1
2A2
2B2
74AVC8T245
SDTOB1
2DIR
VCCA
GND
2OE
VCCB
GND
JP55
SDTOB LOOP
SDTIB
1
C95
0.1u
D3V
C94
0.1u
8
74AVC4T245
Title
AKD4671-B
Size
A2
Document Number
Rev
0
LOGIC
Date:
Sheet
of
Wednesday, April 04, 2007
E
5
5
A
B
C
D
相关型号：
AKD4683-B
24bit CODEC that has two channels of ADC and four channels of DAC with internal DIR, DIT
AKM
©2020 ICPDF网 联系我们和版权申明