A1244LUA-I1-T [ALLEGRO]
Hall Effect Sensor, -8mT Min, 8mT Max, BICMOS, Plastic/epoxy, Rectangular, 3 Pin, Through Hole Mount, SIP-3;
| 型号： | A1244LUA-I1-T |
| 厂家： | 
ALLEGRO MICROSYSTEMS |
| 描述： | Hall Effect Sensor, -8mT Min, 8mT Max, BICMOS, Plastic/epoxy, Rectangular, 3 Pin, Through Hole Mount, SIP-3 信息通信管理 传感器 换能器 |
| 文件： | 总12页 (文件大小：448K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
A1244
Chopper-Stabilized, Two-Wire Hall-Effect Latch
FEATURES AND BENEFITS
DESCRIPTION
▪ꢀAEC-Q100ꢀautomotiveꢀqualified
▪ꢀHigh-speed,ꢀ4-phaseꢀchopperꢀstabilization
▫ꢀLowꢀswitchpointꢀdriftꢀthroughoutꢀtemperatureꢀrange
▫ꢀLowꢀsensitivityꢀtoꢀthermalꢀandꢀmechanicalꢀstresses
▪ꢀOn-chipꢀprotection
The A1244 is a two-wire Hall-effect latch. The devices are
producedontheAllegro™ advancedBiCMOSwaferfabrication
process, which implements a high-frequency, 4-phase,
chopper stabilization technique. This technique achieves
magnetic stability over the full operating temperature range,
and eliminates offsets inherent in devices with a single Hall
element that are exposed to harsh application environments.
▫ꢀSupplyꢀtransientꢀprotection
▫ꢀReverse-batteryꢀprotection
▪ꢀOn-boardꢀvoltageꢀregulatorꢀ
▫ꢀ3ꢀtoꢀ24ꢀVꢀoperation
▪ꢀSolid-stateꢀreliability
▪ꢀRobustꢀEMCꢀandꢀESDꢀperformance
▪ꢀIndustry-leadingꢀISOꢀ7637-2ꢀperformanceꢀthroughꢀuseꢀofꢀ
proprietary,ꢀ40ꢀVꢀclampingꢀstructures
Two-wirelatchesareparticularlyadvantageousincost-sensitive
applications because they require one less wire for operation
versus the more traditional open-collector output switches.
Additionally, the system designer inherently gains diagnostics
because there is always output current flowing, which should
be in either of two narrow ranges.Any current level not within
these ranges indicates a fault condition.
PACKAGES:
The Hall-effect latch will be in the high output current state
in the presence of a magnetic south polarity field of sufficient
magnitude and will remain in this state until a sufficient north
polarity field is present.
3-pin ultra-mini SIP
1.5 mm × 4 mm × 3 mm
(suffix UA)
3-pin SOT23-W
2 mm × 3 mm × 1 mm
(suffix LH)
The device is offered in two package styles. The LH is a
SOT-23W style, miniature low-profile package for surface-
mount applications. The UA is a 3-pin ultra-mini single inline
package (SIP) for through-hole mounting. Both packages are
lead (Pb) free, with 100% matte-tin leadframe plating.
Approximate footprint
Not to scale
Functional Block Diagram
V+
VCC
Regulator
Clock/Logic
Amp
To all subcircuits
0.01 µF
Schmitt
Trigger
Low-Pass
Filter
Polarity
GND
UA package only
GND
A1244-DS, Rev. 3
May 19, 2017
Chopper-Stabilized, Two-Wire
Hall-Effect Latch
A1244
SELECTION GUIDE
Part Number
Operating Ambient
Temperature, TA
(°C)
Supply Current
at ICC(L)
Packing [1]
Package
(mA)
A1244LLHLT-I1-T
A1244LLHLX-I1-T
A1244LLHLT-I2-T
A1244LLHLX-I2-T
A1244LUA-I1-T
7-in. reel, 3000 pieces/reel
13-in. reel, 10000 pieces/reel
7-in. reel, 3000 pieces/reel
13-in. reel, 10000 pieces/reel
Bulk, 500 pieces/bag
3-pin SOT23W surface mount
3-pin SOT23W surface mount
3-pin SOT23W surface mount
3-pin SOT23W surface mount
3-pin SIP through hole
–40 to 150
–40 to 150
–40 to 150
–40 to 150
–40 to 150
–40 to 150
5 to 6.9
5 to 6.9
2 to 5
2 to 5
5 to 6.9
2 to 5
A1244LUA-I2-T
Bulk, 500 pieces/bag
3-pin SIP through hole
™
[1] Contact Allegro for additional packing options.
ABSOLUTE MAXIMUM RATINGS
Characteristic
Forward Supply Voltage [2]
Reverse Supply Voltage
Magnetic Flux Density
Symbol
VCC
Notes
Rating
28
Unit
V
VRCC
B
–18
V
Unlimited
–40 to 150
165
G
Operating Ambient Temperature
Maximum Junction Temperature
Storage Temperature
TA
Range L
°C
°C
°C
TJ(max)
Tstg
–65 to 170
[2] This rating does not apply to extremely short voltage transients such as Load Dump and/or ESD. Those events have individual
ratings, specific to the respective transient voltage event.
Pinout Diagrams
Terminal List Table
Number
Name
Function
3
LH
UA
VCC
NC
1
1
Connects power supply to chip
No connection
2
3
–
GND
2, 3
Ground
NC
2
1
2
3
1
LH Package
3-pin SOT23W
UA Package
3-pin SIP
Allegro MicroSystems, LLC
115 Northeast Cutoff
2
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Chopper-Stabilized, Two-Wire
Hall-Effect Latch
A1244
ELECTRICAL CHARACTERISTICS: Valid at TA = –40°C to 150°C, TJ < TJ(max), CBYP = 0.01 µF, through operating supply
voltage range, unless otherwise noted
Characteristics
Supply Voltage [1][2]
Symbol
Test Conditions
Operating, TJ ≤ 165°C
Min.
3.0
5
Typ.
Max.
24
6.9
5
Unit
V
VCC
–
–
–
–
–
-I1
B < BRP
B < BRP
mA
mA
mA
V
ICC(L)
Supply Current
-I2
2
ICC(H)
B > BOP
12
28
17
–
Supply Zener Clamp Voltage
Supply Zener Clamp Current
Reverse Supply Current
Output Slew Rate [3]
VZ(sup)
ICC(L)(max) + 3 mA, TA = 25°C
VZ(sup) = 28 V
ICC(L)(max)
+ 3 mA
IZ(sup)
IRCC
di/dt
–
–
–
–
–
mA
mA
VRCC = –18 V
–1.6
–
No bypass capacitor, capacitance of probe
CS = 20 pF
90
mA/µs
Chopping Frequency
Power-Up Time [2][4][5]
Power-Up State [4][6][7]
fc
–
–
–
700
–
–
25
–
kHz
µs
–
ton
POS
ton < ton(max), VCC slew rate > 25 mV/µs
ICC(H)
[1]
V
represents the generated voltage between the VCC pin and the GND pin.
CC
[2] The VCC slew rate must exceed 600 mV/ms from 0 to 3 V. A slower slew rate through this range can affect device performance.
[3] Measured without bypass capacitor between VCC and GND. Use of a bypass capacitor results in slower current change.
[4] Power-Up Time is measured without and with bypass capacitor of 0.01 µF, B < BRP – 10 G. Adding a larger bypass capacitor would cause longer
Power-Up Time.
[5] Guaranteed by characterization and design.
[6] Power-Up State as defined is true only with a VCC slew rate of 25 mV/µs or greater.
[7] For t > ton and BRP < B < BOP, Power-Up State is not defined.
MAGNETIC CHARACTERISTICS [8]: Valid at TA = –40°C to 150°C, TJ < TJ (max), unless otherwise noted
Characteristics
Magnetic Operating Point
Magnetic Release Point
Hysteresis
Symbol
BOP
Test Conditions
Min.
5
Typ.
Max.
80
Unit [9]
–
–
–
G
G
G
BRP
–80
40
–5
BHYS
BOP – BRP
110
[8] Relative values of B use the algebraic convention, where positive values indicate south magnetic polarity, and negative values indicate north
magnetic polarity; therefore greater B values indicate a stronger south polarity field (or a weaker north polarity field, if present).
[9] 1 G (gauss) = 0.1 mT (millitesla).
Allegro MicroSystems, LLC
115 Northeast Cutoff
3
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Chopper-Stabilized, Two-Wire
Hall-Effect Latch
A1244
THERMAL CHARACTERISTICS
Characteristic
Symbol
Test Conditions [1]
Value Units
Package LH, 1-layer PCB with copper limited to solder pads
228
110
165
°C/W
°C/W
°C/W
Package LH, 2-layer PCB with 0.463 in.2 of copper area each side
connected by thermal vias
Package Thermal Resistance
RθJA
Package UA, 1-layer PCB with copper limited to solder pads
[1] Additional thermal information available on Allegro website.
Power Derating Curve
25
24
23
V
CC(max)
22
21
20
19
18
17
16
15
14
13
12
11
10
9
LH, 2-layer PCB
(RθJA = 110 ºC/W)
UA, 1-layer PCB
(RθJA = 165 ºC/W)
8
7
6
LH, 1-layer PCB
(RθJA = 228 ºC/W)
5
4
3
V
CC(min)
2
20
40
60
80
100
120
140
160
180
Temperature (ºC)
Power Dissipation versus Ambient Temperature
1900
1800
1700
1600
1500
1400
1300
1200
1100
1000
900
800
700
600
500
400
300
200
100
0
20
40
60
80
100
120
140
160
180
Temperature (°C)
Allegro MicroSystems, LLC
115 Northeast Cutoff
4
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Chopper-Stabilized, Two-Wire
Hall-Effect Latch
A1244
CHARACTERISTIC PERFORMANCE
A1244-I1
A1244-I1
Average Supply Current (Low) versus Supply Voltage
Average Supply Current (Low) versus Temperature
7.0
7.0
TA = 150°C
6.5
6.5
V
= 24 V
= 3.0 V
CC
6.0
6.0
5.5
5.0
T
A = –40°C
T
= 25°C
A
V
CC
5.5
5.0
2
6
10
14
18
22
26
-60
-40
-20
0
20
40
60
80
100 120 140 160
Supply Voltage, V (V)
Ambient Temperature, T (°C)
CC
A
A1244-I1,I2
A1244-I1,I2
Average Supply Current (High) versus Supply Voltage
Average Supply Current (High) versus Temperature
17
17
16
16
T
T
= –40°C
= 150°C
A
V
= 24 V
= 3.0 V
CC
A
15
14
13
12
15
14
13
12
T
= 25°C
A
V
CC
2
6
10
14
18
22
26
-60
-40
-20
0
20
40
60
80
100 120 140 160
Supply Voltage, V (V)
Ambient Temperature, T (°C)
CC
A
Allegro MicroSystems, LLC
115 Northeast Cutoff
5
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Chopper-Stabilized, Two-Wire
Hall-Effect Latch
A1244
A1244-I1,I2
Average Operate Point versus Temperature
A1244-I1,I2
Average Operate Point versus Supply Voltage
85
75
65
55
45
35
25
15
5
85
75
65
55
45
T = 150°C
A
T
A
= 25°C
V
CC
= 3.0 V
V
35
25
15
5
= 24 V
CC
T
= –40°C
A
2
6
10
14
18
22
26
-60
-40
-20
0
20
40
60
80
100 120 140 160
Supply Voltage, V (V)
Ambient Temperature, T (°C)
CC
A
A1244-I1,I2
A1244-I1,I2
Average Release Point versus Supply Voltage
Average Release Point versus Temperature
–5
–15
–25
–5
–15
–25
–35
–45
–55
–65
–75
–85
V
= 3.0 V
= 24 V
T
A = –40°C
= 25°C
CC
–35
–45
–55
–65
–75
–85
T
A
V
CC
TA = 150°C
2
6
10
14
18
22
26
-60
-40
-20
0
20
40
60
80
100 120 140 160
Ambient Temperature, T (°C)
Supply Voltage, V (V)
A
CC
A1244-I1,I2
A1244-I1,I2
Average Switchpoint Hysteresis versus Temperature
Average Switchpoint Hysteresis versus Supply Voltage
110
100
90
110
100
90
T
= 150°C
A
V
V
= 24 V
= 3.0 V
CC
80
70
60
50
40
80
70
60
50
40
T
= 25°C
A
CC
T
= –40°C
A
2
6
10
14
18
22
26
-60
-40
-20
0
20
40
60
80
100 120 140 160
Ambient Temperature, T (°C)
Supply Voltage, V (V)
A
CC
Allegro MicroSystems, LLC
115 Northeast Cutoff
6
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Chopper-Stabilized, Two-Wire
Hall-Effect Latch
A1244
FUNCTIONAL DESCRIPTION
The A1244 output, ICC, switches high after the magnetic field
at the Hall sensor IC exceeds the operate point threshold, BOP
When the magnetic field is reduced to below the release point
threshold, BRPꢀ, the device output goes low. This is shown in
figure 1.
The difference between the magnetic operate and release points is
called the hysteresis of the device, BHYS. This built-in hysteresis
allows clean switching of the output even in the presence of
external mechanical vibration and electrical noise.
.
I+
ICC(H)
ICC(L)
0
B–
B+
BHYS
Figure 1. Hysteresis for the A1244. On the horizontal axis, the B+ direc-
tion indicates increasing south polarity magnetic field strength, and the
B– direction indicates decreasing south polarity field strength (including
the case of increasing north polarity).
APPLICATION INFORMATION
It is strongly recommended that an external bypass capacitor be
under harsh environmental conditions and to reduce noise from
connected (in close proximity to the Hall element) between the
supply and ground of the device to guarantee correct performance
internal circuitry.
R
SENSE
V+
V+
VCC
VCC
C
C
BYP
BYP
A1244
A1244
0.01 µF
0.01 µF
GND
GND
ECU
R
SENSE
(A) Low-side sensing
(B) High-side sensing
Figure 2. Typical application circuits
Allegro MicroSystems, LLC
115 Northeast Cutoff
7
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Chopper-Stabilized, Two-Wire
Hall-Effect Latch
A1244
Chopper Stabilization Technique
When using Hall-effect technology, a limiting factor for
baseband,ꢀwhileꢀtheꢀDCꢀoffsetꢀbecomesꢀaꢀhigh-frequencyꢀsignal.ꢀ
The magnetic-sourced signal then can pass through a low-pass
filter,ꢀwhileꢀtheꢀmodulatedꢀDCꢀoffsetꢀisꢀsuppressed.ꢀꢀTheꢀchopperꢀ
stabilization technique uses a 350 kHz high-frequency clock.
For demodulation process, a sample-and-hold technique is used,
where the sampling is performed at twice the chopper frequency.
This high-frequency operation allows a greater sampling rate,
which results in higher accuracy and faster signal-processing
capability. This approach desensitizes the chip to the effects
of thermal and mechanical stresses, and produces devices that
have extremely stable quiescent Hall output voltages and precise
recoverability after temperature cycling. This technique is made
possible through the use of a BiCMOS process, which allows
the use of low-offset, low-noise amplifiers in combination with
high-density logic integration and sample-and-hold circuits.
switchpoint accuracy is the small signal voltage developed
across the Hall element. This voltage is disproportionally small
relative to the offset that can be produced at the output of the
Hall sensor IC. This makes it difficult to process the signal
while maintaining an accurate, reliable output over the specified
operating temperature and voltage ranges. Chopper stabilization
is a unique approach used to minimize Hall offset on the chip.
Theꢀtechnique,ꢀnamelyꢀDynamicꢀQuadratureꢀOffsetꢀCancellation,ꢀ
removes key sources of the output drift induced by thermal and
mechanical stresses. This offset reduction technique is based on
a signal modulation-demodulation process. The undesired offset
signal is separated from the magnetic field-induced signal in the
frequency domain through modulation. The subsequent demod-
ulation acts as a modulation process for the offset, causing the
magnetic field-induced signal to recover its original spectrum at
Regulator
Clock/Logic
Low-Pass
Filter
Hall Element
Amp
Figure 3. Chopper stabilization circuit (Dynamic Quadrature Offset Cancellation)
Allegro MicroSystems, LLC
115 Northeast Cutoff
8
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Chopper-Stabilized, Two-Wire
Hall-Effect Latch
A1244
Power Derating
The device must be operated below the maximum junction tem-
perature of the device, TJ(max). Under certain combinations of
peak conditions, reliable operation may require derating supplied
power or improving the heat dissipation properties of the appli-
cation. This section presents a procedure for correlating factors
affecting operating TJ. (Thermal data is also available on the
Allegro MicroSystems website.)
Example:ꢀReliabilityꢀforꢀVCC at TA=150°C, package LH, using a
low-KꢀPCB.
Observe the worst-case ratings for the device, specifically:
RθJAꢀ=110°C/W, TJ(max) =165°C,ꢀVCC(max)= 24ꢀV,ꢀandꢀ
ICC(max) = 17 mA.
Calculate the maximum allowable power level, PD(max). First,
invert equation 3:
TheꢀPackageꢀThermalꢀResistance,ꢀRθJA, is a figure of merit sum-
marizing the ability of the application and the device to dissipate
heat from the junction (die), through all paths to the ambient air.
ItsꢀprimaryꢀcomponentꢀisꢀtheꢀEffectiveꢀThermalꢀConductivity,ꢀK,ꢀ
of the printed circuit board, including adjacent devices and traces.
Radiationꢀfromꢀtheꢀdieꢀthroughꢀtheꢀdeviceꢀcase,ꢀRθJC, is relatively
smallꢀcomponentꢀofꢀRθJA. Ambient air temperature, TA, and air
motion are significant external factors, damped by overmolding.
ꢀꢀꢀꢀꢀΔTmax = TJ(max) – TAꢀ=ꢀ165°C–150°C = 15°C
This provides the allowable increase to TJ resulting from internal
power dissipation. Then, invert equation 2:
PD(max) =ꢀΔTmax ÷RθJAꢀ=ꢀ15°Cꢀ÷ꢀ110°C/Wꢀ=ꢀ136ꢀmW
Finally, invert equation 1 with respect to voltage:
ꢀꢀꢀꢀVCC(est) = PD(max) ÷ ICC(max)=ꢀ136ꢀmWꢀ÷ꢀ17ꢀmA= 8ꢀV
Theꢀeffectꢀofꢀvaryingꢀpowerꢀlevelsꢀ(PowerꢀDissipation,ꢀPD), can
be estimated. The following formulas represent the fundamental
relationships used to estimate TJ, at PD.
The result indicates that, at TA, the application and device can
dissipateꢀadequateꢀamountsꢀofꢀheatꢀatꢀvoltagesꢀ≤VCC(est)
.
PD = VIN
I
(1)
(2)
×
IN
CompareꢀVCC(est)ꢀtoꢀVCC(max).ꢀIfꢀVCC(est)ꢀ≤ꢀVCC(max), then reli-
ableꢀoperationꢀbetweenꢀVCC(est)ꢀandꢀVCC(max) requires enhanced
RθJA.ꢀꢀIfꢀVCC(est)ꢀ≥ꢀVCC(max),ꢀthenꢀoperationꢀbetweenꢀVCC(est)
ꢀ
ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀΔTꢀ=ꢀPD
R
θJA
×
ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀTJꢀ=ꢀTAꢀ+ꢀΔTꢀ
ꢀ
(3) andꢀVCC(max) is reliable under these conditions.
For example, given common conditions such as: TA= 25°C,
VCC = 12ꢀV, ICC = 4 mA, and RθJA = 140°C/W, then:
PD = VCC
I
= 12 V 4 mA = 48 mW
CC
×
×
ꢀ
ꢀ
ΔTꢀ=ꢀPD
R
= 48 mW 140°C/W = 7°C
θJA
×
×
ꢀTJꢀ=ꢀTAꢀ+ꢀΔTꢀ=ꢀ25°Cꢀ+ꢀ7°Cꢀ=ꢀ32°C
A worst-case estimate, PD(max), represents the maximum allow-
ableꢀpowerꢀlevelꢀ(VCC(max), ICC(max)), without exceeding
TJ(max),ꢀatꢀaꢀselectedꢀRθJA and TA.
Allegro MicroSystems, LLC
115 Northeast Cutoff
9
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Chopper-Stabilized, Two-Wire
Hall-Effect Latch
A1244
Package LH, 3-Pin SOT23W
+0.12
–0.08
2.98
3
D
1.49
4°±4°
A
+0.020
–0.053
0.180
D
0.96
D
+0.10
–0.20
+0.19
1.91
–0.06
2.40
2.90
0.70
0.25 MIN
1.00
2
1
0.55 REF
0.25 BSC
0.95
PCB Layout Reference View
Seating Plane
Gauge Plane
B
Branded Face
8X 10° REF
1.00 ±0.13
+0.10
NNN
1
0.05
–0.05
C
Standard Branding Reference View
0.95 BSC
0.40 ±0.10
N = Last three digits of device part number
For Reference Only; not for tooling use (reference DWG-2840)
Dimensions in millimeters
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
Active Area Depth, 0.28 mm REF
A
B
Reference land pattern layout
All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary
to meet application process requirements and PCB layout tolerances
C
D
Branding scale and appearance at supplier discretion
Hall element, not to scale
Allegro MicroSystems, LLC
115 Northeast Cutoff
10
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Chopper-Stabilized, Two-Wire
Hall-Effect Latch
A1244
Package UA, 3-Pin SIP
+0.08
–0.05
4.09
45°
B
C
E
2.04
1.52 ±0.05
10°
1.44
E
Mold Ejector
Pin Indent
E
+0.08
–0.05
3.02
45°
Branded
Face
0.79 REF
A
NNN
1.02
MAX
1
Standard Branding Reference View
D
1
2
3
= Supplier emblem
N = Last three digits of device part number
14.99 ±0.25
+0.03
–0.06
0.41
For Reference Only; not for tooling use (reference DWG-9065)
Dimensions in millimeters
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
+0.05
–0.07
0.43
Dambar removal protrusion (6X)
A
B
C
D
Gate and tie bar burr area
Active Area Depth, 0.50 mm REF
Branding scale and appearance at supplier discretion
Hall element (not to scale)
E
1.27 NOM
Allegro MicroSystems, LLC
115 Northeast Cutoff
11
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Chopper-Stabilized, Two-Wire
Hall-Effect Latch
A1244
REVISION HISTORY
Number
Date
Description
1
July 12, 2012
Update package drawing
2
3
September 21, 2015 Added AEC-Q100 qualification under Features and Benefits
May 19, 2017 Added “LT” tape and reel packing option
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Allegro MicroSystems, LLC reserves the right to make, from time to time, such departures from the detail specifications as may be required to
permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that
the information being relied upon is current.
Allegro’s products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of
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use; nor for any infringement of patents or other rights of third parties which may result from its use.
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Allegro MicroSystems, LLC
115 Northeast Cutoff
12
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
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