A3988SJP-T [ALLEGRO]
Quad DMOS Full Bridge PWM Motor Driver; 四路DMOS全桥PWM电机驱动器
| 型号： | A3988SJP-T |
| 厂家： | 
ALLEGRO MICROSYSTEMS |
| 描述： | Quad DMOS Full Bridge PWM Motor Driver |
| 文件： | 总13页 (文件大小：363K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
A3988
Quad DMOS Full Bridge PWM Motor Driver
Features and Benefits
Description
▪ 36 V output rating
▪ 4 full bridges
▪ Dual stepper motor driver
▪ High current outputs
The A3988 is a quad DMOS full-bridge driver capable of
driving up to two stepper motors or four dc motors. Each
full-bridge output is rated up to 1.2 A and 36 V. The A3988
includesfixedoff-timepulsewidthmodulation(PWM)current
▪ 3.3 and 5 V compatible logic supply
▪ Synchronous rectification
▪ Internal undervoltage lockout (UVLO)
▪ Thermal shutdown circuitry
▪ Crossover-current protection
▪ Low profile QFN package
regulators,alongwith2-bitnonlinearDACs(digital-to-analog
converters) that allow stepper motors to be controlled in full,
half, and quarter steps, and dc motors in forward, reverse, and
coast modes. The PWM current regulator uses the Allegro®
patented mixed decay mode for reduced audible motor noise,
increased step accuracy, and reduced power dissipation.
Internalsynchronousrectificationcontrolcircuitryisprovided
to improve power dissipation during PWM operation.
Packages
Protection features include thermal shutdown with hysteresis,
undervoltagelockout(UVLO)andcrossovercurrentprotection.
Special power up sequencing is not required.
Package EV, 36 pin QFN
0.90 mm nominal height
with exposed thermal pad
Package JP, 48 pin LQFP
with exposed thermal pad
The A3988 is supplied in two packages, EV and JP, with
exposed power tabs for enhanced thermal performance. The
EV is a 6 mm x 6 mm, 36 pin QFN package with a nominal
overall package height of 0.90 mm. The JP is a 7 mm × 7 mm
48 pin LQFP. Both packages are lead (Pb) free, with 100%
matte tin leadframe plating.
Approximate scale
0.1 μF
50 V
0.1 μF
50 V
VMOTOR 32 V
0.22 μF
50 V
100 μF
50 V
PHASE1
I01
OUT1A
OUT1B
OUT2A
OUT2B
I11
PHASE2
I02
A3988
Microprocessor
Bipolar Stepper Motors
I12
OUT3A
OUT3B
OUT4A
OUT4B
PHASE3
I03
I13
PHASE4
I04
SENSE2
SENSE1
SENSE3
SENSE4
I14
RS2
RS1
RS3
RS4
VREF1
VREF2
VREF3
VREF4
VDD
VREF
VDD 3.3 V
Figure 1. Typical application circuit
A3988DS, Rev. 5
A3988
Quad DMOS Full Bridge PWM Motor Driver
Selection Guide
Part Number
Package
Packing
A3988SEV-T
36 pin QFN with exposed thermal pad
36 pin QFN with exposed thermal pad
48 pin LQFP with exposed thermal pad
61 pieces per tube
A3988SEVTR-T
A3988SJP-T
1500 pieces per reel
250 pieces per tray
Absolute Maximum Ratings
Characteristic
Symbol
Notes
Rating
-0.5 to 36
38
Units
Load Supply Voltage
VBB
V
V
V
A
Pulsed tw < 1 μs
Logic Supply Voltage
Output Current
VDD
IOUT
–0.4 to 7
1.2
May be limited by duty cycle, ambient temperature, and heat sinking. Under
any set of conditions, do not exceed the specified current rating or a Junction
Temperature of 150°C.
Pulsed tw < 1 μs
2.8
–0.3 to 7
0.5
A
V
Logic Input Voltage Range
SENSEx Pin Voltage
VIN
VSENSEx
V
Pulsed tw < 1 μs
2.5
V
VREFx Pin Voltage
VREFx
TA
2.5
V
Operating Temperature Range
Junction Temperature
Range S
–20 to 85
150
ºC
ºC
ºC
TJ(max)
Tstg
Storage Temperature Range
–40 to 125
Thermal Characteristics (may require derating at maximum conditions)
Characteristic
Symbol
Test Conditions
Min. Units
EV package, 4 layer PCB based on JEDEC standard
27 ºC/W
RθJA
Package Thermal Resistance
JP package, 4 layer PCB based on JEDEC standard
23 ºC/W
Power Dissipation versus Ambient Temperature
5500
5000
4500
4000
3500
3000
2500
2000
1500
1000
500
JP Package
4-layer PCB
(RQJA = 23 ºC/W)
EV Package
4-layer PCB
(RQJA = 27 ºC/W)
0
25
50
75
100
125
150
175
Temperature (°C)
Allegro MicroSystems, Inc.
115 Northeast Cutoff
2
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
A3988
Quad DMOS Full Bridge PWM Motor Driver
Functional Block Diagram
0.1 μF
0.1 μF
50 V
50 V
To
VBB2
100 μF
0.22 μF
50 V
50 V
VBB1
VDD
DMOS
FULL-BRIDGE 1
VCP
OSC
CHARGE PUMP
OUT1A
OUT1B
PHASE1
I01
Control Logic
Bridges 1 and 2
I11
PHASE2
I02
SENSE1
VBB1
GATE
DRIVE
DMOS
FULL-BRIDGE 2
I12
Sense1
PWM Latch
BLANKING
VREF1
VREF2
3
OUT2A
OUT2B
3
PWM Latch
BLANKING
Sense2
PHASE3
I03
VCP
Sense2
SENSE2
Control Logic
I13
Bridges 3 and 4
VBB2
OUT3A
OUT3B
PHASE4
I04
DMOS
FULL-BRIDGE 3
I14
GATE
DRIVE
Sense3
SENSE3
Sense3
3
VBB2
PWM Latch
BLANKING
VREF3
VREF4
OUT4A
OUT4B
DMOS
FULL-BRIDGE 4
3
PWM Latch
BLANKING
Sense4
Sense4
SENSE4
Allegro MicroSystems, Inc.
115 Northeast Cutoff
3
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
A3988
Quad DMOS Full Bridge PWM Motor Driver
ELECTRICAL CHARACTERISTICS1, valid at TA = 25°C, VBB = 36 V, unless otherwise noted
Characteristics
Load Supply Voltage Range
Logic Supply Voltage Range
VDD Supply Current
Symbol
VBB
Test Conditions
Min.
8.0
3.0
–
Typ.2
–
Max.
36
Units
V
Operating
Operating
VDD
–
5.5
10
V
IDD
7
mA
mΩ
mΩ
V
Source driver, IOUT = –1.2 A, T = 25°C
–
700
700
–
800
800
1.2
20
J
Output On Resistance
RDS(on)
Sink driver, IOUT = 1.2 A, T = 25°C
J
–
Vf , Outputs
IOUT = 1.2 A
–
Output Leakage
IDSS
IBB
Outputs, VOUT = 0 to VBB
–20
–
μA
IOUT = 0 mA, outputs on, PWM = 50 kHz,
DC = 50%
VBB Supply Current
–
–
8
mA
Control Logic
VIN(1)
VIN(0)
IIN
0.7×VDD
–
–
–
–
0.3×VDD
20
V
V
Logic Input Voltage
Logic Input Current
Input Hysteresis
VIN = 0 to 5 V
–20
150
350
35
<1.0
300
550
–
μA
mV
ns
ns
ns
ns
ns
μs
V
Vhys
500
1000
300
1000
250
1000
1.3
PWM change to source on
PWM change to source off
PWM change to sink on
PWM change to sink off
Propagation Delay Times
tpd
350
35
550
–
Crossover Delay
tCOD
tBLANK
VREFx
IREF
300
0.7
0.0
–
425
1
Blank Time
VREFx Pin Input Voltage Range
VREFx Pin Reference Input Current
Operating
–
1.5
VREF = 1.5
–
±1
ꢀA
%
VREF = 1.5, phase current = 100%
–5
–
5
Current Trip-Level Error3
VERR
V
V
REF = 1.5, phase current = 67%
REF = 1.5, phase current = 33%
–5
–
5
%
–15
–
15
%
Protection Circuits
VBB UVLO Threshold
VBB Hysteresis
VUV(VBB)
VUV(VBB)hys
VUV(VDD)
VUV(VDD)hys
TJTSD
VBB rising
VDD rising
7.3
400
2.65
75
7.6
500
2.8
105
165
15
7.9
600
2.95
125
175
–
V
mV
V
VDD UVLO Threshold
VDD Hysteresis
mV
°C
°C
Thermal Shutdown Temperature
Thermal Shutdown Hysteresis
155
–
TJTSDhys
1For input and output current specifications, negative current is defined as coming out of (sourcing) the specified device pin.
2Typical data are for initial design estimations only, and assume optimum manufacturing and application conditions. Performance may vary for indi-
vidual units, within the specified maximum and minimum limits.
3VERR = [(VREF/3) – VSENSE] / (VREF/3).
Allegro MicroSystems, Inc.
115 Northeast Cutoff
4
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
A3988
Quad DMOS Full Bridge PWM Motor Driver
Functional Description
Note: It is critical to ensure that the maximum rating of ±500 mV
on each SENSEx pin is not exceeded.
Device Operation The A3988 is designed to operate two
stepper motors, four dc motors, or one stepper and two dc motors.
The currents in each of the output full-bridges, all N-channel
DMOS, are regulated with fixed off-time pulse width modulated
(PWM) control circuitry. Each full-bridge peak current is set by
the value of an external current sense resistor, RSx , and a refer-
Fixed Off-Time The internal PWM current control circuitry
uses a one shot circuit to control the time the drivers remain off.
The one shot off-time, toff, is internally set to 30 μs.
ence voltage, VREFx
.
Blanking This function blanks the output of the current sense
comparator when the outputs are switched by the internal current
control circuitry. The comparator output is blanked to prevent
false detections of overcurrent conditions, due to reverse recovery
currents of the clamp diodes, or to switching transients related to
the capacitance of the load. The stepper blank time, tBLANK , is
approximately 1 μs.
If the logic inputs are pulled up to VDD, it is good practice to use
a high value pull-up resistor in order to limit current to the logic
inputs, should an overvoltage event occur. Logic inputs include:
PHASEx, I0x, and I1x.
Internal PWM Current Control Each full-bridge is con-
trolled by a fixed off-time PWM current control circuit that limits
the load current to a desired value, ITRIP. Initially, a diagonal pair
of source and sink DMOS outputs are enabled and current flows
through the motor winding and RSx. When the voltage across the
current sense resistor equals the voltage on the VREFx pin, the
current sense comparator resets the PWM latch, which turns off
the source driver.
Control Logic Communication is implemented via the indus-
try standard I1, I0, and PHASE interface. This communication
logic allows for full, half, and quarter step modes. Each bridge
also has an independent VREF input so higher resolution step
modes can be programmed by dynamically changing the voltage
on the VREFx pins.
Charge Pump (CP1 and CP2) The charge pump is used to
generate a gate supply greater than the VBB in order to drive the
source-side DMOS gates. A 0.1 μF ceramic capacitor should be
connected between CP1 and CP2 for pumping purposes. A 0.1 μF
ceramic capacitor is required between VCP and VBBx to act as a
reservoir to operate the high-side DMOS devices.
The maximum value of current limiting is set by the selection of
RS and the voltage at the VREF input with a transconductance
function approximated by:
ITripMax = VREF / (3×RS)
Each current step is a percentage of the maximum current,
Shutdown In the event of a fault (excessive junction tem-
perature, or low voltage on VCP), the outputs of the device are
disabled until the fault condition is removed. At power-up, the
undervoltage lockout (UVLO) circuit disables the drivers.
ITripMax. The actual current at each step ITrip is approximated by:
ITrip = (% ITripMax / 100) ITripMax
where % ITripMax is given in the Step Sequencing table.
Allegro MicroSystems, Inc.
115 Northeast Cutoff
5
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
A3988
Quad DMOS Full Bridge PWM Motor Driver
Synchronous Rectification When a PWM-off cycle is
triggered by an internal fixed off-time cycle, load current will
recirculate. The A3988 synchronous rectification feature will turn
on the appropriate MOSFETs during the current decay, and effec-
tively short out the body diodes with the low RDS(on) driver. This
significantly lowers power dissipation. When a zero current level
is detected, synchronous rectification is turned off to prevent
reversal of the load current.
Mixed Decay Operation The bridges operate in mixed
decay mode. Referring to figure 2, as the trip point is reached, the
device goes into fast decay mode for 30.1% of the fixed off-time
period. After this fast decay portion, tFD, the device switches
to slow decay mode for the remainder of the off-time. During
transitions from fast decay to slow decay, the drivers are forced
off for approximately 600 ns. This feature is added to prevent
shoot-through in the bridge. As shown in figure 2, during this
“dead time” portion, synchronous rectification is not active, and
the device operates in fast decay and slow decay only.
VPHASE
+
See Enlargement A
IOUT
0
–
Enlargement A
Fixed Off-Time 30 μs
21 μs
9 μs
ITrip
IOUT
SDSR
FDSR
FDDT
SDDT
SDDT
Figure 2. Mixed Decay Mode Operation
Allegro MicroSystems, Inc.
115 Northeast Cutoff
6
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
A3988
Quad DMOS Full Bridge PWM Motor Driver
Step Sequencing Diagrams
100.0
100.0
66.7
66.7
Phase 1
(%)
Phase 1
(%)
0
0
–66.7
–66.7
–100.0
–100.0
100.0
66.7
100.0
66.7
Phase 2
(%)
Phase 2
(%)
0
0
–66.7
–66.7
–100.0
–100.0
Half step 2 phase
Full step 2 phase
Modified half step 2 phase
Modified full step 2 phase
Figure 3. Step Sequencing for Full-Step Increments.
Figure 4. Step Sequencing for Half-Step Increments.
Allegro MicroSystems, Inc.
115 Northeast Cutoff
7
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
A3988
Quad DMOS Full Bridge PWM Motor Driver
100.0
66.7
33.3
Phase 1
(%)
0
–33.3
–66.7
–100.0
100.0
66.7
33.3
Phase 2
(%)
0
–33.3
–66.7
–100.0
Figure 5. Step Sequence for Quarter-Step Increments
Step Sequencing Settings
Phase 1
Phase 2
(%ITripMax)
Full
1/2
1/4
I0x
I1x
PHASE
I0x
I1x
PHASE
(%ITripMax
)
1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
0
33
100/66*
100
100
100
100/66*
33
0
33
100/66*
100
100
100
100/66*
33
H
L
L/H*
L
L
L
L/H*
L
H
L
L/H*
L
H
H
L
L
L
L
L
H
H
H
L
x
1
1
1
1
1
1
1
x
0
0
0
0
0
0
0
100
100
100/66*
33
0
33
100/66*
100
100
100
100/66*
33
L
L
L/H*
L
H
L
L/H*
L
L
L
L/H*
L
L
L
L
H
H
H
L
L
L
L
L
1
1
1
1
X
0
0
0
0
0
0
0
X
1
1
1
1
2
3
4
5
6
7
8
2
3
4
L
L
L
L
H
H
H
L
L
L
L/H*
L
0
33
100/66*
100
H
L
L/H*
L
H
L
* Denotes modified step mode
Allegro MicroSystems, Inc.
115 Northeast Cutoff
8
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
A3988
Quad DMOS Full Bridge PWM Motor Driver
Applications Information
are used to transfer heat to other layers of the PCB.
Motor Configurations For applications that require either a
stepper/dc motor driver or dual dc motor driver, Allegro offers the
A3989 and A3995. These devices are offered in the same 36 pin
QFN package as the A3988. The dc motor drivers are capable of
supplying 2.4 A at 36 V. Commutation is done with a standard
phase/enable logic interface. Please refer to the Allegro website
for further information and datasheets about those devices.
Grounding In order to minimize the effects of ground bounce
and offset issues, it is important to have a low impedance single-
point ground, known as a star ground, located very close to the
device. By making the connection between the exposed thermal
pad and the groundplane directly under the A3988, that area
becomes an ideal location for a star ground point.
DC Motor Control Each of the 4 full bridges has independent
PWM current control circuitry that makes the A3988 capable of
driving up to four dc motors at currents up to 1.2 A. Control of
the dc motors is accomplished by tying the I0, I1 pins together
creating an equivalent ENABLE function with maximum current
defined by the voltage on the corresponding VREF pin. The dc
motors can be driven via a PWM signal on this enable signal, or
on the corresponding PHASE pin. Motor control includes for-
ward, reverse, and coast.
A low impedance ground will prevent ground bounce during
high current operation and ensure that the supply voltage remains
stable at the input terminal. The recommended PCB layout shown
in the diagram below, illustrates how to create a star ground
under the device, to serve both as low impedance ground point
and thermal path.
Solder
A3988
Layout The printed circuit board should use a heavy ground-
plane. For optimum electrical and thermal performance, the
A3988 must be soldered directly onto the board. On the under-
side of the A3988 package is an exposed pad, which provides a
path for enhanced thermal dissipation. The thermal pad should be
soldered directly to an exposed surface on the PCB. Thermal vias
Trace (2 oz.)
Signal (1 oz.)
Ground (1 oz.)
PCB
Thermal (2 oz.)
Thermal Vias
VBB
VBB
CVCP
GND
CVCP
CIN3
CCP
GND
CCP
CIN3
RS1
1
RS3
I04
I13
OUT3A
SENSE3
OUT3B
VBB2
OUT3A
OUT3B
OUT1A
OUT1B
OUT1A
SENSE1
OUT1B
VBB1
U1
A3988
PAD
RS1
RS3
CIN1
CIN2
OUT2B
SENSE2
OUT2A
PHASE4
OUT4B
SENSE4
OUT4A
I14
CIN1
RS2
CIN2
RS4
RS2
RS4
OUT2B
OUT2A
OUT4B
OUT4A
CVDD1
CVDD2
CVDD1
CVDD2
GND
EV package layout shown
VDD
Figure 6. Printed circuit board layout with typical application circuit, shown at right. The copper area directly under the
A3988 (U1) is soldered to the exposed thermal pad on the underside of the device. The thermal vias serve also as electrical
vias, connecting it to the ground plane on the other side of the PCB , so the two copper areas together form the star ground.
Allegro MicroSystems, Inc.
115 Northeast Cutoff
9
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
A3988
Quad DMOS Full Bridge PWM Motor Driver
The two input capacitors should be placed in parallel, and as
close to the device supply pins as possible. The ceramic capaci-
tor should be closer to the pins than the bulk capacitor. This is
necessary because the ceramic capacitor will be responsible for
delivering the high frequency current components.
additional voltage drops, adversely affecting the ability of the
comparators to accurately measure the current in the windings.
As shown in the layout below, the SENSEx pins have very short
traces to the RSx resistors and very thick, low impedance traces
directly to the star ground underneath the device. If possible,
there should be no other components on the sense circuits.
Sense Pins The sense resistors, RSx, should have a very low
impedance path to ground, because they must carry a large cur-
rent while supporting very accurate voltage measurements by
the current sense comparators. Long ground traces will cause
Note: When selecting a value for the sense resistors, be sure not to
exceed the maximum voltage on the SENSEx pins of ±500 mV.
Allegro MicroSystems, Inc.
115 Northeast Cutoff
10
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
A3988
Quad DMOS Full Bridge PWM Motor Driver
Pin-out Diagrams
Package JP
Package EV
I13
I12
I14
37
38
39
40
41
42
43
44
45
46
47
48
24
23
22
21
20
19
18
17
16
15
14
13
NC
PHASE1
PHASE2
GND
I12
I11
28
29
30
31
32
33
34
35
36
18
17
16
15
14
13
12
11
10
I11
PHASE1
PHASE2
GND
GND
NC
GND
VCP
CP1
CP2
I01
VREF4
VREF3
VREF2
VREF1
VDD
PAD
Packages are not to scale
VCP
CP1
CP2
I01
VREF4
VREF3
VREF2
VREF1
VDD
PAD
I02
PHASE3
I03
I02
I03
PHASE3
PHASE4
I04
Terminal List Table
Number
Pin Name
Pin Description
DMOS Full-Bridge 1 Output A
EV
2
3
4
5
6
7
8
9
JP
3
4
5
6
8
9
10
13
14
15
16
17
18
19
20
21
22
24
27
28
29
31
32
33
34
37
38
39
40
42
43
44
OUT1A
SENSE1
OUT1B
VBB1
OUT2B
SENSE2
OUT2A
PHASE4
PHASE3
VDD
VREF1
VREF2
VREF3
VREF4
GND
Sense Resistor Terminal for Bridge 1
DMOS Full-Bridge 1 Output B
Load Supply Voltage
DMOS Full-Bridge 2 Output B
Sense Resistor Terminal for Bridge 2
DMOS Full-Bridge 2 Output A
Control Input
Control Input
Logic Supply Voltage
Analog Input
Analog Input
Analog Input
Analog Input
Ground
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
1
PHASE2
PHASE1
I14
Control Input
Control Input
Control Input
OUT4A
SENSE4
OUT4B
VBB2
OUT3B
SENSE3
OUT3A
I13
I12
I11
GND
VCP
CP1
CP2
I01
I02
I03
I04
DMOS Full-Bridge 4 Output A
Sense Resistor Terminal for Bridge 4
DMOS Full-Bridge 4 Output B
Load Supply Voltage
DMOS Full-Bridge 3 Output B
Sense Resistor Terminal for Bridge 3
DMOS Full-Bridge 3 Output A
Control Input
Control Input
Control Input
Ground
Reservoir Capacitor Terminal
Charge Pump Capacitor Terminal
Charge Pump Capacitor Terminal
Control Input
Control Input
Control Input
45
46
47
48
Control Input
1, 2, 7, 11,
12, 23, 25,
26, 30, 35,
36, 41
–
–
NC
No Connect
Exposed pad for enhanced thermal perfor-
mance. Should be soldered to the PCB.
–
PAD
Allegro MicroSystems, Inc.
115 Northeast Cutoff
11
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
A3988
Quad DMOS Full Bridge PWM Motor Driver
EV Package, 36 Pin QFN with Exposed Thermal Pad
0.30
0.50
1.15
6.00
36
36
1
2
1
A
2
C
6.00
4.15 5.80
C
D
36X
4.15
5.80
SEATING
PLANE
0.08
C
0.90
0.25
0.50
0.55
All dimensions nominal, not for tooling use
(reference JEDEC MO-220VJJD-1, case fig. 1)
Dimensions in millimeters
Exact case and lead configuration at supplier discretion within limits shown
A
B
Terminal #1 mark area
4.15
Exposed thermal pad (reference only, terminal #1
identifier appearance at supplier discretion)
2
1
Reference land pattern layout (reference IPC7351
C
QFN50P600X600X100-37V1M); All pads a minimum of 0.20 mm from
all adjacent pads; adjust as necessary to meet application process
requirements and PCB layout tolerances; when mounting on a
multilayer PCB, thermal vias at the exposed thermal pad land can
improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5)
36
4.15
D
Coplanarity includes exposed thermal pad and terminals
Allegro MicroSystems, Inc.
115 Northeast Cutoff
12
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
A3988
Quad DMOS Full Bridge PWM Motor Driver
JP Package, 48 Pin LQFP with Exposed Thermal Pad
0.30
9.00
7.00
0.50
1.70
4º
0.15
9.00
7.00
C
B
5.00
8.60
5.00
0.60
1.00
48
A
1
48
2
0.25
1
2
5.00
SEATING PLANE
GAGE PLANE
5.00
8.60
48X
C
SEATING
PLANE
0.08
C
0.22
0.50
Terminal #1 mark area
A
B
1.60 MAX
1.40
Exposed thermal pad (bottom surface)
Reference land pattern layout (reference IPC7351
QFP50P900X900X160-48M); adjust as necessary to meet
application process requirements and PCB layout
tolerances; when mounting on a multilayer PCB, thermal
vias at the exposed thermal pad land can improve thermal
dissipation (reference EIA/JEDEC Standard JESD51-5)
0.10
All dimensions nominal, not for tooling use
(reference JEDEC MS-026 BBCHD)
Dimensions in millimeters
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
The products described here are manufactured under one or more U.S. patents or U.S. patents pending.
Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to per-
mit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the
information being relied upon is current.
Use of any Allegro product in any Aerospace or Aviation application is strictly prohibited. Allegro’s products may only be used in life support de-
vices or systems with the express written approval of an Allegro Vice President, if a failure of an Allegro product can reasonably be expected to cause
the failure of that life support device or system, or to affect the safety or effectiveness of that device or system.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use;
nor for any infringement of patents or other rights of third parties which may result from its use.
Copyright ©2006, 2007, Allegro MicroSystems, Inc.
For the latest version of this document, visit our website:
www.allegromicro.com
Allegro MicroSystems, Inc.
115 Northeast Cutoff
13
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
相关型号：
A3988SJPTR-T
Stepper Motor Controller, 2.8A, NMOS, PQFP48, 7 X 7 MM, LEAD FREE, MS-026BBCHD, LQFP-48
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A3988_11
The A3988 is a quad DMOS full-bridge driver capable of driving up to two stepper motors or four DC motors.
ALLEGRO
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