A4931METTR-T [ALLEGRO]
Brushless DC Motor Controller, 5 X 5 MM, 0.90 MM HEIGHT, LEAD FREE, MO-220VHHD-1, QFN-28;
| 型号： | A4931METTR-T |
| 厂家： | 
ALLEGRO MICROSYSTEMS |
| 描述： | Brushless DC Motor Controller, 5 X 5 MM, 0.90 MM HEIGHT, LEAD FREE, MO-220VHHD-1, QFN-28 电动机控制 驱动 |
| 文件： | 总9页 (文件大小：242K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
A4931
3-Phase Brushless DC Motor Pre-Driver
Features and Benefits
▪ Drives 6 N-channel MOSFETs
Description
TheA4931isacomplete3-phasebrushlessDCmotorpre-driver.
▪ Synchronous rectification for low power dissipation
▪ Internal UVLO and thermal shutdown circuitry
▪ Hall element inputs
The device is capable of driving a wide range of N-channel
power MOSFETs and can support motor supply voltages up to
30 V. Commutation logic is determined by three Hall-element
inputs spaced at 120°.
▪ PWM current limiting
▪ Dead time protection
▪ FG outputs
▪ Standby mode
▪ Lock detect protection
Other features include fixed off-time pulse width modulation
(PWM)currentcontrolforlimitinginrushcurrent,locked-rotor
protectionwithadjustabledelay,thermalshutdown,overvoltage
monitor, and synchronous rectification. Internal synchronous
rectification reduces power dissipation by turning on the
appropriate MOSFETs during current decay, thus shorting
the body diode with the low RDS(on) MOSFET. Overvoltage
protection disables synchronous rectification when the motor
pumps the supply voltage beyond the overvoltage threshold
during current recirculation.
▪ Overvoltage protection
Package: 28-contact QFN (ET package)
The A4931 offers enable, direction, and brake inputs that can
control current using either phase or enable chopping. Logic
outputs FG1 and FG2 can be used to accurately measure motor
rotation. Output signals toggle state during Hall transitions,
providing an accurate speed output to a microcontroller or
speed control circuit.
Approximate Scale 1:1
Operating temperature range is –20°C to 105°C. The A4931
is supplied in a 5 mm × 5 mm, 28-terminal QFN package with
exposed thermal pad. This small footprint package is lead (Pb)
free with 100% matte tin leadframe plating.
Typical Application
0.1 μF
0.1 μF
0.1 μF
0.1 μF 2 kΩ
CLD HBIAS CP1 CP2 VCP
VBB
GHA
VIN
VIN
SA
FG1
A4931
FG2
M
GLA
System
Control
Logic
GHB
SB
GLB
BRAKEZ
ENABLE
DIR
GHC
SC
GLC
SENSE
GND
HA+ HA– HB+ HB– HC+ HC–
4931-DS, Rev. 6
A4931
3-Phase Brushless DC Motor Pre-Driver
Selection Guide
Part Number
Packing
Package
A4931METTR-T
1500 pieces per reel
5 mm x 5 mm, 0.90 mm nominal height QFN
Absolute Maximum Ratings
Characteristic
Symbol
VBB
Notes
Rating
38
Units
V
Load Supply Voltage
Motor Phase Output
SX
tw < 500 ns
DC
–3
V
Hall Input
VHx
–0.3 to 7
–0.3 to 7
–20 to 105
150
V
Logic Input Voltage Range
Operating Ambient Temperature
Maximum Junction Temperature
Storage Temperature
VIN
V
TA
Range M
ºC
ºC
ºC
TJ(max)
Tstg
–40 to 150
Thermal Characteristics
Characteristic
Package Thermal Resistance, Junction
to Ambient
Package Thermal Resistance, Junction
to Exposed Pad
Symbol
Test Conditions*
Rating
Units
ºC/W
ºC/W
RθJA
4-layer PCB based on JEDEC standard
32
2
RθJP
*For additional information, refer to the Allegro website.
Allegro MicroSystems, LLC
115 Northeast Cutoff
2
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
A4931
3-Phase Brushless DC Motor Pre-Driver
Functional Block Diagram
0.1 μF
0.1 μF
Lock
Detect
CLD
FG1
CHARGE PUMP
VCP
VBB
0.1 μF
HBIAS
HA+
VREG
2 kΩ
HALL
VIN
0.1 μF
OVP
HA-
VCP
VREG
Commun-
ication
GHA
SA
HB+
HB-
HALL
HALL
Logic
GHB
SB
GATE
DRIVE
HC+
HC-
GLB
GHC
SC
Control
Logic
GLC
FG1
FG2
GLA
BRAKEZ
DIR
SENSE
RSENSE
System
Logic
200 mV
ENABLE
VIN
GND
Terminal List
Number
Name
Description
Number
15
Name
Description
1
2
HA+
HA -
Hall input A
Hall input A
Hall input B
Hall input B
Hall input C
Hall input C
Ground
GLB
GLA
Low side gate drive B
Low side gate drive A
High side gate drive C
16
3
HB+
17
GHC
SC
4
HB -
18
High side source connection C
High side gate drive B
5
HC+
HC-
19
GHB
SB
6
20
High side source connection B
High side gate drive A
7
GND
HBIAS
CP1
21
GHA
SA
8
Hall bias power supply output
Charge pump capacitor terminal
Charge pump capacitor terminal
Supply voltage
22
High side source connection A
FG 1 speed control output (3 Φ inputs)
FG 2 speed control output (ΦA input)
Locked rotor detect timing capacitor
Logic input – motor direction
9
23
FG1
10
11
12
13
14
CP2
24
FG2
VBB
25
CLD
VCP
SENSE
GLC
Reservoir capacitor terminal
Sense resistor connection
Low side gate drive C
26
DIR
27
ENABLE
BRAKEZ
Logic input – external PWM control
Logic input – motor brake (active low)
28
Allegro MicroSystems, LLC
115 Northeast Cutoff
3
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
A4931
3-Phase Brushless DC Motor Pre-Driver
ELECTRICAL CHARACTERISTICS* Valid at TA= 25°C, VBB = 24 V, unless noted otherwise
Characteristics
Symbol
Test Conditions
Min.
8
Typ.
Max.
VBBOV
6
Units
V
Supply Voltage Range
VBB
Operating
–
5
fPWM < 30 kHz, CLOAD = 1000 pF
Charge pump on, outputs disabled, Standby mode
0 mA ≤ IHBIAS ≤ 24 mA
–
mA
mA
V
Motor Supply Current
IBB
–
3
3.5
HBIAS
VHBIAS
7.2
30
7.5
–
7.8
HBIAS Current Limit
Control Logic
IHBIASlim
–
mA
VIN(1)
VIN(0)
IIN(1)
2
–
–
–
–
0.8
1
V
V
Logic Input Voltage
Logic Input Current
Input Pin Glitch Reject
VIN = 2 V
–1
–1
350
700
2.1
–
<1.0
<–1.0
500
1000
3
μA
μA
ns
ns
ms
μs
IIN(0)
VIN = 0.8 V
1
ENB pin
650
1300
3.9
25
tGLITCH
DIR, BRAKEZ pins
To outputs off
CHBIAS = 0.1 μF
ENB Standby Pulse Propagation Delay
HBIAS Wake-up Delay, Standby Mode
Gate Drive
tdENB
tdHBIAS
15
High-Side Gate Drive Output
Low-Side Gate Drive Output
Gate Drive Current (Sourcing)
Gate Drive Pull Down Resistance
Dead Time
VGS(H)
VGS(L)
IGate
Relative to VBB, IGATE = 2 mA
IGATE = 2 mA
7
7
–
–
–
–
V
V
GH = GL = 4 V
20
10
700
180
18
30
–
mA
Ω
RGate
tdead
VREF
tOFF
28
40
1000
200
25
1300
220
37
ns
mV
μs
Current Limit Input Threshold
Fixed Off-Time
Protection
Thermal Shutdown Temperature
Thermal Shutdown Hysteresis
VBB UVLO Enable Threshold
VBB UVLO Hysteresis
VCP UVLO
TJTSD
TJTSDhys
VBBUV
VBBUVhys
VCPUV
tlock
155
14
170
15
7
185
26
°C
°C
V
Rising VBB
6.2
0.4
4.6
1.5
30
7.85
1
0.75
–
V
Relative to VBB
C = 0.1 μF
6
V
Lock Detect Duration
2
2.5
37.5
s
VBB Overvoltage Threshold
Hall Logic
VBBOV
Rising VBB
33
V
Hall Input Current
IHALL
VCMR
VHALL
Vth
VIN = 0.2 to 3.5 V
–1
0.2
60
–
0
1
3.5
–
μA
V
Common Mode Input Range
AC Input Voltage Range
Hall Thresholds
–
–
+10,–10
20
mVp-p
mV
mV
mV
μs
Difference between Hall inputs at transitions
TJ = 25°C
–
10
5
30
40
–
Hall Threshold Hysteresis
VHYS
tpulse
TJ = –20°C to 125°C
20
Pulse Reject Filter
FG
–
2
FG Output Saturation Voltage
FG Leakage Current
VFG(sat)
IFGlkg
IFG = 2 mA
VFG = 5 V
–
–
–
–
0.5
1
V
μA
*Typical data are for initial design estimations only, and assume optimum manufacturing and application conditions. Performance may vary for
individual units, within the specified maximum and minimum limits.
For input and output current specifications, negative current is defined as coming out of (sourcing) the specified device pin.
Specifications throughout the allowed operating temperature range are guaranteed by design and characterization.
Allegro MicroSystems, LLC
115 Northeast Cutoff
4
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
A4931
3-Phase Brushless DC Motor Pre-Driver
Logic States Table (See timing charts, below) X = Don’t Care, Z = high impedance
Inputs
Resulting Pre-Driver Outputs
ENB GHA GLA GHB GLB GHC GLC
Motor Output
Condition
HA
+
+
+
–
HB
–
HC
+
–
BRAKEZ
A
B
LO
Z
C
A
B
C
D
E
F
HI
HI
HI
HI
HI
HI
HI
HI
HI
HI
HI
HI
HI
HI
LO
LO
LO
LO
LO
LO
LO
LO
LO
LO
LO
LO
LO
X
HI
HI
LO
LO
LO
HI
LO
LO
HI
HI
LO
LO
LO
LO
HI
LO
LO
LO
LO
HI
LO
HI
HI
HI
Z
Z
LO
LO
Z
–
+
+
+
–
–
LO
LO
LO
LO
LO
LO
HI
HI
HI
HI
Z
DIR = 1
(Forward)
–
HI
LO
LO
LO
LO
HI
LO
LO
Z
–
+
+
+
+
+
–
HI
LO
LO
HI
HI
HI
Z
–
LO
HI
HI
LO
HI
HI
Z
A
F
+
–
–
LO
LO
LO
HI
LO
LO
LO
LO
HI
LO
Z
–
LO
LO
LO
LO
HI
HI
LO
LO
Z
E
D
C
B
–
+
+
+
–
LO
LO
LO
LO
LO
LO
LO
HI
HI
HI
Z
DIR = 0
(Reverse)
–
HI
LO
LO
LO
LO
LO
HI
LO
LO
Z
+
+
+
–
–
LO
LO
LO
LO
LO
HI
HI
HI
Z
–
LO
LO
LO
HI
HI
LO
Z
Fault*
Fault*
Brake*
+
–
+
–
LO
LO
HI
LO
LO
LO
Z
X
Z
Z
Z
X
X
X
X
LO
LO
LO
* DIR = Don’t Care
DIR = 1 = FOR
DIR = 0 = REV
A
F
E
D
C
B
A
B
C
D
E
F
HA
HA
HB
HC
HB
HC
FG1
FG1
SA
SB
SC
SA
SB
SC
Allegro MicroSystems, LLC
115 Northeast Cutoff
5
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
A4931
3-Phase Brushless DC Motor Pre-Driver
Power-up and Standby Modes Timing Diagram
VBB
VBBUV
Charge
Pump
HBIAS
Voltage
Standby Mode
Turn off Hall
Bias Supply
3 ms
tdENB
ENB
Outputs Enabled
Outputs Disabled
Outputs Enabled
Power-up and Standby Modes Timing Diagram
VBB
VBBUV
VCPUV
VHBIAS
VBB+7.5 V
Charge
Pump
7.5V
HBIAS
Voltage
ENB
PWM
Outputs Enabled
Outputs Disabled
Allegro MicroSystems, LLC
115 Northeast Cutoff
6
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
A4931
3-Phase Brushless DC Motor Pre-Driver
Functional Description
pletes, in order to provide the blanking function. The blanking
timer is reset when ENB is chopped or DIR is changed. With
external PWM control, a DIR change or an ENB on triggers the
blanking function. The duration is fixed at 1.5 μs.
Current Regulation Load current is regulated by an internal
fixed off-time PWM control circuit. When the outputs of the full
bridge are turned on, current increases in the motor winding until
it reaches a value, ITRIP, given by:
Synchronous Rectification When a PWM-off cycle is
triggered, either by a chop command on ENB or by an internal
fixed off-time cycle, load current recirculates. The A4931 syn-
chronous rectification feature turns on the appropriate MOSFETs
during the current decay, and effectively shorts out the body
diodes with the low RDS(on) driver. This lowers power dissipation
significantly and can eliminate the need for external Schottky
diodes.
ITRIP = 200 mV / RSENSE .
When ITRIP is reached, the sense comparator resets the source
enable latch, turning off the source driver. At this point, load
inductance causes the current to recirculate for the fixed off-time
period.
Enable Logic The Enable input terminal (ENB pin) allows
external PWM. ENB low turns on the selected sink-source pair.
ENB high switches off the appropriate drivers and the load
current decays. If ENB is held low, the current will rise until it
reaches the level set by the internal current control circuit. Typi-
cally PWM frequency is in 20 kHz to 30 kHz range. If the ENB
high pulse width exceeds 3 ms, the gate outputs are disabled. The
Enable logic is summarized in the following table:
Brake Mode A logic low on the BRAKEZ pin activates Brake
mode. A logic high allows normal operation. Braking turns on all
three sink drivers, effectively shorting out the motor-generated
BEMF. The BRAKEZ input overrides the ENB input and also the
Lock Detect function.
It is important to note that the internal PWM current control cir-
cuit does not limit the current when braking, because the current
does not flow through the sense resistor. The maximum current
can be approximated by VBEMF / RLOAD. Care should be taken to
insure that the maximum ratings of the A4391 are not exceeded
in the worse case braking situation, high speed and high inertial
load.
ENB Pin Setting
0
Outputs
On
Outputs State
Drive
Slow Decay with
Synchronous
Rectification
1
Source Chopped
Off
1 for > 3 ms typical
Disable
Fixed Off-Time The A4931 fixed off-time is set to 25 μs
nominal.
HBIAS Function This function provides a power supply of
7.5 V, current-limited to 30 mA. This reference voltage is used to
power the logic sections of the IC and also to power the external
Hall elements.
PWM Blank Timer When a source driver turns on, a current
spike occurs due to the reverse recovery currents of the clamp
diodes as well as switching transients related to distributed
capacitance in the load. To prevent this current spike from errone-
ously resetting the source Enable latch, the sense comparator is
blanked. The blanking timer runs after the off-time counter com-
Standby Mode To prevent excessive power dissipation due
to the current draw of the external Hall elements, Standby mode
turns off the HBIAS output voltage. Standby mode is triggered
Allegro MicroSystems, LLC
115 Northeast Cutoff
7
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
A4931
3-Phase Brushless DC Motor Pre-Driver
by holding ENB high for longer than 3 ms. Note that Brake mode
overrides Standby mode, so hold the BRAKEZ pin high in order
to enter Standby mode.
Lock Detect Function The IC will evaluate a locked rotor
condition under either of these two different conditions:
• The FG1 signal is not consistently changing.
Charge Pump The internal charge pump is used to generate a
supply above VBB to drive the high-side MOSFETs. The volt-
age on the VCP pin is internally monitored, and in case of a fault
condition, the outputs of the device are disabled.
• The proper commutation sequence is not being followed. The
motor can be locked in a condition in which it toggles between
two specific Hall device states.
Both of these fault conditions are allowed to persist for period
of time, tlock. tlock is set by capacitor connected to CLD pin. CLD
produces a triangle waveform (1.67 V peak-to-peak) with fre-
quency linearly related to the capacitor value. tlock is defined as
127 cycles of this triangle waveform, or:
Fault Shutdown In the event of a fault due to excessive
junction temperature or due to low voltage on VCP or VBB,
the outputs of the device are disabled until the fault condition is
removed. At power-up the UVLO circuit disables the drivers.
tlock = CLD × 20 s/μF
Overvoltage Protection VBB is monitored to determine if
a hazardous voltage is present due to the motor generator pump-
ing up the supply bus. When the voltage exceeds VBBOV, the
synchronous rectification feature is disabled.
After the wait time, tlock , has expired, the outputs are disabled,
and the fault is latched. These fault conditions can only be cleared
by any one of the following actions:
• Rising or falling edge on the DIR pin
Overtemperature Protection If die temperature exceeds
approximately 170°C, the Thermal Shutdown function will dis-
able the outputs until the internal temperature falls below the
15°C hysteresis.
• VBB UVLO threshold exceeded (during power-up cycle)
• ENB pin held high for > tlock / 2
The Lock Detect function can be disabled by connecting CLD to
GND.
Hall State Reporting The FG1 pin is an open drain output
that changes state at each transition of an external Hall element.
The FG2 pin is an open drain output that changes state at each
HAx transition.
When the A4931 is in Brake mode, the Lock Detect counter is
disabled.
Allegro MicroSystems, LLC
115 Northeast Cutoff
8
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
A4931
3-Phase Brushless DC Motor Pre-Driver
ET Package, 28-Contact QFN
0.30
5.00 ±0.15
0.50
1.15
28
28
1
2
1
A
5.00 ±0.15
3.15 4.80
3.15
4.80
D
29X
C
SEATING
PLANE
0.08
C
C
PCB Layout Reference View
+0.05
–0.07
0.25
0.90 ±0.10
0.50
For Reference Only
(reference JEDEC MO-220VHHD-1)
Dimensions in millimeters
Exact case and lead configuration at supplier discretion within limits shown
+0.20
–0.10
0.55
A
B
B
Terminal #1 mark area
3.15
Exposed thermal pad (reference only, terminal #1
identifier appearance at supplier discretion)
2
1
C
Reference land pattern layout (reference IPC7351
QFN50P500X500X100-29V1M);
All pads a minimum of 0.20 mm from all adjacent pads; adjust as
necessary to meet application process requirements and PCB layout
tolerances; when mounting on a multilayer PCB, thermal vias at the
exposed thermal pad land can improve thermal dissipation (reference
EIA/JEDEC Standard JESD51-5)
28
3.15
D
Coplanarity includes exposed thermal pad and terminals
Copyright ©2007-2013, Allegro MicroSystems, LLC
Allegro MicroSystems, LLC reserves the right to make, from time to time, such departures from the detail specifications as may be required to
permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that
the information being relied upon is current.
Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the
failure of that life support device or system, or to affect the safety or effectiveness of that device or system.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, LLC assumes no responsibility for its
use; nor for any infringement of patents or other rights of third parties which may result from its use.
For the latest version of this document, visit our website:
www.allegromicro.com
Allegro MicroSystems, LLC
115 Northeast Cutoff
9
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
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