AMT49700KETJTR_技术文档

AMT49700

Automotive Stepper Driver

FEATURES AND BENEFITS

• Peak motor current up to 1.6 A at 28 V.

• Low R_DS(ON)outputs, 0.5 Ω source and sink typical

• Continuous operation at high ambient temperature

• 3.7 to 42 V supply operation

DESCRIPTION

TheAMT49700isaflexiblemicrosteppingsteppermotordriver

with integrated phase current control, a built in translator, and

simple motion control. It is a single chip solution designed to

operate bipolar stepper motors in full, half, quarter, eighth and

sixteenth step modes, at up to 28 V.

• Adaptive mixed current decay

• Synchronous rectification for low power dissipation

• Output slew control and PWM frequency spreading for

EMC noise reduction

• Internal overvoltage and undervoltage lockout

• Hot warning and overtemperature shutdown

• Short-circuit, open-load diagnostics

• Programmable motion control

• Configurable through serial interface

• Simple step and direction control option

The current regulator operates with fixed frequency PWM and

uses adaptive mixed current decay to reduce audible motor

noise and increase step accuracy. The current in each phase

of the motor is controlled through a DMOS full-bridge using

synchronousrectificationtoimprovepowerdissipation.Internal

circuitsandtimerspreventcross-conductionandshootthrough

when switching between high-side and low-side drives.

The outputs are protected from short circuits and features for

low load current detection are included. Chip level protection

includes hot thermal warning, overtemperature shutdown,

overvoltage lockout, and undervoltage lockout.

APPLICATIONS

• Automotive stepper motors

• Engine management

• Headlamp positioning

• HVAC flap and valve control

The AMT49700 is fully controlled and configured through an

SPI-compatible serial interface. It provides single step control

withadjustablemicrostepresolutionforfinepositioningcontrol

andprogrammablemotioncontrolprovidingindependentmotor

acceleration, deceleration, start speed, run speed, and number

of steps with a single SPI command. In addition, detailed

diagnostics are available on the serial data output.

PACKAGE:

32-Pin QFN with Exposed Thermal Pad (suffix ET)

The AMT49700 is supplied in a 32-terminal 5 mm × 5 mm

QFN package with an exposed thermal pad (package type ET).

Not to scale

Logic

Supply

Automotive

12 V Power Net

CP1 CP2

VCP VBB

OAP

STEP

DIR

OAM

Micro-

Controller

^DIAGAMT49700

Stepper

Motor

RESETn

OBP

SCK

SDI

OBM

SDO

STRn

GND

GNDPA GNDPB

Figure 1: Typical Application Diagram

February 15, 2019

AMT49700-DS

MCO-0000614

AMT49700

Automotive Stepper Driver

Selection Guide

Part Number

Packing

Package

5 mm × 5 mm, 0.9 mm nominal height

QFN with exposed thermal pad

AMT49700KETJTR

1500 pieces per 7-inch reel

Table of Contents

Features and Benefits........................................................... 1

Description.......................................................................... 1

Applications......................................................................... 1

Package ............................................................................. 1

Typical Application Diagram................................................... 1

Selection Guide ................................................................... 2

Specifications ...................................................................... 3

Absolute Maximum Ratings................................................ 3

Thermal Characteristics..................................................... 3

Pinout Diagram and Terminal List........................................... 4

Functional Block Diagram ..................................................... 5

Electrical Characteristics....................................................... 6

Timing Diagrams.................................................................. 9

Functional Description ........................................................ 12

Terminal Functions.......................................................... 12

Stepper Motor Motion Control........................................... 13

Single-Step Control ..................................................... 13

Step-Sequence Control................................................ 13

Driving a Stepper Motor................................................... 14

Phase Current Control..................................................... 14

Phase Current Table........................................................ 15

PWM Frequency............................................................. 15

PWM Frequency Dither ................................................... 16

Low Power Sleep Mode................................................... 16

Diagnostics .................................................................... 17

System Diagnostics......................................................... 18

Supply Voltage Monitors............................................... 18

Temperature Monitors.................................................. 18

Bridge and Output Diagnostics ......................................... 19

Shorted Load.............................................................. 19

Overcurrent Fault Blanking ........................................... 19

Overcurrent Fault Reset and Retry ................................ 19

Open-Load Detection................................................... 19

False State Reset ........................................................... 20

Reset Pulse................................................................ 20

Reset Command ......................................................... 20

Sleep......................................................................... 20

Diagnostic Register Read............................................. 20

Status Register Read................................................... 20

Stepping..................................................................... 20

Disable Serial Reset .................................................... 20

Step Angle Reset............................................................ 20

Braking.......................................................................... 20

Serial Interface .................................................................. 21

Serial Registers Definitions table....................................... 21

Serial Register Content.................................................... 23

Status and Diagnostic Registers ....................................... 24

Resetting Status and Diagnostic Registers ..................... 25

Serial Register Reference ................................................... 26

Phase Current Table........................................................... 32

Applications Information...................................................... 33

Motor Microstepping........................................................ 33

Phase Table and Phase Diagram .................................. 33

Microstepping with the Step Sequencer ......................... 35

Single-Step Control ..................................................... 37

Motion Control with the Step Sequencer ............................ 39

Profile Command Update ............................................. 41

Continuous Run Mode ................................................. 41

Layout ........................................................................... 42

Decoupling ................................................................. 42

Grounding .................................................................. 42

Input/Output Structures....................................................... 43

Package Outline Drawing.................................................... 44

2

Allegro MicroSystems, LLC

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

AMT49700

Automotive Stepper Driver

SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS ^[1]

Characteristic

Symbol

V_BB

Notes

Rating

–0.3 to 42

Unit

V

Load Supply Voltage

Terminal CP1

V_CP1

V_CP2

V_CP

–0.3 to V_BB+ 0.3

–0.3 to V_BB+ 8

–0.3 to 6

V

Terminal CP2

V

Terminal VCP

V

Terminals STEP, DIR, SCK, SDI, SDO, STRn

Terminal RESETn

V

V_RESETn

V_DIAG

Can be pulled to V_BBwith 33 kΩ

–0.3 to 6

V

Terminal DIAG

–0.3 to 40

V

Terminals OAP, OAM, OBP, OBM

–0.3 to V_BB

V

V_GNDPA

,

Terminals GNDPA, GNDPB

All ground terminals must be connected together

–0.1 to 0.1

V

Ambient Operating Temperature Range ^[2]

Maximum Continuous Junction Temperature

T_A

–40 to 150

165

°C

T_J(max)

Overtemperature event not exceeding 10 seconds, lifetime

duration not exceeding 10 hours, ensured by design and

characterization.

Transient Junction Temperature

Storage Temperature Range

T_Jt

175

°C

T_stg

–55 to 150

^[1]With respect to GND

^[2]Limited by power dissipation

THERMAL CHARACTERISTICS: May require derating at maximum conditions; see application information

Characteristic

Symbol

Test Conditions ^[3]

Value

Unit

High-K PCB (multilayer with significant copper areas,

based on JEDEC standard JESD51-7)

Package Thermal Resistance

R_θJA

30

°C/W

^[3]Additional thermal information available on the Allegro website.

3

Allegro MicroSystems, LLC

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

AMT49700

Automotive Stepper Driver

PINOUT DIAGRAM AND TERMINAL LIST

1

ꢇ

3

ꢊ

5

ꢍ

ꢌ

ꢋ

ꢇꢊ

ꢇ3

ꢇꢇ

ꢇ1

ꢇ0

19

1ꢋ

1ꢌ

CPꢇ

NC

ꢄNꢁPA

NC

ꢅCP

ꢃAM

NC

PAꢁ

RꢈSꢈꢉn

ꢁꢂR

NC

ꢃꢆM

NC

SꢉꢈP

SꢉRn

ꢄNꢁPꢆ

Package ET, 32-Pin eQFN Pinout Diagram

Terminal List Table

Number

Name

Function

Charge Pump Capacitor

31

CP1

1

CP2

Charge Pump Capacitor

Diagnostic output

12

DIAG

6

29

24

17

22

25

19

16

5

DIR

GND

GNDPA

GNDPB

OAM

OAP

Direction Input

Ground

Power Ground for A Phase

Power Ground for B Phase

Bridge A negative output

Bridge A positive output

Bridge B negative output

Bridge B positive output

Standby Mode Control

Serial Clock Input

OBM

OBP

RESETn

SCK

9

10

11

7

SDI

Serial Data Input

SDO

STEP

STRn

VBB

Serial Data Output

Step Input

8

Serial Strobe (chip select) Input

Main Supply

27

14

3

VBB

Main Supply

VCP

Pump Storage Capacitor

Exposed Thermal Pad

PAD

–

4

Allegro MicroSystems, LLC

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

AMT49700

Automotive Stepper Driver

FUNCTIONAL BLOCK DIAGRAM

CP1

CP2

VCP

Charge

Pump

Oscillator

SENSA

Regulator

VBAT

REF

VBB

6-bit

DAC

OAP

OAM

PWM

Control

System

STEP

DIR

Control

&

RESETn

GNDPA

Registers

Bridge

Gate

Drive

Control

Logic

VBAT

VBB

SCK

SDI

SDO

STRn

Motion

Control

PWM

OBP

OBM

Control

REF

6-bit

DAC

GNDPB

SENSB

Undervoltage, Overvoltage

Hot Warning, Over Temp

Short Detect, Open Detect

DIAG

GND

PAD

5

Allegro MicroSystems, LLC

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

AMT49700

Automotive Stepper Driver

ELECTRICAL CHARACTERISTICS: Valid at T_J= –40°C to 150°C, V_BB= 5.5 to 28 V, unless otherwise speciﬁed

Characteristic

SUPPLIES

Symbol

Test Conditions

Min.

Typ.

Max.

Units

No unsafe states

0

5.5

–

42

V_BBOV

25

V

Supply Voltage Range ^[4][5]

Supply Quiescent Current

Logic I/O Regulator Voltage

V_BB

Outputs driving

DIS = 1

mA

Sleep Mode, V_BB= 12 V, GTS = 1,

STRn = 1 or V_RESETn< 0.5 V, T_J= 25°C

–

20

60

40

µA

I_BBQ

Sleep Mode, V_BB= 12 V, GTS = 1,

STRn = 1 or V_RESETn< 0.5 V, T_J= 150°C

100

VLR = 0

VLR = 1

3.1

4.8

3.3

5.0

3.5

5.2

V

V_LIO

With respect to V_BB, V_BB> 7.5 V, DIS = 1,

GTS = 0, RESETn = 1

Charge Pump Voltage

V_CP

–

7.0

–

V

MOTOR BRIDGE OUTPUT

V_BB≥ 7 V, I_OUT= –1 A^[1], T_J= 25°C

–

500

900

–

600

1100

1.4

mΩ

V

High-Side On-Resistance

R_ONH

V

_BB= 13.5 V, I_OUT= –1 A^[1], T_J= 150°C

I_F= 1 A

High-Side Body Diode Forward Voltage

V_FH

I_F= 0.1 A

–

1.2

V

V_BB≥ 7 V, I_OUT= 1 A, T_J= 25°C,

MXI[4:0] = 3…31

–

500

900

600

1100

1800

3000

mΩ

V_BB= 13.5 V, I_OUT= 1 A, T_J= 150°C,

MXI[4:0] = 3…31

Low-Side On-Resistance

R_ONL

V_BB≥ 7 V, I_OUT= 150 mA, T_J= 25°C,

1200

2100

MXI[4:0] = 0…2

V

_BB= 13.5 V, I_OUT= 150 mA, T_J= 150°C,

MXI[4:0] = 0…2

I_F= –1 A^[1]

–

1.4

1.2

120

–

V

Low-Side Body Diode Forward Voltage

Output Leakage Current ^[1]

V_FL

I_F= –0.1 A^[1]

GTS = 0, RESETn = 1, DIS = 1, V_O= V_BB

GTS = 0, RESETn = 1, DIS = 1, V_O= 0 V

GTS = 1 or V_RESETn< 0.5 V, V_O= V_BB

GTS = 1 or V_RESETn< 0.5 V, V_O= 0 V

SLEW = 0, V_BB= 13.5 V

–

65

µA

–200

–

–120

<1.0

100

30

µA

I_LO

20

–

µA

–20

–

µA

–

V/µs

Output Slew Rate

dV_O/dt

SLEW = 1, V_BB= 13.5 V

–

Continued on the next page…

6

Allegro MicroSystems, LLC

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

AMT49700

Automotive Stepper Driver

ELECTRICAL CHARACTERISTICS (continued): Valid at T_J= –40°C to 150°C, V_BB= 5.5 to 28 V, unless otherwise speciﬁed

Characteristic

CURRENT CONTROL

System Clock Period

Symbol

Test Conditions

Min.

Typ.

Max.

Units

t_OSC

47.5

3.32

1

50

3.5

–

52.5

3.68

3.5

ns

µs

Default power-up value

Blank Time

t_BLANK

Programmable range

Default power-up value

Programmable range

Default power-up value, DS = 0

Programmable range, DS = 0

Default power-up value

Programmable range

Default power-up value

Programmable range

Default power-up value

Programmable range

MXI[4:0] = 3…31

µs

18.32

16.4

49.4

36.0

–

19.20

–

20.24

27.8

54.6

60.8

–

kHz

µs

PWM Frequency

f_PWM

t_PWM

t_PMX

52.0

–

Bridge PWM Period

µs

32

–

µs

Maximum PWM On Time

Bridge PWM Dither Step Period

Bridge PWM Dither Dwell Time

Current Trip Point Error ^[2]

disable

–0.19

–0.2

0.95

1

56

µs

–0.20

–

–0.21

–1.6

1.05

10

µs

Δt_PWM

µs

1.00

–

ms

%

t_DIT

–

±10

±15

E_ITrip

MXI[4:0] = 0…2

–

%

LOGIC INPUT AND OUTPUT – DC PARAMETERS

Input Low Voltage

V_IL

V_ILS

V_IH

–

0.3 × V_LIO

V

Input Low Voltage for Sleep Mode

Input High Voltage

RESETn input only

–

0.5

–

0.7 × V_LIO

–

V

Input Hysteresis

V_IHys

R_PU

R_PD

V_OL

V_OH

I_OSD

I_ODI

100

300

80

–

mV

kΩ

V

Input Pull-Up Resistor

Input Pull-Down Resistor

Output Low Voltage

STRn

–

SDI, STEP, DIR, RESETn

I_OL= 1 mA

–

0.4

–

Output High Voltage

I_OL= –1 mA^[1]

V_LIO– 0.4

–

V

Output Leakage ^[1](SDO)

Output Leakage ^[1](DIAG)

0 V < V_O< V_LIO, STRn = 1

0 V < V_O< 9 V

–1

–

1

µA

–

1

LOGIC INPUT AND OUTPUT – DYNAMIC PARAMETERS ^[3]

Reset Pulse Width

t_RST

t_RSD

t_EN

1.5

40

–

1

8

–

µs

Reset Shutdown Pulse Width

Wake Up From Sleep

1

ms

µs

Interface Ready From Sleep

Input Pulse Filter Time

t_IR

–

1.1

–

t_PIN

STEP, DIR pin

–

Continued on the next page…

7

Allegro MicroSystems, LLC

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

AMT49700

Automotive Stepper Driver

ELECTRICAL CHARACTERISTICS (continued): Valid at T_J= –40°C to 150°C, V_BB= 5.5 to 28 V, unless otherwise speciﬁed

Characteristic

Symbol

Test Conditions

Min.

Typ.

Max.

Units

SERIAL INTERFACE – DYNAMIC PARAMETERS ^[3]

Clock High Time

t_SCKH

t_SCKL

t_STLD

t_STLG

t_STRH

t_SDOE

t_SDOD

t_SDOV

t_SDOH

t_SDIS

A^[3]

B ^[3]

C ^[3]

D ^[3]

E ^[3]

F ^[3]

G ^[3]

H ^[3]

I ^[3]

50

150

30

350

–

ns

Clock Low Time

Strobe Lead Time

–

Strobe Lag Time

–

Strobe High Time

–

Data Out Enable Time

40

30

45

–

Data Out Disable Time

–

Data Out Valid Time from Clock Falling

Data Out Hold Time from Clock Falling

Data In Setup Time to Clock Rising

Data In Hold Time from Clock Rising

DIAGNOSTICS AND PROTECTION

VBB Overvoltage Threshold ^[5]

VBB Overvoltage Hysteresis ^[5]

VBB Undervoltage Threshold ^[5]

VBB Undervoltage Hysteresis

VBB POR

–

5

J ^[3]

K ^[3]

15

10

–

t_SDIH

–

V_BBOV

V_BBOVHys

V_BBUV

V_BBrising

V_BBfalling

32

2

34

–

36

4

V

4.7

100

–

4.9

200

3.2

4.5

350

2.2

5.5

–

5.1

300

3.7

4.85

500

3

V

V_BBUVHys

V_BBPOR

V_CPUVH

V_CPUVHHys

I_OCH

mV

V

V_BBfalling

V_CPfalling

VCP Undervoltage Threshold

VCP Undervoltage Hysteresis

High-Side Overcurrent Threshold

High-Side Overcurrent Limit

High-Side Overcurrent Margin

4.3

200

1.6

2.4

300

1.6

0.35

1.9

8

V

mV

A

I_LIMH

Active during t_OC

I_MAR= I_LIMH– I_OCH

MXI[4:0] = 3…31

MXI[4:0] = 0…2

Default fault delay

OLT = 0 (Default)

OLT = 1

8

A

I_MAR

–

mA

A

2.2

0.55

2.0

14

3

Low-Side Overcurrent Threshold

Overcurrent Fault Delay

I_OCL

t_OC

0.75

2.1

25

39

A

µs

mA

Open Load Current Threshold

E_IOC

21

28

DIAG Output: Clock Division Ratio

DIAG Output: Temperature Range

DIAG Output: Temperature Slope

Hot Temperature Warning Threshold

Hot Temperature Warning Hysteresis

Overtemperature Shutdown

N_D

V_TJD

256000

1440

–3.92

135

15

DG[1:0] = 1,0

–

mV

mV/°C

°C

A_TJD

DG[1:0] = 1,0

T_JWH

T_JWHHys

T_JF

Temperature increasing

125

–

145

–

°C

Temperature increasing

Recovery = T_JF– T_JHys

170

–

180

–

°C

Overtemperature Hysteresis

T_JHys

15

°C

[1]

[2]

For input and output current speciﬁcations, negative current is deﬁned as coming out of (sourcing) the speciﬁed device terminal.

Current Trip Point Error is the diﬀerence between actual current trip point and the target current trip point, referred to maximum full scale (100%) current:

E_ITrip= 100 × (I_TripActual– I_TripTarget) / I_FullScale%.

Timing parameter letters refer to Interface Timing Diagrams.

Function is correct but parameters are not guaranteed above or below the general limits (5.5 to 28 V).

[3]

[4]

[5]

Outputs disabled if V_BB> V_BBOVor V_BB< V_BBUVor V_CP< V_CPUV

.

8

Allegro MicroSystems, LLC

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

AMT49700

Automotive Stepper Driver

TIMING DIAGRAMS

SꢋRn

SCꢅ

Sꢂꢇ

C

A

ꢁ

ꢂ

ꢃ

ꢄ

ꢅ

ꢀ

ꢂ15

ꢀ

ꢂ1ꢉ

ꢀ

ꢂ0

ꢀ

ꢆ

ꢇ

ꢈ

Sꢂꢌ

ꢍ

ꢂ15ꢊ

ꢂ1ꢉꢊ

ꢂ0ꢊ

ꢍ

H

Figure 2: Serial Interface Timing

(X = don’t care; Z = high impedance (tri-state)

RꢀSꢀꢁn

t_EN

t_RSD

Actiꢃe

Sleep

Active

State

Sleeꢂ

Figure 3a: Transition to Sleep (RESETn)

Figure 3b: Transition from Sleep (RESETn)

9

Allegro MicroSystems, LLC

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

AMT49700

Automotive Stepper Driver

SPI bus cycle setting GTS=1

t_RSD

STRn

SCK

SDI

D15

D14

D0

State

Active

Sleep

Start of transition to Sleep

Fully asleep

Figure 4a: Transition to Sleep (SPI)

t_IR

SPI bus cycle setting GTS=0

t_EN

STRn

SCK

SDI

D15

D14

D0

Sleep

State

Active

Serial interface ready

Active

Start of

transition from

sleep

Active state latched

Figure 4b: Transition from Sleep (SPI, Active State Latched)

10

Allegro MicroSystems, LLC

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

AMT49700

Automotive Stepper Driver

SPI bus cycle not setting GTS=0

t_IR

t_EN

t_RSD

STRn

SCK

SDI

D15

D14

D0

Sleep

Active

State

Active

Sleep

Start of

transition

from sleep

Serial interface ready

Active

Active state not latched

Start of transition to sleep

Fully

asleep

Figure 4c: Transition from Sleep (SPI, Active State Not Latched)

11

Allegro MicroSystems, LLC

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

AMT49700

Automotive Stepper Driver

FUNCTIONAL DESCRIPTION

The AMT49700 is an automotive stepper motor driver suitable

for high temperature applications such as headlamp bending and

leveling, throttle control, and gas recirculation control. It is also

suitable for other low current stepper applications such as air

conditioning and venting. It provides a flexible microstepping

motor driver controlled through an SPI-compatible interface. The

CP1, CP2: Pump capacitor connection for charge pump. Connect

a 100 nF (50 V) ceramic capacitor, between CP1 and CP2.

VCP: Above supply voltage for high-side drive. A 100 nF (16 V)

ceramic capacitor should be connected between VCP and VBB to

provide the pump storage reservoir.

stepper motor can be controlled to provide single step movement, GND: Power and reference ground. Connect to GNDPA and

with adjustable microstep resolution for fine positioning control,

or programmable multistep sequencing. The programmable step

sequencer provides independent motor acceleration, decelera-

tion, start speed, run speed, and number of steps with a single SPI

command.

GNDPB pins—see layout recommendations.

GNDPA, GNDPB: Bridge power grounds. Connect to GND—see

layout recommendations.

OAP, OAM: Motor connection for phase A. Positive motor phase

current direction is defined as flowing from OAP to OAM.

The SPI-compatible serial interface also allows the selection of

step mode, configuration of motor control parameters, and pro-

gramming of diagnostic thresholds.

OBP, OBM: Motor connection for phase B. Positive motor phase

current direction is defined as flowing from OBP to OBM.

A single diagnostic output provides simple indication of a fault

condition and detailed diagnostic information can be read from

the serial interface output.

SDI: Serial data input. 16-bit serial word, input MSB first.

SDO: Serial data output. High impedance when the STRn input

is high. Outputs the FF bit of the Status register, the fault flag, as

soon as the STRn input goes low.

The two DMOS full-bridges are capable of driving bipolar step-

per motors in full-, half-, quarter-, eighth- and sixteenth-step

modes, at up to 28 V, with phase current up to ±1.6 A but limited

by power dissipation and ambient temperature. For most appli-

cations, typical phase current is up to ±750 mA. The current in

SCK: Serial clock. Data is latched in from SDI on the rising edge

of SCK. There must be 16 rising edges per write and SCK must

be held high when the STRn input changes.

each phase of the stepper motor is regulated by a fixed-frequency STRn: Serial data strobe and serial access enable. When STRn

peak-detect PWM current control scheme operating in an adap-

tive mixed decay mode. This provides reduced audible motor

noise and increased step accuracy for a wide range of motors and

operating conditions.

is high, any activity on SCK or SDI is ignored and SDO is high

impedance, allowing multiple SDI slaves to have common SDI,

SCK, and SDO connections.

DIAG: Diagnostic output. Function selected through serial inter-

The outputs are protected from short circuits and features for

open load detection are included. Chip level protection includes

hot thermal warning, overtemperature shutdown, and overvoltage

and undervoltage lockout.

face. Default is fault output.

RESETn: Resets faults when pulsed low for a duration compliant

with the Reset Pulse Width (t_RST). Forces low-power shutdown

(sleep) when held low for more than the Reset Shutdown Width

To assist with EMC compliance, the output slew rate is controlled (t_RSD). Can be pulled to VBB with a 33 kΩ resistor.

at two programmable levels and the bridge PWM frequency

STEP: STEP logic input. Motor advances on rising edge. Filtered

includes optional programmable dither to spread the EM energy

input with hysteresis.

in the frequency spectrum.

DIR: Direction logic input. Direction changes on next STEP

rising edge. When high, the Phase Angle Number is increased

Terminal Functions

on the rinsing edge of STEP. Has no effect when using the serial

interface. Filtered input with Hysteresis.

VBB: Main motor supply and chip supply for internal regulators

and charge pump. Both VBB pins should be connected together

and each decoupled to ground with a low ESR electrolytic

capacitor and a good ceramic capacitor.

12

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AMT49700

Automotive Stepper Driver

target steps, NSM[7:0] and NSL[7:0]. The actual motor speed,

acceleration, deceleration and number of steps will always be the

same regardless of the selected microstep resolution.

Stepper Motor Motion Control

The AMT49700 provides two methods of motion control, a

single-step mode and a programmed step-sequence mode. Single-

step mode can be controlled either by STEP and DIR terminals

or through the serial interface. Step-sequence mode can only be

controlled through the serial interface.

The sequence will start or change when STRn goes high at the

end of the transfer of NSL[7:0], the least significant 8 bits of the

step count number. When a programmed step seqence is com-

plete, the motor will remain stopped until the end of the next

NSL[7:0] transfer. When a programmed step seqence is in prog-

ress, the STEP and DIR inputs are ignored. The logic level on the

DIR input has no effect on step-sequence control. In this operat-

ing mode, the direction is only defined by the DIR bit. Opera-

tional direction can be read on DIRR in Register 13 via serial

interface either in the STEP and DIR mode or the Motion Control

mode. The DIRR data is latched at the STRn signal taking low.

SINGLE-STEP CONTROL

The single-step mode is accessed by writing a step change value

into the SC[5:0] variable. The step change value is a two’s

complement (2’sC) number, where a positive value moves the

motor forward by a number of 1/16th microsteps and a negative

value moves the motor backwards by a number of 1/16th micro-

steps. For example, for a full-step forwards the decimal number

16 would be written to SC. For a half step backwards the number

-8 would be written to SC. Further details and examples are pro-

vided in the applications section.

Figure 5 shows the definition of the basic step profile parameters

and the sequence that occurs when the least significant 8 bits of

the step count number are written. From a stationary state, the

AMT49700 will begin by stepping the motor at the programmed

start rate for the first step. The following steps will increase in

step rate according to the programmed acceleration until the

motor reaches the run step rate. At each step, the total step count

remaining is reduced by one. The motor continues to be stepped

at the run step rate until the step count reaches the number of

steps required to decelerate the motor based on the run rate, the

start rate and the deceleration factor. At this point the step rate is

reduced at each step according to the programmed deceleration

until the motor reaches the start step rate. Once the start step rate

is achieved, the motor is stopped.

The Step and Direction control mode uses the STEP and DIR

terminals. When using Step and Direction mode to control stepper

motor, the AMT49700 automatically increases or decreases the

Step Angle Number according to the step sequence associated with

the selected step mode. The default step mode, reset at power-up

or after a power-on reset, is half step. Full-, quarter-, and sixteenth-

step sequences are also available when using the STEP and DIR

inputs and are selected by the contents of MS[2:0].

STEP-SEQUENCE CONTROL

The step-sequence mode provides the ability to command the

motor to run a number of steps in either direction following

a programmable accelerate, run and decelerate profile. The

acceleration, deceleration, running step rate, starting step rate,

total number of steps and direction can all be configured inde-

pendently through the serial interface by writing to the following

variables:

Steꢀ Rate

Rꢁn

Rate

Acceleration

ꢂeceleration

ACC[5:0]:

DEC[5:0]:

SSR[5:0]

RSR[5:0]

DIR

Acceleration in Full steps/s²

Deceleration in Full steps/s²

Starting Step rate in Full steps/s

Running Step rate in Full steps/s

Direction

Start

Rate

Steꢀs

Steꢀ Coꢁnt

Figure 5: Step Proﬁle Parameters

NSM[7:0]

NSL[7:0]

Most significant 8 bits of the step count

Least significant 8 bits of the step count

It is possible to change the variables when the step sequence is

in progress, but the changes only take effect when the lsb of the

step count is written. The effect of any change will depend on the

present state of the step sequence. In each case, the AMT49700

All step profile parameters are based on full step units except the

13

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AMT49700

Automotive Stepper Driver

will either continue running at the run step rate, accelerate the

motor or decelerate the motor. However, note that changing

the deceleration rate to zero, when the motor is running with a

motion profile, will cause the motor to run continuously.

between switching off one MOSFET and switching on the com-

plementary MOSFET. Cross-conduction is prevented by lockout

logic in each driver pair.

Except for the half-step uncompensated mode, the phase cur-

rents and, in particular, the relative phase currents are defined

Three additional single bit commands, END, STP, and BRK, are

available to bring the motor to a halt without having to change the by the phase current table (Table 3). This table defines the two

step sequence variables. When set to 1, the END bit will imme-

diately decelerate the motor to stop, based on the programmed

deceleration value and the start run rate, regardless of the present

speed. change in speed, or remaining step count. When set to 1,

the STP bit will immediately cease any step sequence and stop

and hold the motor. The BRK bit provides the additional ability

to stop driving current into the motor and will short the windings

to provide some amount of dynamic braking. Further details and

examples are provided in the applications section. If a motion

profile is initiated while either END or STP bits are set, the com-

mand is accepted and the CR bit is set low. The profile will not be

imitated until the STP or END bits are set low.

phase currents at each microstep position. For each of the two

phases, the currents are measured in the bridge transistors on

the AMT49700. The target current level is defined by the output

from the digital-to-analog converter (DAC) for that phase.

The actual current delivered to each phase at each step angle

is determined by the value of the MXI[4:0] variable and the

contents of the phase table. For each phase, the value in the phase

table is passed to the DAC, which uses MXI[4:0] as the reference

100% level (code 63) and reduces the current target depending

on the DAC code. The output from the DAC is used as the input

to the current comparators. The controlled step angle can be read

out via serial interface, SA[5:0]. The SA value is equivalent to the

Step number in sixteenth step (Table 3).

Driving a Stepper Motor

The one exception is the uncompensated half-step mode. In this

mode, the current in each phase at the half-step positions (8, 24,

40, and 56), with both phases active, will be the same level as at

the full-step detent positions (0, 16, 32, and 48), with one phase

active.

A two-phase stepper motor is made to rotate by sequencing the

relative currents in each phase. In its simplest form, each phase is

fully energized in turn by applying a voltage to the winding. For

more precise control of the motor torque across temperature and

voltage ranges, current control is required. For efficiency, this is

usually accomplished using PWM techniques. In addition, current

control also allows the relative current in each phase to be con-

trolled, providing more precise control over the motor movement

and hence improvements in torque ripple and mechanical noise.

Low-side on-resistance (R_ONL) is automatically modified at

maximum phase current settings of 120 mA or less (MXI[4:0] =

0…2) to maintain current-sense accuracy. High-side on-resistance

(R_ONH) remains constant across all maximum phase current set-

tings.

For bipolar stepper motors, the current direction is significant,

so the voltage applied to each phase must be reversible. This

requires the use of a full-bridge (also known as an H-bridge),

which can switch each phase connection to supply or ground.

The current comparison is ignored at the start of the PWM on-

time for a duration referred to as the blank time. The blank time

is necessary to prevent any capacitive switching currents from

causing a peak current detection.

Phase Current Control

The PWM on-time starts at the beginning of each PWM period.

The current rises in the phase winding until it reaches the

required peak current level. At this point, the PWM off-time starts

and the bridge is switched into fast decay. The current continues

to be monitored. When the current drops below the peak current

level, the bridge is switched into slow decay for the remainder

of the PWM period. This mixed decay technique automatically

adapts the current control to a wide range of motors and operating

conditions in order to minimize motor torque ripple and motor

noise. It also provides the lowest motor dissipation and highest

motor efficiency over a wide range of voltage and temperature

conditions.

In the AMT49700, current to each phase of the two-phase bipolar

stepper motor is controlled through a low-impedance n-channel

DMOS full-bridge. This allows efficient and precise control of

the phase current using fixed-frequency pulse-width-modulation

(PWM) switching. The full-bridge configuration provides full

control over the current direction during the PWM on-time and the

current decay mode during the PWM off-time. The AMT49700

automatically controls the bridge decay mode to provide the opti-

mum current control completely transparent to the user.

Each leg (high-side, low-side pair) of each bridge is protected

from shoot-through by a fixed dead-time. This is the time

14

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AMT49700

Automotive Stepper Driver

The AMT49700 includes a programmable maximum PWM-on

time limiter. In some cases, for example a phase short to ground,

the motor current does not flow through the low side peak current

sensor. In this case, the current measured by the peak current

detector will not to reach the peak current threshold and the

bridge would remain in the PWM-on state. This may allow the

current to increase until it is limited only by the supply voltage

and motor resistance. The maximum on time is set using the

PM[2:0] variable as a maximum number of PWM periods from

1 to 56 in steps of 8 cycles. Setting PM[2:0] to 0 will disable the

maximum PWM-on time limit. If the PWM-on time reaches the

programmed limit the bridge will be disabled as if an overcur-

rent had been detected and an overcurrent will be indicated in

the Diagnostic register for the high-side output of the opposite

phase to the previously active phase. For example, if OAP is

driven high and OAM driven low when the PWM-on time limit

is reached then the AMH bit would be set indicating a possible

short between OAM and GND and the bridge control follows the

sequence as for an overcurrent detection.

the selected microstep mode. The default microstep mode is com-

pensated half step. Full single-phase-, full two-phase-, uncompen-

sated half-, quarter-, eighth- and sixteenth step sequences are also

available when using the programmable step sequencer and are

selected by the contents of the MS[2:0] variable.

When using single-step control option to control the stepper

motor, a 6-bit step change value is written to SC[5:0] to incre-

ment or decrement the step angle. The step change value is a

two’s complement (2’sC) number, where a positive value incre-

ments the step angle and a negative value decrements the step

angle. A single step change in the step angle is equivalent to a

single 1/16th microstep. Therefore, for correct motor movement,

the step change value should be restricted to no greater than

16 steps positive or negative.

This facility enables full control of the stepper motor at any

microstep resolution up to 16th step, plus the ability to change

microstep resolution “on-the-fly” from one microstep to the next.

The only restriction is that the single-step control mode cannot

operate in uncompensated half-step mode. The microstep mode

selection set by MS[2:0] has no effect in single-step control.

Phase Current Table

Except for the uncompensated half step mode, the relative phase

currents are defined by the phase current table, Table 3. This

table contains 64 lines and is addressed by the step angle number,

where step angle 0 corresponds to 0° or 360°. The step angle

number is generated internally by the step sequencer, which is

controlled by the motion controller or by the step change value

from the serial input. The step angle number determines the

motor position within the 360° electrical cycle and a sequence of

step angles determines the motor movement. Note that there are

four full mechanical steps per 360° electrical cycle.

In both control cases, the resulting step angle number is used to

determine the phase current value and current direction for each

phase based on the phase current table.

PWM Frequency

The base frequency of the bridge PWM signal is fixed by the

value of the base PWM period, t_PW. This base frequency can be

altered by the frequency dither function described below.

The period of the PWM frequency is set by the PW[4:0] variable.

The six bits of PW contain a positive integer that determines the

PWM period derived by division from the system clock.

Each line of the phase current table has a 6-bit value, per phase, to

set the DAC level for each phase plus an additional bit, per phase,

to determine the current direction in each phase. The step angle

number sets the electrical angle of the stepper motor in sixteenth

microsteps, approximately equivalent to electrical steps of 5.625°.

The PWM period is defined as:

t_PW= 36 μs + (n × 0.8) μs

On first power up, after a power-on reset or after sleep, the step

angle number is set to 8, equivalent to the electrical 45° position,

except for full-step single phase drive where the step angle num-

ber is set to 0. This position is defined as the “home” position.

where n is a positive integer defined by PW[4:0]

For example, when PW[4:0] = [1 0100], then t_PW= 52 µs and the

PWM frequency is 19.2 kHz.

The range for the base PWM frequency is 16.4 kHz to 27.8 kHz.

The accuracy of the PWM frequency is defined by the system

When using the programmable step sequencer to control the step-

per motor, the AMT49700 automatically increments or decrements

the step angle according to the step angle sequence associated with clock accuracy.

15

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AMT49700

Automotive Stepper Driver

Following each change, the PWM period will remain at the new

value for the duration of the dither dwell time, selected as 1 ms,

2 ms, 5 ms, or 10 ms by the contents of the DD[1:0] variable.

t_Pꢁ

The number of dither steps, N_DS, is the value in the DS[3:0]

variable. Starting at the base PWM period, the PWM period will

decrease by the dither step period N_DStimes then increase by the

same amount and number of steps before restarting the cycle.

N_DScan have a value between 0 and 15. A value of 0 will disable

PWM frequency dither. The minimum PWM period in any case is

18 µs. If the frequency dither settings attempt to reduce the PWM

period below 18 µs, then it will be held at 18 µs until the dther

sequence brings the required value above 18 µs again.

N_ꢆS

t_∆Pꢁ

t_ꢆꢆ

ꢀime

As the frequency shift is defined by a fixed period change, the

change in frequency will be slightly different for each step, but

the frequency spreading effect will still be effective.

t_ꢆꢆ

∆ꢅ_Pꢁ

Low-Power Sleep Mode

The AMT49700 can be put into a low power sleep mode by

holding the RESETn input low for a duration of at least the Reset

Shutdown Pulse Width, t_RSD(Figure 3a) or setting the GTS bit to

1 via the serial interface (Figure 4a). If GTS is used, the transition

to sleep starts on the rising edge of STRn at the end of the serial

write cycle and is completed one Reset Shutdown Pulse Width

later. In combination, the two means of initiating sleep behave as

detailed in Table 1.

N_ꢆS

ꢅ_Pꢁ

ꢀime

Figure 6: PWM Frequency Dither

Table 1: Sleep Mode Logic

PWM Frequency Dither

RESETn

GTS Bit

Mode

Sleep

Normal

Sleep

The AMT49700 includes an optional PWM frequency dither

scheme that can be used to reduce the peak radiated and con-

ducted electromagnetic (EM) emissions. This is accomplished

by stepping the PWM period in a triangular pattern in order to

spread the EM energy created by the PWM switching. There are

three programmable variables that can be used to adjust the fre-

quency spreading for different applications. These are the dither

step period, t_∆PW, dwell time, t_DD, and the number of steps in the

pattern, N_DS. These are identified in Figure 6.

0

1

0

1

0

1

In sleep mode, the outputs are disabled and the internal regulators

are switched off to minimize current drain from the battery sup-

ply. If the initiation of sleep mode is successful, the DIAG output

is set high; if unsuccessful, it is set low. This behavior occurs

regardless of the value of the DGS[1:0] variable and may be used

to confirm that a command to enter or exit sleep mode has been

successful. The DIAG output state is not defined and should not

be read during the Reset Shutdown Pulse Width, t_RSD, or Wake

from sleep, t_EN, periods.

Figure 6 shows the dithered period on top and the corresponding

frequency below. The PWM frequency at any time is defined by

the PWM period. The base PWM period, t_PW, is indicated as is

the resulting base frequency, f_PW

.

The dither step period, t_∆PW, is the incremental change in PWM

period at each dither step and is defined by:

If sleep mode is initiated by taking RESETn low, it will be exited

on the following rising edge on RESETn per Figure 3b. If sleep

mode is initiated by setting GTS to 1, the part will start to wake

up on the first falling edge on STRn as detailed in Figure 4b. The

t_∆PW= –0.2 – (n × 0.2) µs

where n is a positive integer defined by DP[2:0].

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AMT49700

Automotive Stepper Driver

serial transfer associated with the STRn falling transition initiat-

tion is present. When such a fault condition is removed, the fault

ing wake up must set GTS to 0, otherwise active mode will not be state is no longer present.

latched and the device will revert to sleep at the end of the cycle

In both cases, the fault is always captured independently by the

per Figure 4c.

diagnostic or status registers. The contents of these registers are

not reset when the fault state clears and provide a record of all

faults that have occurred since the last reset of the register in

question. Any fault bits set to 1 in the Diagnostic or Status reg-

isters are reset by a Status or Diagnostic register reset described

below. If any static faults persist following a reset action the

Unlike other bus cycles, the first transfer after coming out of

sleep mode must satisfy the constraint that the first falling edge

on SCK does not occur until at least an Interface Ready period,

t_IR, after the falling edge on STRn. This allows the internal

regulators to power up and the interface logic to become active.

During t_IR, any switching commands on STEP, DIR, STRn, SCK, relevant fault states and register bits will reflect this immediately

and SDI should be avoided to avoid unpredictable operation.

after completion of the reset.

If sleep mode is initiated by setting GTS to 1 and then RESETn

is taken low, exit from sleep requires that RESETn is taken high

prior to setting GTS to 0.

A number of these features automatically disable the current drive

to protect the outputs and the load. Others only provide an indica-

tion of the likely fault status. Fault states and associated actions

are listed in Table 2.

Diagnostics

A single open-drain diagnostic output (DIAG) can be programmed

through the serial interface to provide four different fault signals.

The AMT49700 integrates a number of diagnostic features to

protect the driver and load as far as possible from fault conditions

and extreme operating environments. When a fault condition is

detected or confirmed then a fault state exists and the fault is cap-

tured by the diagnostic register and the status register. There are

two types of fault conditions, defined as dynamic and static.

At power-up or after a power-on-reset, the DIAG terminal

outputs a general fault flag, which goes low when a fault state

is present. It indicates that a static fault condition is present or a

dynamic fault condition has been detected and latched.

In addition to the general fault flag, the DIAG output can be

programmed via the serial interface to output any of seven other

optional fault indicators:

Dynamic fault conditions are those that only exist for a short

duration, either due to some action being taken by the AMT49700

that removes the fault condition, or the fault is only detectable at

specific instants. Fault states generated in response to Dynamic

faults are latched to ensure that such faults are reported through

the diagnostic output terminal, DIAG, and to ensure that danger-

ous conditions cannot return or persist to damage the AMT49700

or the load.

• A supply voltage error signal, which is low when a VBB

overvoltage, VBB undervoltage or VCP undervoltage fault

state is present.

• An open load indicator.

• A voltage that represents the silicon temperature.

• A logic level version of the PWM switching on phase A.

Table 2: Fault State Table

Diagnostic

VBB Overvoltage

VBB Undervoltage

VCP Undervoltage

Temperature Warning

Overtemperature

Bridge Short

Action

Latched

No

• The internal step signal from the sequencer to the stepper

driver.

Disable outputs

Flag fault only

Disable outputs

Disable output

Flag fault only

No

• A step sequence activity indicator which is low when the SSA

bit in the Status register is 1 and high when SSA is zero. This

indicates when a programmed sequence of steps is actively

running.

No

Yes

No

• A divided version of the internal system clock giving

78.125 Hz

Bridge Open

Serial Interface Fault

The DIAG terminal will survive a maximum applied voltage

of 40 V per the Absolute Maximum Ratings table, but switches

into a high impedance state when the applied voltage exceeds

approximately 16 V (regardless of programmed terminal function

Bridge overcurrent (bridge short condition) and bridge open

detect faults are categorized as Dynamic.

Static faults states are those that only exist when the fault condi-

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AMT49700

Automotive Stepper Driver

or device status). On-state drive capability and off-state leakage

current limits are defined in the Electrical Characteristics table

by the V_OLand I_ODIparameters respectively and may be used to

calculate a suitable pull-up resistance. In the majority of applica-

tions, a resistor in the range 10 kΩ to 20 kΩ is suitable.

is set low and held in this state for as long as the supply voltage

permits. When the internal supply voltages rise to acceptable

levels, a power-on reset takes place, the POR and FF bits are set

to 1, and all other register bits are set to their default state. The

VBB POR threshold, V_BBPOR, is an approximate value derived

from the internal logic supply undervoltage threshold and the

regulator dropout voltage. The AMT49700 is guaranteed not

to be disabled if V_BBremains above the maximum value of

System Diagnostics

At the system level, the supply voltages and chip temperature are

monitored.

V_BBPOR. The internal logic supply undervoltage threshold is set

to guarantee that the internal logic will remain fully operational

and correct down to the minimum value of the threshold.

SUPPLY VOLTAGE MONITORS

The main supply VBB, the charge pump voltage VCP, and the

internal supply voltages (derived from VBB but not externally

accessible) are monitored—the main supply for overvoltage and

undervoltage, the others for undervoltage only.

If any of these supply fault states are present, and either the

general fault flag or the supply fault flag is selected for output on

DIAG, then DIAG will be low.

When applying power or when activating from sleep mode, the

outputs should remain inactive for at least the wakeup from reset

time, t_EN, to allow the internal charge pump and regulator to

reach their full operating state.

• If the main supply voltage, V_BB, rises above its overvoltage

threshold, V_BBOV, the AMT49700 disables the outputs, drives

the general fault flag (DIAG) low and sets the OV bit in the

Status register to 1. When the main supply voltage falls below

its overvoltage threshold, V_BBOV- V_BBOVHys, the outputs are

re-enabled, the general fault flag goes high, and the OV bit

remains set in the status register until cleared.

The output drive MOSFETs of the AMT49700 remain protected

from short circuits down to the VBB undervoltage level. How-

ever, when V_BBis less than 5.5 V, the overcurrent thresholds can-

not be guaranteed to meet the precision specified at higher supply

voltage. In addition, the open load detection may indicate a fault

depending on the motor and load characteristics.

• If the main supply voltage, V_BB, falls below the VBB

undervoltage threshold, V_BBUV, the AMT49700 disables the

outputs, drives the general fault flag (DIAG) low, and sets

the UV bit in the Status register to 1. If V_BBremains above

the VBB POR threshold, V_BBPOR, but is low enough such

that the I/O voltage is less than the programmed value, it is

possible that the external microcontroller may not be able to

communicate with the AMT49700 through the serial interface.

However, in this case, all register states (including step

angle) are retained. When V_BBrises above the undervoltage

threshold, V_BBUV+ V_BBUVHys, and no other faults are present,

the outputs are re-enabled, the general fault flag goes high and

the UV bit remains set in the status register until cleared.

TEMPERATURE MONITORS

Two temperature thresholds are provided: a hot warning and an

overtemperature shutdown.

• If the chip temperature rises above the hot temperature

warning threshold (T_JW), the hot warning bit (TW) is set to 1

in the Status register. No action is taken by the AMT49700.

When the temperature drops below T_JWby more than the

hysteresis value (T_JWHys), the fault state is cleared, but the TW

bit remains at1 in the Status register until reset.

• If the output of the charge pump, V_CP, falls below its

undervoltage threshold, V_CPUV, the AMT49700 disables the

outputs, drives the general fault flag (DIAG) low, and sets

the UV bit in the Status register to 1. When the charge pump

output rises above its threshold, V_CPUV+ V_CPUVHys, and no

other faults are present, the outputs are re-enabled, the general

fault flag goes high, and the UV bit remains set in the status

register until cleared.

• If the chip temperature rises above the overtemperature

threshold (T_JF), the overtemperature bit (OT) is set to 1 in the

Status register, and the AMT49700 disables the outputs to try

to prevent a further increase in the chip temperature. When the

temperature drops below T_JFby more than the hysteresis value

(T_JFHys), the fault state is cleared, and the outputs re-enabled.

The OT bit remains at 1 in the Status register until reset.

• If V_BBfalls below the VBB power-on reset (POR) level and

the internal logic supply voltages derived from V_BBdrop below

If either of these supply fault states is present and the general

acceptable levels, the AMT49700 is completely disabled. DIAG fault flag is selected for output on DIAG, then DIAG will be low.

18

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AMT49700

Automotive Stepper Driver

If the cause of the overcurrent persists, the part will repeatedly

cycle between overcurrent and attempted restart. In this condi-

tion, the device will not suffer damage, but if step demands are

being applied at a high rate, the part may eventually shut down

due to overtemperature.

Bridge and Output Diagnostics

The AMT49700 includes monitors that can detect a short to sup-

ply or a short to ground at the motor phase connections. These

conditions are detected by monitoring the current from the motor

phase connections through the bridge to the motor supply and to

ground. In addition, a PWM-on time limiter is provided to ensure

that any motor phase short to ground events do not cause the cur-

rent to increase out of control indefinitely.

If the OFA bit is set to 1, a step occurance does not reset overcur-

rent fault states and the automatic restart capability is disabled.

OPEN-LOAD DETECTION

Low current comparators and timers are provided to help detect

possible open load conditions.

Open load detection is carried out on both phases and if either

phase current drops below the open load current threshold,

I_OL, an open-load state is flagged. (I_OLis set to either 13 mA or

26 mA, according to the state of the OLT bit.)

SHORTED LOAD

If the supply voltage is high enough to drive the bridge current

above the overcurrent thresholds, a short across the load may be

indicated by concurrent overcurrent fault states on both high-side

and low-side MOSFETs.

Unfortunately, simple current monitoring is only viable for sta-

tionary motors where the current rises quickly. When motors are

running at high speed, phase current rise time is severely affected

by motor back emf and the current may not reach its peak until

late in the step period. Consequently, if open-load current com-

parisons were to run continuously, false open-load states would

be flagged for at least part of the step period in many instances.

To avoid such false states, the open-load comparator outputs are

only checked after the expiry of the open-load detect time. This

lockout period starts each time a step occurs and has a duration of

10 ms to 40 ms selected by the contents of the TOL[1:0] vari-

able. Additionally, the comparator output for each phase is only

checked if the target current for that phase is greater than twice

the open load threshold current.

OVERCURRENT FAULT BLANKING

All overcurrent conditions are ignored for the duration of the

overcurrent detection delay time (t_OC) set between 1 and 4 µs by

the contents of the TOC[1:0] variable. The overcurrent detec-

tion delay timer is started when an overcurrent condition is first

detected. If the overcurrent condition is still present at the end

of the overcurrent detection delay time, then an overcurrent fault

state will be detected and latched. If the overcurrent condition is

removed before the overcurrent detection delay time is complete,

then the timer is reset and no fault is detected.

The AMT49700 continues to drive the bridge outputs under an

open-load condition. Any open-load fault state is cleared when

any of four events occurs:

This prevents false overcurrent detection caused by supply and

load transients. It also prevents false overcurrent detection from

the current transients generated by the motor or wiring capaci-

tance when a MOSFET is first switched on.

• A single step command is received by writing to the single

step command register with DSR = 0 or a rising signal at the

STEP terminal.

OVERCURRENT FAULT RESET AND RETRY

Once an overcurrent fault state has been detected, all outputs for

the phase where the fault state is present are disabled until the

fault state is reset by a register reset. In addition, if the Overcur-

rent Fault Action bit, OFA, is set to 0, any overcurrent fault states

are reset every time a step occurs either on a single step or on

each step of a step sequence. When the fault state is reset the

outputs are re-enabled and if the general fault flag is selected for

output on DIAG and there are no other faults, then DIAG will

be allowed to go high. The same sequence is also applied if the

PWM-on time reaches the maximum limit.

• A step sequence is started by writing to the step count lsb

register with DSR = 0.

• The phase current reaches the PWM threshold level.

• The open-load detect time expires and the phase current is

detected to have risen above the open-load current threshold.

When an open-load fault is present and a rising edge is detected

on the STEP input, this will both clear the fault and step the

motor by the programmed microstep value. This will avoid any

systematic step count misalignment if the open-load state is only

temporary and the controller continues to step the motor without

taking any action on the open-load detection.

Resetting overcurrent fault states every time a step occurs allows

automatic restart when the cause of the overcurrent is removed.

19

Allegro MicroSystems, LLC

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

AMT49700

Automotive Stepper Driver

Flag are cleared on every time a step occurs either on a single step.

This provides a means of automatically attempting a restart. No

bits in the Diagnostic or Status registers are cleared thereby allow-

ing suspected faults to be investigated via the serial interface.

False State Reset

Various mechanisms may be used to reset or partially reset the

AMT49700.

If the OFA is set to 1, any overcurrent fault state will remain

and automatic attempts continue stepping are disabled. Any step

sequence in progress will stop immediately.

RESET PULSE

Pulsing the RESETn input low for the duration of the reset pulse-

width time, t_RST, clears all dynamic fault states, the General Fault

Flag (DIAG) and the Diagnostic and Status registers provided no

static faults remain present.

DISABLE SERIAL RESET

The AMT49700 has a function to disable the fault reset action

via the serial communication interface. When the DSR bit set

to 1, AMT49700 will not clear the faults in Status and Diagnos-

tics register by the reading command of Status and Diagnostics

register. The CR and SSR are exclusively operated regardless of

DSR. The reset command by RST bit or RESETn input pulse will

operate as it is, even if DSR is set to 0.

RESET COMMAND

Writing a 1 into the RST bit through the serial interface has the

same effect as a pulse on the RESETn input. All dynamic fault

states, the General Fault Flag (DIAG) and the Diagnostic and Sta-

tus registers are cleared provided no static faults remain present.

SLEEP

Step Angle Reset

Entering and then exiting sleep mode (via RESETn) clears all fault

states (with the exception of POR and FF) and the General Fault

Flag (DIAG). If GTS bit is written with DSR = 1, the recorded

faults will not be cleared. Additionally, the Diagnostic and Status

registers (with the exception of POR and FF) are cleared.

The step angle number may be set to its home value by writing

a logic 1 to the SAR bit in the Control register. If using the SAR

bit, the step angle number reset only takes place on the rising edge

on STRn at the end of the write cycle. Repeatedly overwriting the

value 1 to the SAR bit repeatedly resets the step angle. The SAR

bit may be cleared by writing 0 via the serial interface. The SAR

bit is also reset to 0 by a power-on reset. Maintaining SAR at 1

does not lock the step angle in the home condition, and any step or

sequence commands received via the serial interface are obeyed.

The step angle reset action will not be taken if the following condi-

tions are present: DIS, OT, OV, UV, BRK, and any short fault.

DIAGNOSTIC REGISTER READ

Reading the Diagnostic register via the serial interface, with DSR

= 0, clears all overcurrent fault states and the overcurrent indicator

bits in the Diagnostic register. Clearing all the overcurrent indica-

tor bits will also clear the OCA and OCB bits in the Status register.

Other bits in the Status register are not affected. Reading the Diag-

nostic register will have no effect on the state of the SSA bit. This

is exclusively set or reset by the step sequence controller.

Braking

The AMT49700 can be used to perform dynamic braking by set-

ting the BRK bit to 1. If BRK is set to 1 and HLR = 0, all high-side

MOSFETs are turned on and all low-side MOSFETs are turned off,

effectively short-circuiting any back emf generated by the motor

and creating a braking torque. If BRK is set to 1 and HLR = 1, all

low-side MOSFETs are turned on and all high-side MOSFETs are

turned off, producing a similar effect at the motor. During braking,

motor current, I_BREAK, can be approximated by:

STATUS REGISTER READ

Reading the Status register with DSR = 0 via the serial interface

clears all latched fault states other than those generated by over-

current faults. If no other faults are present this action also clears

the General Fault Flag and the fault bits in the register except for

the overcurrent bits, OCB and OCA, which are derived from the

contents of the overcurrent indicator bits in the Diagnostic regis-

ter. If any static faults are present, e.g. overtemperature, then the

corresponding fault bit will not be affected by reading the Status

register and will remain set.

I_BRAKE= V_BEMF/ R_L

where V_BEMFis the voltage generated by the motor and R_Lis the

resistance of the phase winding. Care must be taken during brak-

ing to ensure that the power MOSFET maximum ratings are not

exceeded. When dynamic braking is commanded, open-load condi-

tions cannot be detected because of the bridge configuration that is

enforced (both ends of each motor winding held in the same state).

STEPPING

If the Overcurrent Fault Action bit, OFA, is set to 0 all overcurrent

fault states and any associated fault indication on the General Fault

20

Allegro MicroSystems, LLC

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

AMT49700

Automotive Stepper Driver

SERIAL INTERFACE

Serial Registers Deﬁnition*

15

14

13

12

11

10

PM4

0

9

PM3

0

8

PM2

1

7

PM1

0

6

PM0

0

5

4

3

2

1

0

PW4 PW3 PW2 PW1 PW0

0: PWM Conﬁg

0

WR

P

1

DD0

0

DS3

0

1

DS2

0

DS1

0

DS0

0

DP2

0

DP1

0

DP0

0

DD1

0

1: PWM Conﬁg

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

WR

R

P

0

DIS

1

HLR

0

SLW TBK1 TBK0 MXI4 MXI3 MXI2 MXI1 MXI0

2: Current Conﬁg

3: Diagnostics Conﬁg

5: Single Step Control

6: System Control

7: Step Count (lsb)

8: Step Count (msb)

9: Acceleration

0

1

0

DGS2 DGS1 DGS0

OLT TOL1 TOL0 OFA TOC1 TOC0

0

SAR

0

SC5

0

1

SC4

0

SC3

0

SC2

0

SC1

0

1

SC0

0

RST

0

VLR

0

MS2

0

GTS

0

MS1

1

MS0

0

DSR BRK END

STP

0

DIR

0

CRM NSL7 NSL6 NSL5 NSL4 NSL3 NSL2 NSL1 NSL0

0

NSM7 NSM6 NSM5 NSM4 NSM3 NSM2 NSM1 NSM0

0

ACC5 ACC4 ACC3 ACC2 ACC1 ACC0

0

DEC5 DEC4 DEC3 DEC2 DEC1 DEC0

10: Deceleration

11: Min Step Rate

12: Max Step Rate

13: STEP Readback

14: Mask

0

SSR5 SSR4 SSR3 SSR2 SSR1 SSR0

0

RSR5 RSR4 RSR3 RSR2 RSR1 RSR0

0

DIRR

0

SA5

0

SA4

0

SA3

0

SA2

0

SA1

0

SA0

0

TW

0

OV

0

UV

0

OT

0

OLB

0

OLA OCB OCA

WR

0

BPL

0

BPH

0

APL

0

APH

0

BML BMH

AML AMH

15: Diagnostic

0

FF

1

POR

1

SE

0

CR

0

SSA

0

OT

0

TW

0

OV

0

UV

0

OLB

0

OLA OCB OCA

Status

P

0

*Power-on reset value shown below each input register bit.

21

Allegro MicroSystems, LLC

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

AMT49700

Automotive Stepper Driver

A three-wire synchronous serial interface, compatible with SPI,

can be used to control all features of the AMT49700. A fourth

wire can be used, during a serial transfer, to provide diagnostic

feedback and read back of the register contents.

The first four bits, D[15:12], in a serial word are the register

address bits, giving the possibility of 16 register addresses. The

fifth bit, WR (D[11]), is the write/read bit. Except for the read-only

registers, when WR is 1, the following 10 bits, D[10:1], clocked in

from the SDI terminal are written to the addressed register. When

WR is 0, no data is written to the serial registers and the contents of

the addressed register are clocked out on the SDO terminal.

The serial interface timing requirements are specified in the Elec-

trical Characteristics table and illustrated in the Serial Interface

Timing diagram, Figure 2. Data is received on the SDI terminal

and clocked through a shift register on the rising edge of the

clock signal input on the SCK terminal. A serial transfer is initi-

ated by pulling the STRn terminal low.

The last bit in any serial transfer, D[0], is a parity bit that is set to

ensure odd parity in the complete 16-bit word. Odd parity means

that the total number of 1s in any transfer should always be an

odd number. This ensures that there is always at least one bit set

to 1 and one bit set to 0 and allows detection of stuck-at faults on

the serial input and output data connections. The parity bit is not

stored but generated on each transfer.

STRn is normally high and is only brought low to initiate a serial

transfer. No data is clocked through the shift register when STRn

is high, allowing multiple slave units to use common SDI and

SCK connections. Each slave then requires an independent STRn

connection. The SDO output assumes a high-impedance state

when STRn is high, allowing a common data readback con-

nection. When driving devices running from a 5 V logic supply

with VLR set to 0 (3.3 V I/O), it may be necessary to add a 2 kΩ

pull-up resistor from SDO to that supply to ensure an adequate

logic-high output voltage level is achieved.

If the AMT49700 detects a parity error during a serial transfer,

the data in question will not be written to the selected device

register.

Register data is output on the SDO terminal msb first while STRn

is low, and changes to the next bit on each falling edge of SCK.

The first bit, which is always the FF bit from the status register, is

output as soon as STRn goes low.

When 16 data bits have been clocked into the shift register, STRn

must be taken high to latch the data into the selected register. When

this occurs, the internal control circuits act on the new data.

Registers 15 (Diagnostic) contains detailed diagnostic indicators

and is read only. If WR is set to 0, the content of the addressed

register is clocked out on SDO D[10:1]. If WR is set to 1, no data

are written to the addressed register and the content of the Status

register is clocked out on SDO D[10:1].

If there are more than 16 rising edges on SCK or if STRn goes high

and there are fewer than 16 rising edges on SCK, the write will be

cancelled without writing data to the registers. In addition, the Diag-

nostic and Status registers will not be reset and the SE bit will be set

to indicate a data transfer error. This fault condition can be cleared by

a subsequent valid serial write, a reset pulse on RESETn, a transi-

tion to sleep mode and back (RESETn or GTS), or a power-on-reset.

If SE is cleared by RESETn pulse, another valid serial transfer is

required to activate serial communication monitor.

In addition to the addressable registers, a read-only status register

is output on SDO for all register addresses when WR is set to

1. For all serial transfers, the first five bits output on SDO will

always be the first five bits from the status register.

22

Allegro MicroSystems, LLC

955 Perimeter Road

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www.allegromicro.com

AMT49700

Automotive Stepper Driver

Register 6: System Control Settings

Serial Register Content

• GTS, initiates go-to-sleep function

• RST, Resets all faults and fault bits

• VLR, Selects the logic I/O voltage

• MS[2:0], 3 bits to select the microstep resolution

• DSR, Disable Serial Reset

The serial data word is 16 bits, input msb first; the four bits are

defined as the register address. This provides 16 addressable reg-

isters, 14 of which are read/write and 1 is read only. The registers

are grouped as follows:

• PWM frequency and dither configuration

• Current and bridge configuration

• Diagnostic settings

• BRK, Applies brake by shorting windings

• END, Decelerates and ends any motor movement

• STP, Stops any motor movement

Register 7: Step count (lsb)

• System function configuration

• Motor function control

• Fault mask

• DIR, Select the step direction

• Status and diagnostics

• CRM, Continuous Run Mode

Register 0: PWM configuration

• NSL[7:0], least significant 8 bits of step count

Register 8: Step count (msb)

• PM[4:0], a 5-bit integer to set the max PWM on time

• PW[5:0], a 6-bit integer to set the PWM period

Register 1: PWM configuration

• NSM[7:0], most significant 8 bits of step count

Register 9: Acceleration

• DP[2:0], 3 bits to select the dither step period

• DD[1:0], 2 bits to select the dither dwell time

• DS[3:0], 3-bit integer to select the dither steps

Register 2: Current configuration

• ACC[5:0], 6 bits to set the acceleration rate

Register 10: Deceleration

• DEC[5:0], 6 bits to set the deceleration rate

Register 11: Start Step Rate

• DIS, Disables the motor drive outputs

• HLR, Selects the slow decay recirculation path

• SLW, Selects the bridge slew rate

• TBK[1:0], 2 bits

• SSR[5:0], 6 bits to set the minimum step rate

Register 12: Running Step Rate

• RSR[5:0], 6 bits to set the running step rate

Register 13: STEP Readback

• MXI[4:0], 5 bits

• DIRR, STEP Direction readback

• SA[5:0], 6 bits step angle readback

Register 14: Fault Mask

Register 3: Diagnostics configuration

• DGS[1:0], 2 bits to select the output on DIAG

• OLT, Selects the open-load threshold current

• TOL[1:0], 2 bits to select the open-load detect timeout

• OFA, Selects action taken on an overcurrent fault

• TOC[1:0], 2 bits select the overcurrent fault delay time

Register 4: Unused

• The Fault Mask Register contains a fault mask bit for each fault

bit in the status register other than FF, POR, and SE. If a bit is set

to one in the mask register, then the corresponding diagnostic will

be completely disabled. No fault states for the disabled diagnostic

will be generated and no fault flags or diagnostic bits will be set.

Register 15: Diagnostic (read only):

Register 5: Single Step Control

• Individual bits indicating overcurrent faults detected in each

bridge MOSFET.

• SAR, Resets the step angle number to the home position

• SC[5:0], 5 bits to move the motor by a number of microsteps

forwards or backwards

23

Allegro MicroSystems, LLC

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

AMT49700

Automotive Stepper Driver

ing a power-on reset as the charge pump will not have reached

its rising undervoltage threshold until after the register reset is

completed.

Status and Diagnostic Registers

There is one read-only status register in addition to the 16

addressable registers. When any register transfer takes place, the

first five bits output on SDO are always the most significant five

bits of the status register regardless of whether the addressed

register is being read or written (see serial timing diagram). The

content of the remaining eleven bits will depend on the state of

the WR bit input on SDI. When WR is 1, the addressed register

will be written and the remaining eleven bits output on SDO will

be the least significant ten bits of the status register and a parity

bit. When WR is 0, the addressed register will be read and the

remaining eleven bits will be the contents of the addressed regis-

ter and a parity bit.

The third bit in the status register (bit 13) is the SE bit, which

indicates that the previous serial transfer (read or write) was not

completed successfully.

Bit 12 is the CR (command ready) bit. CR is set to 1 when the

AMT49700 is able to accept a new profile command. If a new

profile command is input when CR is 0, then that command will

be ignored. CR has no effect on the diagnostic status flag, FF.

Bit 11 is the SSA (step sequence active) bit. SSA is set to 1 when

a programmed step sequence starts and is active and will be set to

0 when the step sequence completes and is inactive. SSA has no

effect on the diagnostic status flag, FF. The value of the SSA bit

can also be indicated by the level on the DIAG output by setting

DSG[2:0] to [110].

The read-only status register provides a summary of the chip sta-

tus by indicating whether any diagnostic monitors have detected

a fault and to determine the status of any programmed profile.

The most significant three bits of the status register indicate criti-

cal system faults. The next two bits, bits 12 and 11, provide the

status of the sequencer. Bits 10 to 7, 4, and 3 provide indicators

for specific individual monitors and bits 2 and 1 are derived from

the contents of the Diagnostic register.

Bits 10 to 3 contain fault bits for the eight individual monitors

OT, TW, OV, UV, OLA, and OLB. If any of these faults remain

following a Status register reset, then the corresponding bit will

remain set. Resetting only affects latched fault bits for faults that

are no longer present. For any static faults that are still present,

for example overtemperature, the fault flag will remain set after

the reset.

The first most significant bit in the status register is the diag-

nostic status flag, FF. If any other fault bits in the status register

are set, this bit is high. When STRn goes low, to start a serial

transfer, SDO outputs the diagnostic status flag. This allows the

main controller to poll the AMT49700 through the serial inter-

face to determine if a fault has been detected. If no faults have

been detected, then the serial transfer may be terminated without

generating a serial read fault by ensuring that SCK remains high

while STRn is low. When STRn goes high, the transfer will be

terminated and SDO will go into its high-impedance state. The

value of the FF bit can also be indicated by the level on the DIAG

output. Note that the CA and SSA bits will not affect the value of

the FF bit.

The remaining bits, OCB and OCA, are derived from the contents

of the Diagnostic register.

The Diagnostic register is an additional read-only register that

can be read with a normal serial register read sequence. This

register contains additional fault information that permits specific

identification of the affected drive MOSFET if an overcurrent

fault is detected. If an attempt is made to write to the Diagnos-

tic register, it will be ignored, no data will be written, and the

remaining eleven bits output on SDO will be the least significant

ten bits of the status register and a parity bit.

The second most significant bit (bit 14) is the POR bit. At power-

up or after a power-on reset, the FF bit and the POR bit are set,

indicating to the external controller that a power-on reset has

taken place. All other diagnostic bits are reset and all other regis-

ters are returned to their default state. Note that a power-on reset

only occurs when the outputs of the internal supply regulators

(derived from VBB) rise to acceptable levels. Power-on reset is

not directly affected by the state of the VBB supply or the charge

pump output, VCP. In general, the UV bit will also be set follow-

If any of the phase B overcurrent fault bits, BML, BMH, BPL,

BPH, in the Diagnostic register are set OCB is set. If any of the

phase A overcurrent fault bits, AML, AMH, APL, APH, in the

Diagnostic register are set, OCA is set. OCB and OCA are not

affected by clearing the Status register. They are only cleared

when the corresponding contents of the Diagnostic register are

cleared. If, upon reading the Status register, OCA or OCB is

found to be set to 1, the Diagnostic register may be read to locate

the source of the fault and clear the fault state.

24

Allegro MicroSystems, LLC

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

AMT49700

Automotive Stepper Driver

RESETTING STATUS AND DIAGNOSTIC REGISTERS

The Status and Diagnostic registers are cleared of latched faults

and any static faults that are no longer present by any of four

actions:

• Reading the register with DSR = 0.

• Performing a fault reset by pulsing the RESETn input low for

the duration reset pulse with, t_RST, or by writing the RST bit

to 1.

• Going through a sleep-wake cycle by holding RESETn low or

writing the GTS bit to 1.

• Cycling the power off and on.

25

Allegro MicroSystems, LLC

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

AMT49700

Automotive Stepper Driver

SERIAL REGISTER REFERENCE

Serial Register Reference

15

14

0

13

0

12

0

11

WR

0

10

PM4

0

9

PM3

0

8

7

6

5

4

3

2

1

0

PM2 PM1 PM0 PW4 PW3 PW2 PW1 PW0

0: PWM config

1: PWM config

0

P

1

DP1

0

DP0

0

DD1

0

1

DD0

0

DS3

0

1

DS2

0

DS1

0

DS0

0

DP2

0

WR

0

1

P

0

Register 0: PWM Configuration

Register 1: PWM Configuration

PM[4:0]

Maximum PWM on time

DP[2:0]

PWM Dither Step Period

t_PMX= t_PW× (n × 64 μs)

t_∆PW= –0.2 μs – (n × 0.2 μs)

where n is a positive integer defined by PM[4:0],

where n is a positive integer defined by DP[2:0],

t_PWis the PWM period (below),

e.g. when DP[2:0] = [101] then t_∆PW= –1.2 µs.

e.g. when PM[4:0] = [00100],

then t_PMX= 256 × t_PWµs.

The range of t_∆PWis –0.2 µs to –1.6 µs.

DD[1:0]

PWM Dither Dwell Time

The range of t_PMXis 64 × t_PWto 1984 × t_PWµs.

DD1

DD0

Dwell Time

1 ms

Default

0

1

0

1

0

1

D

Setting PM[4:0] to 0 will disable checking of the maximum

on-time.

2 ms

5 ms

PW[4:0] Bridge PWM Fixed Period

10 ms

t_PW= 36 µs + (n × 0.8 μs)

where n is a positive integer defined by PW[4:0],

e.g. when PW[4:0] = [1 0100]

then t_PW= 52 µs.

DS[3:0]

PWM Dither Step Count

The number of dither steps is directly defined by the integer

value of DS[3:0],

e.g. when DS[3:0] = [0111] then there will be 7 frequency

steps.

The range of t_PWis 36 to 60.8 µs.

This is equivalent to 27.8 to 16.4 kHz.

The maximum number of steps is 15.

Setting DS[3:0] to 0 will disable PWM dither.

26

Allegro MicroSystems, LLC

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

AMT49700

Automotive Stepper Driver

Serial Register Reference

15

14

13

12

11

WR

0

10

DIS

1

9

HLR

0

8

7

6

5

4

3

2

1

0

SLW TBK1 TBK0 MXI4 MXI3 MXI2 MXI1 MXI0

2: Current Conﬁg

0

1

0

P

0

1

0

WR DGS2 DGS1 DGS0

OLT TOL1 TOL0 OFA TOC1 TOC0

3: Diagnostics Conﬁg

0

1

P

0

1

0

1

Register 2: Current Configuration

Register 3: Diagnostics Configuration

DIS

Disable Bridge Output

DGS[2:0] DIAG output select

DIS

Bridge Output

Enabled

Default

DGS2 DGS1 DGS0 DIAG output

Default

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

General fault, active low

Supply fault, active low

Open load, active low

Temperature as voltage

PWMA output

D

Disabled

D

HLR

SLW

Slow decay recirculation path

HLR

Recirculation Path

High Side

Default

0

1

D

STEP Signal

Low Side

Motion Control, active low

Clock (/256000)

Slew Control

SLW Bridge Slew Time

Default

OLT

Open Load Threshold

0

1

Fast

D

OLT

0

Open Load Threshold

Default

Slow

13 mA

26 mA

D

TBK[1:0] Current Compare Blank Time

1

TBK1 TBK0 Blank time

Default

TOL[1:0] Open Load Detect Time

0

1

0

1

0

1

1.0 µs

1.5 µs

2.5 µs

3.5 µs

TOL1 TOL0 OL Detect Time

Default

0

1

0

1

0

1

10 ms

20 ms

30 ms

40 ms

D

MXI[4:0] Maximum Phase Current

I_MX= (n + 1) × 50 mA

OFA

Overcurrent Fault Action

where n is a positive integer defined by MXI[4:0]

OFA

Overcurrent Fault Action

Retry

Default

e.g. when MXI[4:0] = [1 0000] then I_MX= 850 mA

The range of I_MXis 50 mA to 1600 mA.

0

1

D

Disable outputs

TOC[1:0] Overcurrent fault delay

TOC1 TOC0 Detect delay time

Default

0

1

0

1

0

1

1 µs

2 µs

3 µs

4 µs

D

27

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AMT49700

Automotive Stepper Driver

Serial Register Reference

15

14

13

12

11

WR

0

10

SAR

0

9

8

7

6

SC5

0

5

SC4

0

4

SC3

0

3

SC2

0

2

SC1

0

1

SC0

0

5: Single Step Control

6: System control

0

1

0

1

P

0

RST

0

VLR

0

MS2

0

WR

0

GTS

0

MS1

1

MS0

0

DSR BRK END

STP

0

1

0

P

0

Register 6: System Control (continued)

Register 5: Single Step Control

MS[2:0]

Microstep resolution

SAR

HLR

Step Angle Reset

MS2

MS1

MS0 Microstep Resolution

Default

SAR

Phase Outputs

Default

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Full Two Phase

0

1

Normal operation

Reset to home position

D

Full One Phase Detent

1/2 Compensated

D

Step change number.

2’s complement format.

Positive value increases step angle number.

Negative value decreases step angle number.

1/2 Uncompensated

1/4

1/8

1/16

Register 6: System Control

GTS

RST

VLR

Go to sleep command

DSR

BRK

END

STP

Disable Serial Reset

DSR Brake Action

GTS

Sleep transition

No change in state

Default

0

1

D

0

1

Enable Serial Reset

Disable Serial Reset

D

1 → 0 No change in state

0 → 1 Enter sleep state

Brake command

BRK Brake Action

Default

Reset Faults

0

1

No Brake

D

RST

Fault Reset Action

No action

Default

Brake Applied

0

1

D

End Sequence Command

No Action

0 → 1 Reset faults

1 → 0 No Action

END

Effect on sequence

No effect

Default

0

1

D

Decelerate and halt

Logic I/O voltage select

Stop Sequence Command

VLR

Logic I/O Voltage

Default

0

1

3.3 V

5 V

D

STP

Effect on sequence

No Effect

Default

0

1

D

Immediately halt

28

Allegro MicroSystems, LLC

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www.allegromicro.com

AMT49700

Automotive Stepper Driver

Serial Register Reference

15

14

13

12

11

WR

0

10

DIR

0

9

8

7

6

5

4

3

2

1

0

CRM NSL7 NSL6 NSL5 NSL4 NSL3 NSL2 NSL1 NSL0

7: Step Count (lsb)

8: Step Count (msb)

9: Acceleration

0

1

P

0

WR

0

NSM7 NSM6 NSM5 NSM4 NSM3 NSM2 NSM1 NSM0

1

0

1

0

1

0

P

0

WR

0

ACC5 ACC4 ACC3 ACC2 ACC1 ACC0

0

WR

0

DEC5 DEC4 DEC3 DEC2 DEC1 DEC0

10: Deceleration

0

Register 7: Step Count

Register 8: Step Count

DIR

Motor stepping Direction

NSM[7:0] Most significant 8 bits of the number of steps to take in a

sequence.

DIR

Step Direction

Forward

Default

0

1

D

Register 9: Acceleration

Reverse

ACC[5:0] Acceleration Setting

NSL[7:0] Least significant 8 bits of the number of steps to take in a

sequence.

a = n × 65 Full step / s²

where n is a positive integer defined by ACC[7:0],

a is the acceleration in Step/s²,

e.g., when ACC[5:0] = [01 1000]

then a = 1560 Fullstep/s².

CRM

Continuous Run Mode

CRM Run Mode

Default

0

1

Profile or Step Command

Continuous

D

The range of a is 0 to 4095 Fullstep/s².

Register 10: Deceleration

DEC[5:0] Deceleration Setting

a = –n × 65 Full step / s²

where n is a positive integer defined by DEC[7:0],

a is the acceleration in Full Step/s²,

e.g., when DEC[5:0] = [01 1000]

then a = –1560 Fullstep/s².

The range of a is 0 to –4095 Fullstep/s².

29

Allegro MicroSystems, LLC

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AMT49700

Automotive Stepper Driver

Serial Register Reference

15

14

13

12

11

WR

0

10

9

0

8

0

7

0

6

5

4

3

2

1

0

SSR5 SSR4 SSR3 SSR2 SSR1 SSR0

11: Min Step Rate

12: Max Step Rate

13: STEP Readback

1

0

1

P

0

WR

0

RSR5 RSR4 RSR3 RSR2 RSR1 RSR0

1

0

1

P

0

DIRR

0

SA5

0

SA4

0

SA3

0

SA2

0

SA1

0

SA0

0

R

0

Register 11: Starting Step Rate

Register 13: STEP Readback

SSR[5:0] Starting Step Rate in Full Step/s

DIRR

STEP direction readback

Step Angle Number readback

SA[5:0]

R_STT= (n + 1) × 2 Full step/s

Register 12: Running Step Rate

RSR[5:0] Running Step Rate in Full Step/s

R_RUN= (n + 1) × 16 Full step/s

For both SSR and RSR, the step rate is in full steps/s. This is

maintained for all microstep resolutions. The number of micro-

steps per second is a multiple of the programmed step rate based

on the number of microsteps per full step.

30

Allegro MicroSystems, LLC

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AMT49700

Automotive Stepper Driver

Serial Register Reference

15

14

13

12

11

WR

0

10

OT

0

9

TW

0

8

OV

0

7

UV

0

6

5

4

OLB

0

3

2

1

0

OLA OCB OCA

14: Mask

1

0

P

0

BPL

0

BPH

0

APL

0

APH

0

BML BMH

AML AMH

15: Diagnostic

Status

1

WR

P

0

OT

0

TW

0

OV

0

UV

0

OLB

0

FF

1

POR

1

SE

0

CR

0

SSA

0

OLA OCB OCA

0

Register 14: Mask register

Status Register

OT

Overtemperature

Temperature Warning

VBB Overvoltage

FF

Status Flag

TW

POR

SE

Power-on-reset

Serial Error

OV

UV

Undervoltage on VBB or VCP

Phase B open load

CR

Command Ready for Motion Profile

Step Sequence Active indicator

Overtemperature

OLB

OLA

OCB

OCA

SSA

OT

Phase A open load

Phase B overcurrent

Phase A overcurrent

TW

Temperature warning

OV

Overvoltage on VBB

UV

Undervoltage on VBB or VCP

Open load on phase B

xx

0

Fault mask

Default

OLB

OLA

OCB

OCA

Fault detection permitted

Fault detection disabled

D

Open load on phase A

1

Overcurrent on phase B

Overcurrent on phase A

Register 15: Diagnostic

xx

0

Fault

Default

BML

BMH

BPL

BPH

AML

AMH

APL

APH

Overcurrent on BM Output low-side

Overcurrent on BM Output high-side

No fault detected

Fault detected

D

1

Overcurrent on BP Output low-side

Overcurrent on BP Output high-side

Overcurrent on AM Output low-side

Overcurrent on AM Output high-side

Overcurrent on AP Output low-side

Overcurrent on AP output high-side

Status Register bit map to Diagnostic Register

Status Register Bit Related Diagnostic Register Bits

OCB

OCA

BML, BMH, BPL, BPH

AML, AMH, APL, APH

31

Allegro MicroSystems, LLC

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www.allegromicro.com

AMT49700

Automotive Stepper Driver

Table 3: Phase Current Table ^[1][2](default, power-on content)

Phase Current

[%I_SMAX

Step

Angle

Phase Current

[%I_SMAX

Step

Angle

Step Number

Phase

DAC

Step Number

Phase

DAC

]

Full 1/2 1/4 1/8 1/16

A

B

A

0

B

0

1

A

B

Full 1/2 1/4 1/8 1/16

A

B

A

0

1

0

B

1

0

A

B

0

1

2

3

4

0

1

2

3

4

5

6

7

8

0

0.00%

100.00%

98.44%

95.31%

92.19%

87.50%

82.81%

76.56%

70.31%

64.06%

56.25%

46.88%

37.50%

29.69%

18.75%

9.38%

0.0

0

5

63

4

5

6

7

0

8

16

17

18

19

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

0.00%

–100.00% 180.0

0

5

63

1

9.38%

5.4

–9.38% –100.00% 185.4

–18.75% –98.44% 190.8

–29.69% –95.31% 197.3

–37.50% –92.19% 202.1

–46.88% –87.50% 208.2

–56.25% –82.81% 214.2

–64.06% –76.56% 219.9

–70.31% –70.31% 225.0

–76.56% –64.06% 230.1

–82.81% –56.25% 235.8

–87.50% –46.88% 241.8

–92.19% –37.50% 247.9

–95.31% –29.69% 252.7

–98.44% –18.75% 259.2

1

2

18.75%

29.69%

37.50%

46.88%

56.25%

64.06%

70.31%

76.56%

82.81%

87.50%

92.19%

95.31%

98.44%

100.00%

98.44%

95.31%

92.19%

87.50%

82.81%

76.56%

70.31%

64.06%

56.25%

46.88%

37.50%

29.69%

18.75%

9.38%

10.8

17.3

22.1

28.2

34.2

39.9

45.0

50.1

55.8

61.8

67.9

72.7

79.2

84.6

90.0

95.4

11 62

18 60

23 58

29 55

35 52

40 48

44 44

48 40

52 35

55 29

58 23

60 18

62 11

11 62

18 60

23 58

29 55

35 52

40 48

44 44

48 40

52 35

55 29

58 23

60 18

62 11

3

2

4

9

5

3

6

7

0

4

8

2

10 20

21

9

5

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

6

11 22

23

7

63

5

0

5

47 –100.00% –9.38%

264.6

270.0

275.4

280.8

287.3

292.1

298.2

304.2

309.9

315.0

320.1

325.8

331.8

337.9

342.7

349.2

63

5

0

5

8

0.00%

12 24

25

48 –100.00%

49 –100.00%

0.00%

9.38%

–9.38%

9

–18.75% 100.8

–29.69% 107.3

–37.50% 112.1

–46.88% 118.2

–56.25% 124.2

–64.06% 129.9

–70.31% 135.0

–76.56% 140.1

–82.81% 145.8

–87.50% 151.8

–92.19% 157.9

–95.31% 162.7

–98.44% 169.2

–100.00% 174.6

–100.00% 180.0

62 11

60 18

58 23

55 29

52 35

48 40

44 44

40 48

35 52

29 55

23 58

18 60

11 62

50

51

52

53

54

55

56

57

58

59

60

61

62

63

0

–98.44%

–95.31%

–92.19%

–87.50%

–82.81%

–76.56%

–70.31%

–64.06%

–56.25%

–46.88%

–37.50%

–29.69%

–18.75%

–9.38%

18.75%

29.69%

37.50%

46.88%

56.25%

64.06%

70.31%

76.56%

82.81%

87.50%

92.19%

95.31%

98.44%

62 11

60 18

58 23

55 29

52 35

48 40

44 44

40 48

35 52

29 55

23 58

18 60

11 62

10

11

12

13

14

15

16

13 26

27

1

3

14 28

29

15 30

31

5

0

63

100.00% 354.6

100.00% 0.0

5

0

63

0.00%

0

0.00%

^[1]To be read in conjunction with Table 6: Step Angle Allocation

^[2]The home position is deﬁned as step number 8 for all modes of operation except 1-phase full step in which home is deﬁned as step 0

32

Allegro MicroSystems, LLC

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www.allegromicro.com

AMT49700

Automotive Stepper Driver

APPLICATIONS INFORMATION

The target angle of each microstep position with the electrical

cycle is determined by product of the step angle number and the

angle for a single microstep. So for the example of Figure 7:

Motor Microstepping

The key to understanding microstepping lies in understanding the

phase current table. This table contains the relative phase current

magnitude and direction for each of the two motor phases at each

microstep position. The maximum resolution of the AMT49700

is 1/16th microstep—that is, 16 microsteps per full step. There are

4 full steps per electrical cycle so the phase current table has 64 mic-

rostep entries. The entries are numbered from 0 to 63. This number

represents the phase angle within the full 360° electrical cycle and is

called the step angle number. This is illustrated in Figure 8.

α_28(TARGET)= 28 × 5.625º = 157.5º

The actual angle is calculated using basic trigonometry as:

I_A28

α_28(ACTUAL)= 180 + tan-1

= 180 + (-22.1) = 157.9º

( )

I_B28

So the angle error is only 0.4°. Equivalent to about 0.1% error in

360° and well within the current accuracy of the AMT49700.

Note that each phase current in the AMT49700 is defined by a

6-bit DAC. This means that the smallest resolution of the DAC

is 100 / 64 = 1.56% of the full scale, so the AMT49700 can-

not produce a resultant motor current of exactly 100% at each

microstep, nor can it produce an exact microstep angle. However,

as can be seen from the calculations above, the results for both

are well within the specified accuracy of the AMT49700 current

control. The resultant motor current angle and magnitude are also

more than precise enough for all but the highest precision stepper

motors.

PHASE TABLE AND PHASE DIAGRAM

Figure 8 shows the contents of the phase current table as a phase

diagram. The phase B current, I_B, from the phase current table, is

plotted on horizontal axis and the phase A current, I_A, is plotted

on the vertical axis. The resultant motor current at each microstep

is shown as numbered radial arrows. The number shown cor-

responds to the 1/16th microstep step angle number in the phase

current table.

Figure 7 shows an example of calculating the resultant motor

current magnitude and angle for step number 28. The target is

to have the magnitude of the resultant motor current to be 100%

at all microstep positions. The relative phase currents from the

phase current table are:

With the phase table, control of a stepper motor is simply a

matter of increasing or reducing the step angle number to move

round the phase diagram of Figure 8. This can be in predefined

multiples using the step sequencer or it can be variable using the

direct single step control.

I_A= 37.50%

I_A

I_B= –92.19%

24

Assuming a full-scale (100%) current of 1 A means that the two

phase currents are:

25

26

I_A= 0.3750 A

I_B= –0.9219 A

27

I_A28

=37.5%

28

29

30

31

The magnitude of the resultant will be the square root of the sum

of the squares of these two currents:

α₂₈

=

157.9°

|I₂₈| = I²_A+ I²_B

=

0.1406 + 0.8499 = 0.9953

(A)

So the resultant current magnitude is 99.53% of full scale. This

is within 0.5% of the target 100% and is well within the ±10%

accuracy of the AMT49700.

I_B

32

–

92.19%

=

I_B28

The reference angle, that is zero degrees (0°), within the full elec-

trical cycle (360°), is defined as the angle where I_Bis at +100%

and I_Ais zero. Each full step is represented by 90° in the electri-

cal cycle, so each 1/16th microstep is (90°/16 steps =) 5.625°.

Figure 7: Calculating the Resultant Motor Current

33

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AMT49700

Automotive Stepper Driver

I_A

17 16 15

18

14

19

13

20

12

21

11

22

10

23

9

24

8

25

7

26

27

28

29

30

6

5

4

3

2

31

1

32

33

0

I_B

63

62

61

60

59

58

34

35

36

37

38

39

40

57

56

41

55

42

54

43

53

44

52

45

51

46

50

47 48 49

Figure 8: Phase Current Table as a Phase Diagram

34

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AMT49700

Automotive Stepper Driver

than the single full current positions. With both phases active, the

power dissipation is shared between two drivers. This slightly

improves the ability to dissipate the heat generated and reduces

the stress on each driver. The second advantage is that the hold-

ing torque can be more effective because the forces holding the

motor are mainly rotational rather than mainly radial.

MICROSTEPPING WITH THE STEP SEQUENCER

When using the programmable step sequence control method,

the step sequencer provides a step command at the appropri-

ate time to move the motor at the microstep resolution defined

by the MS[2:0] bits. The DIR input defines the motor direc-

tion. These inputs define the output of a step angle counter that

determines the required step angle number in the phase current

table. Table 3 summarizes the step angle numbers used for the

resolutions available when using the step sequencer to control

the output of the AMT49700.

Two half-step modes are available: compensated and uncompen-

sated. Compensated mode uses eight of the entries in the phase

current table. These are 0, 8, 16, 24, 32, 40, 48, and 56 as shown

in Figure 11. In this mode, the current in each phase is compen-

sated for the step angle to ensure that the average torque is the

same at all step positions.

In sixteenth step mode, the step angle counter simply increments

or decrements the step angle number by one on each rising edge

of the step input depending on the logic state of the DIR input. In

the other microstep resolution modes, the step angle counter out-

puts specific step angle numbers as defined in the phase current

table, Table 3, and summarized in Table 4.

Uncompensated half-step mode does not reduce the current based

on the step angle. Instead, each phase is driven to the current tar-

get defined by the 100% current value at steps 0, 16, 32, or 48 in

the phase angle table. The current polarity is the same at each half

step angle as defined in the phase angle table. The resulting phase

diagram is shown in Figure 12.

Table 4: Step Angle Allocation

Mode

Step angle numbers used

0, 16, 32, 48

Quarter step uses sixteen of the entries in the phase current table.

These are the multiples of 4, namely 0, 4, 8, 12, 16, 20, 24, 28,

32, 36, 40, 44, 48, 52, 56, and 60 as shown in Figure 13. Eighth-

step mode uses the 32 even-numbered entries in the phase current

table including 0, namely 0, 2, 4, and so on, up to 58, 60, and 62

as shown in Figure 14.

Full 1 phase

Full 2 phase

8, 24, 40, 56

Half Compensated.

Half Uncompensated

0, 8, 16, 24, 32, 40, 48,56

0, 0/16, 16, 16/32, 32, 32/48, 48, 48/0

0, 4, 8, 12, 16, 20, 24, 28, 32, 36, 40, 44, 48,

52, 56, 60

Quarter

0, 2, 4, 6, 8, 10, 12, 14, 16 18, 20, 22, 24, 26,

28, 30, 32, 34, 36, 38, 40, 42, 44, 46, 48, 50,

52, 54, 56, 58, 60, 62

In quarter-step, eighth-step, and sixteenth step modes, the current

in each phase is compensated for the step angle to ensure that the

average torque is the same at all step positions.

Eighth

Sixteenth

All

The microstep selection can be changed between step commands

from the step sequencer. When the microstep resolution changes,

the AMT49700 moves to the next available step angle number

at the new resolution on the next rising edge of the STEP input.

For example, if the microstep mode is sixteenth and the pres-

ent step angle is 57, then with the direction forwards (increasing

step angle), changing to quarter-step mode will cause the phase

number to go to 60 on the next rising edge of the STEP input,

changing to half-step mode will cause the phase number to go to

0 on the next rising edge of the STEP input.

There are two full-step modes available: 1-phase and 2-phase. In

both cases, four of the entries in the phase current table are used.

1-phase full-step mode uses step angles 0, 16, 32, and 48, as

shown in Figure 9, and only one phase is active at any time.

These step angles place the motor at the detent points, the posi-

tions where the motor naturally settles to minimize the internal

magnetic path reluctance. This mode has the advantage that once

the motor movement has stopped, the current can be reduced to a

very low level to hold the motor. The magnetic fields will be act-

ing with any hold current to prevent motor movement.

On first power-up, after a power-on reset or after sleep, the step

angle number is set to 8, equivalent to the electrical 45° position,

except for full-step single phase drive where the step angle num-

ber is set to 0. This position is defined as the “home” position.

2-phase mode uses step angles 8, 24, 40, and 56 as shown in

Figure 10. In this case, two phases are always active at each step

position. There are two advantages in using these positions rather

35

Allegro MicroSystems, LLC

955 Perimeter Road

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www.allegromicro.com

AMT49700

Automotive Stepper Driver

I_A

16

24

8

0

I_B

32

40

56

48

Figure 9: Full-Step 1-Phase Drive Phase Diagram

Figure 10: Full-Step 2-Phase Drive Phase Diagram

I_A

16

0/16

16/32

24

8

0

I_B

32

40

56

48

32/48

48/0

Figure 11: Compensated Half-Step Phase Diagram

Figure 12: Uncompensated Half-Step Phase Diagram

I_A

16

14

16

18

12

20

10

22

24

8

24

26

28

30

8

6

4

28

2

0

I_B

32

34

32

36

62

36

38

40

60

58

56

60

40

56

54

42

52

44

52

50

46

48

Figure 13: Quarter-Step Phase Diagram

Figure 14: Eighth-Step Phase Diagram

36

Allegro MicroSystems, LLC

955 Perimeter Road

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AMT49700

Automotive Stepper Driver

Table 5: Two’s Complements

SINGLE-STEP CONTROL

Decimals

2’s Comp.

00 0000

00 0001

00 0010

00 0011

00 0100

00 0101

00 0110

00 0111

00 1000

00 1001

00 1010

00 1011

00 1100

00 1101

00 1110

00 1111

01 0000

Decimals

2’s Comp.

The motor movement can be controlled one step at a time through

the serial interface by directly increasing or decreasing the step

angle number. The maximum value of the step angle number

is 63 and the minimum number is 0. Therefore, any increase or

reduction in the microstep number is performed using modulo

64 arithmetic. This means that increasing a step angle number

of 63 by 1 will produce a step angle number of 0, increasing by

two from 63 will produce 1, and so on. Similarly, in the reverse

direction, reducing a step angle number of 0 by 1 will produce a

step angle number of 63, decreasing by two from 0 will produce

62, and so on.

0

1

–1

–2

11 1111

11 1110

11 1101

11 1100

11 1011

11 1010

11 1001

11 1000

11 0111

11 0110

11 0101

11 0100

11 0011

11 0010

11 0001

11 0000

2

3

–3

4

–4

5

–5

6

–6

7

–7

8

–8

9

–9

The step angle is changed by writing a value to the SC[5:0] vari-

able. This number is a two’s complement number that is added to

the step angle number causing it to increase or decrease. Two’s

complement is the natural integer number system for most micro-

controllers. This allows standard arithmetic operators to be used,

within the microcontroller, to determine the size of the next step

increment. Table 5 shows, for clarity, the binary equivalent of

each decimal number between 16 and +16.

10

11

12

13

14

15

16

–10

–11

–12

–13

–14

–15

–16

Each increase in the step angle number represents a forwards

movement of one-sixteenth microstep. Each decrease in the step

angle number represents a reverse movement of one-sixteenth

microstep.

the motor backwards in quarter step increments, the number –4

(11 1100) is repeatedly written to SC[5:0] (see Figure 17). Figure 17

and Figure 18 show half-step forwards and eighth-step backwards

sequences, respectively.

To move the motor one full step, the step angle number must be

increased or reduced by 16. To move the motor one half step, the

step angle number must be increased or reduced by 8. For one

quarter step, the step angle number must be increased or reduced

by 4. And for one eighth step, the step angle number must be

increased or reduced by 2.

With this control mode, the step rate is controlled by the timing

of the serial interface and is the inverse of the step time, t_STEP

,

shown in Figure 15. The motor step only takes place when the

STRn goes from low to high when writing the value into SC[5:0].

The motor step rate is therefore determined by the timing of the

rising edge of the STRn input. The clock rate of the serial inter-

face, defined by the frequency of the SCK input, has no direct

For example, to continuously move the motor forwards in quar-

ter step increments, the number 4 (00 0100) is repeatedly written

to SC[5:0] through the serial interface (see Figure 15). To move

effect on the step rate.

37

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AMT49700

Automotive Stepper Driver

+4

0 0 0 0 0 0 0 1 0 0 1

0 1 0

1 1

SDI

SCK

STRn

t

STEP

Figure 15: Serial Interface Sequence for Quarter Step in Forward Direction

-4

0 1 0 1 1 0 0 0 0 1 1 1 1 0 0 0

SDI

SCK

STRn

Figure 16: Serial Interface Sequence for Quarter Step in Reverse Direction

+8

0 1 0 1 1 0 0 0 0 0 0 1 0 0 0 1

SDI

SCK

STRn

Figure 17: Serial Interface Sequence for Half Step in Forward Direction

-2

0 1 0 1 1 0 0 0 0 1 1 1 1 1 0 1

SDI

SCK

STRn

Figure 18: Serial Interface Sequence for Eighth Step in Reverse Direction

38

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AMT49700

Automotive Stepper Driver

or run speed settings, the acceleration, deceleration, or the most

significant 8 bits of the step count variable will have no effect

until the least significant 8 bits of the step count variable are suc-

cesfully written.

Motion Control with the Step Sequencer

The basic operation of the programmable step sequencer is

described in the “Stepper Motor Motion Control” section. The

motion is described by 5 programmable variables, giving the

start step rate, run step rate, acceleration, deceleration, and the

total number of steps to take. These are illustrated in Figure 5,

repeated here.

If a change occurs when the sequence is in progress, the step

sequencer will either continue running at the run step rate,

accelerate the motor or decelerate the motor (Figure 20). The

step count will be updated with the new step count. If there is

no change to the most significant 8 bits of the step count, then

the previous value will be retained and only the least significant

8 bits will be changed. If only the step rate is changed, then the

least significant 8 bits of the step count should be written with the

same value as the original programmed input.

Steꢀ Rate

Rꢁn

Rate

There are many profile change combinations possible. The fol-

lowing examples provide the response to specific changes as

examples from which it should be possible to extrapolate other

possible responses.

Acceleration

ꢂeceleration

Start

Rate

Steꢀs

Steꢀ Rate

Steꢀ Coꢁnt

Rꢁn

Rate

Figure 5: Step Proﬁle Parameters

In the normal single sequence from a stationary state shown in

Figure 5, the sequencer will begin by stepping the motor at the

programmed start rate for the first step. The following steps will

increase in step rate according to the programmed acceleration

until the motor reaches the run step rate. At each step, the total

step count remaining is reduced by one. The motor continues to be

stepped at the run step rate until the step count reaches the number

of steps required to decelerate the motor, based on the present step

rate, the start rate, and the deceleration factor. At this point, the step

rate is reduced at each step according to the programmed decelera-

tion until the motor reaches the start step rate at the step count.

Once the step count is reached the motor is stopped.

Start

Rate

Steꢀs

Steꢀ Coꢁnt

Figure 19: Low Step Count

Steꢀ Rate

Accelerates

to new leꢃel

If the number of steps is insufficient to accelerate to the full run

speed, the sequencer will accelerate the motor until it reaches the

number of steps required to decelerate the motor for the present

speed and will then change immediately to deceleration as shown

in Figure 19. The motor will then continue to decelerate until the

motor reaches the step count.

ꢁncreased

Rꢂn Rate

ꢁnital

Rꢂn

Rate

Steꢀ Rate

ꢄecelerates

to new leꢃel

Redꢂced

Rꢂn Rate

A single sequence is relatively simple to comprehend, but it is

also possible to change the variables when a step sequence in in

progress. A sequence can only start or be changed on the rising

edge of the STRn input following the writing of the least signifi-

cant 8 bits of the step count variable, NSL (the serial interface

timing sequence is shown in Figure 2). Any changes to the start

Start

Rate

Steꢀs

Figure 20: Run Speed Change

39

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AMT49700

Automotive Stepper Driver

Change

acceꢀted

If the step count is changed while a step sequence is in progress,

the AMT49700 will immediately update the target count on the

rising edge of the STRn input following the writing of the least

significant 8 bits of the step count variable, NSL. The target count

will still be relative to the starting position of the original step

sequence command.

Rate

Rꢁn

ꢂriginal ꢀroꢃile

ꢂriginal Coꢁnt

New

ꢀroꢃile

Start

Steꢀs

Uꢀdated Coꢁnt

If an update results in a reduced step count and there is still suf-

ficient time to continue stepping at the run rate (in time change)

then the sequence will complete normally as shown in Figure 21a.

Figure 21a: Count Decrease (in time)

Change

acceꢀted

Rate

Rꢁn

If an update results in a reduced step count and there is insuffi-

cient time to decelerate the motor to the new step count end point

(late change), then deceleration will start immediately. The motor

will continue to decelerate until it is running at the start step rate

where it will stop. At this point the target count will be exceeded

and the motor will be stepped in the reverse direction until it

reaches the updated count position as shown in Figure 21b. The

profile applied in the reverse direction will use the same accel-

eration, run rate, and deceleration parameters as in the forward

direction.

ꢂriginal ꢀroꢃile

New

ꢀroꢃile

ꢂriginal Coꢁnt

Start

Steꢀs

Coꢁnt ꢄꢅceeded

Uꢀdated Coꢁnt

Figure 21b: Count Decrease (in time)

Change

acceꢀted

Rate

Rꢁn

ꢂriginal

ꢀroꢃile

New

ꢀroꢃile

If an update results in an increased step count and the motor is

stepping at the run rate (in time change), then the sequence will

complete normally as shown in Figure 22a.

ꢂriginal Coꢁnt

Start

Steꢀs

Uꢀdated Coꢁnt

If an update results in an increased step count and motor is decel-

erating (late change), then the motor will immediately start to

accelerate at the programmed rate and follow the normal profile

sequence as shown in Figure 22b.

Figure 22a: Count Increase (in time)

Change

acceꢀted

Rate

Rꢁn

If an update results in a change of direction, with or without a

step count change, then the motor will immediately start to decel-

erate to a stop, then start a normal profile sequence in reverse, up

to the new step count in the reverse direction. The step count is

still relative to the original start point of the sequence as shown in

Figure 23.

New

ꢀroꢃile

ꢂriginal Coꢁnt

ꢂriginal

ꢀroꢃile

Start

Steꢀs

Uꢀdated Coꢁnt

Figure 22b: Count Decrease (late)

Rate ꢉwd

Change

acceꢀted

Rꢂn

ꢁriginal

ꢀroꢈile

ꢁriginal Coꢂnt

Start

ꢄꢅR ꢆ 1

ꢄꢅR ꢆ 0

Steꢀs

Uꢀdated Coꢂnt

ꢁriginal

Coꢂnt

ꢃꢄꢅRꢆ0ꢇ

Uꢀdated Coꢂnt

with ꢄꢅR change

Uꢀdated

Coꢂnt

ꢃꢄꢅRꢆ1ꢇ

Rꢂn

Reꢊ

Figure 23: Direction Change

40

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AMT49700

Automotive Stepper Driver

PROFILE COMMAND UPDATE

CONTINUOUS RUN MODE

When a new motion profile is input while a motion profile is in

progress, the AMT49700 will update the target position relative

to the existing start position from the previous command. If the

The AMT49700 has a function to continue stepping without the

step number control. When the continuous run mode is active, the

stepper motor will accelerate and run regardless of step demand

previous motion profile has successfully completed, then any new until a stop command is inserted. This function allows to have a

motion profile will start from present position.

simple rotation application.

The status of the motion profile can be determined by reading

the SSA bit in the Status register. The DIAG output can also be

programmed to be low when SSA is set to 1.

The Acceleration rate, ACC[5:0], Deceleration rate, DEC[5:0],

Stating Step Rate, SSR[5:0], Running Step Rate, RSR[5:0], will

be respected. The CRM bit in Configuration register 7 is used to

activate the continuous run mode. When the CRM is set to 1, then

continuous run mode will be active. The ACC, DEC, SSR, and

RSR need to be preprogramed to reflect these ratios before send-

ing the CRM. When the CRM is set to 1, these motion profile

settings value will be taken in account. If the CRM bit set from 1

to 0, then the motion profile will decelerate and stop the motor.

A Command Ready bit, CR, is provided in the Status Register.

If the CR bit is 1 when STRn goes low, then the AMT49700 will

accept a new step sequence command. If the CR bit is 0 when

STRn goes low, then the AMT49700 will not accept a new step

sequence command. CR can be read out at the same time as Con-

fig 7 is being written. If CR = 1, the NSL command is accepted

and then step sequence will start on the rising edge of STRn.

The continuous run mode can accept motion profile parameters

changing while in operation. The new motion profile parameters

will be taken into account after transferring configuration register

7. When the motion profile is in deceleration to move to a new

running step rate, if the same command is updated twice, decel-

eration will be skipped to run at the new running step rate.

If a new command is inserted while CR is 0, then the AMT49700

will ignore the command.

Latch

CR

SꢀRn

SCꢁ

NSLꢅnꢈ1ꢆ

NSLꢅnꢆ

Sꢂꢃ

Statꢇsꢅnꢆ

Statꢇsꢅnꢈ1ꢆ

Sꢂꢄ

CR ꢊitꢋ 0

CR ꢊitꢋ 1

Command Acceꢉted

Command ꢃgnored

Figure 24: Motion Proﬁle Update with CR Status Checking

41

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AMT49700

Automotive Stepper Driver

capacitor should have a value of 100 nF and be placed as close

as possible to the VBB and GND terminals of the AMT49700.

The electrolytic capacitor should be rated to at least 1.5 times

the intended maximum operating voltage and selected to support

the maximum motor ripple current over the full system operating

temperature range. (In many instances, actual capacitance value

will be of secondary importance and device selection will be

driven by ripple current rating and ESR.) This device should also

be located close to the AMT49700.

Layout

The printed wiring board (PWB) should use a higher weight

copper thickness than a standard small signal or digital board.

This helps to reduce the track impedance when conducting high

currents. PWB traces carrying switching currents (i.e. power,

ground, and bridge outputs) should be as wide and short as pos-

sible to minimize their inductance. This will help reduce any volt-

age transients caused by current switching during PWM current

control.

The pump capacitor between CP1 and CP2 and the pump storage

capacitor between VCP and VBB should be connected as close as

possible to the respective terminals of the AMT49700.

For optimum thermal performance, the exposed thermal pad on

the underside of the AMT49700 should be soldered directly onto

the board. A solid ground plane should be added to the opposite

side of the board and multiple vias through the board placed in

the area under the thermal pad.

GROUNDING

A star ground system, with the common star point located close

to the AMT49700 is recommended. All ground terminals must be

connected together externally. The copper ground plane located

under the exposed thermal pad is typically used as the star ground

point.

DECOUPLING

The power supply should be decoupled with an electrolytic

capacitor in parallel with a ceramic capacitor. The ceramic

42

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AMT49700

Automotive Stepper Driver

INPUT/OUTPUT STRUCTURES

V+

CP1

CP2

VCP

VBB

2 kΩ

SCK

SDI

12 V

8 V

6 V

8 V

80 kΩ

6 V

Figure 25d: SDI Input

Figure 25b: SCK Input

46 V

V+

25 Ω

80 kΩ

2 kΩ

DIAG

GNDPA

GNDPB

STRn

32 kΩ

8 V

6 V

46 V

12 V

GND

Figure 25a: Supplies and Reference

Figure 25c: STRn Input

Figure 25g: DIAG Output

VBB

V+

500 Ω

100 kΩ

100 Ω

SDO

OXP

OXM

RESETn

10 V

85 kΩ

6 V

1 pF

8 V

GNDPX

Figure 25e: SDO Output

Figure 25h: RESETn, Input

Figure 25i: PHASE Outputs

V+

120 kΩ

STEP

DIR

6 V

1 pF

80 kΩ

8 V

Figure 25j: STEP, DIR Inputs

43

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AMT49700

Automotive Stepper Driver

PACKAGE OUTLINE DRAWING

For Reference Only – Not for Tooling Use

(Reference JEDEC MO-220VHHD-6)

Dimensions in millimeters – NOT TO SCALE

Exact case and lead conﬁguration at supplier discretion within limits shown

0.30

0.50

5.00 0.ꢀ0

0.ꢀ0 REF

32

ꢀ.00

1

2

1

2

A

5.00 0.ꢀ0

3.20 5.00

DETAIL A

ꢀ

0.85 0.05

D

32X

C

3.20

5.00

0.08

C

SEATING

PLANE

0.22 0.05

PCB Layout Reference View

C

0.50 BSC

0.05 REF

0.40 0.ꢀ0

0.203 REF

0.40 0.ꢀ0

0.ꢀ0 REF

3.20 0.ꢀ0

0.50 0.20

0.05 REF

B

Detail A

2

1

A

B

Terminal #ꢀ mark area

32

Exposed thermal pad (reference only, terminal #ꢀ identiﬁer appearance at supplier

discretion)

Reference land pattern layout (reference IPC735ꢀ QFN50P500X500Xꢀ00-33V6M);

all pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet

application process requirements and PCB layout tolerances; when mounting on a

multilayer PCB, thermal vias at the exposed thermal pad land can improve thermal

dissipation (reference EIA/JEDEC Standard JESD5ꢀ-5)

3.20 0.ꢀ0

C

D

Coplanarity includes exposed thermal pad and terminals

Figure 26: Package LP, 20-Pin TSSOP with Exposed Thermal Pad

44

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AMT49700

Automotive Stepper Driver

Revision History

Number

Date

Description

–

February 15, 2019

Initial release

Allegro MicroSystems, LLC reserves the right to make, from time to time, such departures from the detail specifications as may be required to

permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that

the information being relied upon is current.

Allegro’s products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of

Allegro’s product can reasonably be expected to cause bodily harm.

The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, LLC assumes no responsibility for its

use; nor for any infringement of patents or other rights of third parties which may result from its use.

Copies of this document are considered uncontrolled documents.

For the latest version of this document, visit our website:

www.allegromicro.com

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型号：	AMT49700KETJTR
厂家：	ALLEGRO MICROSYSTEMS
描述：	Automotive Stepper Driver 电动机控制
文件：	总45页 (文件大小：2505K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AMT49700KETJTR [ALLEGRO]

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