APS12400LUAATN-0H1A [ALLEGRO]
Two-Wire Hall-Effect Latch;
| 型号： | APS12400LUAATN-0H1A |
| 厂家： | 
ALLEGRO MICROSYSTEMS |
| 描述： | Two-Wire Hall-Effect Latch |
| 文件： | 总19页 (文件大小：1147K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
APS12400
Two-Wire Hall-Effect Latch
FEATURES AND BENEFITS
• ASIL A functional safety
DESCRIPTION
APS12400 devices are two-wire planar Hall-effect sensor
integrated circuits (ICs) developed in accordance with
ISO 26262:2011 (pending assessment). They include internal
diagnostics and support a functional safety level of ASIL A.
The enhanced two-wire current-mode interface provides
interconnect open/short diagnostics and adds a Safe State
to communicate diagnostic information while maintaining
compatibilitywithlegacytwo-wiresystems.Two-wiresensors
arewell-suitedtosafetyapplications,especiallythoseinvolving
long wire harnesses.
□ Developed in accordance with ISO 26262:2011
(pending assessment)
□ Internal diagnostics and a defined Safe State
□ A2-SIL™ documentation available
• Multiple product options
□ Magnetic polarity, switchpoints, and hysteresis
□ Temperature coefficient (supports SmCo, NdFeB, and
ferrite magnets)
□ Output polarity and current levels
• Reduces module bill of materials (BOM) and assembly cost
□ Integrated overvoltage clamp (40 V load dump) and
reverse-battery diode
□ Integrated series resistor and bypass capacitor (UC package)
□ Enables PCB-less sensor modules
• Automotive-grade ruggedness and fault tolerance
□ Extended AEC-Q100 Grade 0 qualification
□ Operation at –40°C to 175°C junction temperature
□ 3 to 24 V operating voltage range
The APS12400 is a factory-calibrated latch (bipolar switch)
available in several product options including magnetic
switchpoints, temperature coefficient, and output polarity.
The response can be matched to SmCo, NdFeB, or low-cost
ferrite magnets. There is a choice of two output current levels
and either output polarity.
APS12400 sensors are engineered to operate in the harshest
environments with minimal external components. They are
qualified beyond the requirements of AEC-Q100 Grade 0
and will survive extended operation at 175°C junction
Continued on the next page…
□ High EMC/ESD immunity
□ Overtemperature indication
PACKAGES
3-pin SOT23-W (LH)
3-pin ultramini SIP (UA)
3-pin SIP (UC)
TYPICAL APPLICATIONS
• Automotive and Industrial safety systems
• Sun roof/convertible top/tailgate/liftgate actuation
• Clutch-by-wire
• Electric Power Steering (EPS)
• Transmissions actuators
• Wiper motors
Not to scale
VCC
68 Ω
VINT
Device
Configuration
ICC Adjust
0.1 µF
UVLO
Regulator
0.01 µF
Clock Generator
UC Package
Only
Switchpoint
Control
LH and UA
Packages
Only
Output
Polarity
Amp
Low-Pass
Filter
Temp
Comp
GND
Functional Block Diagram
APS12400-DS, Rev. 2
MCO-0000402
April 1, 2019
APS12400
Two-Wire Hall-Effect Latch
DESCRIPTION (continued)
temperature. These monolithic ICs include on-chip reverse-battery protection components into the IC package. Other package options
protection,overvoltageprotection(40Vloaddump),ESDprotection,
overtemperature detection, and an internal voltage regulator for
operation directly from an automotive battery bus. These integrated
features reduce the end-product bill of materials (BOM) and
assembly cost.
include industry-standard surface-mount SOT (LH) and through-
hole SIP (UA) packages. All three packages are RoHS-compliant
and lead (Pb) free with 100% matte-tin-plated leadframes.
Forsituationswhereafunctionallyequivalentbutfactory-programmed
two-wire latch or end-of-line programmable device is preferred, refer
The available SIP package with integrated discrete components
(UC)enablesPCB-lessapplicationsbyincorporatingalloftheEMC to the APS12400 and APS11900 device families, respectively.
RoHS
COMPLIANT
ꢀoꢁꢂlete Part ꢃꢄꢁꢅer ꢆorꢁat
Allegro Iden�fier (Device Family)
APS – Digital Posi�on Sensor
Allegro Device Number
12400 – 2-wire Planar Hall-effect Latch
Configura�on Op�ons
APS 12400
L L H A L X - 0 L 1 A
Temperature Coefficient
A – Flat
B – -0.035%/°C
C – -0.12%/°C
D – -0.2%/°C
ICC(L) Selec�on
1 – 5 to 6.9 mA
2 – 2 to 5 mA
Output Polarity for B > BOP
H – ICC(H)
L – ICC(L)
Device Switch Threshold
0 – BOP: +80 G max; BRP: -80 G max
1 – BOP: +40 G max; BRP: -40 G max
Instruc�ons (Packing)
LT – 7-in. reel, 3,000 pieces/reel (LH Only)
LX – 13-in. reel, 10,000 pieces/reel (LH Only)
TN – 13-in. reel , 4,000 pieces /reel (UA Only)
(no op�on code) – bulk, 500 pieces/bag (UA Only)
Package Designa�on
LHA – 3-pin SOT23W Surface Mount
UAA – 3-pin SIP Through-Hole
UCD*– 3-pin SIP Through-Hole w/ passives
Ambient Opera�ng Temperature Range
L – -40°C to +150°C
* Contact Allegro for availability.
2
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
APS12400
Two-Wire Hall-Effect Latch
SELECTION GUIDE
ICC(L)
Selection
Magnetic
Temperature
Coefficient
Output Polarity
for B > BOP
Device Switch
Threshold (G)
Part Number [1]
Package
Packing
(mA)
APS12400LLHALT-0H1A
APS12400LLHALX-0H1A
APS12400LUAA-0H1A
3-pin SOT23-W surface mount
3-pin SOT23-W surface mount
3-pin SIP through-hole
3-pin SIP through-hole
3-pin SIP through-hole
3-pin SIP through-hole
3-pin SIP through-hole
3-pin SIP through-hole
7-inch reel, 3000 pieces/reel
13-inch reel, 10000 pieces/reel
Bulk, 500 pieces/bag
BOP: +80 max
BRP: –80 max
Flat
Flat
Flat
Flat
ICC(H)
ICC(H)
ICC(H)
ICC(H)
5 to 6.9
BOP: +80 max
5 to 6.9
2 to 5
B
RP: –80 max
APS12400LUAATN-0H1A
APS12400LUAA-0H2A
13-inch reel, 4000 pieces/reel
Bulk, 500 pieces/bag
BOP: +80 max
BRP: –80 max
APS12400LUAATN-0H2A
APS12400LUCD-0H1A[2]
APS12400LUCDTN-0H1A[2]
13-inch reel, 4000 pieces/reel
Bulk, 500 pieces/bag
BOP: +80 max
BRP: –80 max
5 to 6.9
13-inch reel, 4000 pieces/reel
[1] Contact Allegro MicroSystems for options not listed in the selection guide.
[2] Contact Allegro MicroSystems for availability.
3
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
APS12400
Two-Wire Hall-Effect Latch
SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
Characteristic
Symbol
VCC
Notes
Rating
40
Unit
V
Supply Voltage [1]
Reverse Supply Voltage
Magnetic Flux Density
VRCC
B
–23
V
Unlimited
165
G
°C
°C
°C
Maximum Junction Temperature
Storage Temperature
TJ(max)
Tstg
For 500 hours
175
–65 to 170
[1] This rating does not apply to extremely short voltage transients such as load dump and/or ESD. Those events have individual ratings
specific to the respective transient voltage event. Contact your local field applications engineer for information on EMC test results.
INTERNAL DISCRETE COMPONENT RATINGS (UC Package Only)
Characteristics
Component
Symbol
Test Conditions
Rated Nominal
Rated
Rated
Rated Temp. Rated Power
Resistance/Capacitance Voltage Tolerance
Range
Handling
1/8 W
–
Resistor
RSERIES
CSUPPLY
In series with VCC
Connected between VCC and GND
68 Ω
50 V
50 V
±15%
±10%
–
Capacitor
100 nF
X7R
4
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
APS12400
Two-Wire Hall-Effect Latch
PINOUT DIAGRAMS AND TERMINAL LIST TABLE
3
Terminal List Table (LH, UA Packages)
Package Name
Number
Function
LH
UA
1
2
VCC
VCC
Supply voltage
Ground terminal
GND
GND
GND
GND
3
Ground terminal
Note: For best performance, tie Pins 2 and 3 together
close to the IC.
2
2
3
LH Package, 3-Pin SOT23W Pinout
UA Package, 3-Pin SIP Pinout
Terminal List Table (UC Package)
Package Name
Number
Function
UC
1
VCC
Supply voltage
This pin reflects the internal
voltage, VINT, after the
internal series resistor. This
pin should be kept floating.
2
3
VINT
GND
100 nF
68 Ω
Ground terminal
2
1
UC Package, 3-Pin SIP Pinout
5
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
APS12400
Two-Wire Hall-Effect Latch
ELECTRICAL CHARACTERISTICS: Valid over full operating voltage and ambient temperature ranges for TJ < TJ(max) and
CBYP = 0.01 µF, unless otherwise specified
Characteristics
Symbol
Test Conditions
Min.
Typ. [3]
Max.
Unit
SUPPLY AND STARTUP
LH and UA
packages
Operating, TJ < 165°C
3.0
4.33
–
–
24
24
–
V
V
V
V
V
Supply Voltage
VCC
Operating, TJ < 165°C
UC package
–
LH and UA
packages
After power-on, as VCC increases, output
VCC(UV)DIS is forced to POS until this voltage is
reached
2.6
3.5
2.3
UC package
–
–
Undervoltage Lockout [4]
LH and UA
packages
–
–
After POK, when VCC drops below this
VCC(UV)EN
voltage, output is forced to POS
UC package
–
5
3.2
–
–
6.9
5
V
ICC(L1)
ICC(L2)
ICC(H)
mA
mA
mA
2
–
Supply Current
12
–
17
Safe current state. Indicates overtemperature or device
configuration error.
ISAFE
–
–
2
mA
No bypass capacitor; CL [5] = 20 pF
–
–
50
–
–
mA/µs
mA/µs
LH and UA
packages
CBYP = 100 nF; CL [5] = 20 pF
0.22
Output Slew Rate
dI/dt
Internal bypass capacitor; CL [5] = 20 pF
VCC ≥ VCC(min), B > BOP(max), B < BRP(min)
t < tPO, VCC ≥ VCC(UV)EN
UC package
–
–
0.22
–
–
mA/µs
µs
Power-On Time [6]
tPO
POS
fC
70
Power-On State [7]
ICC(H)
800
5
mA
kHz
µs
Chopping Frequency
Output Jitter (p-p)
–
–
–
–
1 kHz square wave signal
ON-BOARD PROTECTION
Supply Zener Clamp Voltage
VZ
ICC = ICC(H) + 1 mA, TA = 25°C
ICC = –1 mA
40
–
–
–
–
V
V
Reverse Supply Zener Clamp
Voltage
VRZ
–23
Overtemperature Shutdown
Overtemperature Hysteresis
TSD
Temperature increasing
–
–
205
25
–
–
°C
°C
TJHYS
[3] Typical data is at TA = 25°C and VCC = 12 V unless otherwise noted; for design information only.
[4] UC minimum VCC is higher to accomodate voltage drop in the internal series resistor. UC package minimum VCC is higher to accommodate voltage
drop in the internal series resistor. This also affects the VCC(UV)
.
[5] CL – scope capacitance.
[6] Measured from VCC ≥ VCC(MIN) to valid output.
[7] Power-on state is defined only when VCC slew rate 1 V/s or greater
6
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
APS12400
Two-Wire Hall-Effect Latch
MAGNETIC CHARACTERISTICS: Valid over full operating voltage and ambient temperature ranges for TJ < TJ(max) and
BYP = 0.01 µF, unless otherwise specified
C
Magnetic
Switchpoint
Option
Temperature
Coefficient
Characteristics
Symbol
Test Conditions
Min.
Typ. [8]
Max.
Unit [9]
-0
-1
-0
-1
-0
-1
A – Flat
A – Flat
A – Flat
A – Flat
A – Flat
A – Flat
TA = –40°C to 150°C
TA = –40°C to 150°C
TA = –40°C to 150°C
TA = –40°C to 150°C
TA = –40°C to 150°C
TA = –40°C to 150°C
5
5
–
–
80
40
G
G
G
G
G
G
Operate Point
Release Point
Hysteresis
BOP
–80
–40
40
15
–
–5
BRP
–
–5
–
110
65
BHYS
40
Switchpoint Temperature
Coefficient
All
A – Flat
TA = –40°C to 150°C
–
0
–
%/°C
[8] Typical data is at TA = 25°C and VCC = 12 V, unless otherwise noted; for design information only.
[9] Magnetic flux density, B, is indicated as a negative value for north-polarity magnetic fields, and a positive value for south-polarity magnetic fields.
7
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
APS12400
Two-Wire Hall-Effect Latch
THERMAL CHARACTERISTICS: May require derating at maximum conditions; see application information
Characteristic
Symbol
Test Conditions*
Value
Unit
Package LH, on 1-layer PCB based on JEDEC standard
228
°C/W
Package LH, on 2-layer PCB with 0.463 in.2 of copper area each side
Package UA, on 1-layer PCB with copper limited to solder pads
Package UC, on 1-layer PCB with copper limited to solder pads
110
165
270
°C/W
°C/W
°C/W
Package Thermal Resistance
RθJA
*Additional thermal information available on the Allegro website.
Power ꢒeratiꢏꢓ ꢌꢉrꢔe
2ꢄ
2ꢃ
2ꢂ
2ꢁ
24
2ꢀ
22
21
20
1ꢅ
1ꢄ
1ꢃ
1ꢂ
1ꢁ
14
1ꢀ
12
11
10
ꢅ
ꢋꢌꢌꢍꢈaꢇꢎ
2-laꢕer Pꢌꢖꢗ LH ꢐacꢘaꢓe
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1-laꢕer Pꢌꢖꢗ Pacꢘaꢓe ꢝꢌ
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4
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2
20
40
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ꢄ0 100 120 140 1ꢂ0 1ꢄ0
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1ꢅ00
1ꢄ00
1ꢃ00
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1400
1ꢀ00
1200
1100
1000
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ꢋꢗθꢘA ꢙ 110°ꢐꢚWꢍ
Pacꢓaꢔe ꢛAꢊ 1-laꢕer Pꢐꢖ
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400
ꢀ00
200
100
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100 120 140 1ꢂ0 1ꢄ0
Teꢌꢈeratꢎre ꢋꢏꢐꢍ
8
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
APS12400
Two-Wire Hall-Effect Latch
CHARACTERISTIC PERFORMANCE DATA
ICC(H) vs. TA
ICC(H) vs. VCC
17
16
15
14
13
12
17
16
15
14
13
12
VCC (V)
TA (°C)
3
-40
12
15
24
25
150
-50
-20
10
40
70
100
130
130
130
160
160
160
0
5
10
15
20
25
30
Ambient Temperature, TA (°C)
Supply Voltage, VCC (V)
ICC(L1) vs. TA
ICC(L1) vs. VCC
7
6.75
7
6.8
6.6
6.4
6.2
6
6.5
6.25
6
VCC (V)
TA (°C)
3
-40
25
12
15
24
5.8
5.6
5.4
5.2
5
5.75
5.5
5.25
5
150
-50
-20
10
40
70
100
0
5
10
15
20
25
30
Ambient Temperature, TA (°C)
Supply Voltage, VCC (V)
ICC(L2) vs. TA
ICC(L2) vs. VCC
5
4.5
4
5
4.5
4
VCC (V)
TA (°C)
3
3.5
3
3.5
3
-40
25
12
15
24
150
2.5
2
2.5
2
-50
-20
10
40
70
100
0
5
10
15
20
25
30
Ambient Temperature, TA (°C)
Supply Voltage, VCC (V)
ISAFE vs. TA
ISAFE vs. VCC
2
1.75
1.5
1.25
1
2
1.75
1.5
1.25
1
VCC (V)
TA (°C)
-40
25
3
0.75
0.5
0.25
0
0.75
0.5
0.25
0
24
150
-50
-20
10
40
70
100
130
160
0
5
10
15
20
25
30
Ambient Temperature, TA (°C)
Supply Voltage, VCC (V)
9
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
APS12400
Two-Wire Hall-Effect Latch
FUNCTIONAL DESCRIPTION
Operation
Functional Safety
The APS12400 was designed in accordance with the international The APS12400 devices are two-wire unipolar planar Hall-effect
standard for automotive functional safety,
ISO 26262:2011 (pending assessment). This
product achieves an ASIL (Automotive Safety
Integrity Level) rating of ASIL A according to
the standard. The APS12400 is classified as a
SEooC (Safety Element out of Context) and
latches. The user can select a device that respond to a north or
south magnetic field. There is a choice of two output current
levels, ICC(L1) and ICC(L2), and the user can determine which cur-
rent state is applied, ICC(L) or ICC(H), when the magnetic field is
greater than BOP or less than BRP.
2
-
The difference between the magnetic operate and release points is
called the hysteresis of the device, BHYS. Hysteresis allows clean
switching of the output even in the presence of external mechani-
cal vibration and electrical noise.
can be easily integrated into safety-critical systems requiring
higher ASIL ratings that incorporate external diagnostics or use
measures such as redundancy. Safety documentation will be
provided to support and guide the integration process. Contact
your local FAE for A2-SIL™ documentation: www.allegromicro.
com/ASIL.
Figure 1 shows the potential configuration options for the
APS12400. The direction of the applied magnetic field is perpen-
dicular to the branded face for the APS12400. See Figure 2 for an
illustration.
The APS12400 has internal diagnostics to check the voltage supply
(an undervoltage lockout regulator) and to detect overtemperature
conditions. See the Diagnostics section for more information.
Latch
ꢀꢅ
ꢀCCꢁHꢂ
Staꢀꢁarꢁ
ꢂꢃtꢄꢃt
Polaritꢅ
ꢆPꢂL ꢇ 0ꢈ
ꢀCCꢁLꢂ
Y
Y
X
X
Y
A
B
C
X
0
0
ꢃꢅ
ꢃHꢄS
Z
Z
Latch
ꢀꢅ
ꢉeꢊerꢋeꢁ
ꢂꢃtꢄꢃt
Polaritꢅ
ꢆPꢂL ꢇ 1ꢈ
ꢀCCꢁHꢂ
Figure 2: Magnetic Sensing Orientations
APS12400 LH (Panel A), UA (Panel B), and UC (Panel C)
ꢀCCꢁLꢂ
0
0
ꢃꢅ
ꢃHꢄS
Figure 1: Unipolar Hall Latch Magnetic and
Output Current Polarity Options
B- indicates increasing north polarity magnetic field strength, and
B+ indicates increasing south polarity magnetic field strength.
10
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
APS12400
Two-Wire Hall-Effect Latch
Any value of ICC between the allowed ranges for ICC(H) and ICC(L)
indicates a general fault condition.
Power-On Behavior
The APS12400 has an internal voltage regulator with undervolt-
age lockout. As the device powers up, it stays in the power-on
state (POS) of ICC(H) until the supply voltage exceeds VCC(UV)DIS
After tPO, the current consumption is ICC(L) or ICC(H), according
to the magnetic field and the device configuration, as shown in
Figure 1.
+ mA
.
Fault
ICC(H) (max)
ICC(H) Range
ICC(H) (min)
Fault
Similarly, when the supply voltage decreases, the device returns
to the power on state (POS) when the supply voltage drops below
VCC(UV)EN, as shown in Figure 3.
ICC(L) (max)
ICC(L) Range
ICC(L) (min)
ISAFE
Fault
When the device powers on in the hysteresis range (less than BOP
and higher than BRP), the output corresponds to the power-on
state. In this case, the correct state is attained after the first excur-
sion beyond BOP or BRP.
Overtemp, Device Config Error ISAFE Range
Fault
0
Figure 4: Interpreting ICC for System-Level Diagnostics
Key
POS
ꢀ
Temperature Coefficient and Magnet Selection
VCC(min)
VCC(UV)DIS
VCC(UV)EN
The APS12400 allows the user to select the magnetic tempera-
ture coefficient to compensate for drifts of SmCo, NdFeB, and
ferrite magnets over temperature—as indicated in the specifica-
tions table on page 5. This compensation improves the magnetic
system performance over the entire temperature range. For
example, the magnetic field strength from ferrite decreases as the
temperature increases from 25°C to 150°C. This lower magnetic
field strength means that a lower switching threshold is required
to maintain switching at the same distance from the magnet to the
sensor. Correspondingly, higher switching thresholds are required
at cold temperatures, as low as –40°C, due to the higher magnetic
field strength from the ferrite magnet. The APS12400 compen-
sates the switching thresholds over temperature as described
above. It is recommended that system designers evaluate their
magnetic circuit over the expected operating temperature range to
ensure the magnetic switching requirements are met.
0
ꢀ
t
tPO
POS
POS
ICC(H)
Output according to
device se�ngs, based
on B
Current
Undefined
Current Undefined
ICC(Lx)
t
Figure 3: Power-On/UVLO Behavior
Diagnostic Features
When properly supplied, APS12400 always has current flowing at
a specified level: either ICC(H), ICC(L ), or ISAFE. Any current out-
side of these narrow ranges is a fault condition. If there is a short,
current increases so that ICC > ICC(H) (max), outside the valid ICC(H)
range. If there is an open, the current lowers below the ICC(L) (min),
outside the valid output current range. In this way, connectivity
issues between the ECU and the sensor can easily be detected.
For example, the typical ferrite compensation is –0.2%/°C. With
a 25°C temperature BOP switchpoint of 80 G, the switchpoint
changes nominally by –0.2%/°C × 80 × (150°C – 25°C) = –20 G
to 80 G – 20 G = 60 G at 150°C. And at –40°C, the switchpoint
changes by –0.2%/°C × 80 × (–40°C – 25°C) = 10 G to
80 G + 10 G = 90 G.
Additionally, the APS12400 has an overtemperature feature: if
the junction temperature increases beyond TSD, then the current
is reduced to ISAFE. The device current also changes to ISAFE if
there is an error in the device configuration which is checked at
power-on and after an overtemperature event.
11
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APS12400
Two-Wire Hall-Effect Latch
Applications
For the LH and UA packages, an external bypass capacitor (from
0.01 µF to 0.1 µF) should be connected (in close proximity to
the Hall element) between the supply and ground of the device
to reduce both external noise and noise generated by the chop-
per stabilization. Some applications may require additional EMC
immunity which is achieved with an enhanced protection circuit.
For example, increasing the bypass capacitor from 0.01 µF to
0.1 µF improves immunity to Powered ESD (ISO 10605) and
Direct Capacitive Coupling.
A series resistor and a 0.1 µF bypass capacitor is integrated into
the UC package, making it easy to achieve an EMC-robust design
with no external components or PCB required.
Note that the bypass capacitor selection directly affects the slew
rate. See the Electrical Characteristics table for the typical slew
rate with 0.1 µF bypass capacitor. A 0.01 µF bypass capacitor
slew rate is ten times faster.
Typical application circuits are shown in “Figure 5: Typical
Application Circuits” on page 13.
Extensive applications information for Hall-effect devices is
available in:
• Hall-Effect IC Applications Guide, AN27701
• Hall-Effect Devices: Guidelines For Designing Subassemblies
Using Hall-Effect Devices, AN27703.1
• Soldering Methods for Allegro’s Products – SMT and Through-
Hole, AN26009
•
www.allegromicro.com/ASIL
All are provided on the Allegro Web site:
www.allegromicro.com
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APS12400
Two-Wire Hall-Effect Latch
ECU
V+
VCC
RSENSE
APS12400
VSENSE
V+
CBYP
0.1 µF
VCC
APS12400
CBYP
0.1 µF
GND
VSENSE
ECU
RSENSE
GND
(A) Low-Side Sensing (LH, UA package)
VCC
(B) High-Side Sensing (LH, UA package)
ECU
RSENSE
APS12400
V+
VSENSE
68 Ω
VINT
V+
VCC
APS12400
68 Ω
VINT
0.1 µF
GND
0.1 µF
VSENSE
RSENSE
ECU
GND
(D) High-Side Sensing (UC package)
(C) Low-Side Sensing (UC package)
Figure 5: Typical Application Circuits
13
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APS12400
Two-Wire Hall-Effect Latch
Chopper Stabilization Technique
A limiting factor for switchpoint accuracy when using Hall-
effect technology is the small-signal voltage developed across
the Hall plate. This voltage is proportionally small relative to the
offset that can be produced at the output of the Hall sensor. This
makes it difficult to process the signal and maintain an accurate,
reliable output over the specified temperature and voltage range.
Chopper stabilization is a proven approach used to minimize
Hall offset.
subsequent demodulation acts as a modulation process for the
offset causing the magnetically induced signal to recover its origi-
nal spectrum at baseband while the DC offset becomes a high-
frequency signal. Then, using a low-pass filter, the signal passes
while the modulated DC offset is suppressed. Allegro’s innovative
chopper-stabilization technique uses a high-frequency clock.
The high-frequency operation allows a greater sampling rate that
produces higher accuracy, reduced jitter, and faster signal pro-
cessing. Additionally, filtering is more effective and results in a
lower noise analog signal at the sensor output. Devices such as the
APS12400 that use this approach have an extremely stable quies-
cent Hall output voltage, are immune to thermal stress, and have
precise recoverability after temperature cycling. This technique is
made possible through the use of a BiCMOS process which allows
the use of low offset and low noise amplifiers in combination with
high-density logic and sample-and-hold circuits.
The technique, dynamic quadrature offset cancellation, removes
key sources of the output drift induced by temperature and pack-
age stress. This offset reduction technique is based on a signal
modulation-demodulation process. “Figure 6: Model of Chopper
Stabilization Circuit (Dynamic Offset Cancellation)” illustrates
how it is implemented.
The undesired offset signal is separated from the magnetically
induced signal in the frequency domain through modulation. The
Regulator
Clock/Logic
Low-Pass
Filter
Hall Element
Amp
Figure 6: Model of Chopper Stabilization Circuit
(Dynamic Offset Cancellation)
14
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APS12400
Two-Wire Hall-Effect Latch
POWER DERATING
The device must be operated below the maximum junction
temperature, TJ (max). Reliable operation may require derating
supplied power and/or improving the heat dissipation properties
of the application.
17 mA, calculate the maximum allowable power level, PD (max).
First, using equation 3:
∆Tꢀ(max)ꢀ=ꢀTJ (max) – TAꢀ=ꢀ165°Cꢀ–ꢀ150°Cꢀ=ꢀ15°C
This provides the allowable increase to TJ resulting from internal
power dissipation. Then, from equation 2:
Thermal Resistance (junction to ambient), RθJA, is a figure of
merit summarizing the ability of the application and the device to
dissipate heat from the junction (die), through all paths to ambi-
ent air. RθJA is dominated by the Effective Thermal Conductivity,
K, of the printed circuit board which includes adjacent devices
and board layout. Thermal resistance from the die junction to
case, RθJC, is a relatively small component of RθJA. Ambient air
temperature, TA, and air motion are significant external factors in
determining a reliable thermal operating point.
PDꢀ(max)ꢀ=ꢀ∆Tꢀ(max)ꢀ÷ꢀRθJAꢀ=ꢀ15°Cꢀ÷ꢀ165°C/Wꢀ=ꢀ91ꢀmW
Finally, using equation 1, solve for maximum allowable VCC for
the given conditions:
V
CC (est) = PDꢀ(max)ꢀ÷ꢀICCꢀ(max)ꢀ=ꢀ91ꢀmWꢀ÷ꢀ17ꢀmAꢀ=ꢀ5.4ꢀV
The result indicates that, at TA, the application and device can
dissipate adequate amounts of heat at voltages ≤ VCC (est).
The following three equations can be used to determine operation
points for given power and thermal conditions.
If the application requires VCC > VCC(est) then RθJA must by
improved. This can be accomplished by adjusting the layout,
PCB materials, or by controlling the ambient temperature.
PD = VIN × IIN
∆Tꢀ=ꢀPD × RθJA
TJ = TAꢀ+ꢀ∆Tꢀꢀ
(1)
(2)
(3)
Determining Maximum TA
ꢀ
ꢀ
In cases where the VCC (max) level is known, and the system
designer would like to determine the maximum allowable ambi-
ent temperature TA (max), for example, in a worst-case scenario
with conditions VCC (max) = 24 V, ICC (max) = 17 mA, and RθJA
= 228°C/W for the LH package using equation 1, the largest pos-
sible amount of dissipated power is:
For example, given common conditions: TA = 25°C, VCC = 12 V,
ICC = 6 mA, and RθJA = 110°C/W for the LH package, then:
PD = VCC × ICC = 12 V × 6 mA = 72 mW
ꢀ
∆Tꢀ=ꢀPD × RθJA = 72 mW × 110°C/W = 7.92°C
TJ = TAꢀ+ꢀ∆Tꢀ=ꢀ25°Cꢀ+ꢀ7.92°Cꢀ=ꢀ32.92°C
PD = VIN × IIN
PDꢀ=ꢀ24ꢀVꢀ×ꢀ17ꢀmAꢀ=ꢀ408ꢀmW
Determining Maximum VCC
Then, by rearranging equation 3 and substituting with equation 2:
For a given ambient temperature, TA, the maximum allow-
able power dissipation as a function of VCC can be calculated.
PD (max) represents the maximum allowable power level without
exceeding TJ (max) at a selected RθJA and TA.
TA (max) = TJꢀ(max)ꢀ–ꢀΔT
TAꢀ(max)ꢀ=ꢀ165°Cꢀ–ꢀ(408ꢀmWꢀ×ꢀ228°C/W)
TAꢀ(max)ꢀ=ꢀ165°Cꢀ–ꢀ93°Cꢀ=ꢀ72°C
Example: VCC at TA = 150°C, package UA, using low-K PCB.
Finally, note that the TA (max) rating of the device is 150°C and
performance is not guaranteed above this temperature for any
power level.
Using the worst-case ratings for the device, specifically: RθJA
=
165°C/W, TJ (max) = 165°C, VCC (max) = 24 V, and ICC (max) =
15
Allegro MicroSystems, LLC
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APS12400
Two-Wire Hall-Effect Latch
Package LH, 3-Pin SOT23W
+0.12
–0.08
2.98
3
D
1.49
4ꢌꢃ4ꢌ
A
+0.020
–0.053
0.180
D
0.96
D
+0.10
2.90
+0.19
–0.06
2.40
1.91
–0.20
0.70
0.25 ꢎIN
1.00
2
1
0.55 RꢀF
0.25 BSC
0.95
PCB Laꢅout Reference ꢉieꢊ
Seating Plane
ꢁauge Plane
B
Branꢄeꢄ Face
8ꢍ 10ꢌ RꢀF
1.00 ꢃ0.13
+0.10
XXX
1
0.05
–0.05
C
Stanꢄarꢄ Branꢄing Reference ꢉieꢊ
0.95 BSC
0.40 ꢃ0.10
Line 1 ꢋ Three ꢄigit assigneꢄ branꢄ number
For reference onlꢅꢇ not for tooling use (reference DWꢁ-0000367, Reꢂ. 2).
Dimensions in millimeters.
Dimensions exclusiꢂe of molꢄ flash, gate burrs, anꢄ ꢄambar protrusions.
ꢀxact case anꢄ leaꢄ configuration at supplier ꢄiscretion ꢊithin limits shoꢊn.
Actiꢂe Area Depth, 0.28 ꢃ0.04 mm
A
B
Reference lanꢄ pattern laꢅout
All paꢄs a minimum of 0.20 mm from all aꢄꢆacent paꢄsꢇ aꢄꢆust as necessarꢅ
to meet application process reꢈuirements anꢄ PCB laꢅout tolerances
C
D
Branꢄing scale anꢄ appearance at supplier ꢄiscretion
Hall element, not to scale
16
Allegro MicroSystems, LLC
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APS12400
Two-Wire Hall-Effect Latch
Package UA, 3-Pin SIP
+0.08
–0.05
4.09
45ꢁ
B
C
ꢇ
2.05 NOꢀ
1.52 ꢂ0.05
10ꢁ
1.44 NOꢀ
ꢇ
ꢇ
ꢀolꢄ ꢇꢌector
Pin Inꢄent
+0.08
–0.05
3.02
45ꢁ
Branꢄeꢄ
Face
XXX
0.79 RꢇF
A
1.02
ꢀAX
1
Stanꢄarꢄ Branꢄing Reference ꢋieꢊ
D
Line 1: Logo A
Line 2: Three ꢄigit assigneꢄ branꢄ number
1
2
3
14.99 ꢂ0.25
+0.03
–0.06
0.41
For reference onlꢈꢉ not for tooling use (reference DWꢃ-0000404, Reꢅ. 1).
Dimensions in millimeters.
Dimensions exclusiꢅe of molꢄ flash, gate burrs, anꢄ ꢄambar protrusions.
ꢇxact case anꢄ leaꢄ configuration at supplier ꢄiscretion ꢊithin limits shoꢊn.
+0.05
–0.07
0.43
Dambar remoꢅal protrusion (6ꢆ)
ꢃate anꢄ tie bar burr area
A
ꢀ
C
D
Actiꢅe Area Depth, 0.50 ꢂ0.08 mm
Branꢄing scale anꢄ appearance at supplier ꢄiscretion
Hall element (not to scale)
ꢇ
1.27 NOꢀ
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Allegro MicroSystems, LLC
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APS12400
Two-Wire Hall-Effect Latch
Package UC, 3-Pin SIP
For Reference Only – Not for Tooling Use
(Reference DWG-0000409, Rev. 2)
Dimensions in millimeters – NOT TO SCALE
Dimensions exclusive of mold flash, gate burs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
0.ꢀ4ꢀ REF× 2
1.36 REF
+0.0ꢀ
B
0.15 REF
0.10
–0.10
4×10°
+0.06
–0.05
1.ꢀ0 0.0ꢀ
4.00
C
Detail A
R 0.20 All Corners
0.2ꢀ REF × 4
1.5
Detail A
Mold Ejector
Pin Indent
+0.06
4.00
–0.07
E
Branded
Face
4ꢀ°
A
XXXXX
Date Code
Lot Number
0.2ꢀ REF
0.30 REF
0.8ꢀ 0.0ꢀ
0.42 0.0ꢀ
1.27 REF × 2
D
Standard Branding Reference View
1
2
3
Lines 1, 2, 3: max. 5 characters per line
18.00 0.10
Line 1: 5-digit Part Number
Line 2: 4-digit Date Code
Line 3: Characters 5, 6, 7, 8 of
Assembly Lot Number
12.20 0.10
+0.07
0.2ꢀ
–0.03
Plating Included
0.38 REF
A
B
C
D
E
F
Dambar removal protrusion (12×)
Gate and tie burr area
0.25 REF
0.8ꢀ 0.0ꢀ
Active Area Depth, 0.38 0.0ꢀ mm
Branding scale and appearance at supplier discretion
Hall element (not to scale)
+0.06
1.80
–0.07
F
R 0.30 All Corners
+0.06
–0.05
Molded Lead Bar to prevent damage to leads during shipment
4.00
1.ꢀ0 0.0ꢀ
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Allegro MicroSystems, LLC
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APS12400
Two-Wire Hall-Effect Latch
REVISION HISTORY
Number
Date
Description
–
1
2
March 23, 2018
Initial release
Updated Selection Guide table (page 3), Corrected supply current values and plots (pages 6 and 9);
September 11, 2018 added UC package availability footnote to Complete Part Number Format diagram and Selection Guide
table (page 2-3)
April 1, 2019
Updated ASIL status (page 1 and 10)
Copyright 2019, Allegro MicroSystems, LLC
Allegro MicroSystems, LLC reserves the right to make, from time to time, such departures from the detail specifications as may be required to
permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that
the information being relied upon is current.
Allegro’s products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of
Allegro’s product can reasonably be expected to cause bodily harm.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, LLC assumes no responsibility for its
use; nor for any infringement of patents or other rights of third parties which may result from its use.
Copies of this document are considered uncontrolled documents.
For the latest version of this document, visit our website:
www.allegromicro.com
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