UCQ5812EPF [ALLEGRO]
BiMOS II 20-BIT SERIAL-INPUT, LATCHED SOURCE DRIVERS FOR -40 Degrees Celcious TO +85 Degrees Celcious OPERATION; 采用BiMOS II 20位串行输入，锁存源极驱动器工作在-40度Celcious至+ 85° Celcious操作
| 型号： | UCQ5812EPF |
| 厂家： | 
ALLEGRO MICROSYSTEMS |
| 描述： | BiMOS II 20-BIT SERIAL-INPUT, LATCHED SOURCE DRIVERS FOR -40 Degrees Celcious TO +85 Degrees Celcious OPERATION |
| 文件： | 总8页 (文件大小：125K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
5812-F
BiMOS II 20-BIT SERIAL-INPUT, LATCHED
SOURCE DRIVERS FOR -40°C TO +85°C OPERATION
The UCQ5812AF/EPF combine a 20-bit CMOS shift register, data
UCQ5812EPF
latches, and control circuitry with high-voltage bipolar source drivers and
active DMOS pull-downs for reduced supply current requirements. Although
designed primarily for vacuum-fluorescent displays, the high-voltage, high-
current outputs also allow them to be used in other peripheral power driver
applications.
25
5
6
7
8
OUT
2
OUT
18
The CMOS shift register and latches allow direct interfacing with
microprocessor-based systems. With a 5 V supply, they will operate to at
least 3.3 MHz. At 12 V, higher speeds are possible. Especially useful for
inter-digit blanking, the BLANKING input disables the output source drives
and turns on the DMOS sink drivers. Use with TTL may require the use of
appropriate pull-up resistors to ensure an input logic high.
24
23
22
21
20
19
9
10
11
OUT
8
A CMOS serial data output enables cascade connections in applications
requiring additional drive lines. Similar devices are available as the
UCQ5810AF/LWF (10 bits), UCQ5811A (12 bits), and UCQ5818AF/EPF
(32 bits).
OUT
12
Dwg. PP-059-1
The output source drivers are high-voltage PNP-NPN Darlingtons with a
minimum breakdown of 60 V and are capable of sourcing up to 40 mA. The
DMOS active pull-downs are capable of sinking up to 15 mA.
ABSOLUTE MAXIMUM RATINGS
at TA = 25°C
Logic Supply Voltage, VDD .....................15 V
Driver Supply Voltage, VBB ....................60 V
The UCQ5812AF is supplied in a 28-pin dual in-line plastic package with
0.600" (15.24 mm) row spacing. For surface mounting, the UCQ5812EPF is
furnished in 28-lead plastic chip carrier (quad pack) with 0.050"(1.22 mm)
centers. Copper lead-frames, reduced supply current requirements and lower
output saturation voltages, allow continuous operation, with all outputs
sourcing 25 mA, of the UCQ5812AF over the operating temperature range,
and the UCQ5812EPF up to +75°C.
Continuous Output Current Range,
IOUT ................................. -40 to +15 mA
Input Voltage Range,
VIN ........................ -0.3 V to VDD + 0.3 V
Package Power Dissipation, PD
(UCQ5812AF)........................... 3.12 W*
(UCQ5812EPF) ........................1.84 W†
Operating Temperature Range,
TA .................................. -40°C to +85°C
Storage Temperature Range,
FEATURES
■ High-Speed Source Drivers
■ 60 V Source Outputs
■ To 3.3 MHz Data Input Rate
■ Low-Output Saturation Voltages
■ Low-Power CMOS Logic and Latches
■ Active DMOS Pull-Downs
■ Reduced Supply Current
Requirements
■ Improved Replacement
for TL5812
TS ................................ -55°C to +150°C
* Derate at rate of 22 mW/°C above TA = +25°C
† Derate at rate of 15 mW/°C above TA = +25°C
Caution: Allegro CMOS devices have input static
protection but are susceptible to damage when
exposed to extremely high static electrical
charges.
Note that the UCQ5812AF (dual in-line package)
and UCQ5812EPF (PLCC package) are
electrically identical and share a common pin
number assignment.
Always order by complete part number, e.g., UCQ5812AF .
5812-F
20-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVERS
FOR -40°C TO +85°C OPERATION
UCQ5812AF
FUNCTIONAL BLOCK DIAGRAM
LOGIC
SUPPLY
LOAD
SUPPLY
LOGIC
SUPPLY
28
27
1
2
3
V
V
DD
V
BB
DD
CLOCK
SERIAL
DATA IN
SERIAL
DATA OUT
SERIAL
DATA IN
SERIAL
DATA OUT
SERIAL-PARALLEL SHIFT REGISTER
LATCHES
26 OUT
25 OUT
24 OUT
23 OUT
OUT
20
1
2
3
4
5
STROBE
4
OUT
19
5
6
BLANKING
OUT
18
MOS
OUT
17
BIPOLAR
OUT
16
22
21
20
19
18
OUT
OUT
OUT
OUT
OUT
7
8
LOAD
SUPPLY
V
BB
OUT
15
6
7
8
9
GROUND
OUT OUT OUT
OUT
N
OUT
14
9
Dwg. FP-013-1
1
2
3
10
11
12
13
14
OUT
13
OUT
OUT
12
11
TYPICAL INPUT CIRCUIT
17 OUT
10
V
DD
16
BLANKING
GROUND
BLNK
STROBE
ST
15 CLOCK
CLK
Dwg. PP-029-7
IN
Dwg. EP-010-5
TYPICAL OUTPUT DRIVER
V BB
OUTN
Dwg. No. A-14,219
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
Copyright © 1995, 2002 Allegro MicroSystems, Inc.
5812-F
20-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVERS
FOR -40°C TO +85°C OPERATION
ELECTRICAL CHARACTERISTICS over operating temperature range, at V
otherwise noted).
= 60 V (unless
BB
Limits @ VDD = 5 V Limits @ VDD = 12 V
Mln. Typ. Max. Min. Typ. Max.
Characteristic
Symbol
ICEX
Test Conditions
VOUT = 0 V, TA = +70°C
IOUT = -25 mA, VBB = 60 V
IOUT = 1 mA
Units
µA
Output Leakage Current
Output Voltage
—
-5.0
-15
—
-5.0
-15
VOUT(1)
VOUT(0)
58
58.5
—
58
58.5
—
V
—
—
2.0
3.0
—
—
—
—
V
V
I
OUT = 2 mA
VOUT = 5 V to VBB
OUT = 20 V to VBB
—
—
2.0
3.5
Output Pull-Down Current
Input Voltage
IOUT(0)
2.0
—
3.5
—
—
—
—
8.0
10.5
-0.3
—
—
13
—
—
mA
mA
V
V
VIN(1)
VIN(0)
IIN(1)
IIN(0)
VOUT(1)
VOUT(0)
fclk
3.5
-0.3
—
—
5.3
+0.8
0.5
—
12.3
+0.8
1.0
-1.0
—
—
—
V
Input Current
VIN = VDD
0.05
0.1
-0.1
µA
µA
V
VIN = 0.8 V
—
-0.05 -0.5
—
Serial Data
IOUT = -200 µA
IOUT = 200 µA
4.5
—
4.7
200
—
—
250
—
11.7 11.8
—
—
—
—
—
—
—
—
—
—
100
—
200
—
mV
MHz
µA
µA
mA
µA
ns
Maximum Clock Frequency
Supply Current
3.3*
—
IDD(1)
IDD(0)
IBB(1)
IBB(0)
tPHL
All Outputs High
100
100
1.5
300
300
4.0
100
—
200
200
1.5
500
500
4.0
100
—
All Outputs Low
—
Outputs High, No Load
Outputs Low
—
—
10
10
Blanking to Output Delay
CL = 30 pF, 50% to 50%
CL = 30 pF, 50% to 50%
CL = 30 pF, 90% to 10%
CL = 30 pF, 10% to 90%
—
2000
1000
1450
650
1000
850
650
700
tPLH
—
—
—
ns
Output Fall Time
Output Rise Time
tf
—
—
—
ns
tr
—
—
—
ns
Negative current is defined as coming out of (sourcing) the specified device pin.
* Operation at a clock frequency greater than the specified minimum value is possible but not warranteed.
www.allegromicro.com
5812-F
20-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVERS
FOR -40°C TO +85°C OPERATION
Serial Data present at the input is transferred
to the shift register on the logic “0” to logic “1”
transition of the CLOCK input pulse. On succeed-
ing CLOCK pulses, the registers shift data
information towards the SERIAL DATA OUT-
PUT. The SERIAL DATA must appear at the
input prior to the rising edge of the CLOCK input
waveform.
CLOCK
A
D
B
DATA IN
STROBE
BLANKING
OUTN
E
F
C
G
Information present at any register is trans-
ferred to the respective latch when the STROBE
is high (serial-to-parallel conversion). The latches
will continue to accept
Dwg. No. 12,649A
new data as long as the STROBE is held high.
Applications where the latches are bypassed
(STROBE tied high) will require that the
BLANKING input be high during serial data
entry.
TIMING REQUIREMENTS
(TA = +25°C,VDD = 5 V, Logic Levels are VDD and Ground)
A. Minimum Data Active Time Before Clock Pulse
(Data Set-Up Time) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 ns
B. Minimum Data Active Time After Clock Pulse
When the BLANKING input is high, the
output source drivers are disabled (OFF); the
DMOS sink drivers are ON, the information
stored in the latches is not affected by the
BLANKING input. With the BLANKING input
low, the outputs are controlled by the state of
their respective latches.
(Data Hold Time) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 ns
C. Minimum Data Pulse Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 ns
D. Minimum Clock Pulse Width. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 ns
E. Minimum Time Between Clock Activation and Strobe . . . . . . . . . . . 300 ns
F. Minimum Strobe Pulse Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 ns
G. Typical Time Between Strobe Activation and
Output Transistion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 ns
Timing is representative of a 3.3 MHz clock. Higher speeds may be attainable
with increased supply voltage; operation at high temperatures will reduce the
specified maximum clock frequency.
TRUTH TABLE
Serial
Shift Register Contents
Serial
Latch Contents
Output Contents
Data Clock
Input Input
Data Strobe
Output Input
I1 I2 I3
…
…
…
…
…
…
IN-1 IN
I1 I2 I3
…
IN-1 IN Blanking
I1 I2 I3
…
IN-1 IN
H
L
H
L
R1 R2
R1 R2
RN-2 RN-1 RN-1
RN-2 RN-1 RN-1
X
R1 R2 R3
RN-1 RN
RN
X
X
X
X
X
X
L
R1 R2 R3
P1 P2 P3
…
…
…
RN-1 RN
P1 P2 P3
PN-1 PN
PN
H
PN-1 PN
L
P1 P2 P3
…
…
PN1 PN
X
X
X
X
X
H
L
L
L
L
L
L = Low Logic Level H = High Logic Level
X = Irrelevant
P = Present State R = Previous State
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
5812-F
20-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVERS
FOR -40°C TO +85°C OPERATION
UCQ5812AF
Dimensions in Inches
(controlling dimensions)
0.015
0.008
28
15
0.700
MAX
0.580
0.485
0.600
BSC
1
2
14
0.100
BSC
3
4
0.005
MIN
0.070
0.030
1.565
1.380
0.250
MAX
0.200
0.115
0.015
MIN
0.022
0.014
Dwg. MA-003-28 in
Dimensions in Millimeters
(for reference only)
0.381
0.204
28
15
17.78
MAX
14.73
12.32
15.24
BSC
1
2
14
2.54
BSC
3
4
0.13
1.77
MIN
0.77
39.7
35.1
6.35
MAX
0.39
MIN
5.08
2.93
0.558
0.356
Dwg. MA-003-28 mm
NOTES: 1. Exact body and lead configuration at vendor’s option within limits shown.
2. Lead spacing tolerance is non-cumulative.
3. Lead thickness is measured at seating plane or below.
4. Supplied in standard sticks/tubes of 12 devices.
www.allegromicro.com
5812-F
20-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVERS
FOR -40°C TO +85°C OPERATION
UCN5812EPF
Dimensions in Inches
(controlling dimensions)
18
12
0.013
0.021
19
11
0.219
0.191
0.026
0.032
0.456
0.450
INDEX AREA
0.495
0.485
0.050
BSC
0.219
0.191
25
5
26
28
1
4
0.020
0.456
0.450
MIN
0.165
0.180
0.495
0.485
Dwg. MA-005-28A in
Dimensions in Millimeters
(for reference only)
18
12
0.331
0.533
19
11
5.56
4.85
0.812
0.661
11.58
11.43
12.57
INDEX AREA
1.27
BSC
12.32
5.56
4.85
25
5
26
28
1
4
0.51
MIN
11.582
11.430
4.57
4.20
12.57
12.32
Dwg. MA-005-28A mm
NOTES: 1. Exact body and lead configuration at vendor’s option within limits shown.
2. Lead spacing tolerance is non-cumulative.
3. Supplied in standard sticks/tubes of 38 devices or add “TR” to part number for tape and reel.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
5812-F
20-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVERS
FOR -40°C TO +85°C OPERATION
The products described here are manufactured under one or more
U.S. patents or U.S. patents pending.
Allegro MicroSystems, Inc. reserves the right to make, from time to
time, such departures from the detail specifications as may be
required to permit improvements in the performance, reliability, or
manufacturability of its products. Before placing an order, the user is
cautioned to verify that the information being relied upon is current.
Allegro products are not authorized for use as critical components
in life-support devices or systems without express written approval.
The information included herein is believed to be accurate and
reliable. However, Allegro MicroSystems, Inc. assumes no responsi-
bility for its use; nor for any infringement of patents or other rights of
third parties which may result from its use.
www.allegromicro.com
5812-F
20-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVERS
FOR -40°C TO +85°C OPERATION
POWER
INTERFACE DRIVERS
†
Function
Output Ratings*
SERIAL-INPUT LATCHED DRIVERS
Part Number
8-Bit (saturated drivers)
8-Bit
8-Bit
8-Bit
-120 mA
350 mA
350 mA
350 mA
350 mA
75 mA
120 mA
250 mA
350 mA
100 mA
50 V‡
50 V
80 V
50 V‡
80 V‡
17 V
24 V
50 V
50 V‡
50 V
5895
5821
5822
5841
5842
6275
6277
6595
6A595
6B595
8-Bit
8-Bit (constant-current LED driver)
8-Bit (constant-current LED driver)
8-Bit (DMOS drivers)
8-Bit (DMOS drivers)
8-Bit (DMOS drivers)
10-Bit (active pull-downs)
-25 mA
-25 mA
75 mA
-25 mA
60 V
60 V
17 V
60 V
5810-F and 6810
5811
12-Bit (active pull-downs)
16-Bit (constant-current LED driver)
20-Bit (active pull-downs)
6276
5812-F and 6812
32-Bit (active pull-downs)
32-Bit
32-Bit (saturated drivers)
-25 mA
100 mA
100 mA
60 V
30 V
40 V
5818-F and 6818
5833
5832
PARALLEL-INPUT LATCHED DRIVERS
4-Bit
350 mA
50 V‡
5800
8-Bit
8-Bit
-25 mA
350 mA
100 mA
250 mA
60 V
50 V‡
50 V
50 V
5815
5801
6B273
6273
8-Bit (DMOS drivers)
8-Bit (DMOS drivers)
SPECIAL-PURPOSE DEVICES
Unipolar Stepper Motor Translator/Driver
Addressable 8-Bit Decoder/DMOS Driver
Addressable 8-Bit Decoder/DMOS Driver
Addressable 8-Bit Decoder/DMOS Driver
Addressable 28-Line Decoder/Driver
1.25 A
250 mA
350 mA
100 mA
450 mA
50 V‡
5804
6259
6A259
6B259
6817
50 V
50 V‡
50 V
30 V
*
Current is maximum specified test condition, voltage is maximum rating. See specification for sustaining voltage limits.
Negative current is defined as coming out of (sourcing) the output.
†
‡
Complete part number includes additional characters to indicate operating temperature range and package style.
Internal transient-suppression diodes included for inductive-load protection.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
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