AS4C32M16SM [ALSC]
PC133-compliant;
| 型号： | AS4C32M16SM |
| 厂家： | 
ALLIANCE SEMICONDUCTOR CORPORATION |
| 描述： | PC133-compliant PC |
| 文件： | 总73页 (文件大小：3394K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
AS4C32M16SM
512M (32M x 16) bit Synchronous DRAM (SDRAM)
Confidential
Preliminary (Rev. 1.0, July /2014)
Revision History AS4C32M16SM
Revision Details
Date
Rev 1.0
Preliminary datasheet
July 2014
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AS4C32M16SM
512M (32M x 16) bit Synchronous DRAM (SDRAM)
Confidential
Preliminary (Rev. 1.0, July /2014)
Features
PC133-compliant
Configurations – 32 Meg x 16 (8 Meg x 16 x 4 banks)
Fully synchronous; all signals registered on positive edge of system clock
Internal, pipelined operation; column address can be changed every clock cycle
Internal banks for hiding row access/precharge
Programmable burst lengths: 1, 2, 4, 8, or full page
Auto precharge, includes concurrent auto precharge and auto refresh modes
Self refresh mode
Auto refresh–64ms, 8192-cycle refresh (commercial and industrial)
LVTTL-compatible inputs and outputs
Single 3.3V ±0.3V power supply
Operating temperature range
o Commercial (0˚C to +70˚C)
o Industrial (–40˚C to +85˚C)
Timing – cycle time
o 7.5ns @ CL = 3 (PC133)
o 7.5ns @ CL = 2 (PC133)
Plastic package – OCPL2
o 54-pin TSOP II (400 mil) Pb-free
All parts ROHS Compliant
Table 1. Key Timing Parameters
Clock Frequency Set up time Hold time Access time tRCD (ns) tRP (ns)
CL =3
133 MHz
CL = CAS (READ) latency
1.5ns
0.8ns
5.4ns
13.75
13.75
Table 2 – Ordering Information
Product part No
Org
Temperature
Package
AS4C32M16SM-7TCN
AS4C32M16SM-7TIN
32M x 16
32M x 16
Commercial 0°C to 70°C
Industrial -40°C to 85°C
54-pin TSOP II (400mil)
54-pin TSOP II (400mil)
Table 3 – Address Table
Parameter
32M x 16
Configuration
Refresh Count
8 Meg x 16 x 4 banks
8K
Row Addressing
Bank Addressing
Column Addressing
8K A [12:0]
4 BA [1:0]
1K A [9:0]
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AS4C32M16SM
General Description
The 512Mb SDRAM is a high-speed CMOS, dynamic random-access memory containing 536,870,912 bits. It is
internally configured as a quad-bank DRAM with a synchronous interface (all signals are registered on the positive
edge of the clock signal, CLK).Each of the x4’s 134,217,728-bit banks is organized as 8192 rows by 4096 columns by
4bits. Each of the x8’s 134,217,728-bit banks is organized as 8192 rows by 2048 columns by 8 bits. Each of the
x16’s 134,217,728-bit banks is organized as 8192 rows by 1024 columns by 16 bits.
Read and write accesses to the SDRAM are burst-oriented; accesses start at a selected location and continue for a
programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE
command, which is then followed by a READ or WRITE command. The address bits registered coincident with the
ACTIVE command are used to select the bank and row to be accessed (BA[1:0] select the bank; A[12:0] select the
row). The address bits registered coincident with the READ or WRITE command are used to select the starting
column location for the burst access.
The SDRAM provides for programmable read or write burst lengths (BL) of 1, 2, 4, or 8locations, or the full page,
with a burst terminate option. An auto precharge function may be enabled to provide a self-timed row precharge
that is initiated at the end of the burst sequence.
The 512Mb SDRAM uses an internal pipelined architecture to achieve high-speed operation. This architecture is
compatible with the 2n rule of prefetch architectures, but it also allows the column address to be changed on
every clock cycle to achieve a high-speed, fully random access. Precharging one bank while accessing one of the
other three banks will hide the PRECHARGE cycles and provide seamless, high-speed, random-access operation.
The 512Mb SDRAM is designed to operate in 3.3V memory systems. An auto refresh mode is provided, along with
a power-saving, power-down mode. All inputs and out-puts are LVTTL-compatible.
SDRAMs offer substantial advances in DRAM operating performance, including the ability to synchronously burst
data at a high data rate with automatic column-address generation, the ability to interleave between internal
banks to hide precharge time, and the capability to randomly change column addresses on each clock cycle during
a burst access.
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AS4C32M16SM
Functional Block Diagrams
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AS4C32M16SM
Pin and Ball Assignments and Descriptions
Figure 4: 54-Pin TSOP (Top View)
Notes:
1. The # symbol indicates that the signal is active LOW
2. Package may or may not be assembled with a location notch.
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Table 4: Pin and Ball Descriptions
Symbol
Type
Description
CLK
Input
Clock: CLK is driven by the system clock. All SDRAM input signals are
sampled on the positive edge of CLK. CLK also increments the internal burst
counter and controls the output registers.
CKE
Input
Clock enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal.
Deactivating the clock provides precharge power-down and SELF REFRESH
operation (all banks idle), active power-down (row active in any bank), or
CLOCK SUSPEND operation (burst/access in progress). CKE is synchronous
except after the device enters power-down and self-refresh modes, where
CKE becomes asynchronous until after exiting the same mode. The input
buffers, including CLK, are disabled during power-down and self-refresh
modes, providing low stand by power. CKE may be tied HIGH.
Chip select: CS# enables (registered LOW) and disables (registered HIGH) the
command decoder. All commands are masked when CS# is registered HIGH,
but READ/WRITE bursts already in progress will continue, and DQM
operation will retain its DQ mask capability while CS# is HIGH. CS# provides
for external bank selection on systems with multiple banks. CS# is
considered part of the command code.
CS#
Input
CAS#, RAS#,WE#
Input
Input
Command inputs: RAS#, CAS#, and WE# (along with CS#) define the
command being entered.
x16:DQML,
DQMHLDQM,
UDQM(54-ball)
Input/output mask: DQM is an input mask signal for write accesses and an
output enable signal for read accesses. Input data is masked when DQM is
sampled HIGH during a WRITE cycle. The output buffers are placed in a High-
Z state (two-clock latency) when DQM is sampled HIGH during a READ cycle.
On the x4 and x8, DQML (pin 15) is a NC and DQMH is DQM. On the x16,
DQML corresponds to DQ[7:0], and DQMH corresponds to DQ[15:8]. DQML
and DQMH are considered same state when referenced as DQM.
Bank address input(s): BA[1:0] defines to which bank the ACTIVE, READ,
WRITE, or PRECHARGE command is being applied.
Address inputs: A[12:0] are sampled during the ACTIVE command (row
address A[12:0]) and READ or WRITE command (column address A[9:0], A11,
and A12 for x4; A[9:0] and A11 for x8;A[9:0] for x16; with A10 defining auto
precharge) to select one location out of the memory array in the respective
bank. A10 is sampled during a PRECHARGE command to determine if all
banks are to be precharged (A10 HIGH) or bank selected by A10 (LOW). The
address inputs also provide the op-code during a LOAD MODE REGISTER
command.
BA[1:0]
A[12:0]
Input
Input
x16:DQ[15:0]
I/O
Data input/output: Data bus for x16 (pins 4, 7, 10, 13, 15, 42, 45, 48, and 51
are NC for x8; and pins 2, 4, 7, 8, 10, 13, 15, 42, 45, 47, 48, 51, and 53 are NC
for x4).
VDDQ
VSSQ
VDD
VSS
Supply DQ power: DQ power to the die for improved noise immunity.
Supply DQ ground: DQ ground to the die for improved noise immunity.
Supply Power supply: +3.3V ±0.3V.
Supply Ground.
NC
-
These should be left unconnected.
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AS4C32M16SM
Package Dimensions
Figure 5: 54-Pin Plastic TSOP (400 mil) – Package Codes T
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AS4C32M16SM
Temperature and Thermal Impedance
It is imperative that the SDRAM device’s temperature specifications, shown in Table 6(page 14), be maintained to
ensure the junction temperature is in the proper operating range to meet data sheet specifications. An important
step in maintaining the proper junction temperature is using the device’s thermal impedances correctly. The
thermal impedances are listed in Table 6 (page 14) for the applicable die revision and packages being made
available. These thermal impedance values vary according to the density, package, and particular design used for
each device.
Incorrectly using thermal impedances can produce significant errors. To ensure the compatibility of current and
future de-signs, contact Alliance Memory Applications Engineering to confirm thermal impedance values.
The SDRAM device’s safe junction temperature range can be maintained when the TC specification is not exceeded.
In applications where the device’s ambient temperature is too high, use of forced air and/or heat sinks may be
required to satisfy the case temperature specifications.
Table 5: Temperature Limits
Parameter
Symbol Min
Max Unit
Notes
Operating case temperature
Commercial Tc
0
-40
0
-40
0
80
90
85
95
70
85
°C
°C
°C
1,2,3,4
Industrial
Commercial
Industrial
Junction temperature
Ambient temperature
Peak reflow temperature
Notes:
T
J
3
Commercial Tᴀ
Industrial
3,5
-40
-
T
PEAK
260 °C
1. MAX operating case temperature, TC, is measured in the center of the package on the top side of the device, as shown in
Figure 6 (page 14).
2. Device functionality is not guaranteed if the device exceeds maximum TC during operation.
3. All temperature specifications must be satisfied.
4. The case temperature should be measured by gluing a thermocouple to the top-center of the component. This should be
done with a 1mm bead of conductive epoxy, as de-fined by the JEDEC EIA/JESD51 standards. Take care to ensure that the
thermocouple bead is touching the case.
5. Operating ambient temperature surrounding the package.
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Table 6: Thermal Impedance Simulated Values
Θ JA (°C/W)
Airflow =
Θ JA (°C/W)
Airflow =
Θ JA (°C/W)
Airflow =
Die Revision
Θ
JB (°C/W) Θ JC (°C/W)
Package
Substrate
0m/s
1m/s
2m/s
Rev D
54-pin TSOP
2-layer
4-layer
62.6
39.2
48.4
32.3
44.2
30.6
19.2
19.3
6.7
Notes: 1. For designs expected to last beyond the die revision listed, contact Alliance Memory
Applications Engineering to confirm thermal impedance values.
2. Thermal resistance data is sampled from multiple lots, and the values should be viewed as
typical.
3. These are estimates; actual results may vary.
Figure 6: Example: Temperature Test Point Location, 54-Pin TSOP (Top View)
22.22mm
11.11mm
Test point
10.16mm
5.08mm
Note: 1. Package may or may not be assembled with a location notch.
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Electrical Specifications
Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and
functional operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect reliability.
Table 7: Absolute Maximum Ratings
Voltage/Temperature
Symbol
Min Max
Unit
Notes
V /V
Voltage on V /V
DD DDQ
supply relative to V
DD
DDQ
–1
–1
+4.6
+4.6
V
1
SS
V
Voltage on inputs, NC, or I/O balls relative to V
IN
SS
T
STG
Storage temperature (plastic)
Power dissipation
–55
+155
1
°C
W
–
–
Note: 1. V
and V
must be within 300mV of each other at all times. V
must not exceed V
.
DD
DD
DDQ
DDQ
Table 8: DC Electrical Characteristics and Operating Conditions
Notes 1–3 apply to all parameters and conditions; VDD/VDDQ = +3.3V ±0.3V
Parameter/Condition
Symbol
Min
Max
Unit
Notes
V , V
DD
DDQ
Supply voltage
3
2
3.6
V
V
V
V
V
V
VIH
V
+ 0.3
Input high voltage: Logic 1; All inputs
Input low voltage: Logic 0; All inputs
4
4
DD
V IL
–0.3
2.4
–
+0.8
–
Output high voltage: I
Output low voltage: I
= –4mA
VOH
OUT
= 4mA
OL
0.4
OUT
I
μ A
Input leakage current:
–5
5
L
Any input 0V ≤ V ≤ V
(All other balls not under test = 0V)
IN DD
I
Output leakage current: DQ are disabled; 0V ≤ V
≤ V
DDQ
OZ
μ A
˚C
–5
0
–5
OUT
T
A
Operating temperature:
Commercial
Industrial
+70
+85
T
A
–40
˚C
Notes:
1. All voltages referenced to VSS.
2. The minimum specifications are used only to indicate cycle time at which proper operation over the full
temperature range is ensured; (0°C ≤ TA ≤ +70°C (commercial), –40°C ≤ TA ≤ +85°C (industrial), and –40°C
≤ TA ≤ +105°C (automotive)).
3. An initial pause of 100μs is required after power-up, followed by two AUTO REFRESH commands, before
proper device operation is ensured. (VDD and VDDQ must be powered up simultaneously. VSS and VSSQ must
be at same potential.) The two AUTO REFRESH command wake-ups should be repeated any time the tREF
refresh requirement is exceeded.
4. VIH overshoot: VIH, max = VDDQ + 2V for a pulse width ≤ 3ns, and the pulse width cannot be greater than one-
third of the cycle rate. VIL undershoot: VIL, min = –2V for a pulse width ≤3ns.
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Table 9: Capacitance
Note 1 applies to all parameters and conditions
Notes: 1. this parameter is sampled. V , V
DD DDQ
= +3.3V; f = 1 MHz, T = 25°C; pin under test
A
biased at 1.4V.
2. PC100 specifies a maximum of 4pF.
3. PC100 specifies a maximum of 5pF.
4. PC100 specifies a maximum of 6.5pF.
5. PC133 specifies a minimum of 2.5pF.
6. PC133 specifies a minimum of 2.5pF.
7. PC133 specifies a minimum of 3.0pF.
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AS4C32M16SM
Electrical Specifications – I
Parameters
DD
Table 10: I
Specifications and Conditions (-7)
DD
Notes 1–5 apply to all parameters and conditions; V /V
= +3.3V ±0.3V
DD DDQ
Max
-7
Parameter/Condition
Symbol
Unit
Notes
I
t
t
Operating current: Active mode; Burst = 2; READ or WRITE; RC = RC
(MIN)
DD1
110
mA
6, 9, 10,
13
I
IDD2
Standby current: Power-down mode; All banks idle; CKE = LOW
3.5
45
mA
mA
13
6, 8, 10,
13
Standby current: Active mode; CKE = HIGH; CS# = HIGH; All banks active
DD3
t
after RCD met; No accesses in progress
I
DD4
Operating current: Burst mode; Page burst; READ or WRITE; All banks active
115
mA
6, 9, 10,
13
I
t
t
t
IDD5
RFC = RFC (MIN)
Auto refresh current: CKE = HIGH; CS# = HIGH
255
6
mA
mA
mA
mA
6, 8, 9, 10,
13, 14
IDD6
RFC = 7.813μs
IDD7
Self refresh current: CKE ≤ 0.2V
Standard
6
DD7
Low power (L)
3
7
Notes: 1. all voltages referenced to VSS.
2. The minimum specifications are used only to indicate cycle time at which proper operation
over the full temperature range is ensured; (0°C ≤ TA ≤ +70°C (commercial), –40°C ≤ TA ≤
+85°C (industrial), and –40°C ≤ TA ≤ +105°C (automotive)).
3. An initial pause of 100μs is required after power-up, followed by two AUTO REFRESH
commands, before proper device operation is ensured. (VDD and VDDQ must be powered up
simultaneously. VSS and VSSQ must be at same potential.) The two AUTO REFRESH
command wake-ups should be repeated any time the tREF refresh requirement is
exceeded.
4. AC operating and IDD test conditions have VIL = 0V and VIH = 3.0V using a measurement
reference level of 1.5V. If the input transition time is longer than 1ns, then the timing is
measured from VIL, max and VIH, min and no longer from the 1.5V midpoint. CLK should
always be 1.5V referenced to crossover.
5. IDD specifications are tested after the device is properly initialized.
6. IDD is dependent on output loading and cycle rates. Specified values are obtained with
minimum cycle time and the outputs open.
7. Enables on-chip refresh and address counters.
8. Other input signals are allowed to transition no more than once every two clocks and
are otherwise at valid VIH or VIL levels.
9. The IDD current will increase or decrease proportionally according to the amount of
frequency alteration for the test condition.
10. Address transitions average one transition every two clocks.
11. PC100 specifies a maximum of 4pF.
12. PC100 specifies a maximum of 5pF.
13. For -7, CL = 3 and tCK = 7.5ns, CL = 2 and tCK = 7.5ns.
t
14. CKE is HIGH during REFRESH command period RFC (MIN) else CKE is LOW. The IDD6 limit is
actually a nominal value and does not result in a fail value.
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Electrical Specifications – AC Operating Conditions
Table 11: Electrical Characteristics and Recommended AC Operating Conditions (-7)
Notes 1, 2, 4, 5, 7, and 20 apply to all parameters and conditions
-7
Parameter
Symbol
Min
Max
Unit
Notes
t
AC(3)
Access time from CLK (positive edge)
CL = 3
CL = 2
–
5.4
ns
18
t
AC(2)
–
6
t
AH
Address hold time
Address setup time
CLK high-level width
CLK low-level width
Clock cycle time
0.8
1.5
2.5
2.5
7.5
10
0.8
1.5
0.8
1.5
0.8
1.5
–
–
ns
ns
ns
ns
ns
t
AS
–
t
CH
–
t
CL
–
t
CK(3)
CL = 3
CL = 2
–
14
21
t
CK(2)
–
t
CKH
CKE hold time
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
ns
t
CKS
CKE setup time
–
t
CMH
CS#, RAS#, CAS#, WE#, DQM hold time
CS#, RAS#, CAS#, WE#, DQM setup time
Data-in hold time
–
t
CMS
–
t
DH
–
t
DS
Data-in setup time
–
t
HZ(3)
Data-out High-Z time
CL = 3
CL = 2
5.4
6
t
HZ(2)
–
6
t
LZ
Data-out Low-Z time
1
–
t
OH
Data-out hold time (load)
Data-out hold time (no load)
ACTIVE-to-PRECHARGE command
ACTIVE-to-ACTIVE command period
ACTIVE-to-READ or WRITE delay
Refresh period (8192 rows)
AUTO REFRESH period
2.7
1.8
44
66
20
–
–
t
OHn
–
19
23
t
RAS
120,000
t
RC
–
–
t
RCD
t
REF
64
–
t
RFC
66
20
15
0.3
t
RP
PRECHARGE command period
ACTIVE bank a to ACTIVE bank b command
Transition time
–
t
t
RRD
CK
–
t
t
1.2
–
ns
ns
3
WR
WRITE recovery time
1 CLK +
7.5ns
15
15
75
–
–
16
12
t
XSR
Exit SELF REFRESH-to-ACTIVE command
ns
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Table 12: AC Functional Characteristics (-7)
Notes 1–5 and note 7 apply to all parameters and conditions
-7
Parameter
Symbol
Unit
Notes
t
t
BDL
CK
Last data-in to burst STOP command
1
1
1
1
5
2
0
0
2
0
2
1
2
3
2
11
11
t
t
CCD
CK
READ/WRITE command to READ/WRITE command
Last data-in to new READ/WRITE command
CKE to clock disable or power-down entry mode
Data-in to ACTIVE command
t
t
CDL
CK
11
t
t
CKED
CK
8
t
t
DAL
CK
9, 13
10, 13
11
t
t
DPL
CK
Data-in to PRECHARGE command
t
t
DQD
CK
DQM to input data delay
t
t
DQM
CK
DQM to data mask during WRITEs
11
t
t
DQZ
CK
DQM to data High-Z during READs
11
t
t
DWD
CK
WRITE command to input data delay
11
t
t
MRD
CK
LOAD MODE REGISTER command to ACTIVE or REFRESH command
CKE to clock enable or power-down exit setup mode
Last data-in to PRECHARGE command
17
t
t
PED
CK
8
t
t
RDL
CK
10, 13
11
t
t
ROH(3)
CK
Data-out High-Z from PRECHARGE command
CL = 3
CL = 2
t
t
ROH(2)
CK
11
Notes:
1. The minimum specifications are used only to indicate cycle time at which proper operation over the full temperature
range (0˚C ≤ T ≤ +70˚C commercial temperature, -40˚C ≤ T ≤ +85˚C industrial temperature, and -40˚C ≤
A
A
T
A
≤ +105˚C automotive temperature) is ensured.
2. An initial pause of 100μ s is required after power-up, followed by two AUTO REFRESH commands, before proper
device operation is ensured. (V
and V
must be powered up simultaneously. V
and V
must be at
SSQ
DD
DDQ
SS
t
same potential.) The two AUTO REFRESH command wake-ups should be repeated any time the REF refresh
requirement is exceeded.
3. AC characteristics assume T = 1ns.
t
4. In addition to meeting the transition rate specification, the clock and CKE must transit between V and V (or
IH IL
between V and V ) in a monotonic manner.
IL IH
5. Outputs measured at 1.5V with equivalent load:
Q
50pF
t
6. HZ defines the time at which the output achieves the open circuit condition; it is not a reference to V
or V . The last
OL
OH
t
valid data element will meet OH before going High-Z.
7. AC operating and I
test conditions have V = 0V and V = 3.0V using a measurement reference level of 1.5V. If the
IL IH
DD
input transition time is longer than 1ns, then the timing is measured from V
and V
and no longer from the
IL, max
IH, min
1.5V midpoint. CLK should al-ways be 1.5V referenced to crossover.
t
8. Timing is specified by CKS. Clock(s) specified as a reference only at minimum cycle rate.
t
t
9. Timing is specified by WR plus RP. Clock(s) specified as a reference only at minimum cycle rate.
t
10. Timing is specified by WR.
11. Required clocks are specified by JEDEC functionality and are not dependent on any timing parameter.
12. CLK must be toggled a minimum of two times during this period.
t
13. Based on CK = 7.5ns for -7
14. The clock frequency must remain constant (stable clock is defined as a signal cycling within timing constraints specified
for the clock pin) during access or precharge states (READ, WRITE, including tWR, and PRECHARGE commands). CKE
may be used to reduce the data rate.
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t
15. Auto precharge mode only. The precharge timing budget ( RP) begins at 7ns for –CL2 and 7.5ns for -7 CL3 after the
first clock delay and after the last WRITE is executed.
16. Precharge mode only.
17. JEDEC and PC100 specify three clocks.
t
18. AC for -75/-7E at CL = 3 with no load is 4.6ns and is guaranteed by design
19. Parameter guaranteed by design.
20. PC100 specifies a maximum of 6.5pF.
t
21. For operating frequencies ≤ 45 MHz, CKS = 3.0ns.
t
22. Auto precharge mode only. The precharge timing budget ( RP) begins 6ns for -6A after the first clock delay, after the
last WRITE is executed. May not exceed limit set for pre-charge mode.
23. DRAM devices should be evenly addressed when being accessed. Disproportionate accesses to a particular row
address may result in reduction of the product lifetime.
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Functional Description
In general, 512Mb SDRAM devices (32 Meg x 4 x 4 banks) are quad-bank DRAM
that operate at 3.3V and include a synchronous interface. All signals are registered
on the positive edge of the clock signal, CLK. Each of the x16’s 134,217,728-bit
banks is organized as 8192 rows by 1024 columns by 16 bits.
Read and write accesses to the SDRAM are burst-oriented; accesses start at a
selected location and continue for a programmed number of locations in a
programmed sequence. Accesses begin with the registration of an ACTIVE
command, followed by a READ or WRITE command. The address bits registered
coincident with the ACTIVE command are used to select the bank and row to be
accessed (BA0 and BA1 select the bank; A [12:0] select the row). The address bits
(x4: A [9:0], A11, A12; x8: A [9:0], A11; x16: A [9:0]) registered coincident with the
READ or WRITE command are used to select the starting column location for the
burst access.
Prior to normal operation, the SDRAM must be initialized. The following sections
pro-vide detailed information covering device initialization, register definition,
command descriptions, and device operation.
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Commands
The following table provides a quick reference of available commands, followed by a
written description of each command. Additional Truth Tables (Table 14 (page 28), Table
15 (page 30), and Table 16 (page 32)) provide current state/next state information.
Table 13: Truth Table – Commands and DQM Operation
Note 1 applies to all parameters and conditions
Name (Function)
CS# RAS# CAS# WE# DQM
ADDR
X
DQ
X
Notes
COMMAND INHIBIT (NOP)
H
L
X
H
L
X
H
H
L
X
H
H
H
L
X
X
NO OPERATION (NOP)
X
X
ACTIVE (select bank and activate row)
READ (select bank and column, and start READ burst)
WRITE (select bank and column, and start WRITE burst)
BURST TERMINATE
L
X
Bank/row
Bank/col
X
2
3
L
H
H
H
L
L/H
L/H
X
X
L
L
Bank/col Valid
3
L
H
H
L
L
X
Active
X
4
PRECHARGE (Deactivate row in bank or banks)
AUTO REFRESH or SELF REFRESH (enter self refresh mode)
LOAD MODE REGISTER
L
L
X
Code
5
L
L
H
L
X
X
X
6, 7
8
L
L
L
X
Op-code
X
Write enable/output enable
X
X
X
X
X
X
X
X
L
X
X
Active
High-Z
9
Write inhibit/output High-Z
H
9
Notes: 1. CKE is HIGH for all commands shown except SELF REFRESH.
2. A[0:n] provide row address (where An is the most significant address bit), BA0
and BA1 determine which bank is made active.
3. A[0:i] provide column address (where i = the most significant column address
for a given device configuration). A10 HIGH enables the auto precharge feature
(nonpersistent), while A10 LOW disables the auto precharge feature. BA0 and
BA1 determine which bank is being read from or written to.
4. The purpose of the BURST TERMINATE command is to stop a data burst, thus
the command could coincide with data on the bus. However, the DQ column
reads a “Don’t Care” state to illustrate that the BURST TERMINATE command
can occur when there is no data present.
5. A10 LOW: BA0, BA1 determine the bank being precharged. A10 HIGH: all
banks pre-charged and BA0, BA1 are “Don’t Care.”
6. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
7. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t
Care” except for CKE.
8. A[11:0] define the op-code written to the mode register.
9. Activates or deactivates the DQ during WRITEs (zero-clock delay) and READs
(two-clock delay).
COMMAND INHIBIT
The COMMAND INHIBIT function prevents new commands from being executed by
the device, regardless of whether the CLK signal is enabled. The device is effectively
de-selected. Operations already in progress are not affected.
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NO OPERATION (NOP)
The NO OPERATION (NOP) command is used to perform a NOP to the selected device
(CS# is LOW). This prevents unwanted commands from being registered during idle or wait
states. Operations already in progress are not affected.
LOAD MODE REGISTER (LMR)
The mode registers are loaded via inputs A[n:0] (where An is the most significant ad-dress
term), BA0, and BA1(see Mode Register (page 35)). The LOAD MODE REGISTER
command can only be issued when all banks are idle and a subsequent executable command
t
cannot be issued until MRD is met.
ACTIVE
The ACTIVE command is used to activate a row in a particular bank for a subsequent access.
The value on the BA0, BA1 inputs selects the bank, and the address provided selects the row.
This row remains active for accesses until a PRECHARGE command is is-sued to that bank. A
PRECHARGE command must be issued before opening a different row in the same bank.
Figure 7: ACTIVE Command
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READ
The READ command is used to initiate a burst read access to an active row. The values on the
BA0 and BA1 inputs select the bank; the address provided selects the starting column location.
The value on input A10 determines whether auto precharge is used. If au-to precharge is
selected, the row being accessed is precharged at the end of the READ burst; if auto precharge
is not selected, the row remains open for subsequent accesses. Read data appears on the DQ
subject to the logic level on the DQM inputs two clocks earlier. If a given DQM signal was
registered HIGH, the corresponding DQ will be High-Z two clocks later; if the DQM signal
was registered LOW, the DQ will provide valid data.
Figure 8: READ Command
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WRITE
The WRITE command is used to initiate a burst write access to an active row. The values on
the BA0 and BA1 inputs select the bank; the address provided selects the starting column
location. The value on input A10 determines whether auto precharge is used. If au-to precharge
is selected, the row being accessed is precharged at the end of the write burst; if auto precharge
is not selected, the row remains open for subsequent accesses. Input data appearing on the DQ
is written to the memory array, subject to the DQM in-put logic level appearing coincident with
the data. If a given DQM signal is registered LOW, the corresponding data is written to
memory; if the DQM signal is registered HIGH, the corresponding data inputs are ignored and
a WRITE is not executed to that byte/column location.
Figure 9: WRITE Command
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PRECHARGE
The PRECHARGE command is used to deactivate the open row in a particular bank or the
open row in all banks. The bank(s) will be available for a subsequent row access a specified
t
time ( RP) after the PRECHARGE command is issued. Input A10 determines whether one or
all banks are to be precharged, and in the case where only one bank is precharged, inputs BA0
and BA1 select the bank. Otherwise BA0 and BA1 are treated as “Don’t Care.” After a bank
has been precharged, it is in the idle state and must be activated prior to any READ or
WRITE commands are issued to that bank.
Figure 10: PRECHARGE Command
BURST TERMINATE
The BURST TERMINATE command is used to truncate either fixed-length or continuous page bursts. The most recently
registered READ or WRITE command prior to the BURST TERMINATE command is truncated.
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REFRESH
AUTO REFRESH
AUTO REFRESH is used during normal operation of the SDRAM and is analogous to CAS#-
BEFORE-RAS# (CBR) refresh in conventional DRAMs. This command is non-persistent, so it
must be issued each time a refresh is required. All active banks must be pre-charged prior to
issuing an AUTO REFRESH command. The AUTO REFRESH command should not be issued
t
until the minimum RP has been met after the PRECHARGE command, as shown in
Bank/Row Activation (page 40).
The addressing is generated by the internal refresh controller. This makes the address bits a
“Don’t Care” during an AUTO REFRESH command. Regardless of device width, the 512Mb
SDRAM requires 8192 AUTO REFRESH cycles every 64ms (commercial and industrial).
Providing a distributed AUTO REFRESH command every 7.813μ s (commercial and
industrial) will meet the refresh requirement and ensure that each row is refreshed.
Alternatively, 8192 AUTO REFRESH commands can be issued in a burst at the minimum
t
cycle rate ( RFC), once every 64ms (commercial and industrial).
SELF REFRESH
The SELF REFRESH command can be used to retain data in the SDRAM, even if the rest of
the system is powered-down. When in the self-refresh mode, the SDRAM retains data without
external clocking.
The SELF REFRESH command is initiated like an AUTO REFRESH command except CKE
is disabled (LOW). After the SELF REFRESH command is registered, all the inputs to the
SDRAM become a “Don’t Care” with the exception of CKE, which must remain LOW.
After self refresh mode is engaged, the SDRAM provides its own internal clocking, causing it
to perform its own AUTO REFRESH cycles. The SDRAM must remain in self re-fresh mode
t
for a minimum period equal to RAS and may remain in self refresh mode for an indefinite
period beyond that.
The procedure for exiting self refresh requires a sequence of commands. First, CLK must be
stable (stable clock is defined as a signal cycling within timing constraints specified for the
clock pin) prior to CKE going back HIGH. After CKE is HIGH, the SDRAM must have NOP
t
commands issued (a minimum of two clocks) for XSR because time is required for the
completion of any internal refresh in progress.
Upon exiting the self-refresh mode, AUTO REFRESH commands must be issued at the
specified intervals, as both SELF REFRESH and AUTO REFRESH utilize the row refresh
counter.
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Truth Tables
Table 14: Truth Table – Current State Bank n, Command to Bank n
Notes 1–6 apply to all parameters and conditions
Current State
CS# RAS# CAS# WE# Command/Action
Notes
Any
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
H
L
X
H
H
L
X
H
H
H
L
COMMAND INHIBIT (NOP/continue previous operation)
NO OPERATION (NOP/continue previous operation)
ACTIVE (select and activate row)
Idle
L
AUTO REFRESH
7
7
L
L
LOAD MODE REGISTER
L
H
L
L
PRECHARGE
8
Row active
H
H
L
H
L
READ (select column and start READ burst)
WRITE (select column and start WRITE burst)
PRECHARGE (deactivate row in bank or banks)
READ (select column and start new READ burst)
WRITE (select column and start WRITE burst)
PRECHARGE (truncate READ burst, start PRECHARGE)
BURST TERMINATE
9
L
9
H
L
L
10
9
Read
H
H
L
H
L
(auto precharge disabled)
L
9
H
H
L
L
10
11
9
H
H
H
L
L
Write
H
L
READ (select column and start READ burst)
WRITE (select column and start new WRITE burst)
PRECHARGE (truncate WRITE burst, start PRECHARGE)
BURST TERMINATE
(auto precharge disabled)
L
9
H
H
L
10
11
H
L
Notes: 1. This table applies when CKE
t
was HIGH and CKE is HIGH (see Table 16 (page
n
n-1
32)) and after XSR has been met (if the previous state was self refresh).
2. This table is bank-specific, except where noted (for example, the current state is for a
specific bank and the commands shown can be issued to that bank when in that state).
Exceptions are covered below.
3. Current state definitions:
t
Idle: The bank has been precharged, and RP has been met.
t
Row active: A row in the bank has been activated, and RCD has been met. No data
bursts/accesses and no register accesses are in progress.
Read: A READ burst has been initiated, with auto precharge disabled, and has not yet
terminated or been terminated.
Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet
terminated or been terminated.
4. The following states must not be interrupted by a command issued to the same bank.
COMMAND INHIBIT or NOP commands, or supported commands to the other bank
should be issued on any clock edge occurring during these states. Supported
commands to any other bank are determined by the bank’s current state and the
conditions described in this and the following table.
t
Precharging: Starts with registration of a PRECHARGE command and ends when RP
t
is met. After RP is met, the bank will be in the idle state.
t
t
Row activating: Starts with registration of an ACTIVE command and ends when RCD is met. After RCD is met, the bank
will be in the row active state.
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Read with auto precharge enabled: Starts with registration of a READ command with auto precharge enabled
t
t
and ends when RP has been met. After RP is met, the bank will be in the idle state.
Write with auto precharge enabled: Starts with registration of a WRITE command with auto precharge enabled and
t
t
ends when RP has been met. After RP is met, the bank will be in the idle state.
5. The following states must not be interrupted by any executable command; COMMAND INHIBIT or NOP commands
must be applied on each positive clock edge during these states.
t
t
Refreshing: Starts with registration of an AUTO REFRESH command and ends when RFC is met. After RFC is
met, the device will be in the all banks idle state.
t
Accessing mode register: Starts with registration of a LOAD MODE REGISTER command and ends when MRD
t
has been met. After MRD is met, the device will be in the all banks idle state.
t
t
Precharging all: Starts with registration of a PRECHARGE ALL command and ends when RP is met. After RP is
met, all banks will be in the idle state.
6. All states and sequences not shown are illegal or reserved.
7. Not bank specific; requires that all banks are idle.
8. Does not affect the state of the bank and acts as a NOP to that bank.
9. READs or WRITEs listed in the Command/Action column include READs or WRITEs with auto precharge enabled
and READs or WRITEs with auto precharge disabled.
10. May or may not be bank specific; if all banks need to be precharged, each must be in a valid state for precharging.
11. Not bank-specific; BURST TERMINATE affects the most recent READ or WRITE burst, regardless of bank.
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Table 15: Truth Table – Current State Bank n, Command to Bank m
Notes 1–6 apply to all parameters and conditions
Current State
CS# RAS# CAS# WE# Command/Action
Notes
Any
H
L
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
H
X
L
X
H
X
H
L
X
H
X
H
H
L
COMMAND INHIBIT (NOP/continue previous operation)
NO OPERATION (NOP/continue previous operation)
Any command otherwise supported for bank m
ACTIVE (select and activate row)
Idle
Row activating, active, or
precharging
H
H
L
READ (select column and start READ burst)
WRITE (select column and start WRITE burst)
PRECHARGE
7
7
L
H
H
L
L
Read
L
H
H
L
ACTIVE (select and activate row)
(auto precharge disabled)
H
H
L
READ (select column and start new READ burst)
WRITE (select column and start WRITE burst)
PRECHARGE
7, 10
7, 11
9
L
H
H
L
L
Write
L
H
H
L
ACTIVE (select and activate row)
(auto precharge disabled)
H
H
L
READ (select column and start READ burst)
WRITE (select column and start new WRITE burst)
PRECHARGE
7, 12
7, 13
9
L
H
H
L
L
Read
(with auto precharge)
L
H
H
L
ACTIVE (select and activate row)
H
H
L
READ (select column and start new READ burst)
WRITE (select column and start WRITE burst)
PRECHARGE
7, 8, 14
7, 8, 15
9
L
H
H
L
L
Write
(with auto precharge)
L
H
H
L
ACTIVE (select and activate row)
H
H
L
READ (select column and start READ burst)
WRITE (select column and start new WRITE burst)
PRECHARGE
7, 8, 16
7, 8, 17
9
L
H
L
Notes: 1. This table applies when CKE
t
was HIGH and CKE is HIGH (Table 16 (page 32)),
n
n-1
and after XSR has been met (if the previous state was self refresh).
2. This table describes alternate bank operation, except where noted; for example, the cur-
rent state is for bank n and the commands shown can be issued to bank m, assuming
that bank m is in such a state that the given command is supported. Exceptions are
covered below.
3. Current state definitions:
t
Idle: The bank has been precharged, and RP has been met.
t
Row active: A row in the bank has been activated, and RCD has been met. No data
bursts/accesses and no register accesses are in progress.
Read: A READ burst has been initiated, with auto precharge disabled, and has not yet
terminated or been terminated.
Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet
terminated or been terminated.
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Read with auto precharge enabled: Starts with registration of a READ command with auto precharge enabled
t
t
and ends when RP has been met. After RP is met, the bank will be in the idle state.
Write with auto precharge enabled: Starts with registration of a WRITE command with auto precharge enabled and
t
t
ends when RP has been met. After RP is met, the bank will be in the idle state.
4. AUTO REFRESH, SELF REFRESH, and LOAD MODE REGISTER commands can only be issued when all banks
are idle.
5. A BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented by the current
state only.
6. All states and sequences not shown are illegal or reserved.
7. READs or WRITEs to bank m listed in the Command/Action column include READs or WRITEs with auto precharge
enabled and READs or WRITEs with auto precharge disabled.
8. Concurrent auto precharge: Bank n will initiate the auto precharge command when its burst has been interrupted by
bank m burst.
9. The burst in bank n continues as initiated.
10. For a READ without auto precharge interrupted by a READ (with or without auto pre-charge), the READ to bank m will
interrupt the READ on bank n, CAS latency (CL) later.
11. For a READ without auto precharge interrupted by a WRITE (with or without auto pre-charge), the WRITE to bank m will
interrupt the READ on bank n when registered. DQM should be used one clock prior to the WRITE command to prevent
bus contention.
12. For a WRITE without auto precharge interrupted by a READ (with or without auto pre-charge), the READ to bank m will
interrupt the WRITE on bank n when registered, with the data-out appearing CL later. The last valid WRITE to bank n
will be data-in registered one clock prior to the READ to bank m.
13. For a WRITE without auto precharge interrupted by a WRITE (with or without auto pre-charge), the WRITE to bank m
will interrupt the WRITE on bank n when registered. The last valid WRITE to bank n will be data-in registered one clock
prior to the READ to bank m.
14. For a READ with auto precharge interrupted by a READ (with or without auto pre-charge), the READ to bank m
will interrupt the READ on bank n, CL later. The PRE-CHARGE to bank n will begin when the READ to bank m is
registered.
15. For a READ with auto precharge interrupted by a WRITE (with or without auto pre-charge), the WRITE to bank m will
interrupt the READ on bank n when registered. DQM should be used two clocks prior to the WRITE command to
prevent bus contention. The PRECHARGE to bank n will begin when the WRITE to bank m is registered.
16. For a WRITE with auto precharge interrupted by a READ (with or without auto pre-charge), the READ to bank m will
interrupt the WRITE on bank n when registered, with the data-out appearing CL later. The PRECHARGE to bank n will
t
t
begin after WR is met, where WR begins when the READ to bank m is registered. The last valid WRITE bank n will
be data-in registered one clock prior to the READ to bank m.
17. For a WRITE with auto precharge interrupted by a WRITE (with or without auto pre-charge), the WRITE to bank m will
t
t
interrupt the WRITE on bank n when registered. The PRECHARGE to bank n will begin after WR is met, where WR
begins when the WRITE to bank m is registered. The last valid WRITE to bank n will be data registered one clock to the
WRITE to bank m.
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Table 16: Truth Table – CKE
Notes 1–4 apply to all parameters and conditions
CKE
n-1
CKE
Command
Action
n
Current State
Power-down
Self refresh
Notes
n
n
L
L
L
X
X
X
Maintain power-down
Maintain self refresh
Maintain clock suspend
Exit power-down
Clock suspend
Power-down
Self refresh
H
L
COMMAND INHIBIT or NOP
COMMAND INHIBIT or NOP
X
5
6
7
Exit self refresh
Clock suspend
Exit clock suspend
Power-down entry
Self refresh entry
All banks idle
H
H
COMMAND INHIBIT or NOP
AUTO REFRESH
All banks idle
Reading or writing
VALID
Clock suspend entry
H
See Table 15 (page 30).
Notes: 1. CKE is the logic state of CKE at clock edge n; CKE
n
was the state of CKE at the
n-1
previous clock edge.
2. Current state is the state of the SDRAM immediately prior to clock edge n.
3. COMMAND is the command registered at clock edge n, and ACTION is a result
n
n
of COMMAND .
n
4. All states and sequences not shown are illegal or reserved.
5. Exiting power-down at clock edge n will put the device in the all banks idle state in time
t
for clock edge n + 1 (provided that CKS is met).
6. Exiting self refresh at clock edge n will put the device in the all banks idle state after
t
XSR is met. COMMAND INHIBIT or NOP commands should be issued on any clock
t
edges occurring during the XSR period. A minimum of two NOP commands must be
t
provided during the XSR period.
7. After exiting clock suspend at clock edge n, the device will resume operation and
recognize the next command at clock edge n + 1.
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Initialization
SDRAM must be powered up and initialized in a predefined manner. Operational procedures
other than those specified may result in undefined operation. After power is applied to V
DD
(simultaneously) and the clock is stable (stable clock is defined as a signal cycling
and V
DDQ
within timing constraints specified for the clock pin), the SDRAM requires a 100μ s delay
prior to issuing any command other than a COMMAND INHIBIT or NOP. Starting at some
point during this 100μ s period and continuing at least through the end of this period,
COMMAND INHIBIT or NOP commands must be applied.
After the 100μ s delay has been satisfied with at least one COMMAND INHIBIT or NOP
command having been applied, a PRECHARGE command should be applied. All banks must
then be precharged, thereby placing the device in the all banks idle state.
Once in the idle state, at least two AUTO REFRESH cycles must be performed. After the
AUTO REFRESH cycles are complete, the SDRAM is ready for mode register programming.
Because the mode register will power up in an unknown state, it must be loaded prior to
applying any operational command. If desired, the two AUTO REFRESH commands can be
issued after the LMR command.
The recommended power-up sequence for SDRAM:
1. Simultaneously apply power to V
and V
.
DD
DDQ
2. Assert and hold CKE at a LVTTL logic LOW since all inputs and outputs are LVTTL-
compatible.
3. Provide stable CLOCK signal. Stable clock is defined as a signal cycling within timing
constraints specified for the clock pin.
4. Wait at least 100μ s prior to issuing any command other than a COMMAND INHIBIT
or NOP.
5. Starting at some point during this 100μ s period, bring CKE HIGH. Continuing at least
through the end of this period, 1 or more COMMAND INHIBIT or NOP commands
must be applied.
6. Perform a PRECHARGE ALL command.
t
7. Wait at least RP time; during this time NOPs or DESELECT commands must be given.
All banks will complete their precharge, thereby placing the device in the all banks idle
state.
8. Issue an AUTO REFRESH command.
t
9. Wait at least RFC time, during which only NOPs or COMMAND INHIBIT
commands are allowed.
10. Issue an AUTO REFRESH command.
t
11. Wait at least RFC time, during which only NOPs or COMMAND INHIBIT
commands are allowed.
12. The SDRAM is now ready for mode register programming. Because the mode register
will power up in an unknown state, it should be loaded with desired bit values prior to
applying any operational command. Using the LMR command, program the mode
register. The mode register is programmed via the MODE REGISTER SET command
with BA1 = 0, BA0 = 0 and retains the stored information until it is programmed again or
the device loses power. Not programming the mode register upon initialization will result
in default settings which may not be desired. Out-puts are guaranteed High-Z after the
LMR command is issued. Outputs should be High-Z already before the LMR command
is issued.
t
13. Wait at least MRD time, during which only NOP or DESELECT commands are al-
lowed.
At this point the DRAM is ready for any valid command.
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Note:
More than two AUTO REFRESH commands can be issued in the sequence. After steps 9 and
t
10 are complete, repeat them until the desired number of AUTO REFRESH + RFC loops is
achieved.
Figure 11: Initialize and Load Mode Register
Notes: 1. The mode register may be loaded prior to the AUTO REFRESH cycles if desired.
2. If CS is HIGH at clock HIGH time, all commands applied are NOP.
3. JEDEC and PC100 specify three clocks.
4. Outputs are guaranteed High-Z after command is issued.
t
5. A12 should be a LOW at P + 1.
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Mode Register
The mode register defines the specific mode of operation, including burst length (BL), burst
type, CAS latency (CL), operating mode, and write burst mode. The mode register is
programmed via the LOAD MODE REGISTER command and retains the stored information
until it is programmed again or the device loses power.
Mode register bits M[2:0] specify the BL; M3 specifies the type of burst; M[6:4] specify the
CL; M7 and M8 specify the operating mode; M9 specifies the write burst mode; and M10–Mn
should be set to zero to ensure compatibility with future revisions. Mn + 1 and Mn + 2 should
be set to zero to select the mode register.
t
The mode registers must be loaded when all banks are idle, and the controller must wait MRD
before initiating the subsequent operation. Violating either of these requirements will result in
unspecified operation.
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Burst Length
Read and write accesses to the device are burst oriented, and the burst length (BL) is
programmable. The burst length determines the maximum number of column locations that
can be accessed for a given READ or WRITE command. Burst lengths of 1, 2, 4, 8, or
continuous locations are available for both the sequential and the interleaved burst types, and
a continuous page burst is available for the sequential type. The continuous page burst is
used in conjunction with the BURST TERMINATE command to generate arbitrary burst
lengths.
Reserved states should not be used, as unknown operation or incompatibility with future
versions may result.
When a READ or WRITE command is issued, a block of columns equal to the burst length is
effectively selected. All accesses for that burst take place within this block, meaning that the
burst wraps within the block when a boundary is reached. The block is uniquely selected by
A[8:1] when BL = 2, A[8:2] when BL = 4, and A[8:3] when BL = 8. The remaining (least
significant) address bit(s) is (are) used to select the starting location within the block.
Continuous page bursts wrap within the page when the boundary is reached.
Burst Type
Accesses within a given burst can be programmed to be either sequential or interleaved; this is
referred to as the burst type and is selected via bit M3.
The ordering of accesses within a burst is determined by the burst length, the burst type,
and the starting column address.
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Table 17: Burst Definition Table
Order of Accesses Within a Burst
Burst Length
Starting Column Address
Type = Sequential
Type = Interleaved
2
A0
0
0-1
1-0
0-1
1-0
1
4
8
A1
0
A0
0
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
0
1
1
0
1
1
A2
0
A1
0
A0
0
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
0-1-2-3-4-5-6-7
1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Continuous
n = A0–An/9/8 (location 0–y)
Cn, Cn + 1, Cn + 2, Cn + 3...Cn - 1,
Cn...
Not supported
Notes: 1. For full-page accesses: y = 2048 (x4); y = 1024 (x8); y = 512 (x16).
2. For BL = 2, A1–A9, A11 (x4); A1–A9 (x8); or A1–A8 (x16) select the block-of-two burst;
A0 selects the starting column within the block.
3. For BL = 4, A2–A9, A11 (x4); A2–A9 (x8); or A2–A8 (x16) select the block-of-four
burst; A0–A1 select the starting column within the block.
4. For BL = 8, A3–A9, A11 (x4); A3–A9 (x8); or A3–A8 (x16) select the block-of-eight
burst; A0–A2 select the starting column within the block.
5. For a full-page burst, the full row is selected and A0–A9, A11 (x4); A0–A9 (x8); or A0–A8
(x16) select the starting column.
6. Whenever a boundary of the block is reached within a given sequence above, the
following access wraps within the block.
For BL = 1, A0–A9, A11 (x4); A0–A9 (x8); or A0–A8 (x16) select the unique column to be accessed, and mode register bit M3
is ignored.
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CAS Latency
The CAS latency (CL) is the delay, in clock cycles, between the registration of a READ
command and the availability of the output data. The latency can be set to two or three clocks.
If a READ command is registered at clock edge n, and the latency is m clocks, the data will
be available by clock edge n + m. The DQ start driving as a result of the clock edge one
cycle earlier (n + m - 1), and provided that the relevant access times are met, the data is
valid by clock edge n + m. For example, assuming that the clock cycle time is such that all
relevant access times are met, if a READ command is registered at T0 and the latency is
programmed to two clocks, the DQ start driving after T1 and the data is valid by T2.
Reserved states should not be used as unknown operation or incompatibility with future
versions may result.
Figure 13: CAS Latency
Operating Mode
Write Burst Mode
The normal operating mode is selected by setting M7 and M8 to zero; the other combinations
of values for M7 and M8 are reserved for future use. Reserved states should not be used
because unknown operation or incompatibility with future versions may result.
When M9 = 0, the burst length programmed via M[2:0] applies to both READ and WRITE
bursts; when M9 = 1, the programmed burst length applies to READ bursts, but write
accesses are single-location (non-burst) accesses.
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Bank/Row Activation
Before any READ or WRITE commands can be issued to a bank within the SDRAM, a
row in that bank must be opened. This is accomplished via the ACTIVE command, which
selects both the bank and the row to be activated.
After a row is opened with the ACTIVE command, a READ or WRITE command can be
t
t
issued to that row, subject to the RCD specification. RCD (MIN) should be divided by the
clock period and rounded up to the next whole number to determine the earliest clock edge
after the ACTIVE command on which a READ or WRITE command can be entered. For
t
example, a RCD specification of 20ns with a 125 MHz clock (8ns period) results in 2.5
clocks, rounded to 3. This is reflected in Figure 14 (page 40), which covers any case where 2
t
t
< RCD (MIN)/ CK ≤ 3. (The same procedure is used to convert other specification limits
from time units to clock cycles.)
A subsequent ACTIVE command to a different row in the same bank can only be issued after
the previous active row has been precharged. The minimum time interval between successive
t
ACTIVE commands to the same bank is defined by RC.
A subsequent ACTIVE command to another bank can be issued while the first bank is being
accessed, which results in a reduction of total row-access overhead. The mini-mum time
t
interval between successive ACTIVE commands to different banks is defined by RRD.
t
t
t
Figure 14: Example: Meeting RCD (MIN) When 2 < RCD (MIN)/ CK < 3
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READ Operation
READ bursts are initiated with a READ command, as shown in Figure 8 (page 24). The
starting column and bank addresses are provided with the READ command, and auto
precharge is either enabled or disabled for that burst access. If auto precharge is enabled, the
row being accessed is precharged at the completion of the burst. In the following figures, auto
precharge is disabled.
During READ bursts, the valid data-out element from the starting column address is
available following the CAS latency after the READ command. Each subsequent data-out
element will be valid by the next positive clock edge. Figure 16 (page 43) shows general
timing for each possible CAS latency setting.
Upon completion of a burst, assuming no other commands have been initiated, the DQ signals
will go to High-Z. A continuous page burst continues until terminated. At the end of the page,
it wraps to column 0 and continues.
Data from any READ burst can be truncated with a subsequent READ command, and data
from a fixed-length READ burst can be followed immediately by data from a READ
command. In either case, a continuous flow of data can be maintained. The first data element
from the new burst either follows the last element of a completed burst or the last desired data
element of a longer burst that is being truncated. The new READ command should be issued x
cycles before the clock edge at which the last desired data element is valid, where x = CL - 1.
This is shown in Figure 16 (page 43) for CL2 and CL3.
SDRAM devices use a pipelined architecture and therefore do not require the 2n rule
associated with a prefetch architecture. A READ command can be initiated on any clock cycle
following a READ command. Full-speed random read accesses can be performed to the same
bank, or each subsequent READ can be performed to a different bank.
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Figure 15: Consecutive READ Bursts
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Figure 16: Random READ Accesses
Data from any READ burst can be truncated with a subsequent WRITE command, and data
from a fixed-length READ burst can be followed immediately by data from a WRITE
command (subject to bus turnaround limitations). The WRITE burst can be initiated on the
clock edge immediately following the last (or last desired) data element from the READ burst,
provided that I/O contention can be avoided. In a given system design, there is a possibility
that the device driving the input data will go Low-Z before the DQ go High-Z. In this case, at
least a single-cycle delay should occur between the last read data and the WRITE command.
The DQM input is used to avoid I/O contention, as shown in Figure 17 (page 44) and Figure
18 (page 45). The DQM signal must be asserted (HIGH) at least two clocks prior to the
WRITE command (DQM latency is two clocks for output buffers) to suppress da-ta-out from
the READ. After the WRITE command is registered, the DQ will go to High-Z (or remain
High-Z), regardless of the state of the DQM signal, provided the DQM was active on the clock
just prior to the WRITE command that truncated the READ command. If not, the second
WRITE will be an invalid WRITE. For example, if DQM was LOW during T4, then the
WRITEs at T5 and T7 would be valid, and the WRITE at T6 would be invalid.
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The DQM signal must be de-asserted prior to the WRITE command (DQM latency is zero
clocks for input buffers) to ensure that the written data is not masked. Figure 17 (page 44)
shows where, due to the clock cycle frequency, bus contention is avoided without having to
add a NOP cycle, while Figure 18 (page 45) shows the case where an additional NOP cycle
is required.
A fixed-length READ burst may be followed by or truncated with a PRECHARGE command
to the same bank, provided that auto precharge was not activated. The PRE-CHARGE
command should be issued x cycles before the clock edge at which the last de-sired data
element is valid, where x = CL - 1. This is shown in Figure 19 (page 45) for each possible CL;
data element n + 3 is either the last of a burst of four or the last de-sired data element of a
longer burst. Following the PRECHARGE command, a subsequent command to the same bank
t
cannot be issued until RP is met. Note that part of the row precharge time is hidden during the
access of the last data element(s).
In the case of a fixed-length burst being executed to completion, a PRECHARGE command
issued at the optimum time (as described above) provides the same operation that would result
from the same fixed-length burst with auto precharge. The disadvantage of the PRECHARGE
command is that it requires that the command and address buses be available at the
appropriate time to issue the command. The advantage of the PRECHARGE command is that
it can be used to truncate fixed-length or continuous page bursts.
Figure 17: READ-to-WRITE
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Figure 18: READ-to-WRITE With Extra Clock Cycle
Figure 19: READ-to-PRECHARGE
Continuous-page READ bursts can be truncated with a BURST TERMINATE command and
fixed-length READ bursts can be truncated with a BURST TERMINATE command, provided
that auto precharge was not activated. The BURST TERMINATE command should be issued
x cycles before the clock edge at which the last desired data element is valid, where x = CL - 1.
This is shown in Figure 20 (page 46) for each possible CAS latency; data element n + 3 is the
last desired data element of a longer burst.
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Figure 20: Terminating a READ Burst
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Figure 21: Alternating Bank Read Accesses
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Figure 22: READ Continuous Page Burst
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Figure 23: READ – DQM Operation
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WRITE Operation
WRITE bursts are initiated with a WRITE command, as shown in Figure 9 (page 25). The
starting column and bank addresses are provided with the WRITE command and auto
precharge is either enabled or disabled for that access. If auto precharge is enabled, the row
being accessed is precharged at the completion of the burst. For the generic WRITE
commands used in the following figures, auto precharge is disabled.
During WRITE bursts, the first valid data-in element is registered coincident with the WRITE
command. Subsequent data elements are registered on each successive positive clock edge.
Upon completion of a fixed-length burst, assuming no other commands have been initiated, the
DQ will remain at High-Z and any additional input data will be ignored (see Figure 24 (page
50)). A continuous page burst continues until terminated; at the end of the page, it wraps to
column 0 and continues.
Data for any WRITE burst can be truncated with a subsequent WRITE command, and data
for a fixed-length WRITE burst can be followed immediately by data for a WRITE
command. The new WRITE command can be issued on any clock following the previous
WRITE command, and the data provided coincident with the new command applies to the
new command (see Figure 25 (page 51)). Data n + 1 is either the last of a burst of two or the
last desired data element of a longer burst.
SDRAM devices use a pipelined architecture and therefore do not require the 2n rule
associated with a prefetch architecture. A WRITE command can be initiated on any clock cycle
following a previous WRITE command. Full-speed random write accesses within a page can be
performed to the same bank, as shown in Figure 26 (page 52), or each subsequent WRITE can
be performed to a different bank.
Figure 24: WRITE Burst
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Figure 25: WRITE-to-WRITE
Data for any WRITE burst can be truncated with a subsequent READ command, and data for
a fixed-length WRITE burst can be followed immediately by a READ command. After the
READ command is registered, data input is ignored and WRITEs will not be executed (see
Figure 27 (page 52)). Data n + 1 is either the last of a burst of two or the last desired data
element of a longer burst.
Data for a fixed-length WRITE burst can be followed by or truncated with a PRE-CHARGE
command to the same bank, provided that auto precharge was not activated. A continuous-
page WRITE burst can be truncated with a PRECHARGE command to the same bank. The
t
PRECHARGE command should be issued WR after the clock edge at which the last desired
t
input data element is registered. The auto precharge mode re-quires a WR of at least one
clock with time to complete, regardless of frequency.
t
In addition, when truncating a WRITE burst at high clock frequencies ( CK < 15ns), the
DQM signal must be used to mask input data for the clock edge prior to and the clock edge
coincident with the PRECHARGE command (see Figure 28 (page 53)). Data n + 1 is either
the last of a burst of two or the last desired data element of a longer burst. Following the
t
PRECHARGE command, a subsequent command to the same bank cannot be issued until RP
is met.
In the case of a fixed-length burst being executed to completion, a PRECHARGE command
issued at the optimum time (as described above) provides the same operation that would result
from the same fixed-length burst with auto precharge. The disadvantage of the PRECHARGE
command is that it requires that the command and address buses be available at the appropriate
time to issue the command. The advantage of the PRECHARGE command is that it can be used
to truncate fixed-length bursts or continuous page bursts.
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Figure 26: Random WRITE Cycles
Figure 27: WRITE-to-READ
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Figure 28: WRITE-to-PRECHARGE
Fixed-length WRITE bursts can be truncated with the BURST TERMINATE command.
When truncating a WRITE burst, the input data applied coincident with the BURST
TERMINATE command is ignored. The last data written (provided that DQM is LOW at that
time) will be the input data applied one clock previous to the BURST TERMINATE
command. This is shown in Figure 29 (page 54), where data n is the last desired data element
of a longer burst.
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Figure 29: Terminating a WRITE Burst
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Figure 30: Alternating Bank Write Accesses
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Figure 31: WRITE – Continuous Page Burst
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Figure 32: WRITE – DQM Operation
Burst Read/Single Write
The burst read/single write mode is entered by programming the write burst mode bit (M9) in
the mode register to a 1. In this mode, all WRITE commands result in the access of a single
column location (burst of one), regardless of the programmed burst length. READ commands
access columns according to the programmed burst length and sequence, just as in the normal
mode of operation (M9 = 0).
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PRECHARGE Operation
The PRECHARGE command (see Figure 10 (page 26)) is used to deactivate the open row in a
particular bank or the open row in all banks. The bank(s) will be available for a sub-sequent
t
row access some specified time ( RP) after the PRECHARGE command is is-sued. Input A10
determines whether one or all banks are to be precharged, and in the case where only one bank
is to be precharged (A10 = LOW), inputs BA0 and BA1 select the bank. When all banks are to
be precharged (A10 = HIGH), inputs BA0 and BA1 are treated as “Don’t Care.” After a bank
has been precharged, it is in the idle state and must be activated prior to any READ or WRITE
commands being issued to that bank.
Auto Precharge
Auto precharge is a feature that performs the same individual-bank PRECHARGE function
described previously, without requiring an explicit command. This is accomplished by using
A10 to enable auto precharge in conjunction with a specific READ or WRITE command. A
precharge of the bank/row that is addressed with the READ or WRITE command is
automatically performed upon completion of the READ or WRITE burst, except in the
continuous page burst mode where auto precharge does not apply. In the specific case of write
burst mode set to single location access with burst length set to continuous, the burst length
setting is the overriding setting and auto precharge does not apply. Auto precharge is
nonpersistent in that it is either enabled or disabled for each individual READ or WRITE
command.
Auto precharge ensures that the precharge is initiated at the earliest valid stage within a burst.
t
Another command cannot be issued to the same bank until the precharge time ( RP) is
completed. This is determined as if an explicit PRECHARGE command was is-sued at the
earliest possible time, as described for each burst type in the Burst Type (page 37) section.
Alliance Memory SDRAM supports concurrent auto precharge; cases of concurrent auto
pre-charge for READs and WRITEs are defined below.
READ with auto precharge interrupted by a READ (with or without auto precharge)
A READ to bank m will interrupt a READ on bank n following the programmed CAS
latency. The precharge to bank n begins when the READ to bank m is registered (see Figure
33 (page 59)).
READ with auto precharge interrupted by a WRITE (with or without auto precharge)
A WRITE to bank m will interrupt a READ on bank n when registered. DQM should be
used two clocks prior to the WRITE command to prevent bus contention. The pre-charge to
bank n begins when the WRITE to bank m is registered (see Figure 34
(page 60)).
WRITE with auto precharge interrupted by a READ (with or without auto precharge)
A READ to bank m will interrupt a WRITE on bank n when registered, with the data-out
t
t
appearing CL later. The precharge to bank n will begin after WR is met, where WR be-gins
when the READ to bank m is registered. The last valid WRITE to bank n will be da-ta-in
registered one clock prior to the READ to bank m (see Figure 39 (page 65)).
WRITE with auto precharge interrupted by a WRITE (with or without auto precharge)
A WRITE to bank m will interrupt a WRITE on bank n when registered. The precharge to
t
t
bank n will begin after WR is met, where WR begins when the WRITE to bank m is
registered. The last valid data WRITE to bank n will be data registered one clock prior to a
WRITE to bank m (see Figure 40 (page 65)).
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Figure 33: READ With Auto Precharge Interrupted by a READ
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Figure 34: READ With Auto Precharge Interrupted by a WRITE
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Figure 35: READ With Auto Precharge
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Figure 36: READ Without Auto Precharge
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Figure 37: Single READ With Auto Precharge
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Figure 38: Single READ Without Auto Precharge
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Figure 39: WRITE With Auto Precharge Interrupted by a READ
Figure 40: WRITE With Auto Precharge Interrupted by a WRITE
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Figure 41: WRITE With Auto Precharge
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Figure 42: WRITE Without Auto Precharge
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Figure 43: Single WRITE With Auto Precharge
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Figure 44: Single WRITE Without Auto Precharge
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AUTO REFRESH Operation
The AUTO REFRESH command is used during normal operation of the device to refresh the
contents of the array. This command is nonpersistent, so it must be issued each time a refresh is
required. All active banks must be precharged prior to issuing an AUTO REFRESH command.
t
The AUTO REFRESH command should not be issued until the minimum RP is met following
the PRECHARGE command. Addressing is generated by the internal refresh controller. This
makes the address bits “Don’t Care” during an AU-TO REFRESH command.
After the AUTO REFRESH command is initiated, it must not be interrupted by any executable
t
t
command until RFC has been met. During RFC time, COMMAND INHIBIT or NOP
commands must be issued on each positive edge of the clock. The SDRAM re-quires that every
t
row be refreshed each REF period. Providing a distributed AUTO RE-FRESH command—
t
calculated by dividing the refresh period ( REF) by the number of rows to be refreshed—meets
the timing requirement and ensures that each row is refreshed. Alternatively, to satisfy the
t
refresh requirement a burst refresh can be employed after every REF period by issuing
consecutive AUTO REFRESH commands for the number of rows to be refreshed at the
t
minimum cycle rate ( RFC).
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Figure 45: Auto Refresh Mode
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SELF REFRESH Operation
The self-refresh mode can be used to retain data in the device, even when the rest of the system
is powered down. When in self refresh mode, the device retains data without external clocking.
The SELF REFRESH command is initiated like an AUTO REFRESH command, except CKE
is disabled (LOW). After the SELF REFRESH command is registered, all the inputs to the
device become “Don’t Care” with the exception of CKE, which must remain LOW.
After self-refresh mode is engaged, the device provides its own internal clocking, enabling it to
perform its own AUTO REFRESH cycles. The device must remain in self re-fresh mode for a
t
minimum period equal to RAS and remains in self refresh mode for an indefinite period
beyond that.
The procedure for exiting self refresh requires a sequence of commands. First, CLK must be
stable prior to CKE going back HIGH. (Stable clock is defined as a signal cycling within timing
constraints specified for the clock ball.) After CKE is HIGH, the device must have NOP
t
commands issued for a minimum of two clocks for XSR because time is required for the
completion of any internal refresh in progress.
Upon exiting the self-refresh mode, AUTO REFRESH commands must be issued according to
t
the distributed refresh rate ( REF/refresh row count) as both SELF REFRESH and AUTO
REFRESH utilize the row refresh counter.
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Figure 46: Self Refresh Mode
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Power-Down
Power-down occurs if CKE is registered LOW coincident with a NOP or COMMAND IN-
HIBIT when no accesses are in progress. If power-down occurs when all banks are idle, this
mode is referred to as precharge power-down; if power-down occurs when there is a row active
in any bank, this mode is referred to as active power-down. Entering power-down deactivates
the input and output buffers, excluding CKE, for maximum power savings while in standby.
The device cannot remain in the power-down state longer than the refresh period (64ms)
because no REFRESH operations are performed in this mode.
The power-down state is exited by registering a NOP or COMMAND INHIBIT with CKE
t
HIGH at the desired clock edge (meeting CKS).
Figure 47: Power-Down Mode
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Clock Suspend
The clock suspend mode occurs when a column access/burst is in progress and CKE is
registered LOW. In the clock suspend mode, the internal clock is deactivated, freezing the
synchronous logic.
For each positive clock edge on which CKE is sampled LOW, the next internal positive clock
edge is suspended. Any command or data present on the input balls when an internal clock
edge is suspended will be ignored; any data present on the DQ balls re-mains driven; and
burst counters are not incremented, as long as the clock is suspended.
Exit clock suspend mode by registering CKE HIGH; the internal clock and related operation
will resume on the subsequent positive clock edge.
Figure 48: Clock Suspend During WRITE Burst
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Figure 49: Clock Suspend During READ Burst
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Figure 50: Clock Suspend Mode
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This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth
herein. Although considered final, these specifications are subject to change, as further product development and data
characterization some-times occur
Alliance Memory Inc. 551 Taylor Way, San Carlos, CA 94070
TEL: (650) 610-6800 FAX: (650) 620-9211
Alliance Memory Inc. reserves the right to change products or specification without notice.
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