AS4C64M32MD1-5BIN [ALSC]
Power Down Mode;
| 型号： | AS4C64M32MD1-5BIN |
| 厂家： | 
ALLIANCE SEMICONDUCTOR CORPORATION |
| 描述： | Power Down Mode |
| 文件： | 总43页 (文件大小：1356K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
AS4C64M32MD1
Revision History AS4C64M32MD1 - 90-ball FBGA PACKAGE
Revision Details
Date
Rev 1.0
Preliminary datasheet
September 2014
Confidential
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V.1.0 Sept. 2014
AS4C64M32MD1
64M x 32 bit MOBILE DDR Synchronous DRAM (SDRAM)
Confidential
Advanced (Rev. 1.0, Sep. /2014)
Feature
Description
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4 banks x 16M x 32 organization
The AS4C64M32MD1 is a four bank mobile
DDR DRAM organized as 4 banks x 16M x 32. It
achieves high speed data transfer rates by
employing a chip architecture that pre-fetches
multiple bits and then synchronizes the output data
to a system clock.
Two Die-stacked 4 banks x 16M x 16
Data Mask for Write Control (DM)
Four Banks controlled by BA0 & BA1
Programmable CAS Latency: 2, 3
Programmable Wrap Sequence: Sequential
or Interleave
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Programmable Burst Length:
2, 4, 8, for Sequential Type
2, 4, 8, for Interleave Type
Automatic and Controlled Precharge Command
Power Down Mode
Auto Refresh and Self Refresh
Refresh Interval: 8192 cycles/64ms
Available in 90-ball BGA
All of the controls, address, circuits are
synchronized with the positive edge of an
externally supplied clock. I/O transactions are
possible on both edges of DQS.
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Operating the four memory banks in an inter-
leaved fashion allows random access operation to
occur at a higher rate than is possible with
standard DRAMs. A sequential and gapless data
rate is possible depending on burst length, CAS
latency and speed grade of the device.
Double Data Rate (DDR)
Bidirectional Data Strobe (DQS) for input
and output data, active on both edges
Differential clock inputs CLK and /CLK
Power Supply 1.7V - 1.95V
Drive Strength (DS) Option:Full, 1/2, 1/4, 1/8
Auto Temperature-Compensated Self Refresh
(Auto TCSR)
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Additionally, the device supports low power
saving features like PASR, Auto-TCSR, DPD as
well as options for different drive strength. It’s
ideally suitable for mobile application.
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Partial-Array Self Refresh (PASR) Option: Full,
1/2, 1/4, 1/8, 1/16
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Deep Power Down (DPD) mode
Operating Temperature Range
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Commercial 25°C to 85°C
Industrial-40°C to 85°C
All parts are ROHS Compliant
Table 1. Speed Grade Information
Speed Grade – Data rate Clock Frequency CAS Latency
tRCD
tRP
(ns)
(ns)
400Mbps (max) 200 MHz (max)
3
15
15
Table 2 – Ordering Information for ROHS Compliant Products
Product part No Org Temperature Package
AS4C64M32MD1-5BCN 64M x 32 Commercial - 0°C to 70°C 90-ball BGA
AS4C64M32MD1-5BIN
64M x 32 Industrial-40°C to 85°C
90-ball BGA
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AS4C64M32MD1
IDD Max Specifications and Conditions
Conditions
Symbol
-5
Unit
Operating current - One bank Active-Precharge; tRC = tRC (min); tCK = tCK (min);
CKE = High; CS = High between valid command; Address inputs are switching every
2 clock cycles; Data bus inputs are stable
IDD0
190
mA
Precharge power-down standby current; All banks idle; CKE = Low; CS = High;
IDD2P
10
10
mA
mA
tCK = tCK (min); Address and control inputs are switching; Data bus inputs are stable
Precharge power-down standby current; Clock stopped; All banks idle; CKE = Low;
CS = High; CK = Low; CK = High; Address and control inputs are switching;
Data bus inputs are stable
IDD2PS
Precharge nonpower-down standby current; All banks idle; CKE = High; CS = High;
IDD2N
70
60
mA
mA
tCK = tCK (min); Address and control inputs are switching; Data bus inputs are stable
Precharge nonpower-down standby current; Clock stopped; All banks idle;
CKE = High; CS = High; CK = Low; CK = High; Address and control inputs are switching; IDD2NS
Data bus inputs are stable
Active power-down standby current; One bank active; CKE = Low; CS = High;
IDD3P
10
10
mA
mA
tCK = tCK (min); Address and control inputs are switching; Data bus inputs are stable
Active power-down standby current; Clock stopped; One bank active; CKE =Low;
CS = High; CK = Low; CK = High; Address and control inputs are switching;
Data bus inputs are stable
IDD3PS
Active nonpower-down standby current; One bank active; CKE = High; CS = High;
IDD3N
70
54
mA
mA
tCK = tCK (min); Address and control inputs are switching; Data bus inputs are stable
Active nonpower-down standby current; Clock stopped; One bank active; CKE = High;
CS = High; CK = Low; CK = High; Address and control inputs are switching;
Data bus inputs are stable
IDD3NS
Operating current - burst read; One bank active; Burst length = 4; tCK = tCK (min);
Continuous Read burst; Address inputs are switching every 2 clock cycles;
50% of data changing at every burst; lout = 0 m A
IDD4R
IDD4W
180
180
mA
mA
Operating current - burst write; One bank active; Burst length = 4; tCK = tCK (min);
Continuous Write burst; Address inputs are switching every 2 clock cycles;
50% of data changing at every burst
Auto refresh current; Burst refresh; CKE = High; Address and
IDD5
IDD8
160
20
mA
uA
control inputs are switching; Data bus inputs are stable
Deep Power Down Current; Address and control inputs are stable;
Data bus inputs are stable
Confidential
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V.1.0 Sept. 2014
AS4C64M32MD1
Partial Array Self Refresh Current (PASR)
Extended Mode
Parameter & Test Condition
Register A[2:0]
Symb.
ICC6
ICC6
ICC6
ICC6
ICC6
Max.
Unit
mA
mA
mA
mA
mA
Note
o
Tcase [ C]
Self-Refresh Current
Self-Refresh Mode
CKE = 0.2V, tck = infinity,
full array activations, all banks
o
85 C max.
3
Self-Refresh Current
Self-Refresh Mode
CKE = 0.2V, tck = infinity,
1/2 array activations
o
85 C max.
2.4
2.2
2
Self-Refresh Current
Self-Refresh Mode
CKE = 0.2V, tck = infinity,
1/4 array activation
o
85 C max.
Self-Refresh Current
Self-Refresh Mode
CKE = 0.2V, tck = infinity,
1/8 array activation
o
85 C max.
Self-Refresh Current
Self-Refresh Mode
CKE = 0.2V, tck = infinity,
1/16 array activation
o
85 C max.
2
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AS4C64M32MD1
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AS4C64M32MD1
AC Timing Parameters & Specification
AC CHARACTERISTICS
-5
PARAMETER
SYMBOL MIN
MAX UNITS NOTES
t
AC
Output data access time from CK/CK
CK high-level width
2
0.45
0.45
5
5
ns
3
t
t
t
CH
CK
CK
0.55
0.55
-
t
CL
CK low-level width
t
CK (3)
Clock cycle time
CL = 3
ns
ns
ns
ns
ns
CK
CK
1
t
DH
DQ and DM input hold time relative to DQS
DQ and DM input setup time relative to DQS
DQ and DM input pulse width (for each input)
Access window of DQS from CK/CK
DQS input high pulse width
0.4
0.4
1.4
2
5,6
5,6
t
DS
t
DIPW
t
DQSCK
5
t
t
t
DQSH
0.4
0.4
0.6
0.6
t
DQSL
DQS input low pulse width
DQS-DQ skew, DQS to last DQ valid,
per group, per access
t
DQSQ
0.4
1.2
ns
1
Write command to first DQS latching
transition
t
t
t
DQSS
CK
0.7
t
CH,
Half clock period
t
t
HP
ns
CL
Data-out high-impedance window
from CK/CK
t
HZ
CK
0.4
1
0.6
Data-out low-impedance window
from CK/CK
t
LZ
ns
t
IH
Address and control input hold time
Address and control input setup time
0.9
0.9
ns
ns
1
1
t
IS
LOAD MODE REGISTER command
cycle time
t
t
MRD
CK
ns
2
t
HP
DQ-DQS hold, DQS to first DQ to go
non-valid, per access
t
t
QH
- QHS
t
QHS
Data hold skew factor
0.5
ns
ns
t
RAS
ACTIVE to PRECHARGE command
40
15
70K
ACTIVE to READ with Auto precharge
command
t
RAP
ns
ns
ACTIVE to ACTIVE/AUTO REFRESH
command period
t
RC
55
t
RFC
AUTO REFRESH command period
ACTIVE to READ or WRITE delay
PRECHARGE command period
72
15
15
ns
ns
ns
t
RCD
t
RP
Confidential
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V.1.0 Sept. 2014
AS4C64M32MD1
AC CHARACTERISTICS
PARAMETER
-5
SYMBOL MIN MAX UNITS NOTES
t
t
RPRE
CK
CK
DQS read preamble
0.9
0.4
10
1.1
0.6
t
t
RPST
DQS read postamble
t
RRD
ACTIVE bank A to ACTIVE bank B command
DQS write preamble
ns
t
t
t
WPRE
CK
0.25
0
t
WPRES
DQS write preamble setup time
DQS write postamble
ns
4
t
WPST
CK
0.4
15
0.6
7.8
t
WR
Write recovery time
ns
CK
us
Internal WRITE to READ command
delay
t
t
WTR
2
t
REFI
Average periodic refresh interval
Power down exit time
1*tCK
t
t
PDEX
+ IS
ns
Confidential
Page 40
V.1.0 Sept. 2014
AS4C64M32MD1
1. Input Setup/Hold Slew Rate Derating
Input Setup/Hold Slew Rate
tIS
(ps)
0
tIH
(ps)
0
(V/ns)
1.0
0.8
+50
+100
+50
+100
0.6
This derating table is used to increase t /t in the case where the input slew rate is below 1.0V/ns.
IS IH
1. Minimum 3CLK of tDAL(= tWR + tRP) is required because it need minimum 2CLK for tWR and minimum 1CLK for tRP.
2. tAC(min) value is measured at the high Vdd(1.95V) and cold temperature(-25 C).
tAC (max) value is measured at the low Vdd(1.7V) and hot temperature(85 C).
tAC is measured in the device with half driver strength and under the AC output load condition .
2. The specific requirement is that DQS be valid(High or Low) on or before this CK edge. The case shown(DQS going from
High_Z to logic Low) applies when no writes were previously in progress on the bus. If a previous write was in progress,
DQS could be High at this time, depending on tDQSS.
3. I/O Setup/Hold Slew Rate Derating
I/O Setup/Hold Slew Rate
tDS
tDH
(ps)
0
(V/ns)
1.0
(ps)
0
0.8
+75
+150
+75
+150
0.6
This derating table is used to increase t
/t
DS DH
in the case where the I/O slew rate is below 1.0V/ns.
6. I/O Delta Rise/Fall Rate(1/slew-rate) Derating
Delta Rise/Fall Rate
(ns/V)
tDS
(ps)
tDH
(ps)
0
0
0
0.25
0.5
+50
+100
+50
+100
This derating table is used to increase tDS/tDH in the case where the DQ and DQS slew rates differ. The Delta Rise/Fall Rate
is calculated as 1/SlewRate1-1/SlewRate2. For example, if slew rate 1 = 1.0V/ns and slew rate 2 =0.8V/ns, then the Delta Rise/Fall
Rate =-0.25ns/V.
Confidential
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V.1.0 Sept. 2014
AS4C64M32MD1
Package Diagram
90-BALL 0.8mm pitch BGA
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V.1.0 Sept. 2014
AS4C64M32MD1
Alliance Memory Inc. 551 Taylor Way, San Carlos, CA 94070
TEL: (650) 610-6800 FAX: (650) 620-9211
Alliance Memory Inc. reserves the right to change products or specification without notice.
Confidential
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V.1.0 Sept. 2014
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