AS8C401800 [ALSC]
Power down controlled by ZZ input;
| 型号： | AS8C401800 |
| 厂家： | 
ALLIANCE SEMICONDUCTOR CORPORATION |
| 描述： | Power down controlled by ZZ input |
| 文件： | 总17页 (文件大小：2603K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
128K x 36, 256K x 18
AS8C403600
AS8C401800
3.3V Synchronous SRAMs
3.3V I/O, Pipelined Outputs
Burst Counter, Single Cycle Deselect
Features
Description
◆
128K x 36, 256K x 18 memory configurations
TheAS8C403600/1800 are high- speed SRAMs organized as
128K x 36/256K x 18. TheAS8C403600/401800 SRAMs contain write,
data, address and control registers. Internal logic allows the SRAM to
generate a self-timed write based upon a decision which can be left until
the end of the write cycle.
◆
Supports high system speed:
Commercial:
– 150MHz 3.8ns clock access time
◆
LBO input selects interleaved or linear burst mode
Self-timed write cycle with global write control ( Gl (W), byte
The burst mode feature offers the highest level of performance to the
system designer,as theAS8C403600/1800 can provide four cycles of data
for a single address presented to the SRAM. An internal burst address
counter accepts the first cycle address from the processor, initiating the
access sequence. The first cycle of output data will be pipelined for one
cycle before it is available on the next rising clock edge. If burst mode
operation is selected (A( DV=LOW), the subsequent three cycles of output
data will be available to the user on the next three rising clock edges. The
order of these three addresses are defined by the internal burst counter
and the LBO input pin.
◆
write enable (BWE), and byte writes (BWx)
3.3V core power supply
Power down controlled by ZZ input
3.3V I/O
◆
◆
◆
◆
Optional - Boundary Scan JTAG Interface (IEEE 1149.1
compliant)
◆
Packaged in a JEDEC Standard 100-pin plastic thin quad
flatpack (TQFP).
The AS8C403600/1800 SRAMs utilize the latest high- performance
CMOS process and are packagedin a JEDEC standard 14mm x 20mm
100-pin thin plastic quad flatpack (TQFP).
Pin Description Summary
A
0-A17
Address In puts
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Output
Input
I/O
Synchronous
Synchronous
Synchronous
Asynchronous
Synchronous
Synchronous
Synchronous
N/A
Chip Enab le
CE
CS
0
, CS
1
Chip Se lects
Output Enable
OE
GW
Global Write Enable
Byte Write Enable
Individual By te Write Se lects
Clock
BWE
BW , BW
(1)
1
2
, BW
3
, BW
4
CLK
Burst Ad dress Advance
Address Status (Cache Controller)
Address S tatus (Processor)
Linear / Interleaved Burst Order
Test Mode Select
Test Data Input
Synchronous
Synchronous
Synchronous
DC
ADV
ADSC
ADSP
LBO
TMS
TDI
Synchronous
Synchronous
N/A
TCK
TDO
ZZ
Test Clock
Test Data Output
Synchronous
Asynchronous
Synchronous
N/A
Sleep Mode
I/O
0
-I/O31, I/OP1-I/OP4
Data Input / Ou tput
Core Power, I/O Power
Ground
V
V
DD, VDDQ
SS
Supply
Supply
N/A
NOTE:
1. BW3 and BW4 are not applicable for the AS8C401800.
September 2010
1
DSC-5279/05
AS8C403600, AS8C401800, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect
Commercial Temperature Range
(1)
Pin Definitions
Symbol
Pin Function
I/O
Active
Description
Synchronous Address inputs. The address register is triggered by a combination of the rising edge
of CLK and ADSC Lo w o r ADSP Low and CE Lo w.
A
0-A17
Address Inputs
I
N/A
Address Status
(Cache Controller)
Synchronous Address Status from Cache Controller. ADSC i s an active LOW i nput that i s used to l oad
I
I
LOW
LOW
ADSC
ADSP
the address registers with new addresses.
Address Status
(Processor)
Synchronous Address Status from Processor. ADSP i s a n ac tive LO W i nput that is us ed to l oad the
address registers with new addresses. ADSP is gated by CE.
Synchronous Address Advance. ADV i s an a ctive L OW i nput that i s u sed to advance the i nternal
burst counter, controlling burst access after the initial address is loaded. When the input is HIGH the
burst c ounter i s n ot i ncremented; th at i s, th ere i s n o a ddress a dvance.
Burst Address
Advance
I
I
LOW
LOW
ADV
Synchronous byte write enable gates the byte write inputs BW
1
-BW . If BWE is LOW at the rising
4
Byte Wr ite Enable
edge of CLK then BWx i nputs a re p assed to the next s tage i n the c ircuit. If BWE is HIGH then the
byte write inputs are blocked and only GW c an i nitiate a w rite cycle.
BWE
Individual Byte
Write E nables
Synchronous byte write enables. BW
1
controls I/O0-7, I/OP1, BW2 controls I/O8-15, I/OP2, etc. Any
I
I
LOW
LOW
BW
1
-BW
4
active byte write causes all outputs to be disabled.
Synchronous chip enable. CE is used with CS
ADSP.
0
and CS to e nable the AS8C403600/1800. CE al so g ates
1
Chip Enable
CE
CLK
Clock
I
I
I
N/A
This i s the clock i nput. A ll ti ming r eferences fo r the d evice a re made with r espect t o th is i nput.
CS
CS
GW
I/O -I/O31
0
Chip Select 0
Chip Select 1
HIGH
LOW
Synchronous active HIGH chip select. CS
Synchronous active LOW chip select. CS
0
is used with CE and CS
1
to e nable th e c hip.
1
is used with CE and CS
0 to e nable the c hip.
1
Global Write
Enable
Synchronous global write enable. This input will write all four 9-bit data bytes when LOW on the rising
edge of CLK. GW supersedes individual byte write enables.
I
LOW
N/A
0
Synchronous d ata i nput/output ( I/O) p ins. B oth the d ata i nput p ath a nd d ata o utput p ath are registered
and triggered by the rising edge of CLK.
Data Input/Output
Linear B urst Order
I/O
I/OP1-I/OP4
Asynchronous burst order selection input. When LBO is HIGH, the interleaved burst sequence is
selected. When LBO is LOW the Linear burst sequence is selected. LBO i s a s tatic i nput and must
not change state while the device is operating.
I
LOW
LBO
Asynchronous o utput e nable. When OE is LOW the data output drivers are enabled on the I/O pins if
the chip is also selected. When OE is HIGH the I/O pins are in a high-impedance state.
Output E nable
Test M odeSelect
Test D ata Input
Test C lock
I
I
LOW
N/A
N/A
N/A
N/A
OE
TMS
TDI
Gives input command for TAP controller. Sampled on rising edge of TDK. This pin has an internal
pullup.
Serial input of registers placed between TDI and TDO. Sampled on rising edge of TCK. This pin has
an internal pullup.
I
Clock input of TAP controller. Each TAP event is clocked. Test inputs are captured on rising edge of
TCK, while test outputs are driven from the falling edge of TCK. This pin has an internal pullup.
TCK
TDO
I
Serial output of registers placed between TDI and TDO. This output is active depending on the state
of the TAP controller.
Test Da taOutput
O
Asynchronous sleep mode input. ZZ HIGH will gate the CLK internally and power down the
AS8C403600/1800 to its lowest power consumption level. Data retention is guaranteed in Sleep
Mode.This pin has an internal pull down.
ZZ
Sleep Mode
I
HIGH
V
DD
DDQ
SS
Power S upply
Power Supply
Ground
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
3.3V c ore p ower s upply.
3.3V I/O Supply.
Ground.
V
V
NC
No C onnect
NC pins are not e lectrically c onnected to th e d evice.
5279 tbl 02
NOTE:
1. All synchronous inputs must meet specified setup and hold times with respect to CLK.
6.42
2
AS8C403600, AS8C401800, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect
Commercial Temperature Range
Functional Block Diagram
LBO
ADV
CEN
INTERNAL
ADDRESS
128K x 36/
256K x 18-
BIT
MEMORY
ARRAY
CLK
2
Burst
Logic
17/18
Binary
Counter
ADSC
A0*
A1*
Q0
Q1
CLR
ADSP
2
CLK EN
A0,A1
A2–A17
A0 -
A16/17
ADDRESS
REGISTER
36/18
36/18
17/18
GW
Byte 1
Write Register
BWE
Byte 1
Write Driver
BW
1
9
9
Byte 2
Write Register
Byte 2
Write Driver
BW2
Byte 3
Write Register
Byte 3
Write Driver
BW
3
9
9
Byte 4
Write Register
Byte 4
Write Driver
BW4
OUTPUT
REGISTER
CE
CS
CS
Q
D
0
Enable
DATA INPUT
REGISTER
1
Register
CLK EN
ZZ
Powerdown
D
Q
Enable
Delay
Register
OE
OUTPUT
BUFFER
OE
,
36/18
I/O
0 — I/O31
I/OP1 — I/OP4
5279 drw 01
TMS
TDI
TCK
TRST
JTAG
(SA Version)
TDO
(Optional)
6.42AS8
3
AS8C403600, AS8C401800, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect
Commercial Temperature Range
(1)
Absolute Maximum Ratings
Recommended Operating
Temperature and Supply Voltage
Commercial &
Industrial
Symbol
Rating
Unit
Grade
Commercial
Industrial
Temperature(1)
0°C to +70°C
-40°C to +85°C
V
SS
V
DD
VDDQ
(2)
V
V
V
V
TERM
Terminal Voltage with
Respect to G ND
-0.5 to +4.6
V
0V
0V
3.3V±5%
3.3V±5%
3.3V±5%
3.3V±5%
(3,6)
TERM
Terminal Voltage with
Respect to G ND
-0.5 to VDD
-0.5 to VDD +0.5
-0.5 to VDDQ +0.5
-0 to +70
V
5279 t bl 04
NOTES:
1. TA is the "instant on" case temperature.
(4,6)
TERM
Terminal Voltage with
Respect to G ND
V
(5,6)
Recommended DC Operating
Conditions
TERM
Terminal Voltage with
Respect to G ND
V
Commercial
oC
oC
oC
oC
W
Symbol
Parameter
Min.
3.135
3.135
0
Typ.
Max.
3.465
3.465
0
Unit
V
Operating Temperature
T
A(7)
V
DD
Core Supply Voltage
3.3
Industrial
Operating Temperature
-40 to +85
V
DDQ I/O Supp ly Voltage
3.3
V
V
SS
Supply Voltage
0
V
Temperature
Under Bias
-55 to + 125
TBIAS
____
V
IH
IH
Input High Voltage - Inputs
Input High Voltage - I/O
Input Low Voltage
2.0
V
DD +0.3
V
V
V
2.0
V
DDQ +0.3(1)
0.8
____
____
Storage
-55 to + 125
TSTG
Temperature
V
IL
-0.3(2)
V
5279 tbl 06
P
T
Power Dissipation
DC Output Current
2.0
50
NOTES:
1. VIH (max) = V DDQ + 1.0V for pulse width less than tCYC/2, once per cycle.
2. VIL (min) = -1.0V for pulse width less than tCYC/2, once per cycle.
IOUT
mA
5279 tbl 03
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. VDD terminals only.
3. VDDQ terminals only.
4. Input terminals only.
5. I/O terminals only.
6. This is a steady-state DC parameter that applies after the power supplies have
ramped up. Power supply sequencing is not necessary; however, the voltage
on any input or I/O pin cannot exceed VDDQ during power supply ramp up.
7. TA is the "instant on" case temperature.
100 Pin TQFP Capacitance
(TA = +25°C, f = 1.0MHz)
Symbol
Parameter(1)
Input Capacitance
I/O Cap acitance
Conditions
IN = 3dV
OUT = 3dV
Max. Unit
CIN
V
5
7
pF
CI/O
V
pF
5279 t bl 07
NOTE:
1. This parameter is guaranteed by device characterization, but not production tested.
6.42
4
IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperat ure Ranges
Pin Configuration – 128K x 36
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
80
I/OP3
I/O16
I/O17
I/OP2
I/O15
I/O14
2
79
78
77
3
4
V
DDQ
VDDQ
5
V
SS
76
75
74
73
V
SS
6
I/O18
I/O19
I/O20
I/O21
I/O13
I/O12
I/O11
I/O10
7
8
9
72
71
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
V
SS
VSS
70
69
68
67
66
V
DDQ
VDDQ
I/O22
I/O23
I/O
I/O
9
8
V
DD / NC(1)
VSS
VDD
NC
65
64
NC
V
DD
ZZ(2)
V
SS
I/O24
I/O25
63
62
I/O7
I/O6
61
60
59
58
57
56
55
V
DDQ
V
V
DDQ
SS
V
SS
I/O26
I/O27
I/O28
I/O29
I/O
I/O
I/O
I/O
5
4
3
2
V
SS
VSS
54
53
52
51
V
DDQ
VDDQ
I/O30
I/O31
I/OP4
I/O
I/O
I/OP1
1
,
0
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
5279 drw 02
TQFP
Top View
NOTES:
1. Pin 14 can either be directly connected to V DD, or connected to an input voltage ≥ VIH, or left unconnected.
2. Pin 64 can be left unconnected and the device will always remain in active mode.
6.42
5
IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperat ure Ranges
Pin Configuration – 256K x 18
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
80
NC
NC
NC
A
NC
NC
10
2
79
78
77
3
4
V
DDQ
V
DDQ
5
V
SS
76
75
74
73
V
SS
6
NC
NC
I/O8
NC
I/OP1
I/O
7
8
7
9
I/O9
72
71
70
I/O
6
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
V
SS
V
V
SS
V
DDQ
DDQ
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
I/O10
I/O11
I/O
I/O
5
4
V
DD / NC(1)
V
SS
VDD
NC
NC
V
DD
ZZ(2)
V
SS
I/O12
I/O13
I/O
I/O
3
2
V
DDQ
V
V
DDQ
SS
V
SS
I/O14
I/O15
I/OP2
NC
I/O
I/O
NC
NC
1
0
V
SS
V
V
SS
,
54
53
V
DDQ
NC
NC
NC
DDQ
NC
NC
NC
52
51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
5279 drw 03
TQFP
Top View
NOTES:
1. Pin 14 can either be directly connected to V DD, or connected to an input voltage ≥ VIH, or left unconnected.
2. Pin 64 can be left unconnected and the device will always remain in active mode.
6.42
6
AS8C403600, AS8C401800, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect
Commercial Temperature Range
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(VDD = 3.3V ± 5%)
Symbol
Parameter
Test Conditions
Min.
Max.
Unit
___
|ILI|
Input Le akage Current
V
DD = Max., VIN = 0V to VDD
5
µA
ZZ, LBO and J TAG Input Le akage Current(1)
Output Leakage Current
___
___
___
|ILZZ
|
V
V
DD = Max., VIN = 0V to VDD
30
5
µA
µA
V
|ILO
|
OUT = 0V to VDDQ, Device Deselected
V
OL
OH
Output Low Voltage
IOL = +8mA, VDD = Min.
0.4
___
V
Output High Voltage
IOH = -8mA, VDD = Min.
2.4
V
5279 tbl 08
NOTE:
1. The LBO, TMS, TDI, TCK and TRST pins will be internally pulled to V DD and the ZZ pin will be internally pulled to V SS if they are not actively driven in the application.
DC Electrical Characteristics Over the Operating
(1)
Temperature and SupplyVoltage Range
150MHz
Com'l
133MHz
Com'l
Symbol
Parameter
Test Conditions
Ind
Ind
Unit
Operating Power Supply
Current
Device Selected, Outputs Open, VDD = Max.,
295
305
250
260
mA
IDD
(2)
V
DDQ = Max., VIN > VIH or < VIL, f = fMAX
I
SB1
CMOS Standby Power
Supply Current
Device Deselected, Outputs Open, VDD = Max.,
DDQ = Max., VIN > VHD or < VLD, f = 0(2,3)
30
35
115
35
30
35
110
35
mA
mA
V
ISB2
Clock Run ning Power
Supply Current
Device Deselected, Outputs Open, VDD = Max.,
105
30
100
30
(2,3)
V
DDQ = Max., VIN > VHD or < VLD, f = fMAX
ZZ > VHD, DD = Max.
V
Full Sleep Mode Supply
Current
mA
I
ZZ
5279 t bl 0 9
NOTES:
1. All values are maximum guaranteed values.
2. At f = f MAX, inputs are cycling at the maximum frequency of read cycles of 1/ Tcyc while ADSC = LOW; f=0 means no input lines are changing.
3. For I/Os V HD = V DDQ - 0.2V, V LD = 0.2V. For other inputs V HD = V DD - 0.2V, V LD = 0.2V.
AC Test Conditions
AC Test Load
V
DDQ/2
(VDDQ = 3.3V)
50Ω
Input P ulse Levels
0 to 3V
2ns
I/O
Z0 = 50Ω
Input R ise/Fall T imes
,
5279 drw 06
Input T iming Reference L evels
Output Timing Reference Le vels
AC Test Load
1.5V
Figure 1. AC Test Load
6
5
4
3
1.5V
See Figure 1
5279 t bl 10
ΔtCD
(Typical, ns)
2
1
20 30 50
80 100
Capacitance (pF)
200
5279 drw 07
,
Figure 2. Lumped Capacitive Load, Typical Derating
6.42
7
AS8C403600, AS8C401800, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect
Commercial Temperature Range
Synchronous Truth Table(1,3)
CE
CS1
ADSP ADSC ADV
GW
BWE BWx
OE
(2)
Operation
Address
Used
CS0
CLK
I/O
Deselected Cycle, ower Pown D
Deselected Cycle, ower Pown D
Deselected Cycle, ower Pown D
Deselected Cycle, ower Pown D
Deselected Cycle, ower Pown D
Read Cy cle, Begin B urst
None
None
H
L
X
X
L
X
H
X
H
X
L
X
L
L
X
X
L
X
X
X
X
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
X
H
H
H
H
L
X
X
X
X
X
X
X
H
L
X
X
X
X
X
X
X
X
H
H
L
X
X
X
X
X
L
-
-
-
HI-Z
HI-Z
HI-Z
H- I-Z
HI-Z
None
L
L
None
L
X
L
X
X
L
None
L
L
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
External
External
External
External
External
External
External
Next
L
H
H
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
DOUT
Read Cy cle, Begin B urst
L
L
L
H
L
HI-Z
Read Cy cle, Begin B urst
L
L
H
H
H
H
H
H
H
H
H
X
X
X
X
H
H
X
X
H
H
H
H
X
X
X
X
H
H
X
X
DOUT
Read Cy cle, Begin B urst
L
L
L
L
DOUT
Read Cy cle, Begin B urst
L
L
L
L
H
X
X
L
HI-Z
Write Cycle, Begin Burst
L
L
L
L
D
IN
IN
Write Cycle, Begin Burst
L
L
L
X
H
H
X
X
H
H
X
X
L
X
X
X
H
H
X
X
H
H
L
D
Read Cycle, Continue B urst
Read Cycle, Continue B urst
Read Cycle, Continue B urst
Read Cycle, Continue B urst
Read Cycle, Continue B urst
Read Cycle, Continue B urst
Read Cycle, Continue B urst
Read Cycle, Continue B urst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
Read Cycle, S uspend B urst
Read Cycle, S uspend B urst
Read Cycle, S uspend B urst
Read Cycle, S uspend B urst
Read Cycle, S uspend B urst
Read Cycle, S uspend B urst
Read Cycle, S uspend B urst
Read Cycle, S uspend B urst
Write Cycle, Suspend Burst
Write ycle, CuspenSd urst B
Write Cycle, Suspend Burst
Write Cycle, Suspend Burst
X
X
X
X
H
H
H
H
X
X
H
H
X
X
X
X
H
H
H
H
X
X
H
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
DOUT
Next
L
H
L
HI-Z
Next
L
DOUT
Next
L
H
L
HI-Z
Next
L
DOUT
Next
L
H
L
HI-Z
Next
L
DOUT
Next
L
H
X
X
X
X
L
HI-Z
Next
L
DIN
DIN
DIN
DIN
Next
L
X
L
X
L
Next
L
H
L
Next
L
X
H
H
X
X
H
H
X
X
L
X
X
X
H
H
X
X
H
H
L
Current
Current
Current
Current
Current
Current
Current
Current
Current
Current
Current
Current
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
DOUT
H
L
HI-Z
DOUT
H
L
HI-Z
DOUT
H
L
HI-Z
DOUT
H
X
X
X
X
HI-Z
DIN
DIN
DIN
DIN
X
L
X
L
H
L
X
X
5279 tbl 11
NOTES:
1. L = V IL, H = V IH, X = Don’t Care.
2. OE is an asynchronous input.
3. ZZ = low for this table.
6.42
8
AS8C403600, AS8C401800, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect
Commercial Temperature Range
SynchronousWrite Function Truth Table(1, 2)
GW
BWE
BW1
BW2
BW3
BW4
Operation
Read
H
H
L
X
L
L
L
L
L
X
X
X
X
Read
H
H
X
H
X
H
X
H
X
Write all Bytes
Write all Bytes
Write B yte 1(3)
Write B yte 2(3)
Write B yte 3(3)
Write B yte 4(3)
L
H
L
L
L
L
H
L
H
L
H
H
L
H
H
H
L
H
H
H
H
H
H
H
H
H
5279 tbl 12
NOTES:
1. L = V IL, H = V IH, X = Don’t Care.
2. BW3 andBW4 are not applicable for the AS8C401800.
3. Multiple bytes may be selected during the same cycle.
Asynchronous Truth Table(1)
Operation(2)
OE
ZZ
I/O Status
Power
Read
Read
L
H
X
X
X
L
L
L
L
H
Data O ut
High-Z
Active
Active
Active
Standby
Sleep
Write
High-Z – Data In
High-Z
Deselected
Sleep Mode
High-Z
5279 tbl 13
NOTES:
1. L = V IL, H = V IH, X = Don’t Care.
2. Synchronous function pins must be biased appropriately to satisfy operation requirements.
Interleaved Burst SequenceTable (LBO=VDD)
Sequence 1
Sequence 2
Sequence 3
Sequence 4
A1
A0
0
A1
A0
1
A1
1
A0
A1
A0
First Address
0
0
1
1
0
0
1
1
0
1
0
1
1
1
0
0
1
Second Address
Third Address
1
0
1
0
0
1
0
1
Fourth Address(1)
1
0
0
0
5279 tbl 14
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state.
Linear Burst Sequence Table (LBO=VSS)
Sequence 1
Sequence 2
Sequence 3
Sequence 4
A1
0
A0
0
A1
0
A0
1
A1
1
A0
0
A1
1
A0
First Address
1
Second Address
Third Address
0
1
1
0
1
1
0
0
1
0
1
1
0
0
0
1
Fourth Address(1)
1
1
0
0
0
1
1
0
5279 tbl 15
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state.
6.42
9
AS8C403600, AS8C401800, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect
Commercial Temperature Range
AC Electrical Characteristics
(VDD = 3.3V ±5%, Commercial and Industrial Temperature Ranges)
150MHz
133MHz
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
____
____
____
____
t
CY C
Clock Cycle Time
6.7
2.6
2.6
7.5
3
ns
ns
ns
(1 )
CH
Clock High P ulse Width
Clock Low Pulse Width
t
(1)
CL
____
____
3
t
Output Parameters
____
____
t
CD
Clock High to Valid Data
3.8
4.2
ns
ns
ns
____
____
tCDC
Clock High to Data Cha nge
1.5
0
1.5
0
____
____
(2)
CLZ
Clock High to Output Active
Clock High to Data Hi gh-Z
t
(2)
1.5
3.8
1.5
4.2
ns
ns
ns
ns
tCHZ
____
____
tOE
Output Enable Access Time
Output Enable Lo w to Output Active
Output Enable High to Output High-Z
3.8
4.2
____
____
(2)
(2)
0
0
tOL Z
____
____
3.8
4.2
tOHZ
Set Up Times
____
____
____
____
____
____
____
____
____
____
____
____
t
SA
SS
SD
SW
SAV
SC
Address Setup Time
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
ns
ns
ns
ns
ns
ns
t
Address Status Setup Time
Data In S etup Time
t
t
Write Setup Time
t
Address Advance Setup Time
Chip Enable/Select Setup Time
t
Hold Times
____
____
____
____
____
____
____
____
____
____
____
____
t
HA
HS
HD
HW
HAV
HC
Address Hold Time
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
ns
ns
ns
ns
ns
ns
t
Address Status Hold Time
Data In Ho ld Time
t
t
Write Hold Time
t
Address Advance Hold Time
Chip Enable/Select Hold Time
t
Sleep M ode and Configuration Parameters
____
____
____
____
t
ZZP W
ZZ Pulse Width
100
100
27
100
100
30
ns
ns
(3)
ZZ R ecovery Time
Configuration Set-up Time
tZZR
____
____
(4 )
ns
tCFG
5279 t bl 16
NOTES:
1. Measured as HIGH above VIH and LOW below VIL.
2. Transition is measured ±200mV from steady-state.
3. Device must be deselected when powered-up from sleep mode.
4. tCFG is the minimum time required to configure the device based on the
LBO input. LBO is a static input and must not change during normal operation.
6.42
10
IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperat ure Ranges
Timing Waveform of Pipelined Read Cycle(1,2)
,
6.42
11
IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperat ure Ranges
Timing Waveform of Combined Pipelined Read and Write Cycles(1,2,3)
,
6.42
12
IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperat ure Ranges
Timing Waveform of Write Cycle No. 1 - GW Controlled(1,2,3)
,
6.42
13
IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperat ure Ranges
(1,2,3)
Timing Waveform of Write Cycle No. 2 - Byte Controlled
,
6.42
14
IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperat ure Ranges
Timing Waveform of Sleep (ZZ) and Power-Down Modes(1,2,3)
,
6.42
15
AS8C403600, AS8C401800, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect
Commercial Temperature Range
Non-Burst Read Cycle Timing Waveform
CLK
ADSP
ADSC
Av
Aw
Ax
Ay
Az
ADDRESS
GW, BWE, BWx
CE, CS
1
0
CS
OE
(Av)
(Aw)
(Ax)
(Ay)
DATAOUT
,
5279 drw 14
NOTES:
1. ZZ input is LOW,ADV is HIGH andLBO is Don't Care for this cycle.
2. (Ax) represents the data for address Ax, etc.
3. For read cycles,ADSP andADSCfunction identically and are therefore interchangable.
Non-Burst Write Cycle Timing Wa veform
CLK
ADSP
ADSC
Av
Aw
Ax
Ay
Az
ADDRESS
GW
CE, CS
1
CS0
(Av)
(Aw)
(Ax)
(Ay)
(Az)
DATAIN
,
5279 drw 15
NOTES:
1. ZZ input is LOW, ADV and OE are HIGH, and LBO is Don't Care for this cycle.
2. (Ax) represents the data for address Ax, etc.
3. Although only GW writes are shown, the functionality of BWE and BWx together is the same as GW.
4. For write cycles, ADSP and ADSC have different limitations.
6.42
16
AS8C403600, AS8C401800, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect
Commercial Temperature Range
ORDERING INFORMATION
VCC
Range
Speed
Operating Temp
Mhz
Alliance
Organization
Package
AS8C403600-QC150N
AS8C401800-QC150N
128K x 36
256K x 18
3.1 - 3.4V
3.1 - 3.4V
100 pin TQFP
100 pin TQFP
Commercial: 0 C - 70C
Commercial: 0 C - 70C
150
150
PART NUMBERING SYSTEM
Device
Conf.
Mode
Package
Q = 100 Pin TQFP
Operating Temp
N
AS8C
Speed
01= ZBT
00 = Pipelined
25 = Flow- Thru
0 ~ 70C
150MHz N= Leadfree
Sync.
SRAM prefix
18= x18
36 = x36
40 = 4M
O
R
D
E
R
I
G
I
F
O
R
M
A
T
I
N
A
l
i
n
c
e
Organiza it on
512K 16
R
V
C
C
e
Package
Operat
i
g
T
e
m
p
S
p
e
e
d
A
S
6
C
8
0
16
A
-
B
N
x
16
22
.
-
5
.
V
44pin
8
b
a
l
F
B
G
A
I
Indust
r
~
0
C
-
85
C
55
P
A
R
T
N
U
M
B
E
R
I
G
S
Y
S
T
E
M
AS6C
8016
evi x1ec 6
-5
X
X
N
D
=
8
N
u
mber
c
e
s
s
Pa
-
ge
n
O
S
O
P
T
=
m
n
d
u
s
t
e
Roc
Lea
Free
S
R
A
owe
p
r
r
ix
6
=
T
i
4
+
85
C)
o
l
n
t
par
t
®
Alliance Memory, Inc.
551 Taylor way, Suite#1,
San Carlos, CA 94070
Tel: 650-610-6800
Copyright © Alliance Memory
All Rights Reserved
Part Number: AS8C403600/401800
Document Version: v. 1.0
Fax: 650-620-9211
www.alliancememory.com
© Copyright 2003 Alliance Memory, Inc. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of
Alliance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make changes to this
document and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document. The data
contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at any
time, without notice. If the product described herein is under development, significant changes to these specifications are possible. The information in
this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide,
any guarantee or warrantee to any user or customer. Alliance does not assume any responsibility or liability arising out of the application or use of any
product described herein, and disclaims any express or implied warranties related to the sale and/or use of Alliance products including liability or
warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in
Alliance's Terms and Conditions of Sale (which are available from Alliance). All sales of Alliance products are made exclusively according to Alliance's
Terms and Conditions of Sale. The purchase of products from Alliance does not convey a license under any patent rights, copyrights; mask works rights,
trademarks, or any other intellectual property rights of Alliance or third parties. Alliance does not authorize its products for use as critical components in
life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of
Alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify Alliance against all
claims arising from such use.
17
6.42
相关型号：
©2020 ICPDF网 联系我们和版权申明