S3043A [AMCC]
Transmitter, 1-Func, Bipolar, PQFP80, HEAT SINK, PLASTIC, QFP-80;
| 型号： | S3043A |
| 厂家： | 
APPLIED MICRO CIRCUITS CORPORATION |
| 描述： | Transmitter, 1-Func, Bipolar, PQFP80, HEAT SINK, PLASTIC, QFP-80 ATM 异步传输模式 电信 电信集成电路 |
| 文件： | 总25页 (文件大小：158K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
DEVICE
SPECIFICATION
SONET/SDH/ATM OC-48 16:1 TRANSMITTER
S3043
GENERAL DESCRIPTION
FEATURES
• Micro-power Bipolar supply
• Complies with Bellcore, and ITU-T
specifications
• On-chip high-frequency PLL for clock
generation
• Supports 2.488 Gbps (OC-48)
• Reference frequency of 155.52 MHz
• Interface to both LVPECL and LVTTL logic
• 16-bit LVPECL data path
• Compact 80 PQFP/TEP package
• Diagnostic loopback mode
• Line loopback
The S3043 SONET/SDH MUX chip is a fully integrated
serialization SONET OC-48 (2.488 Gbps) interface de-
vice. The chip performs all necessary parallel-to-serial
functions in conformance with SONET/SDH transmis-
sion standards. The device is suitable for SONET-
based ATM applications. Figure 1 shows a typical
network application.
On-chip clock synthesis PLL components are con-
tained in the S3043 MUX chip allowing the use of a
slower external transmit clock reference. The chip
can be used with a 155.52 MHz reference clock, in
support of existing system clocking schemes.
• Lock detect
• Low jitter LVPECL interface
• Single 3.3V supply
The low jitter LVPECL interface guarantees compli-
ance with the bit-error rate requirements of the
Bellcore, and ITU-T standards. The S3043 is pack-
aged in an 80 PQFP/TEP, offering designers a small
package outline.
APPLICATIONS
• SONET/SDH-based transmission systems
• SONET/SDH modules
• SONET/SDH test equipment
• ATM over SONET/SDH
• Section repeaters
• Add Drop Multiplexers (ADM)
• Broad-band cross-connects
• Fiber optic terminators
• Fiber optic test equipment
Figure 1. System Block Diagram
16
16
S3043
Tx
S3044
OTX
ORX
S3040
OTX
Rx
16
16
S3044
Rx
S3043
Tx
S3040
ORX
August 10, 1999 / Revision E
1
S3043
SONET/SDH/ATM OC-48 16:1 TRANSMITTER
part of each STS-N signal is an optical carrier level-N
signal (OC-N). The S3043 chip supports the OC-48
rate (2.488 Gbps).
SONET OVERVIEW
Synchronous Optical Network (SONET) is a standard
for connecting one fiber system to another at the opti-
cal level. SONET, together with the Synchronous
Digital Hierarchy (SDH) administered by the ITU-T,
forms a single international standard for fiber inter-
connect between telephone networks of different
countries. SONET is capable of accommodating a
variety of transmission rates and applications.
Frame and Byte Boundary Detection
The SONET/SDH fundamental frame format for STS-48
consists of 144 transport overhead bytes followed by
Synchronous Payload Envelope (SPE) bytes. This
pattern of 144 overhead and 4176 SPE bytes is re-
peated nine times in each frame. Frame and byte
boundaries are detected using the A1 and A2 bytes
found in the transport overhead. (See Figure 3.)
The SONET standard is a layered protocol with four
separate layers defined. These are:
• Photonic
• Section
• Line
For more details on SONET operations, refer to the
Bellcore SONET standard document.
• Path
Figure 2. SONET Structure
Figure 2 shows the layers and their functions. Each
of the layers has overhead bandwidth dedicated to
administration and maintenance. The photonic layer
simply handles the conversion from electrical to optical
and back with no overhead. It is responsible for
transmitting the electrical signals in optical form over
the physical media. The section layer handles the
transport of the framed electrical signals across the
optical cable from one end to the next. Key functions
of this layer are framing, scrambling, and error moni-
toring. The line layer is responsible for the reliable
transmission of the path layer information stream
carrying voice, data, and video signals. Its main
functions are synchronization, multiplexing, and reli-
able transport. The path layer is responsible for the
actual transport of services at the appropriate signaling
rates.
Functions
Payload to
SPE mapping
Path layer
Line layer
Path layer
Line layer
Maintenance,
protection,
switching
Scrambling,
framing
Section layer
Section layer
Optical
transmission
Photonic layer
Photonic layer
Fiber Cable
End Equipment
End Equipment
Table 1. SONET Signal Hierarchy
Data Rates and Signal Hierarchy
Elec.
STS-1
CCITT
Optical Data Rate (Mbps)
OC-1
51.84
Table 1 contains the data rates and signal designations
of the SONET hierarchy. The lowest level is the basic
SONET signal referred to as the synchronous transport
signal level-1 (STS-1). An STS-N signal is made up of
N byte-interleaved STS-1 signals. The optical counter-
STS-3
STM-1
STM-4
STM-8
STM-16
OC-3
155.52
622.08
1244.16
2488.32
STS-12
STS-24
STS-48
OC-12
OC-24
OC-48
Figure 3. STS-48/OC-48 Frame Format
A1 A1
A1 A1
A2 A2
A2 A2
48 A1
Bytes
48 A2
Bytes
Synchronous Payload Envelope 4176 Columns
4176 x 9 = 37,584 bytes
Transport Overhead 144 Columns
144 x 9 = 1296 bytes
125 µsec
2
August 10, 1999 / Revision E
SONET/SDH/ATM OC-48 16:1 TRANSMITTER
S3043 OVERVIEW
S3043
The sequence of operations is as follows:
Transmitter Operations:
The S3043 transmitter implements SONET/SDH se-
rialization and transmission functions. The block dia-
gram in Figure 4 shows the basic operation of the
chip. This chip can be used to implement the front
end of SONET equipment, which consists primarily
of the serial transmit interface and the serial receive
interface. The chip includes parallel-to-serial conver-
sion and system timing. The system timing circuitry
consists of a high-speed phase detector, clock divid-
ers, and clock distribution throughout the front end.
1. 16-bit parallel input
2. Parallel-to-serial conversion
3. Serial output
Internal clocking and control functions are transpar-
ent to the user. Details of data timing can be seen in
Figures 7, 16 and 17.
Suggested Interface Devices
AMCC
AMCC
S3040
S3044
OC-48 Clock Recovery Device
OC-48 Receiver
Figure 4. S3043 Functional Block Diagram
DLEB
LLDP/N
LLCLKP/N
LLEB
LSDP/N
M
U
X
16
D
TSDP/N
PIN[15:0]
16:1 PARALLEL
PICLKP/N
TO SERIAL
LSCLKP/N
TSCLKP/N
M
U
X
PCLKP/N
PULSE
TIMING
GEN
READ
TESTEN
LOCKDET
155MCK
CLOCK
DIVIDER and
PHASE DETECTOR
REFCLKP/N
RSTB
2
CAP1/2
August 10, 1999 / Revision E
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S3043
SONET/SDH/ATM OC-48 16:1 TRANSMITTER
The PCLK output is a byte rate version of TSCLK.
For STS-48, the PCLK frequency is 155.52 MHz.
PCLK is intended for use as a byte speed clock for
upstream multiplexing and overhead processing cir-
cuits. Using PCLK for upstream circuits will ensure a
stable frequency and phase relationship between the
data coming into and leaving the S3043 device.
S3043 ARCHITECTURE/FUNCTIONAL
DESIGN
MUX OPERATION
The S3043 performs the serializing stage in the pro-
cessing of a transmit SONET STS-48 bit serial data
stream. It converts the byte serial 155.52 Mbyte/sec
data stream to bit serial format at 2.488 Gbps. Diag-
nostic loopback is provided (transmitter to receiver),
and Line Loopback is also provided (receiver to trans-
mitter).
In the parallel-to-serial conversion process, the in-
coming data is passed from the PICLK byte clock
timing domain to the internally generated byte clock
timing domain, which is phase aligned to TSCLK.
A high-frequency bit clock is generated from a
155.52 MHz frequency reference by using a fre-
quency synthesizer consisting of an on-chip phase-
locked loop circuit with a divider, VCO and loop filter.
The timing generator also produces a feedback ref-
erence clock to the Phase Detector. A counter divides
the synthesized clock down to the same frequency
as the reference clock REFCLK.
Clock Divider and Phase Detector
Parallel-to-Serial Converter
The clock divider and phase detector, shown in the
block diagram in Figure 4, contains monolithic PLL
components that generate signals required to drive
the loop filter.
The parallel-to-serial converter shown in Figure 4 is
comprised of two byte-wide registers. The first register
latches the data from the PIN[15:0] bus on the rising
edge of PICLK. The second register is a parallel
loadable shift register which takes its parallel input
from the first register.
The REFCLK input must be generated from a differ-
ential LVPECL crystal oscillator which has a fre-
quency accuracy of better than 20 ppm in order for
the VCOCLK frequency to have the same accuracy
required for operation in a SONET system.
An internally generated byte clock, which is phase
aligned to the transmit serial clock as described in the
Timing Generator description, activates the parallel
data transfer between registers. The serial data is
In order to meet the 0.01 UI SONET jitter specifica-
tions, the maximum reference clock jitter must be
guaranteed over the 12 kHz to 20 MHz bandwidth.
For details of reference clock jitter requirements, see
Table 2.
shifted out of the second register at the TSCLK rate
.
OTHER OPERATING MODES
The on–chip phase detector, which compares the
phase relationship between the VCO input and the
REFCLK input, drives the loop filter.
Diagnostic Loopback
When the Diagnostic Loopback Enable (DLEB) input
is low, a loopback from the transmitter to the re-
ceiver at the serial data rate can be set up for diag-
nostic purposes. The differential serial output data
from the transmitter is routed to the receiver in place
of the normal data stream (RSD).
Timing Generator
The timing generator function, seen in Figure 4, pro-
vides two separate functions. It provides a byte rate
version of the TSCLK, and a mechanism for aligning
the phase between the incoming byte clock and the
clock which loads the parallel-to-serial shift register.
Line Loopback
The line loopback circuitry consists of alternate clock
and data output drivers. For the S3043, it selects the
source of the data and clock which is output on TSD
and TSCLK. When the Line Loopback Enable
(LLEB) input is active, it selects data and clock from
the Parallel to Serial Converter block. When LLEB is
inactive, it forces the output data multiplexer to se-
lect data and clock from the LLD and LLCLK inputs,
and a receive-to-transmit loopback can be estab-
lished at the serial data rate.
Table 2. Reference Jitter Limits
Maximum Reference Clock Jitter in
12 kHz to 20 MHz Band
Operating
Mode
1 ps rms
STS-48
4
August 10, 1999 / Revision E
SONET/SDH/ATM OC-48 16:1 TRANSMITTER
S3043
Table 3. Input Pin Assignment and Descriptions
Pin Name
Level
I/O
Pin #
Description
PIN0
PIN1
PIN2
PIN3
PIN4
PIN5
PIN6
PIN7
Single-
Ended
LVPECL
I
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
Parallel Data Input. A 155.52 Mbyte/sec word, aligned to the
PICLK parallel input clock. PIN[15] is the most significant bit
(corresponding to bit 1 of each PCM word, the first bit transmitted).
PIN[0] is the least significant bit (corresponding to bit 16 of each
PCM word, the last bit transmitted). PIN[15:0] is sampled on the
rising edge of PICLK.
PIN8
PIN9
PIN10
PIN11
PIN12
PIN13
PIN14
PIN15
PICLKP
PICLKN
Diff.
LVPECL
I
I
I
22
21
Parallel Input Clock. A 155.52 MHz nominally 50% duty cycle
input clock, to which PIN[15:0] is aligned. PICLK is used to
transfer the data on the PIN inputs into a holding register in the
parallel-to-serial converter. The rising edge of PICLK samples
PIN[15:0].
LLDP
LLDN
Externally
Biased
Diff.
14
15
Line Loopback Data. Inputs normally provided from a
companion S3044 device. Used to implement a line loopback
function in which the receive serial bit serial data and clock
signals are regenerated and passed through the S3043
transmitter. Internally terminated.
LVPECL
LLCLKP
LLCLKN
Externally
Biased
Diff.
11
12
Line Loopback Clock. Inputs normally provided from a
companion S3044 device. Used to implement a line loopback
function in which the receive serial bit serial data and clock
signals are regenerated and passed through the S3043
transmitter. Internally terminated.
LVPECL
TESTEN
LVTTL
I
I
13
Test Clock Enable. Set High to provide access to the PLL during
production tests.
REFCLKP
REFCLKN
Internally
Biased
Diff.
78
77
Reference Clock. Input used as the reference for the internal bit
clock frequency synthesizer. Internally terminated and biased.
LVPECL
DLEB
RSTB
LVTTL
I
I
8
9
Diagnostic Loopback Enable. Active Low. When active, selects
diagnostic loopback. When DLEB is inactive, LSD and LSCLK
are powered down and inactive. When active, the diagnostic
loopback clock, (LSCLK), and data (LSD) outputs are active.
TSD and TSCLK remain active in both states of DLEB.
LVTTL
Master Reset. Reset input for the device, active Low. During
reset, PCLK does not toggle.
August 10, 1999 / Revision E
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S3043
SONET/SDH/ATM OC-48 16:1 TRANSMITTER
Table 3. Input Pin Assignment and Descriptions (Continued)
Pin Name
LLEB
Level
I/O
Pin #
Description
LVTTL
I
5
Line Loopback Enable. Selects Line Loopback. Active Low.
When LLEB is active, the S3043 will route the data from the
LLD/LLCLK inputs to the TSD/TSCLK outputs.
CAP1
CAP2
Analog
I
I
67
66
Loop Filter Pins. Connections for external loop filter capacitor
and resistors.
READ
Single-
Ended
LVPECL
45
Elastic Store Write Single-Ended Input. This input pin is clocked
in using the rising edge of PICLK clock. This input is used to align
the elastic store. The S3043 MUX will monitor the READ input for
a fault condition.
6
August 10, 1999 / Revision E
SONET/SDH/ATM OC-48 16:1 TRANSMITTER
S3043
Table 4. Output Pin Assignment and Descriptions
Pin Name
Level
I/O
Pin #
Description
TSCLKP
TSCLKN
Diff.
CML
O
57
56
Transmit Clock Output. Transmit serial clock output that can be
used to retime the TSD signal.
TSDP
TSDN
Diff.
CML
O
O
55
54
Transmit Serial Data. Serial data stream signals, normally
connected to an optical transmitter module.
PCLKP
PCLKN
Diff.
LVPECL
23
24
Parallel Clock. A reference clock generated by dividing the internal
bit clock by sixteen. It is normally used to coordinate byte-wide
transfers between upstream logic and the S3043 device.
LSDP
LSDN
O
6
7
Loopback Serial Data. Serial data stream signals normally
connected to a companion S3044 device for diagnostic loopback
purposes. The LSD outputs are updated on the falling edge of the
LSCLK.
Low Swing
Diff.
CML
LSCLKP
LSCLKN
O
O
1
2
Loopback Serial Clock. Serial clock signals normally connected
to a companion S3044 device for diagnostic loopback purposes.
The LSD outputs are updated on the falling edge of the LSCLK.
Low Swing
Diff.
CML
155MCK
Single-
Ended
LVPECL
20
155 MHz Clock Output. 155 MHz clock output from the clock
synthesizer. This output should be connected to the reference
clock input of the external clock recovery function (such as the
S3040).
PULSE
Single-
Ended
LVPECL
O
O
43
Elastic Store Read Single-Ended Outputs. This output pulse is
sychronized with the falling edge of PCLKP/N. This signal is used
to align the elastic store. The PULSE output should be active for
only one pulse every third 155 MHz clock cycle during the normal
(no fault) operation.
LOCKDET
LVTTL
47
Lock Detect. Goes Low after the PLL has locked to the clock
provided on the REFCLK pins. LOCKDET is an asynchronous
output.
August 10, 1999 / Revision E
7
S3043
SONET/SDH/ATM OC-48 16:1 TRANSMITTER
Table 5. Common Pin Assignment and Description
Pin Name
Level
I/O
Pin #
Description
COREGND
GND
51, 61,
Core Ground
63, 65, 75
COREVCC
LVPECLVCC
LVPECLGND
TTLVCC
+3.3V
+3.3V
GND
50, 60,
62, 64, 70
Core VCC
3, 16, 17, LVPECL VCC
52, 59
4, 10, 18, LVPECL Ground
53, 58
+3.3V
GND
48
TTL VCC
LVTTLGND
NC
19
TTL Ground
44, 46,
49, 76
Not Connected
LVPECL VCC
LVPECL Ground
Analog VCC
Analog Ground
LVPECLVCC
LVPECLGND
AVCC
+3.3V
GND
+3.3V
GND
41
42
69, 72,
74, 80
AGND
68, 71
73, 79
8
August 10, 1999 / Revision E
SONET/SDH/ATM OC-48 16:1 TRANSMITTER
S3043
Figure 5. S3043 Pinout
LSCLKP
LSCLKN
LVPECLVCC
LVPECLGND
60
59
58
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
COREVCC
LVPECLVCC
LVPECLGND
TSCLKP
TSCLKN
TSDP
57
56
55
54
53
52
51
50
LLEB
LSDP
LSDN
DLEB
RSTB
TSDN
S3043
LVPECLGND
LVPECLVCC
COREGND
COREVCC
NC
TTLVCC
LOCKDET
NC
READ
NC
PULSE
LVPECLGND
LVPECLGND
LLCLKP
80 PQFP/TEP
TOP VIEW
49
48
47
LLCLKN
TESTEN
LLDP
LLDN
LVPECLVCC
LVPECLVCC
LVPECLGND
LVTTLGND
46
45
44
43
42
41
LVPECLVCC
155MCK
20
August 10, 1999 / Revision E
9
S3043
SONET/SDH/ATM OC-48 16:1 TRANSMITTER
Figure 6. 80 PQFP/TEP Package
BOTTOM VIEW
TOP VIEW
Note: The S3043 package is equipped with an embedded conductive heatsink on the bottom (board side). Active circuitry and
vias should not appear in the area immediately under the package. This heatsink is electrically biased to the Vee potential of the
S3043. For optimum thermal management, a foil surface at ground (or Vee if other than ground) is recommended immediately
under the package, and connected with multiple vias to the internal plane(s) of similar potential. Thermally conductive epoxy or
other conductive interposer can be used to establish a good thermal dissipation path.
Table 6. Thermal Management
Θjc
Device
Max
S3043
1.56 W
2.1˚C/W
1. Add 0.24W for loopback active.
10
August 10, 1999 / Revision E
SONET/SDH/ATM OC-48 16:1 TRANSMITTER
S3043
Table 7. Performance Specifications
Parameter
Min
Typ
Max
Units
Conditions
Nominal VCO Center
Frequency
2.488
±12%
GHz
TSCLK Clock Output
Jitter
OC-48/STS-48
0.01
UI (rms)
Data Output Jitter
STS-48
155.52 MHz Ref. Clk.
0.01
UI (rms)
ppm
rms jitter, in lock.
± 20 ppm. Required to meet
SONET output frequency
specification.
Reference Clock
Frequency Tolerance
-100
30
+100
Reference Clock Input
Duty Cycle
70
%
Reference Clock Rise &
Fall Times
1.5
ns
20% to 80% of amplitude.
Table 8. Absolute Maximum Ratings
Parameter
Min
-65
-0.5
-0.5
0
Typ
Max Units
Storage Temperature
150
+5.0
+5.5
VCC
8
˚ C
V
Voltage on VCC with Respect to GND
Voltage on any LVTTL Input Pin
Voltage on any LVPECL Input Pin
LVTTL Output Sink Current
V
V
mA
mA
mA
V
LVTTL Output Source Current
High Speed LVPECL Output Source Current
8
50
Static Discharge Voltage1
500
1. Except CAP1, CAP2.
Table 9. Recommended Operating Conditions
Parameter
Min
Typ
Max Units
Ambient Temperature Under Bias
Junction Temperature Under Bias
-40
85
˚ C
˚ C
V
130
Voltage on VCC with Respect to GND
Voltage on any LVPECL Input Pin
3.135
3.3
3.465
VCC
-2
VCC
V
August 10, 1999 / Revision E
11
S3043
SONET/SDH/ATM OC-48 16:1 TRANSMITTER
Table 10. Power Consumption
Parameter
Min
Typ
Max Units
450 mA
ICC1
383
1. Add 70 mA for loopback active.
Table 11. LVTTL Input/Output DC Characteristics
Symbol
Description
Conditions
Min
Typ
Max
Unit
TTL VCC
+ 1.0
VIH
Input High Voltage
TTL VCC = Max
2.0
0.0
V
VIL
IIH
IIL
Input Low Voltage
Input High Current
Input Low Current
TTL VCC = Max
VIN = 2.4 V
0.8
50
V
µA
µA
VIN = 0.5 V
-500
2.1
VIH = Min.
VIL = Max.
VOH
Output High Voltage
Output Low Voltage
V
V
I
OH = -100 µA
VIH = Min.
VIL = Max.
IoL = 4 mA
VOL
0.5
Table 12. Differential CML Output DC Characteristics
Parameter
Description
Min
Typ
Max Units
Condition
Vcc
-0.95
Vcc
V
VOL
VOH
CML Output LOW Voltage
100Ω line-to-line.
-0.55
Vcc
-0.35
Vcc
V
CML Output HIGH Voltage
100Ω line-to-line.
-0.10
CML Serial Output Differential
Voltage Swing
100Ω line-to-line. See
Figure 18.
∆VOUTDIFF
560
280
1300
650
mV
mV
CML Serial Output Single-
ended Voltage Swing
100Ω line-to-line. See
Figure 18.
∆VOUTSINGLE
Table 13. Low Swing Differential CML Output DC Characteristics
Parameters
Description
Min
Typ
Max
Units
Conditions
Vcc
-0.50
Vcc
-0.25
VOL
Loopback CML Output LOW Voltage
V
V
100Ω line-to-line.
Vcc
-0.20
Vcc
-0.05
VOH
Loopback CML Output HIGH Voltage
100Ω line-to-line.
100Ω line-to-line.
100Ω line-to-line.
Loopback CML Serial Output
Differential Voltage Swing
∆VOUTDIFF
360
180
800
400
mV
mV
Loopback CML Serial Output
Single-ended Voltage Swing
∆VOUTSINGLE
12
August 10, 1999 / Revision E
SONET/SDH/ATM OC-48 16:1 TRANSMITTER
S3043
Table 14. Internally Biased Differential LVPECL Input DC Characteristics
Parameters
∆VINDIFF
Description
Min
300
150
80
Typ
Max
1200
600
Units
mV
mV
Ω
Conditions
See Figure 18.
See Figure 18.
Differential Input Voltage Swing
Single-ended Input Voltage Swing
Differential Input Resistance
∆VINSINGLE
RDIFF
100
120
Table 15. Externally Biased Differential LVPECL Input DC Characteristics
Parameters
Description
Min
Typ
Max
Units
Conditions
VBIAS
LVPECL DC Bias Voltage
V
Inputs open.
Vcc -1.2
Vcc -0.8
Vcc
-2.000
Vcc
-0.25
VIL
VIH
LVPECL Input LOW Voltage
LVPECL Input HIGH Voltage
V
V
Vcc
-1.20
Vcc
-0.05
∆VINDIFF
∆VINSINGLE
RDIFF
Differential Input Voltage Swing
Single-ended Input Voltage Swing
Differential Input Resistance
300
150
80
1200
600
mV
mV
Ω
See Figure 18.
See Figure 18.
100
120
Table 16. Single Ended LVPECL Input DC Characteristics1
Parameters
Description
Min
Typ
Max
Units
Conditions
Vcc
-2.30
Vcc
-1.441
VIL
PECL Input Low Voltage
V
Guaranteed at 85˚ C.
Guaranteed at 85˚ C.
Vcc
-1.250
Vcc
-0.570
VIH
PECL Input High Voltage
V
1. The AMCC LVPECL inputs (VIL and VIH) are non-temperature compensated I/O which vary at 1.3mV/C.
Table 17. Single Ended LVPECL Output DC Characteristics1
Parameters
Description
Min
Typ
Max
Units
Conditions
Vcc
-2.2
Vcc
-1.50
VOL
PECL Output Low Voltage
V
Vcc
-1.2
Vcc
-0.65
VOH
PECL Output High Voltage
V
1. For 155MCK and Pulse signals. Maximum voltage swing = 500 mV for these two signals.
August 10, 1999 / Revision E
13
S3043
SONET/SDH/ATM OC-48 16:1 TRANSMITTER
Table 18. Differential LVPECL Input DC Characteristics
Parameters
Description
Min
Typ
Max Units
Comments
Vcc
-2.0
Vcc
V
VIL
LVPECL Input Low
-0.5
Vcc
-1.2
Vcc
V
VIH
LVPECL Input High
-0.3
∆VINDIFF
Diff. Input Voltage Swing
400
200
2000
1000
mV
mV
See Figure 18.
See Figure 18.
∆VINSINGLE
Single Ended Input Voltage Swing
Table 19. Differential LVPECL Output DC Characteristics
Parameters
Description
Min
Typ
Max Units
Comments
220Ω to GND, 100Ω line to
line. See Figure 12.
∆VOUTSINGLE
Single Ended Output Voltage Swing
550
950
mV
mV
V
220Ω to GND, 100Ω line to
line. See Figure 12.
∆VOUTDIFF
Diff. Output Voltage Swing
Output High Voltage
Output Low Voltage
1100
1900
Vcc
-1.15
Vcc
-0.60
220Ω to GND, 100Ω line to
line. See Figure 12.
VOH
Vcc
-1.95
Vcc
-1.50
220Ω to GND, 100Ω line to
line. See Figure 12.
VOL
V
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August 10, 1999 / Revision E
SONET/SDH/ATM OC-48 16:1 TRANSMITTER
S3043
Figure 7. Line Loopback Input Timing Diagram
LLCLKP
tS
tH
LLD
LLD
LLDP/N
Notes on High-Speed LVPECL Input Timing:
1. Timing is measured from the cross-over point of the reference signal to the cross-over point of the input.
Table 20. AC Transmitter Timing Characteristics
Symbol
Description
TSCLK/LSCLK Frequency (nom. 2.48 GHz)
TSCLK/LSCLK Duty Cycle
Min
Max
2.6
60
Units
GHz
%
40
40
PICLK Duty Cycle
60
%
tSPIN
READ, PIN [15.0] Set-up Time w.r.t. PICLKP
READ, PIN [15.0] Hold Time w.r.t. PICLKP
TSCLK/LSCLK Low to TSD/LSD Valid Propagation Delay*
TSD/LSD Set-up Time w.r.t. TSCLK/LSCLK
TSD/LSD Hold Time w.r.t. TSCLK/LSCLK
LLDP/N Set-up Time w.r.t. LLCLKP/N
LLDP/N Hold Time w.r.t. LLCLKP/N
PCLKP/N Duty Cycle
1.5
0.5
-100
105
105
100
100
43
ns
ns
ps
ps
ps
ps
ps
%
tHPIN
tPTSD
tSTSD
tHTSD
tSLLD
tHLLD
100
57
170
13
CML Output Rise and Fall Time (20% - 80%)
PICLK Delay from PCLK
ps
ns
ns
ns
ns
ns
tPPICLK
0
tPPRCLK
tSPULSE
tHPULSE
tPREFCLK
READ Delay from PULSE
0
13
PULSE Set-up Time w.r.t. PCLK
PULSE Hold Time w.r.t. PCLK
1.8
2.0
PCLK Delay from REFCLK
6.5
* Measured at 50/50 nominal duty cycle.
August 10, 1999 / Revision E
15
S3043
SONET/SDH/ATM OC-48 16:1 TRANSMITTER
Figure 8. External Loop Filter
2.2 µF
75Ω
CAP2
75Ω
CAP1
Figure 9. CML Output to +5V PECL Input AC Coupled Termination
+3.3V
+5V
0.01 µF
0.01 µF
Zo=50Ω
Zo=50Ω
100Ω
S3043
TSDP/N
TSCLKP/N
Figure 10. -5V Single Ended ECL Driver to S3043 Input AC Coupled Termination
+3.3V
-5.2V
+3.3V
0.01 µF
82Ω
330Ω
-5.2V
Zo=50Ω 130Ω
ECL
S3043
16
August 10, 1999 / Revision E
SONET/SDH/ATM OC-48 16:1 TRANSMITTER
S3043
Figure 11. +5V Differential PECL Driver to S3043 Input AC Coupled Termination
3.3V
82Ω
130Ω
+5V
+3.3V
0.01µF
0.01µF
Zo=50Ω
Zo=50Ω
330Ω
3.3V
82Ω
130Ω
330Ω
S3043
PICLKP/N
Figure 12. S3043 to S3043 Terminations
+3.3V
+3.3V
Zo=50Ω
220Ω
100Ω
Zo=50Ω
220Ω
S3043
PCLKP/N
S3043
PICLKP/N
August 10, 1999 / Revision E
17
S3043
SONET/SDH/ATM OC-48 16:1 TRANSMITTER
Figure 13. Single-Ended PECL Output Termination
+3.3V
+3.3V
Zo=50Ω
330 Ω
S3043
READ
S3043
PULSE
Figure 14. S3043 to S3044 for Diagnostic Loopback
+3.3V
+3.3V
Zo=50Ω
100Ω
Zo=50Ω
S3043
LSDP/N
S3044
LSDP/N
LSCLKP/N
LSCLKP/N
Figure 15. Single-Ended LVPECL Driver to S3043 Input AC Coupled Termination
Vcc
Vcc -0.70V
(DC AVG)
+3.3V
0.01µF
Zo=50Ω
300Ω
0.01µF
60Ω
Vcc -0.70V
(DC AVG)
Single-Ended
Driver
S3043
REFCLKP/N
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August 10, 1999 / Revision E
SONET/SDH/ATM OC-48 16:1 TRANSMITTER
S3043
Figure 16. AC Input Timing
PICLKP
tS
tH
PIN
PIN
PIN[15:0]
1. When a set-up time is specified on LVPECL signals between an input and a clock, the set-up time is the time in
picoseconds from the 50% point of the input to the 50% point of the clock.
2. When a hold time is specified on LVPECL signals between an input and a clock, the hold time is the time in
picoseconds from the 50% point of the clock to the 50% point of the input.
Figure 17. Output Timing
TSCLKP/
LSCLKP
tS
tP
TSD
tH
TSD
TSD
TSD/
LSD
Notes on High-Speed PECL Output Timing
1. Output propagation delay time is the time in nanoseconds from thecross-over point of the reference signal to
the cross-over point of the output.
2. When a set-up time is specified on differential LVPECL signals between an input and a clock, the set-up time is
the time in picoseconds from the cross-over point of the input to the cross-over point of the clock.
3. When a hold time is specified on differential LVPECL signals between an input and a clock, the hold time is the
time in picoseconds from the cross-over point of the clock to the cross-over point of the input.
Figure 18. Differential Voltage Measurement
Single-ended
V
SINGLE
swing
∆V
2X Single-ended
swing
=
DIFF
August 10, 1999 / Revision E
19
APPLICATION NOTE
S3043
SONET/SDH/ATM OC-48 16:1 TRANSMITTER
The S3043 utilizes a unique elastic store buffer which can be set in two different configurations allowing the
system designer to be flexible in the way a system is to be layed out. The configuration of the elastic store buffer
is dependent upon the I/O pins which comprise the Synch Timing loop. This loop is formed from PULSE(I/P) to
READ(O/P) and PCLK(I/P) to PICLK(O/P). The elastic store buffer can be thought of as a memory stack with a
read pointer. The PULSE signal is the read pointer which announces that it has read a register and when fed
back to READ input, it synchronizes the write operation of the buffer so as not to simultaneously write over the
same register that it has read previously.
Figure 19. Block Diagram
OSCILLATOR
REFCLK P/N
PCLK P/N
DIV
PLL
PICLK P/N
PIN[15:0]
16
FIFO
Pulse
Read
CUSTOMER LOGIC
S3043
Block Diagram
In the configuration shown above, both the loops (PCLK to PICLK) and (Pulse to Read) have 0 delay (they are
shorted). S3043 is clocking data out of the customer logic. The oscillator frequency REFCLK is given to the PLL.
The output of the PLL is given to the multiplier and divider circuits. The output of the chip PCLK, is used to clock
data out of the customer logic. The PICLK is in phase and has the same frequency as PCLK. It is used to clock
data into the register in the S3043. The data will have the same frequency as PICLK, but it may not be in phase
with PICLK. It is important to meet the set-up and hold time constraints in this case.
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August 10, 1999 / Revision E
APPLICATION NOTE
SONET/SDH/ATM OC-48 16:1 TRANSMITTER
S3043
Figure 20.
PCLK
PICLK
tH
PIN
tS
PIN
VALID DATA 4
VALID DATA 3
VALID DATA 2
PIN[15:0] VALID DATA 1
tS
PIN
tH
PIN
PULSE
READ
DON’T CARE
August 10, 1999 / Revision E
21
APPLICATION NOTE
S3043
SONET/SDH/ATM OC-48 16:1 TRANSMITTER
In the figure shown below, we are using the 2nd configuration of the elastic store buffer. This configuration fully
utilizes the elastic store buffer and allows the user a delay accommodation of 0 to 14 ns. The PULSE delay must
follow the PCLK delay. It is very important that the relationship between these two signals be kept all the way
through the loop. Otherwise it is possible to under or over spill the buffer. It is important to insure that the PULSE
signal is retimed along with the outgoing data to the S3043.
Figure 21.
OSCILLATOR
REFCLK P/N
PCLK P/N
DIV
PLL
PICLK P/N
PIN[15:0]
16
FIFO
D
Q
Pulse
Read
S3043
CUSTOMER LOGIC
22
August 10, 1999 / Revision E
APPLICATION NOTE
SONET/SDH/ATM OC-48 16:1 TRANSMITTER
S3043
Figure 22.
PCLK
tP
PICLK
PICLK
tS
tH
PULSE
PULSE
PULSE
READ
tP
PRCLK
tH
PIN
tS
PIN
tH
PIN
tS
PIN
PIN[15:0]
VALID DATA 1
VALID DATA 2
VALID DATA 3
August 10, 1999 / Revision E
23
APPLICATION NOTE
S3043
SONET/SDH/ATM OC-48 16:1 TRANSMITTER
Figure 23.
OSCILLATOR
REFCLK P/N
DIV
PLL
PICLK P/N
PIN[15:0]
16
FIFO
Pulse
Read
CUSTOMER LOGIC
S3043
In some applications it is necessary to "forward clock" the data in a SONET/SDH system. In this application the
reference clock from which the high speed serial clock is synthesized and the parallel data clock both originate
from the same clock source. The timing control logic in the S3043 automatically generates an internal load signal
which has the fixed relationship to the reference clock. The logic takes into account the variation of the reference
clock to the internal load signal over temperature and voltage. The connections required to implement the design
are shown in the above figure. The setup and hold times for the PICLK to the data must be met by the customer
logic. For the timing diagram refer to Figure 16.
Possible Problems: In order to meet the jitter generation specifications required by SONET, the jitter of the
reference clock must be minimized. It may be difficult to meet the SONET jitter generation specifications using a
reference clock generated from the customer logic.
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August 10, 1999 / Revision E
SONET/SDH/ATM OC-48 16:1 TRANSMITTER
S3043
Ordering Information
GRADE
TRANSMITTER
PACKAGE
S – Industrial/Commercial
3043
A – 80 PQFP/TEP
X XXXX
X
Grade Part number
Package
Applied Micro Circuits Corporation
6290 Sequence Drive, San Diego, CA 92121
Phone: (858) 450-9333 • (800) 755-2622 • Fax: (858) 450-9885
http://www.amcc.com
AMCC reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and
advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information being relied
on is current.
AMCC does not assume any liability arising out of the application or use of any product or circuit described herein, neither does it convey
any license under its patent rights nor the rights of others.
AMCC reserves the right to ship devices of higher grade in place of those of lower grade.
AMCC SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTED TO BE SUITABLE
FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS.
AMCC is a registered trademark of Applied Micro Circuits Corporation.
Copyright ® 1998 Applied Micro Circuits Corporation
August 10, 1999 / Revision E
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