S3045B [AMCC]
Mux/Demux, 1-Func, Bipolar, PQFP208, 28 X 28 MM, 3.40 MM HEIGHT, PLASTIC, QFP-208;
| 型号： | S3045B |
| 厂家： | 
APPLIED MICRO CIRCUITS CORPORATION |
| 描述： | Mux/Demux, 1-Func, Bipolar, PQFP208, 28 X 28 MM, 3.40 MM HEIGHT, PLASTIC, QFP-208 ATM 异步传输模式 电信 电信集成电路 |
| 文件： | 总30页 (文件大小：206K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
DEVICE
SPECIFICATION
S3045
SONET/SDH OC-12 TO OC-48 MUX/DEMUX
APPLICATIONS
FEATURES
• SONET/SDH-based transmission systems
• SONET/SDH modules
• Complies with Bellcore and ITU-T
specifications
• Supports STS-12/STM-4 to STS-48/STM-16
Mux/Demux functions
• 8-bit LVDS data path for STS-48/STM-16 data
• 8-bit LVTTL data path with parity for each
STS-12/STM-4 data stream
• SONET/SDH test equipment
• ATM over SONET/SDH
• Section repeaters
• Add drop multiplexers
• Broad-band cross-connects
• Fiber optic terminators
• Optionally calculates even or odd parity over
parallel data bus or data and frame pulse
• Compatible with AMCC S3041/S3042 Mux/
Demux chipset
• Compatible with PMC PM5355 User Network
Interface device and PMC PM5312 STTX
• Optionally calculates and inserts Byte
Interleaved Parity (B1)
• Fiber optic test equipment
• ATM Switch Backbones
GENERAL DESCRIPTION
The S3045 SONET/SDH byte interleave chip is a
fully integrated STS-12/STM-4 to STS-48/STM-16
Mux/Demux device. The S3045 performs all neces-
sary byte interleave and byte de-interleave functions
for multiplexing and de-multiplexing of four STS-12/
STM-4 data streams into/from a single STS-48/STM-
16 data stream. The S3045 functions in conformance
with SONET/SDH transmission standards and is suit-
able for SONET-based ATM applications. Figure 1
shows a typical network application. Byte Interleave
parity (B1) is calculated and inserted for the transmit
path and calculated, compared and inserted for the
receive path. Optional frame synchronous scram-
bling and descrambling are performed, and an
STS-12/STM-4 framing signal is provided to the
STS-12/STM-4 interface processors to allow syn-
chronization of the receive STS-12/STM-4 data
streams.
• Optionally compares B1 Byte Interleave Parity
on the receive side. Generates and inserts B1
Error indications (B1ERR)
• Optionally calculates and inserts M1 Bytes, and
recalculates and inserts the B2 parity bytes
due to the M1 insertions
• Optionally inserts section-trace bytes (J0/Z0) in
the transmit path
• Diagnostic Loopback Mode
• Out of Frame (OOF) monitor and alarm indication
• Loss of Signal (LOS) monitor and alarm indication
• Squelch Mode: Provides downstream clock
during Clock Recovery Failure
• Receive J0 Frame Pulse (J0FP) indicator
• Performs optional Frame synchronous
scrambling and descrambling
• Provides synchronization signal to STS-12/
STM-4 Network Interface Processors
• Single 3.3V supply
• 5 Volt tolerant input
• 208-pin PQFP/TEP package
Figure 1. System Block Diagram
8
8
8
8
8
8
8
8
S3040
CDR
S3041
Tx
S3042
Rx
OTX
ORX
8
8
8
8
8
8
8
8
8
S3042
Rx
S3040
CDR
8
ORX
S3041
Tx
8
8
OTX
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December 13, 1999 / Revision E
S3045
SONET/SDH OC-12 TO OC-48 MUX/DEMUX
7. Frame synchronous scrambling.
8. B1 calculation and insertion.
S3045 OVERVIEW
The S3045 byte interleave chip implements SONET/
SDH byte interleave functions required to multiplex/
demultiplex four STS-12/STM-4 data streams into a
single STS-48/STM-16 data stream. Each of the four
STS-12/STM-4 transmit/receive data streams uses
an 8-bit parallel interface with parity to maintain com-
patibility with industry standard network interface
processors. The STS-48/STM-16 data stream uses
an 8-bit parallel LVDS data path to be compatible
with the S3041/S3042 Mux/Demux chipset. The
block diagram in Figure 2 shows the basic operation
of the chip. This chip can be used with the S3041
and S3042 to implement the front end of SONET
equipment. The chip includes byte interleave cir-
cuitry along with B1 calculation, M1 calculation, J0/
Z0 insertion, and B1 verification circuitry. STS-48/
STM-16 data stream is monitored in the receive path
for OOF and LOS, and alarm outputs are generated.
9. STS-48/STM-16 compatible 8-bit wide 311 MHz
LVDS output (311DATOUT).
Receiver Operations
1. STS-48/STM-16 compatible 8-bit wide 311 MHz
LVDS input (311DATIN).
2. OOF and LOS states are monitored and alarms
are generated.
3. B1 extraction and calculation of the STS-48/STM-16
frame.
4. B1 calculation of the number one STS-12/STM-4
frame.
5. Frame synchronous descrambling.
6. B1 compare and error indication (B1ERR) genera-
tion for the STS-48/STM-16 frame.
The S3045 is divided into a transmitter section and a
receiver section. The sequence of operation is as
follows:
7. Insert the number one STS-12/STM-4 B1 parity byte
into the number one STS-12/STM-4 frame and insert
errors if any found in the STS-48/STM-16 B1 parity
byte.
Transmitter Operations
1. 32-bit LVTTL parallel input from four 8-bit STS-
12/ STM-4 data streams (PIN A,B,C,D) with parity
(PARIN A,B,C,D).
8. 32-bit (4 x 8 bit) parallel output of four STS-12/
STM-4 data streams (POUT A,B,C,D) with parity
output (PAROUT A,B,C,D).
2. Four Byte interleave conversion Mux.
3. Section-trace insertion (J0/Z0).
Suggested Interface Devices
4. M1 calculation (addition of four STS-12/STM-4
M1 values) and insertion into the number one
STS-12/STM-4 location.
AMCC
AMCC
AMCC
AMCC
AMCC
S3040/S3047
S3041
Clock Recovery Device
OC-48 Mux
5. M1 insertion of zero into STS-12/STM-4 number
two, three, and four locations.
S3042
OC-48 Demux
CONGO S1201 POS/ATM SONET Mapper
NILE S1202 ATM SONET Mapper
6. Four B2 parity byte calculations and insertions for
STS-1 frames after M1 insertions.
S3045 Acronym List
SDH
SEF
–
–
Synchronous Digital Heirarchy
Severely Errored Frame
BER
CDR
LOS
OOF
ORX
OTX
–
–
–
–
–
–
Bit Error rate
Clock and Data Recovery
Loss Of Signal
SONET –
Synchronous Optical Network
Synchronous Transport Module
Synchronous Transport Signal
STM
STS
–
–
Out Of Frame
Optical Receiver\
Optical Transmitter
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December 13, 1999 / Revision E
SONET/SDH OC-12 TO OC-48 MUX/DEMUX
S3045
Figure 2. Functional Block Diagram
*A. J0/Z0 Insertions
*B. M1 Calculations &
insertions
*C. B2 Calculations
and Insertions
*D. B1 Calculation
and Insertion
PARFPTXSEL
SCRBENB
FIFO
Register
Parity
B2/M1SELB
B1SELB
1
1
Calculation
PARIN A
PINA
PARERR A
8
PICLK
8 bit
Register
PARIN B
PINB
PARERR B
8
8
8
D*
A* B*
8
C*
Scrambler
311DATOUT
Register
Register
Register
Byte
Interleave
Mux
PICLK
1
1
PARIN C
PINC
PARERR C
8
8
B1 Parity
Calculation &
Insertion
311CLKOUT
J0/Z0SEL
PICLK
PARIN D
PIND
PARERR D
READP/N
PICLK
Register
PULSEP/N
PCLK A,B,C,D
Transmit Clock
Divider
311TCLK
Frame
Control
Counter
4
TIFP A,B,C,D
SYNCRSTB
TRANSMITTER
RECEIVER
LB_FRAME
PARSEL
DSCRBENB
PAROUT A,B,C,D
POUT A
SDVBB
SDLVPECL
SDLVTTL
SQUELCHB
DLEB
4
8
8
MUX
2*
Byte
Interleave
Demux
1*
POUT B
Register
8
8
8
Descrambler
POUT C
POUT D
311DATIN
PARFPRXSEL
POCLK A,B,C,D
4
311CLKIN
FRAME
PULSEOOF
OOF
Frame
Control
Counter &
Alarm
4
B1 Parity
FP A,B,C,D
STS-12
Calculation
Insertion
Calculation for
STS-48 and the
number 1 STS-12
frames
Detection
J0FP
FPSEL
LOS
*1. Extract STS-48 B1
for Comparison
Receive Clock
Divider
*2. LOS monitoring
B1ERR
RSTB
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December 13, 1999 / Revision E
S3045
SONET/SDH OC-12 TO OC-48 MUX/DEMUX
the byte following the last byte of the first row (last
C1 byte) of the STS-12/STM-4 section overhead.
This bit and all subsequent bits to be scrambled will
be added modulo 2 to the output from the X7 position
of the scrambler (A1, A2, or C1 bytes are not
scrambled). The scrambler will run continuously
throughout the complete STS-48/STM-16 frame. A
set of signals from the frame control counter block
controls when the scrambler is on, off, or reset.
ARCHITECTURE/FUNCTIONAL DESIGN
Transmit Operation
The S3045 transmit section performs the byte inter-
leaving stage in the processing of a transmit
SONET/SDH STS-48/STM-16 byte wide data
stream. It converts four byte wide STS-12/STM-4
data streams into a single byte serial STS-48/STM-
16 data stream. The byte interleaved parity (B1) is
calculated over the entire STS-48/STM-16 frame and
inserted into the appropriate B1 location. In each
STS-48/STM-16 frame there is one B1 byte located
in the first STS-1 frame. The M1 byte is calculated
(addition of four STS-12/STM-4 M1 bytes) and in-
serted into the number one STS-12/STM-4 M1
position. Zero is inserted into the number two, three,
and four STS-12/STM-4 M1 positions. The section-
trace bytes (J0/Z0) can be optionally inserted by
setting the J0/Z0SEL high. The SONET/SDH scram-
bler can be enabled or disabled by the SCRBENB
input.
Frame Synchronization
The four STS-12/STM-4 input data streams from the
four controllers must be frame aligned before this
data is fed into the S3045 since the S3045 does not
have any data buffering. The four controllers each
output an active high framing position signal that is
input into the TIFP inputs of the S3045 that marks
the frame alignment on the output bus. This signal
goes high for a single 77.76 MHz clock period during
the first synchronous payload envelope byte immedi-
ately following the C1 bytes. The TIFP A,B,C,D
inputs associated with each of the four STS-12/STM-
4 data streams must be high at the same time so as
to indicate frame alignment of all four data streams.
These frame pulses will indicate frame alignment
with the first payload byte of the STS-12/STM-4
frames. When frame alignment occurs, valid data will
start to be output by the next valid frame. Valid B1
and B2 parity bytes will be output on the following
frame. Otherwise random data will be clocked out of
the 311DATOUT[7:0] output. In the event that all
four pulses are not high at the same time (frames
are not exactly aligned), a reset sequence will be
generated by the S3045 to re-synchronize the four
data streams.
STS-48/STM-16 Byte Interleave Multiplexing
The byte interleave mux shown in Figure 2 takes in
the four byte wide STS-12/STM-4 data streams four
bytes at a time and outputs byte wide STS-48/STM-
16 data stream. The byte interleave mux inputs are
registered on the STS-12/STM-4 interface. The mux
first takes four bytes from the A input, followed by
four from B, four from C, and four from D. The pat-
tern is repeated as data on the A, B, C, and D inputs
are registered and passed into a four word deep
pipeline register. Each of the four data words are
then latched into holding registers. A counter at the
STS-48/STM-16 byte rate (311 MHz) controls a mux
that loads data into a register at the STS-48/STM-16
byte rate and is then transmitted. STS-48/STM-16
byte interleaving must be done four bytes at a time,
where as STS-3/STM-1 and STS-12/STM-4 is ac-
complished one byte at a time.
In order to guarantee the synchronization of the four
controllers, a reset sequence will be applied by the
S3045. This reset will align the four STS-12/STM-4
inputs for multiplexing. Note that parity errors may
be erroneously generated during this reset se-
quence. Figure 3 depicts the following synchroniza-
tion sequence.
Scrambler
The scrambler can be utilized in order to guarantee
a suitable bit pattern, which prevents a long se-
quence of 1’s or 0’s. The frame synchronous
scrambler can be optionally used to scramble the
STS-48/STM-16 data stream. The SONET scram-
bling generator polynomial of 1 + x6 + x7 with a
sequence length of 127 is used. The scrambler will
be reset to “1111111” on the most significant bit of
1. The SYNCRSTB will be asserted low to reset the
four controllers upon a misalignment of the four
TIFP pulses and will be held low for a minimum
16 PCLK A,B,C,D clock cycles (77.76 MHz).
2. The transmitter data clock (PCLK A,B,C,D) will
stop for a minimum 16 clock cycles while the
SYNCRSTB is asserted low.
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December 13, 1999 / Revision E
SONET/SDH OC-12 TO OC-48 MUX/DEMUX
S3045
3. The SYNCRSTB will be removed (de-asserted
high) from the four controllers for a minimum 16
PCLK A,B,C,D clock cycles.
Clock Generation
The clock generation circuitry generates the 77.76
MHz PCLK A,B,C,D clock required for the byte wide
STS-12/STM-4 interface from the 311 MHz clock
(311TCLK) required for the byte wide STS-48/STM-
16 interface.
4. The transmit data clock (PCLK A,B,C,D) will con-
tinue to be stopped for a minimum 16 clock
cycles after reset is de-asserted and then start
clocking.
Bit Interleaved Parity - N
5. STS-12/STM-4 data out of the four controllers will
start to flow into the S3045. The S3045 will
search for a high pulse on the TIFP input pulses
on all four channels. If the four controllers are not
frame aligned in 250us this sequence will restart.
Bit Interleaved Parity-N (BIP-N) is a method of error
monitoring. Even parity is used for the BIP-8 calcula-
tion. The transmitting equipment generates an N-bit
code over a specified portion of the signal in such a
manner that the first bit of the code provides even
parity over the first bit of all N-bit sequences on the
covered portion of the signal, the second bit provides
even parity over the second bit of all N-bit se-
quences within the specified portion, etc. Even parity
is generated by setting the BIP-N bits so that there
are an even number of ones in each of all N-bit
sequences including the BIP-N.
Frame Control Counter
The frame counter receives the TIFP signals indicat-
ing the frame boundaries and counts 38,880 bytes (9
rows x 90 columns x 48 STS-1) to ensure that the
transmitter is receiving synchronous TIFP pulses.
The frame counter keeps track of the overhead bytes
so that proper location and insertion of bytes is ac-
complished.
B1 Parity Calculation
The frame control block outputs a frame synchro-
nous reset signal (SYNCRSTB) that frame aligns the
STS-12/STM-4 network interface processors. The
Transmit Input Frame Pulse (TIFP) signal indicates
to the frame counter the frame position of the input
data channel. If the transmitter does not get four
simultaneous TIFP signals after 250us the
SYNCRSTB pin is asserted low. The frame counter
controls the output mux on the scrambler to allow
scrambling, parity byte (B1) generation and inser-
tion, M1 calculations and insertions, Z0 calculations
insertions, and parity byte (B2) generations and in-
sertions.
This byte is allocated for regeneration section error
monitoring. This byte will be calculated using even
parity. Even parity is generated by setting the bit
interleaved parity bits so that there is an even num-
ber of ones in each monitored partition of the signal.
The interleaved even parity byte B1 is calculated
over the entire scrambled STS-48/STM-16 frame
and inserted into the B1 location of the next frame
before going through the scrambling process. The
computed bit interleaved parity is only placed in the
B1 byte of the first STS-1 signal of the STS-48/STM-
16 frame before scrambling (one B1 byte is valid in a
Figure 3. S3045 Synchronous Reset Functional Timing Diagram
PCLK A,B,C,D
16 cycles
16 cycles
TIFP A
TIFP B
TIFP C
TIFP D
TIFP D misaligned
SYNCRSTB
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December 13, 1999 / Revision E
S3045
SONET/SDH OC-12 TO OC-48 MUX/DEMUX
single STS-48/STM-16 frame). The B1 parity byte is
calculated after the M1 bytes are inserted, the sec-
tion-trace J0/Z0 bytes are inserted, and the B2 parity
bytes are inserted.
frame). These parity bytes are optionally calculated
and inserted after the M1 bytes are inserted into the
STS-48/STM-16 and before the B1 is calculated and
inserted. The B2/M1SELB select line allows for B2
and M1 calculations to be turned off.
B2 Parity Calculation
M1 Byte ( B2 Parity Error Count )
The B2 byte is allocated in each STS-1 frame for a
line error monitoring function. The interleave even
parity byte B2 is optionally calculated and inserted
only over the four STS-1 frames that the four M1
bytes were inserted (the B2 byte will not be calculated
for all 48 STS-1’s). These four B2 bytes are calcu-
lated over the STS-1 frames of the previous STS-48/
STM-16 frame except for the first three rows of the
section overhead (computed over all bits of the line
overhead and capacity envelope of the previous STS-
1 frame before scrambling) and is inserted into the
appropriate B2 locations (locations of the B2 bytes
are found by control from the frame counter block) of
the current frame before scrambling. These bytes will
be inserted within a STS-48/STM-16 signal (48 B2
bytes are contained in a single STS-48/STM-16
The STS-48/STM-16 M1 byte is calculated by ex-
tracting each of the four M1 bytes of the STS-12/
STM-4 frames and adding them together and insert-
ing this new M1 byte into the STS-48/STM-16 M1
byte. For STS-48/STM-16 rate the M1 count will
truncate at 255 (never report more than 255 errors).
The STS-48/STM-16 M1 byte will only be transmitted
over the number one STS-12/STM-4 data stream.
The other 3 STS-12/STM-4 M1 bytes will be inserted
with the value of zero.
Section-trace Insertion (J0/Z0) Bytes
The section-trace bytes (J0/Z0) can optionally be
filled by setting J0/Z0SEL as indicated below in
Table 1.
Table 1. Section-Trace Insertion (J0/Z0) Bytes
J0/Z0SEL
Description
0
Transparent Operation - J0/Z0 bytes are passed through with no modification.
Byte 1 of 48 (J0 byte) is passed through with no modification (transparent) and
bytes 2 through 48 (Z0 bytes) are filled with the values of 02hex to 30hex (48
decimal) respectively.
1
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December 13, 1999 / Revision E
SONET/SDH OC-12 TO OC-48 MUX/DEMUX
RECEIVER OPERATION
S3045
Receive Frame Counter
The S3045 byte interleave receive section converts
the byte wide STS-48/STM-16 LVDS data stream
into four byte wide STS-12/STM-4 LVTTL data
streams with parity. The B1 parity byte is calculated
over the STS-48/STM-16 frame and over the number
one STS-12/STM-4 frame. The STS-48/STM-16 B1
parity byte is compared to the one received, if an
error exists then B1ERR will be asserted and the
STS-12/STM-4 parity B1 will be inserted with the
same number of bit errors found in the STS-48/STM-
16 B1 parity byte. Also, if no errors exist then the
calculated STS-12/STM-4 B1 will be inserted into the
number one STS-12/STM-4 frame. A frame synchro-
nous descrambler can be optionally disabled by the
DSCRBENB input. The input data stream is moni-
tored for Loss of Signal (LOS) and Out of Frame
(OOF) and alarms are generated for each one.
The frame counter receives the FRAME signal indi-
cating the frame boundaries and counts 38,880
bytes (9 rows x 90 columns x 48 STS-1) to ensure
that the receiver is receiving synchronous FRAME
pulses. The frame counter keeps track of the over-
head bytes so that proper location and insertion of
bytes is accomplished. In diagnostic loopback mode,
a loopback frame (LB_FRAME) signal is generated
internally and the FRAME input is disabled.
Clock Generation
The clock generation circuitry generates the 77.76
MHz POCLK clock required for the byte wide STS-12/
STM-4 interface from the 311 MHz clock (311CLKIN)
required for the byte wide STS-48/STM-16 interface.
B1 Parity Calculation and Compare
The B1 byte is allocated for regeneration section error
monitoring. This byte will be calculated using even
parity. The section bit interleaved parity (BIP-8) error
detection code B1 will be optionally calculated for ev-
ery STS-48/STM-16 frame before descrambling and
for the number one STS-12/STM-4 frame after
descrambling. The B1 value is compared to the ex-
tracted value of the STS-48/STM-16 B1 parity byte
after descrambling in the following frame. B1 errors
will be shown at the B1ERR output when the B1SELB
is active. The calculated STS-12/STM-4 B1 parity
byte will be inserted after descrambling into the num-
ber one STS-12/STM-4 frame if there are no errors
found on the STS-48/STM-16 B1 parity byte. If there
are errors found with the STS-48/STM-16 B1 parity
byte, the number of bit errors (1 to 8) will be passed
onto the STS-12/STM-4 B1 parity byte for insertion
into the number one STS-12/STM-4 frame. The num-
ber one STS-12/STM-4 frame is output on the
POUT[7:0]A data bus. The following functional timing
diagram depicts the B1ERR timing.
Descrambling
The byte wide STS-48/STM-16 data stream is op-
tionally descrambled using the SONET frame syn-
chronous descrambler with a generator polynomial
of 1 + x6 + x7 with a sequence length of 127. The
descrambler algorithm is identical to the scrambler
algorithm. The descrambler will be reset to
“1111111” on the most significant bit of the byte fol-
lowing the last byte of the first row of the STS-12/
STM-4 section overhead. This bit and all subsequent
bits to be descrambled will be added modulo 2 to the
output from the X7 position of the descrambler (A1,
A2, or C1 bytes are not descrambled). The
descrambler will run continuously throughout the
complete STS-48/STM-16 frame. A signal from the
frame counter block controls when the descrambler
is on, off, or reset.
Figure 4. B1 Error (B1ERR) Functional Timing Diagram
POCLK
B1ERR
low for a minimum of 2
clock cycles
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December 13, 1999 / Revision E
S3045
SONET/SDH OC-12 TO OC-48 MUX/DEMUX
Loss of Signal (LOS)
FRAMER (In-frame, going out-of-frame)
The frame acquisition algorithm determines whether
the receiver is in-frame or out-of-frame. In-frame is
defined as the state where the frame boundaries are
known. Out-of-Frame (OOF) is defined as the state
where the frame boundaries of the incoming signal
are unknown. OOF is also referred to as the Se-
verely Errored Frame (SEF) in the SONET
standards. The frame pulse (FRAME) input of the
S3045 indicates if the frame boundaries are known
(in-frame) or unknown (out-of frame).
The Loss of Signal (LOS) block monitors the incom-
ing data stream for all zero’s. When a minimum of 27
µsec of all zero’s are detected, a loss of signal (LOS)
is declared (high signal). LOS is deactivated (low
signal) when two consecutive valid framing patterns
are detected and no LOS condition is detected in
between. LOS is updated on the falling edge of
POCLKA,B,C,D.
J0 Frame Pulse
The J0 Frame Pulse output will be active high when
the J0 byte is presented on the POUT[7:0]A data
bus. Figure 6 depicts the functional timing of this
signal.
An Out-of-Frame (OOF) also known as an SEF con-
dition on an STS-48/STM-16 signal will be declared
when a minimum of four consecutive errored framing
patterns have been received. The maximum SEF de-
tection time will be 625 µs for a random signal. The
framing algorithm used to check the alignment is
such that 10-3 BER does not cause an SEF more
than once every 6 minutes. This algorithm examines
the 48th A1 (F6h) byte and the first four bits of the
first A2 (28h) byte for a total of 12 bits to guarantee
this requirement.
FP Frame Pulse
The FP output indicates frame boundaries in the in-
coming data stream. FP pulses high for one POCLK
cycle when the third A2 byte of the framing se-
quence is valid on the POUT[7:0]A data bus. Figure
7 depicts the functional timing of this signal.
STS-48/STM-16 Byte Interleave Demux
When in an SEF condition the S3045 will assume
the frame has been recovered and declare an in-
frame condition on detecting two successive error-
free framing patterns. This implementation of the
frame recovery circuit achieves realignment follow-
ing a declared SEF within 250-µs.
The byte interleave demux shown in Figure 2 con-
verts the byte wide STS-48/STM-16 data stream into
four byte wide STS-12/STM-4 data streams. The
data is byte de-interleaved using four bytes at a
time. The data is output with a 77.76 MHz clock.
Figure 5. OOF State Machine
4 consecutive errored framing patterns
Reset
OOF (SEF)
STATE
NORMAL STATE
2 consecutive error free
framing patterns
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December 13, 1999 / Revision E
SONET/SDH OC-12 TO OC-48 MUX/DEMUX
S3045
It is important to note that in squelch mode there
may be up to 3.2 nsec shortening or lengthening of
the POCLK A,B,C,D cycle, resulting in an apparent
phase shift in the POCLK at the de-assertion of the
SD condition. Another similar phase shift will occur
when the SD condition is reasserted. Figure 8 de-
picts this operation.
OTHER OPERATING MODES
Diagnostic Loopback
When the Diagnostic Loopback Enable (DLEB) input is
low, a loopback from the transmitter to the receiver at
the serial data rate can be set up for diagnostic pur-
poses. In loopback mode the STS-48/STM-16
transmitter outputs (311DATOUT[7:0], 311CLKOUT
and an internally generated Frame pulse on the third
A2 byte (that is not accessible to the outside of the
chip)) are internally connected to the STS-48/STM-16
receiver inputs (311DATIN[7:0], 311CLKIN, and
FRAME). In loopback mode the STS-48/STM-16 trans-
mitter outputs (311DATOUT[7:0] and 311CLKOUT) are
still active.
In the normal operating mode with SQUELCHB input
inactive (high), there will be no phase discontinuities
at the POCLK A,B,C,D output during signal loss or
re-acquisition (assuming operation with continuous
clock from the CRU device such as the AMCC
S3040 or S3047). Figure 9 depicts this operation.
Byte wide Parity Calculation
Odd parity or even parity can be calculated using the
PIN A,B,C,D and POUT A,B,C,D data busses by set-
ting the PARSEL line high for even parity or low for
odd parity. Even parity is generated by setting the
parity bit so that there are an even number of ones
throughout the 9 bits. Odd parity is generated by
setting the parity bit so that there is an odd number
of ones throughout the 9 bits.
“Squelched Clock” Operation
Some integrated optical receiver/clock recovery
modules force their recovered serial receive clock
output to the logic zero state (squelched clock) if the
optical signal is removed or reduced below a fixed
threshold. This condition is accompanied by the ex-
pected deassertion of the Signal Detect (SD) output.
Reset Operation
The S3045 has been designed for operation with
clock recovery devices that provide continuous serial
clock for seamless down stream clocking in the
event of optical signal loss. For operation with an
optical transceiver that provides the “squelched
clock” behavior as described above, the S3045 can
be operated in the “squelched clock mode” using the
SQUELCHB input.
The RESET (RSTB) input forces all the internal logic
of the S3045 to its deasserted state. All of the se-
quential logic inside the S3045 will remain static for
as long as reset is asserted. The RESET input is
implemented using a schmitt type receiver. The RE-
SET input is asynchronous to the input clock.
RESET should be asserted for at least 30 nano sec-
onds after power up for proper operation. During
reset PCLK A,B,C,D and POCLK A,B,C,D will stop,
and SYNCRSTB will remain high.
In squelch mode, the 311CLKIN is used for all re-
ceiver timing when the SDLVPECL or SDLVTTL
inputs are in the active state. (SDLVPECL and
SDLVTTL are in opposite logical states.) When the
SDLVPECL or SDLVTTL inputs are placed in the
inactive state (usually by the de-assertion of the Sig-
nal Detect [SDLVPECL and SDLVTTL are in the
same logical state] from the optical transceiver/clock
recovery unit) the transmitter serial clock (311TCLK)
will be used to maintain timing in the receiver sec-
tion. This will allow the POCLK A,B,C,D to continue
to run and the parallel outputs to flush out the last
received characters and assume the all zero state
imposed at the serial data input.
9
December 13, 1999 / Revision E
S3045
SONET/SDH OC-12 TO OC-48 MUX/DEMUX
Figure 6. J0 Frame Pulse Functional Timing Diagram
J0FP
POUTA[7:0]
J0
Z0
Z0
Z0
Z0
Z0
POUTB[7:0]
POUTC[7:0]
POUTD[7:0]
Z0
Z0
Z0
Z0
Z0
Z0
Z0
Z0
Z0
Z0
Z0
Z0
Z0
Z0
Z0
Z0
Z0
Z0
Figure 7. FP Frame Pulse Functional Timing Diagram
FP
POUTA[7:0]
A1
A2
A2
A2
A2
A2
POUTB[7:0]
POUTC[7:0]
POUTD[7:0]
A1
A1
A1
A2
A2
A2
A2
A2
A2
A2
A2
A2
A2
A2
A2
A2
A2
A2
10
December 13, 1999 / Revision E
SONET/SDH OC-12 TO OC-48 MUX/DEMUX
S3045
Figure 8. Functional Operation of SQUELCH Mode
SDLVPECL
Note: POCLK A,B,C,D is now
derived from 311TCLKP/N
(from the transmitter)
POCLK A,B,C,D
SDLVTTL = LOW
SQUELCHB = LOW
Note: A shortening or lengthening of
POCLK A,B,C,D of up to 3.2 ns.
(Assuming 311CLKIN is within
its specification)
Figure 9. Functional Operation of Non-SQUELCH Mode
SDLVPECL
POCLK A,B,C,D
SDLVTTL = LOW
SQUELCHB = HIGH
Note: POCLK A,B,C,D continues
to be derived from 311CLKINP/N
(from the receiver)
11
December 13, 1999 / Revision E
S3045
SONET/SDH OC-12 TO OC-48 MUX/DEMUX
Table 2. Transmitter Input Pin Assignment and Descriptions
Pin Name
PICLK
Level
I/O
Pin #
Description
LVTTL
I
129
Parallel Input Clock. PICLK is a 77.76 MHz input clock which
PIN[7:0] is aligned. PICLK is used to transfer the data on the PIN
inputs into a holding register. The rising edge of PICLK samples
PIN A, B, C, D[7:0].
PINA[7:0]
PINB[7:0]
PINC[7:0]
PIND[7:0]
LVTTL
LVTTL
I
I
180–173, Parallel Data Input. A 77.76 Mbytes/sec word, aligned to the
156–149, PICLK parallel input clock. PIN[7] is the most significant bit
121–117, (corresponding to bit 1 of each word, the first bit transmitted).
115–113, PIN[0] is the least significant bit (corresponding to bit 8 of each
94–91,
89–86
word, the last bit transmitted). PIN[7:0] is sampled on the rising
edge of PICLK.
SCRBENB
198
Scramble Enable. Active low. When active, the frame
synchronous scrambler is enabled. When inactive, the scrambler
is disabled. This signal is static and must not be changed in normal
operation.
311TCLKN
311TCLKP
LVDS
I
I
30
31
311 MHz Transmit Clock. Used by the transmitter to generate the
77.76 MHz clocks and retime the STS-48/STM-16 byte wide data.
TIFPA
TIFPB
TIFPC
TIFPD
LVTTL
172
148
112
85
Transmit Input Frame Pulse. Active high. When active, it indicates
the frame position of the transmit data (PIN[7:0]). TIFP goes high
for a single PCLK A, B, C, D (77.76 MHz) period during the first
synchronous payload envelope byte after 12 C1 bytes. TIFP is
clocked in on the rising edge of PICLK.
PARINA
PARINB
PARINC
PARIND
LVTTL
LVTTL
I
I
181
146
111
84
Parity Input. Odd or even parity depending on the input of parity
select (PARSEL) for the 8 bit PIN[7:0] A, B, C, D data bus. PARIN
is clocked in on the rising edge of PICLK.
B2/M1SELB
200
B2/M1 Parity Byte and Parity Count Select. Active low. When
inactive the B2/M1 byte calculations and insertions are disabled.
When active, normal operation occurs (B2 and M1 calculations
and insertions are enabled). This signal is static and must not be
changed in normal operation.
J0/Z0SEL
LVTTL
I
I
205
Section-Trace Insertion Select. Select pin, select section-trace
bytes J0/Z0 options. When low the J0/Z0 bytes are passed
through with no modification. When high, byte 1 of 48 (J0 byte) is
passed though with no modification (transparent) and bytes 2
through 48 (Z0 bytes) are filled with the values of 02hex to 30hex
(48 decimal) respectively. (See Table 1.) This signal is static and
must not be changed in normal operation.
PULSEP
PULSEN
LVDS
52
51
PULSE Input. This input is used to generate the READP/N output
by synchronizing the PULSEP/N input to the 311TCLK input clock
through a register. (Required for operation with the AMCC S3041
OC-48 TX Mux).
PARFPTXSEL
LVTTL
208
Parity Frame Pulse Transmit Select. When low, parity is calculated
over the data bus PIN[7:0] A, B, C, D. When high, parity is
calculated over the PIN[7:0] A, B, C, D data bus and the Transmit
Input Frame Pulse (TIFP A, B, C, D). This signal is static and must
not be changed in normal operation.
12
December 13, 1999 / Revision E
SONET/SDH OC-12 TO OC-48 MUX/DEMUX
S3045
Table 3. Transmitter Output Pin Assignment and Descriptions
Pin Name
Level
I/O
Pin #
Description
PCLKA
LVTTL
O
128
127
126
125
Parallel Clock. A 77.76 MHz clock generated by dividing the
internal 311TCLK by four. It is normally used to coordinate byte
wide transfers between the STS-12/STM-4 overhead processors
and the S3045 device.
PCLKB
PCLKC
PCLKD
311DATOUT-
P/N[7:0]
LVDS
O
48–41
39–32
311 Mbit Data. STS-48/STM-16 byte wide data path. A 311
Mbytes/sec word, aligned to the 311 MHz parallel output clock
(311CLKOUT). 311DATOUT [7] is the most significant bit
(corresponding to bit 1 of each word, the first bit transmitted).
311DATOUT[0] is the least significant bit (corresponding to bit 8
of each word, the last bit transmitted).
311CLKOUTP
311CLKOUTN
LVDS
O
O
27
26
311 MHz Clock. 311 CLKOUT is a clock for the transmit STS-
48/STM-16 byte wide data path. A 311 MHz output clock, which
311DATAOUT [7:0] is aligned.
SYNCRSTB
LVTTL
122
Synchronous Reset. Active low. When active, the Network
Interface Processors are reset to synchronize the four STS-
12/STM-4 incoming data streams. Figure 3 shows the S3045
synchronous reset timing diagram.
PARERRA
PARERRB
PARERRC
PARERRD
LVTTL
O
182
145
110
83
Parity Error Output. Active high. Indicates to the controller that a
parity error has been detected on the PIN[7:0] A, B, C, D data bus
on a previous byte of data. When active, a parity error has been
received. When inactive, PIN[7:0] A, B, C, D data has been
received without parity errors. PARERR output can be delayed by
one to five PCLK cycles due to the internal data FIFO. See Figure
10. Note that during a sync reset condition and a hardware reset,
parity errors may erroneously be generated.
READP
READN
LVDS
O
54
53
Read Output. This output is the result of synchronizing the
PULSEP/N input to the 311TCLK input clock through a register.
(Required for operation with the AMCC S3041.)
13
December 13, 1999 / Revision E
S3045
SONET/SDH OC-12 TO OC-48 MUX/DEMUX
Table 4. Receiver Input Pin Assignment and Descriptions
Pin Name
Level
I/O
Pin #
Description
311DATINN/P
[7:0]
LVDS
I
21–14,
11–4
311 Mbit Data Inputs. Parallel STS-48/STM-16 data bus, a 311
Mbyte/sec word aligned to the parallel input [311CLKIN]. 311DATAIN
[7] is the most significant bit (corresponding to bit 1 of each word, the
first bit received). 311DATAIN [0] is the least significant bit
(corresponding to bit 8 of each word, the last bit received).
311DATAIN [7:0] is latched on the rising edge of 311CLKIN.
311CLKINN
311CLKINP
LVDS
LVDS
I
I
25
24
311 MHz Clock. 311CLKIN is a 311 MHz byte rate input clock that
is aligned to 311DATAIN [7:0] byte serial input data. 311DATIN [7:0]
and FRAME are clocked in on the rising edge of the 311CLKIN.
FRAMEN
FRAMEP
2
1
Frame. Active high. When active, it indicates that the third A2 byte
of the framing sequence is valid on the 311DATIN<7:0> pins.
Therefore it indicates frame boundaries in the incoming data stream
(311DATIN[7:0]).
DSCRBENB
SQUELCHB
LVTTL
LVTTL
I
I
199
201
Descrambler Enable. Active low. When active, the frame
synchronous descrambler is enabled. When inactive the frame
synchronous descrambler is disabled. This signal is static and must
not be changed in normal operation.
Squelch Clock Mode. Active low. Set inactive when a clock recovery
device used provides a continuous clock during signal loss or re-
acquisition. Set active when the clock recovery device used does
not provide a continuous clock during signal loss or signal
acquisition. When active and SDLVPECL/SDLVTTL is inactive
(SDLVPECL and SDLVTTL are in the same logical states) the
transmitter serial clock (311TCLK) will be used to maintain timing
in the receiving section. This signal is static and must not be
changed in normal operation.
SDLVTTL
LVTTL
I
192
Signal Detect. Active High when SDLVPECL is tied to logic 0. Active
Low when SDLVPECL is held at logic 1. A single-ended LVTTL
input to be driven by the external optical receiver module to indicate
a loss of received optical power. When SDLVTTL is inactive, the
data on the 311DATIN[7:0] pins will be internally forced to a
constant zero with the descrambler bypassed. Note: When B1SEL
is active, a B1 byte is inserted into each frame. When SDLVTTL is
active, data on the 311DATIN[7:0] pins will be processed normally.
SDLVPECL
LVPECL
I
191
Signal Detect. Active High when SDLVTTL is held at logic 0. Active
Low when SDLVTTL is held at logic 1. A single-ended LVPECL
input to be driven by the external optical receiver module to indicate
a loss of received optical power. When SDLVPECL is inactive, the
data on the Serial Data in 311DATIN[7:0] pins will be internally
forced to a constant zero with the descrambler bypassed. Note:
When B1SEL is active, a B1 byte is inserted into each frame. When
SDLVPECL is active, data on the 311DATIN[7:0] pins will be
processed normally. When SDLVTTL is to be connected to the
optical receiver module instead of SDLVPECL, then SDLVPECL
should be tied High to implement an active low Signal Detect.
14
December 13, 1999 / Revision E
SONET/SDH OC-12 TO OC-48 MUX/DEMUX
S3045
Table 4. Receiver Input Pin Assignment and Descriptions (Continued)
Pin Name
SDVBB
Level
I/O
Pin #
Description
I
190
Signal Detect. Bias pin for the SDLVPECL input. Biased internally
to VDD -1.3V.
FPSEL
LVTTL
I
I
204
207
Frame Pulse Select. When low the FRAME input is used to
generate the FP A, B, C, D pulse when the third A2 byte is output.
When high, the FP A, B, C, D output is internally generated using
the A1A2 frame boundary. The FP A, B, C, D is asserted high when
the third A2 (28h) byte is output. For normal operation set high. This
signal is static and must not be changed in normal operation.
PARFPRXSEL
LVTTL
Parity Frame Pulse Receive Select. When low, parity is calculated
over the data POUT[7:0] A, B, C, D. When high, parity is calculated
over the data POUT[7:0] A, B, C, D and the frame pulse (FP A, B,
C, D) output. This signal is static and must not be changed in normal
operation.
Table 5. Receiver Output Pin Assignment and Descriptions
Pin Name
Level
I/O
Pin #
Description
POUTA[7:0]
POUTB[7:0]
POUTC[7:0]
POUTD[7:0]
LVTTL
O
168–161 Parallel Data Output. Parallel data bus, a 77.76 Mbyte/sec word,
140–133 aligned to the parallel output clock (POCLK). POUT[7] is the most
106–99 significant bit (corresponding to bit 1 of each word, the first bit
79–72
received). POUT[0] is the least significant bit (corresponding to bit
8 of each word, the last bit received). POUT[7:0], LOS, PAROUT
A, B, C, D, B1ERR, FP A, B, C, D and OOF are updated on the
falling edge of POCLK.
POCLKA
POCLKB
POCLKC
POCLKD
LVTTL
LVTTL
LVTTL
O
O
O
169
141
107
80
Parallel Output Clock. POCLKA, B, C, D are 77.76 MHz byte rate
output clocks that are aligned to POUT[7:0]A, B, C, D byte serial
output data. POUT[7:0] is updated on the falling edge of POCLK.
FPA
FPB
FPC
FPD
157
130
95
Frame Pulse. Indicate frame boundaries in the incoming data
stream. FP pulses high for one POCLK cycle when the third A2 byte
of the framing sequence is valid on the POUTA[7:0] data. FP is
updated on the falling edge of POCLK.
69
OOF
185
Out of Frame. The Out of Frame (OOF) signal is active when the
S3045 has detected an out of frame condition. The OOF is inactive
when the S3045 is in frame. An OOF declaration occurs when four
consecutive errored framing patterns are received. OOF is used to
enable upstream framing pattern detector to search for the framing
pattern. Figure 13 depicts the functional timing of this signal.
15
December 13, 1999 / Revision E
S3045
SONET/SDH OC-12 TO OC-48 MUX/DEMUX
Table 5. Receiver Output Pin Assignment and Descriptions (Continued)
Pin Name
Level
I/O
Pin #
Description
PULSEOOF
LVTTL
O
186
Pulse Out of Frame. Active high. The Out of Frame (OOF) signal
will pulse for a minimum of 7.5ns when the S3045 is out of frame
and when the A1A2 boundary is not received for 250µs. The
PULSEOOF is inactive when the S3045 is in frame. An OOF
declaration occurs when four consecutive errored framing patterns
are received. OOF is used to enable upstream framing pattern
detector to search for the framing pattern. Figure 13 depicts the
functional timing of this signal.
J0FP
LVTTL
LVTTL
O
O
206
183
J0 Frame Pulse. Active high. Active when the J0 byte is presented
on the POUTA[7:0] data bus.
B1ERR
B1 Parity Error. Active high. Indicates that a B1 bit error has been
detected when high. For each frame B1ERR will pulse a maximum
of 8 times. In between pulses (bit errors) the B1ERR will be low for
a minimum of 2 POCLK cycles. This may be turned off by setting
the B1SELB inactive.
PAROUTA
PAROUTB
PAROUTC
PAROUTD
LVTTL
LVTTL
O
O
158
144
96
Parity Output. Odd or even parity depending on the input of parity
select (PARSEL) for the 8 bit POUT[7:0] A, B, C, D and FP A, B, C,
D (optional) data bus. PAROUT A, B, C, D, (FP A, B, C, D optional)
is updated on the falling edge of POCLK.
68
LOS
184
Loss of Signal. Active high. When active, LOS indicates that a
consecutive zero pattern for a minimum of 27usec of all zeros is
detected on the incoming scrambled STS-48/STM-16 signal before
descrambling. LOS is deactivated when two valid framing words are
detected and no LOS is detected in between. LOS is updated on
the falling edge of POCLK.
Table 6. Common Pin Assignment and Descriptions
Pin Name
B1SELB
Level
I/O
Pin #
Description
LVTTL
I
203
B1 Parity Byte Select. Active low. When active, B1 calculation and
insertion in both the transmitter and receiver sections is enabled.
When inactive, the B1 calculation and insertion in both the
transmitter and receiver sections is disabled. This signal is static
and must not be changed in normal operation.
PARSEL
RSTB
LVTTL
LVTTL
I
I
197
193
Parity Select. When high selects even parity. When low selects
odd parity. This signal is static and must not be changed in normal
operation.
Reset. Active low. Asyncronous reset input for the device. During
reset PCLK A, B, C, D does not toggle and frame synchronization
with SYNCRST will be activated.
16
December 13, 1999 / Revision E
SONET/SDH OC-12 TO OC-48 MUX/DEMUX
S3045
Table 6. Common Pin Assignment and Descriptions (continued)
Pin Name
DLEB
Level
I/O
Pin #
Description
LVTTL
I
196
Diagnostic Loopback Enable. Active low. When DLEB is inactive,
the S3045 uses the primary data 311DATIN[7:0] and clock
311CLKIN inputs. When active, the S3045 selects diagnostic
loopback mode. In loopback mode the STS-48/STM-16
transmitter outputs (311DATOUT[7:0] and 311CLKOUT) are
internally connected to the STS-48/STM-16 receiver inputs
(311DATIN[7:0] and 311CLKIN). This signal is static and must not
be changed in normal operation.
VDD
202, 194, Power Pins. VDD pins must be tied to 3.3V. Note that it is
159, 143, recommended that VDD be powered on after VDD5.
123, 116,
109, 97,
82, 66,
58, 56,
55, 50,
28, 22, 12
VSS
195, 188, Ground Pins. VSS pins must be tied to ground.
170, 160,
147, 142,
132, 124,
108, 98,
90, 81,
71, 67,
63, 62,
61, 60,
59, 57,
49, 40,
29, 23,
13, 3
VDD5
171, 131, TTL I/O Power Pins. There are three power pins that may be
70
connected to 3.3 volts or 5 volts. When these pins are connected
to 3.3 volts, the TTL interface is a 3.3 volt LVTTL interface. When
these pins are connected to 5 volts, the TTL inputs are 5 volt TTL
tolerant. The TTL outputs are the same regardless of which
voltage is tied to VDD5. All three pins must be connected to the
same voltage level. Note that it is recommended that VDD5 be
powered on before VDD.
TEST_EN[0:1]
TEST1
LVTTL
LVTTL
LVTTL
64, 65
187
TEST Enable. For factory test. For normal operation tie low.
TEST Pins. For factory test. Must leave unconnected.
TEST Pins. For factory test. Must leave unconnected.
TEST2
189
17
December 13, 1999 / Revision E
S3045
SONET/SDH OC-12 TO OC-48 MUX/DEMUX
Figure 10. Parity Error (PARERR) Output Functional Timing Diagram
Bad parity supplied to the S3045.
PCLK A,B,C,D
PARERR A,B,C,D
Note: PARERR A,B,C,D output
can be delayed by one to five
PCLK A,B,C,D cycles.
Figure 11. S3045 LVDS Inputs
S3041/S3042
S3045
Z = 50Ω
o
P
N
P
100Ω
N
275Ω
275Ω
Figure 12. S3045 LVDS Outputs
S3041
S3045
Z
= 50
o
P
N
P
N
18
December 13, 1999 / Revision E
SONET/SDH OC-12 TO OC-48 MUX/DEMUX
S3045
Figure 13. OOF and PULSEOOF Functional Timing Diagram
Frame
Boundary
/A1A2 A1A2 /A1A2 /A1A2 /A1A2 /A1A2 /A1A2 /A1A2 /A1A2 /A1A2
A1A2
A1A2
OOF
PULSEOOF
Notes:
– PULSEOOF minimum pulse width is 7.5ns.
– Timing specifications are met with a 15pf load.
19
December 13, 1999 / Revision E
S3045
SONET/SDH OC-12 TO OC-48 MUX/DEMUX
Figure 14. S3045 Pinout
FRAMEP
FRAMEN
1
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
PINB[7]
PINB[6]
PINB[5]
PINB[4]
PINB[3]
PINB[2]
PINB[1]
PINB[0]
TIFPB
2
3
VSS
311DATINP[0]
311DATINN[0]
311DATINP[1]
311DATINN[1]
311DATINP[2]
311DATINN[2]
311DATINP[3]
311DATINN[3]
VDD
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
VSS
PARINB
PARERRB
PAROUTB
VDD
VSS
311DATINP[4]
311DATINN[4]
311DATINP[5]
311DATINN[5]
311DATINP[6]
311DATINN[6]
311DATINP[7]
311DATINN[7]
VDD
VSS
POCLKB
POUTB[7]
POUTB[6]
POUTB[5]
POUTB[4]
POUTB[3]
POUTB[2]
POUTB[1]
POUTB[0]
VSS
S3045 Pinout
Top View
208-pin PQFP/TEP
28mm x 28mm x 3.4mm
VSS
311CLKINP
311CLKINN
311CLKOUTN
311CLKOUTP
VDD
VDD5
FPB
PICLK
VSS
PCLKA
PCLKB
PCLKC
PCLKD
VSS
311TCLKN
311TCLKP
311DATOUTN[0]
311DATOUTP[0]
311DATOUTN[1]
311DATOUTP[1]
311DATOUTN[2]
311DATOUTP[2]
311DATOUTN[3]
311DATOUTP[3]
VSS
VDD
SYNCRSTB
PINC[7]
PINC[6]
PINC[5]
PINC[4]
PINC[3]
VDD
311DATOUTN[4]
311DATOUTP[4]
311DATOUTN[5]
311DATOUTP[5]
311DATOUTN[6]
311DATOUTP[6]
311DATOUTN[7]
311DATOUTP[7]
VSS
PINC[2]
PINC[1]
PINC[0]
TIFPC
PARINC
PARERRC
VDD
VSS
POCLKC
POUTC[7]
POUTC[6]
VDD
PULSEN
PULSEP
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December 13, 1999 / Revision E
SONET/SDH OC-12 TO OC-48 MUX/DEMUX
S3045
Figure 15. S3045 208 PQFP TEP (28 x 28 x 3.40mm) - Plastic Quad Flat Pack
Top View
Bottom View
Note: The S3045 package is equipped with an embedded conductive heatsink on the top.
Thermal Management
Θja (Still Air)
Θjc
Device
Max Package Power
S3045
2.20 W
12.9 oC/W
0.3 oC/W
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December 13, 1999 / Revision E
S3045
SONET/SDH OC-12 TO OC-48 MUX/DEMUX
Table 7. Absolute Maximum Ratings
Parameter
Min
-65
-0.5
0
Typ
Max Units
Storage Temperature
150
+5.0
+5.0
˚ C
V
Voltage on VDD/VDD5 with respect to GND
Voltage on any LVPECL Input Pin
V
VDD5
+0.5
Voltage on any LVTTL Input Pin
-0.5
V
ESD Ratings
The S3045 is rated to the following ESD voltages based on the human body
model:
1. All pins are rated above 1000 V.
Table 8. Recommended Operating Conditions
Parameter
Min
0
Typ
Max Units
Ambient Temperature Under Bias
Voltage on Vdd with respect to GND
+70
˚ C
V
3.14
3.3
3.47
VDD
-2.00
VDD
-0.4
Voltage on any LVPECL Input Pin
Voltage on any LVTTL Input Pin
V
V
VDD5
+0.5V
0
VDD
+0.5V
Voltage on any LVTTL Output Pin
Power Dissipation
V
1.66
2.2
W
Note: Power dissipation characterized using pseudo random pattern.
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December 13, 1999 / Revision E
SONET/SDH OC-12 TO OC-48 MUX/DEMUX
S3045
Table 9. LVPECL Input DC Characteristics
Parameters
VIL
Description
Input LOW Voltage
Min
VDD -2.0
VDD -1.0
-20
Max
VDD -1.6
VDD -0.4
20
Units
V
Conditions
VIH
IIH
Input HIGH Voltage
V
Single-ended input HIGH current
Single-ended input LOW current
SDVBB pin
µA
µA
V
VIN = VDD -0.4V
IIL
-20
20
VIN = VDD -2.0V
VOUT
1.8
2.2
IOUT = 0, VDD = 3.47V
Table 10. LVTTL Input/Output DC Characteristics
Parameters Description
VOH Output HIGH Voltage
Min
Typ
Max Units
Conditions
2.4
VDD
.5
V
V
VDD = 3.14V, IOH = -2.4mA
VDD = 3.14V, IOL = 2.4mA
VOL
VIH
Output LOW Voltage
Input HIGH Voltage
0.7
VDD
V
V
0.3
VDD
VIL
Input LOW Voltage
Input HIGH Current, for 5V tolerant
input
II
1
50
50
10
50
-0.2
mA
µA
µA
µA
µA
V
V
IN = VDD5 = 5.5V
VIN = 2.4V
VIN = 2.4V
IIH
IIH
IIL
IIL
VIK
Input HIGH Current
-50
10
2
Input HIGH Current with pulldowns
TEST_EN0, TEST_EN1
25
Input LOW Current
-500
1
VIN = 0.5V
VIN = 0.5V
IIN = -18mA
Input LOW Current with pulldowns
TEST_EN0, TEST_EN1
10
Input Clamp Voltage
-1.2
-0.8
Note: The term LVTTL implies CMOS levels for this device.
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December 13, 1999 / Revision E
S3045
SONET/SDH OC-12 TO OC-48 MUX/DEMUX
Table 11. LVDS Input/Output Characteristics
Parameters
IIH
Description
Input High Current
Min
-10
Typ
Max Units
Conditions
VIN = 1.4V
10
10
µA
µA
mV
V
IIL
Input Low Current
-10
VIN = 1.0V
VDIFF
VIH
VIL
Ro
Input Voltage Differential
100
0.95
450
1.75
117
V
Output Impedence Single ended
57
Ohm
Ro mismatch between differential
outputs
Delta Ro
1
%
VOS
VOH
VOL
Output Offset Voltage
Output High Voltage
Output Low Voltage
1.1
1.2
1.30
1.45
1.15
1.40
1.60
1.25
V
V
V
100 Ohms across diff. pair
100 Ohms across diff. pair
100 Ohms across diff. pair
0.93
VOUT
(diff)
Output Differential Voltage
Input Differential Threshold
250
300
450
mV
mV
100 Ohms across diff. pair
Vdim
-100
+100
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December 13, 1999 / Revision E
SONET/SDH OC-12 TO OC-48 MUX/DEMUX
S3045
Figure 16. AC Transmitter Parallel Input Data Timing Diagram
t
PCLK
PCLK A,B,C,D
t
PICLK
PICLK
tS
tH
PIN
PIN
PINA[7:0]
PINB[7:0]
PINC[7:0]
PIND[7:0]
TIFP A,B,C,D
PARIN A,B,C,D
Table 12. AC Transmitter Parallel Data Input Timing Characteristics
Parameters
Characteristics
PCLK A, B, C, D 77.76 MHz Output Clock
PCLK A, B, C, D 77.76 MHz Output Clock duty cycle
Parallel Input Clock (PICLK) period
Min
Typ
Max Units
tPCLK
12.86
ns
40
60
60
%
ns
%
tPICLK
12.86
Parallel Input Clock (PICLK) duty cycle
40
PINA[7:0], PINB[7:0], PINC[7:0], PIND[7:0] PARIN A, B, C, D and
TIFP A, B, C, D, data setup time with respect to rising edge of PICLK
tSPIN
tHPIN
1.3
ns
PINA[7:0], PINB[7:0], PINC[7:0], PIND[7:0] PARIN A, B, C, D and
TIFP A, B, C, D, data hold time with respect to rising edge of PICLK
0.85
ns
ns
PCLK Rise and Fall Times (10%–90%)
2.5
Notes
1. Timing depicted in Figure 16 assumes PCLKA,B,C,D and PICLK are the same frequency.
2. Timing specifications are met with a 15pf load.
3. Timing specifications are measured with VDD = 3.3V at 25˚ C.
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December 13, 1999 / Revision E
S3045
SONET/SDH OC-12 TO OC-48 MUX/DEMUX
Figure 17. AC Parity Error Timing Diagram
PCLK A,B,C,D
tHERR
tSERR
PARERR A,B,C,D
Table 13. Parity Error Timing Characteristics
Symbol
Description
Min
3.5
3.5
Max Units
tSERR
tHERR
Parity Error Output Set-up Time w.r.t. PCLK
Parity Error Output Hold Time w.r.t. PCLK
ns
ns
Note: Timing specifications are met with a 15pf load.
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December 13, 1999 / Revision E
SONET/SDH OC-12 TO OC-48 MUX/DEMUX
S3045
Figure 18. AC Transmitter Output Timing Diagram
311CLKOUTP
tS
311
tH
311
311DATOUT[7:0]
READP/N
Notes:
1. When a set-up time is specified on differential LVDS signals between an input and a clock, the set-up time is the time in nanoseconds from
the cross-over point of the input to the cross-over point of the clock.
2. When a hold time is specified on differential LVDS signals between an input and a clock, the hold time is the time in nanoseconds from the
cross-over point of the clock to the cross-over point of the input.
Table 14. Transmitter Output Timing Characteristics
Symbol
Description
Min
33
Max Units
311CLKOUT Duty Cycle
67
%
ns
ns
tS311
tH311
311DATOUT[7:0] Set-up Time w.r.t. 311CLKOUTP
311DATOUT[7:0] Hold Time w.r.t. 311CLKOUTP
0.65
0.55
Table 15. Transmitter Input Timing Characteristics
Symbol Description
311TCLK
Min
Max Units
55
311TCLK Duty Cycle
45
%
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December 13, 1999 / Revision E
S3045
SONET/SDH OC-12 TO OC-48 MUX/DEMUX
Figure 19. AC Receiver Input Timing Diagram
311CLKINP
tS
tH
311O
311O
311DATIN[7:0]
Frame
Notes:
1. When a set-up time is specified on differential LVDS signals between an input and a clock, the set-up time is the time in nanoseconds from
the cross-over point of the input to the cross-over point of the clock.
2. When a hold time is specified on differential LVDS signals between an input and a clock, the hold time is the time in nanoseconds from the
cross-over point of the clock to the cross-over point of the input.
Table 16. AC Receiver Input Timing Characteristics
Symbol
Description
Min
40
Max Units
311CLKIN Duty Cycle
60
%
ns
ns
tS311O
tH311O
311DATIN[7:0] and Frame Set-up Time w.r.t. 311CLKINP
311DATIN[7:0] and Frame Hold Time w.r.t. 311CLKINP
0.8
0.8
Figure 20. AC Pulse Timing Diagram
311TCLKP
PULSEP/N
tS
tH
PS
PS
Table 17. AC Pulse Timing Characteristics
Symbol
Description
Min
Max Units
tSPS
tHPS
PULSEP/N Setup Time w.r.t. 311TCLKP
PULSEP/N Hold Time w.r.t. 311TCLKP
0.8
0.8
ns
ns
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December 13, 1999 / Revision E
SONET/SDH OC-12 TO OC-48 MUX/DEMUX
S3045
Table 18. AC Receiver Output Timing Characteristics
Symbol
Description
Min
Max Units
POCLK Frequency (nominally 77.76MHz)
POCLK Duty Cycle
78
60
MHz
%
40
4
tSPOUT
tHPOUT
POUT[7:0] Set-up Time to POCLK
POUT[7:0] Hold Time to POCLK
POCLK Rise and Fall Times (10% – 90%)
ns
3.5
ns
2.5
ns
Note: Timing specifications are met with a 15pf load. Timing specifications are measured with VDD = 3.3V at 25˚ C.
Figure 21. AC Receiver Output Timing Diagram
POCLKA, B, C, D
tS
tH
POUT
POUT
POUT[7:0]A, B, C, D,
FP, PAROUTA, B, C, D
J0FP, B1ERR
Table 19. Reset Timing Characteristics
Symbol
Description
Min
Max Units
RSTB
Minimum assertion of RESET(RSTB), to reset the S3045
30
ns
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December 13, 1999 / Revision E
S3045
SONET/SDH OC-12 TO OC-48 MUX/DEMUX
Ordering Information
PREFIX
DEVICE
PACKAGE
S – Integrated Circuit
3045
B – 208 PQFP/TEP
X
XXXX
X
Prefix Device
Package
Applied Micro Circuits Corporation • 6290 Sequence Dr., San Diego, CA 92121
Phone: (858) 450-9333 • (800) 755-2622 • Fax: (858) 450-9885
http://www.amcc.com
AMCC reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and
advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information being relied
on is current.
AMCC does not assume any liability arising out of the application or use of any product or circuit described herein, neither does it
convey any license under its patent rights nor the rights of others.
AMCC reserves the right to ship devices of higher grade in place of those of lower grade.
AMCC SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR
USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS.
AMCC is a registered trademark of Applied Micro Circuits Corporation.
Copyright ® 1999 Applied Micro Circuits Corporation
30
December 13, 1999 / Revision E
相关型号：
S30460E3
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