AM79C981 [AMD]
Integrated Multiport Repeater Plus⑩ (IMR+⑩); 集成多端口中继加™ （ IMR + ™ ）
| 型号： | AM79C981 |
| 厂家： | 
AMD |
| 描述： | Integrated Multiport Repeater Plus⑩ (IMR+⑩) |
| 文件： | 总40页 (文件大小：256K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
Am79C981
Integrated Multiport Repeater Plus™ (IMR+™)
DISTINCTIVE CHARACTERISTICS
■ Enhanced version of AMD’s Am79C980
Integrated Multiport Repeater™ (IMR™) chip
with the following enhancements:
10BASE-F and/or Fiber Optic Inter-Repeater
Link (FOIRL) segments
■ On-board PLL, Manchester encoder/decoder,
— Additional management port features
and FIFO
— Minimum mode provides support for an extra
four LED outputs per port for additional status in
non-intelligent repeater designs
■ Expandable to increase number of repeater
ports
■ All ports can be separately isolated (partitioned)
in response to excessive collision conditions or
fault conditions
— Pin/socket-compatible with the Am79C980
IMR chip
— Fully backward-compatible with existing IMR
device designs
■ Network management and optional features are
accessible through a dedicated serial
management port
■ Interfaces directly with the Am79C987 HIMIB™
device to build a fully managed multiport
repeater
■ Twisted-pair Link Test capability conforming to
the 10BASE-T standard. The receive Link Test
function can be optionally disabled through the
management port to facilitate interoperability
with devices that do not implement the LinkTest
function
■ CMOS device features high integration and low
power with a single +5 V supply
■ Repeater functions comply with IEEE 802.3
Repeater Unit specifications
■ Programmable option of Automatic Polarity
Detection and Correction permits automatic
recovery due to wiring errors
■ Eight integral 10BASE-T transceivers utilize the
required predistortion transmission technique
■ Attachment unit interface (AUI) port allows
connectivity with 10BASE-5 (Ethernet) and
10BASE-2 (Cheapernet) networks, as well as
■ Full amplitude and timing regeneration for
retransmitted waveforms
■ Preamble loss effects eliminated by deep FIFO
GENERAL DESCRIPTION
The Integrated Multiport Repeater Plus (IMR+) chip is a
VLSI circuit that provides a system-level solution to de-
signing a compliant 802.3 repeater incorporating
10BASE-T transceivers. The device integrates the
Repeater functions specified by Section 9 of the IEEE
802.3 standard and Twisted-Pair Transceiver functions
complying with the 10BASE-T standard. The Am79C981
provides eight integral twisted-pair medium attachment
units (MAUs) and an attachment unit interface (AUI) port
in an 84-pin plastic leaded chip carrier (PLCC).
their expansion ports, minimizing the total cost per re-
peater port. Furthermore, a general-purpose attach-
ment unit interface (AUI) provides connection capability
to 10BASE-5 (Ethernet) and 10BASE-2 (Cheapernet)
coaxial networks, as well as 10BASE-F and/or Fiber
Optic Inter-Repeater Link (FOIRL) fiber segments. Net-
work management and test functions are provided
through TTL-compatible I/O pins.
The IMR+ device interfaces directly with AMD’s
Am79C987 Hardware Implemented Management In-
formation Base™ (HIMIB) chip to build a fully managed
multiport repeater as specified by the IEEE 802.3
(Layer Management for 10 Mb/s Baseband Repeaters)
standard. When the IMR+ and HIMIB devices are
interconnected, complete repeater and per-port statis-
tics are maintained and can be accessed on demand
using a simple 8-bit parallel interface.
A network based on the 10BASE-T standard uses un-
shielded twisted-pair cables, thereby providing an eco-
nomical solution to networking by allowing the use of
low-cost unshielded twisted-pair (UTP) cable or existing
telephone wiring.
The total number of ports per repeater unit can be in-
creased by connecting multiple IMR+ devices through
Publication# 17306 Rev: B Amendment/0
Issue Date: January 1999
This document contains information on a product under development at Advanced Micro Devices. The
information is intended to help you evaluate this product. AMD reserves the right to change or discontinue
work on this proposed product without notice.
1-71
PRELIMINARY
AMD
For application examples on building a fully managed
repeater using the IMR+ and HIMIB devices, refer to
AMD’s IEEE 802.3 Repeater Technical Manual
(PID#17314A) and the ISA-HUBTM User Manual
(PID # 17642A).
The device is fabricated in CMOS technology and re-
quires a single +5 V supply.
BLOCK DIAGRAM
DI±
AUI
Port
Manchester
Decoder
RX
MUX
CI±
FIFO
DO±
TX
MUX
Preamble
Phase =
Locked
Loop
Jam Sequence
RXD±
FIFO
Control
TP
Port
0
TXD±
TXP±
Manchester
Encoder
RXD±
REQ
ACK
TP
Port
7
IMR+ Chip
Control
TXD±
TXP±
Expansion Port
COL
Partitioning
Link Test
DAT
JAM
RST
Reset
SI
X
1
Clock
Gen
SO
Test
and
Management
Port
SCLK
TEST
X
2
Timers
CRS
STR
17306B-1
RELATED AMD PRODUCTS
Part No.
Description
Am79C98
Am79C100
Am7996
Twisted Pair Ethernet Transceiver (TPEX)
Twisted Pair Ethernet Transceiver Plus (TPEX+)
IEEE 802.3/Ethernet/Cheapernet Transceiver
Am79C987
Am79C940
Am7990
Hardware Implemented Management Information Base (HIMIB )
Media Access Controller for Ethernet (MACE )
Local Area Network Controller for Ethernet (LANCE)
Am79C90
Am79C900
Am79C960
Am79C961
Am79C965
Am79C970
Am79C974
CMOS Local Area Network Controller for Ethernet (C-LANCE)
Integrated Local Area Communications Controller (ILACC )
PCnet-ISA Single-Chip Ethernet Controller (for ISA bus)
PCnet-ISA+ Single-Chip Ethernet Controller for ISA (with Microsoft Plug n’ Play Support)
PCnet-32 Single-Chip 32-Bit Ethernet Controller
PCnet-PCI Single-Chip Ethernet Controller (for PCI bus)
PCnet-SCSI Combination Ethernet and SCSI Controller for PCI Systems
1–72
Am79C981
P R E L I M I N A R Y
CONNECTION DIAGRAM
PLCC
76
75
11 10 9 8 7
6
5
4
3 2 1 84 83 82 81 80 79 78 77
DO–
12
13
14
74
73
72
71
70
69
68
RXD7–
TXD7+
TXD7–
DVSS
DO+
TXD0+
15
16
17
18
19
20
TXD0–
DVSS
TXP7+
TXP7–
DVDD
TXD6+
TXD6–
TXP1+
TXP1–
DVDD
67
66
65
TXD1+
TXD1–
TXP1+
TXP1–
21
22
TXP6+
TXP6–
TXD5+
IMR+ Chip
Am79C981
64
63
62
61
60
59
58
23
24
25
26
27
28
29
30
31
32
TXD2+
TXD2–
TXD5–
TXP5+
TXP2+
TXP2–
DVDD
TXP5–
DVDD
TXD4+
TXD3+
57
56
TXD4–
DVSS
TXD3–
DVSS
55
54
TXP4+
TXP4–
TXP3+
33 34 35 36 37 38 39 40 41 42 43 44 45 46 4748 49 50 51 52 53
17306B-2
Am79C981
1–73
PRELIMINARY
AMD
LOGIC SYMBOL
DVDD
AVDD
TXD+
TXP+
DO+
DO–
Twisted Pair
Ports
(8 Ports)
TXD–
TXP–
DI+
DI–
AUI
RXD+
RXD–
CI+
CI–
Am79C981
DAT
JAM
SCLK
SI
SO
Management
Port
Expansion
Port
ACK
COL
REQ
X2
X1
CRS
STR
Port
Activity
Monitor
TEST
RST
DVSS
AVSS
17306B-3
LOGIC DIAGRAM
AUI
Repeater
State
Machine
Management
Port
Expansion
Port
Twisted Pair
Port 0
Twisted Pair
Port 7
17306B-4
1–74
Am79C981
P R E L I M I N A R Y
ORDERING INFORMATION
Standard Products
AMD standard products are available in several packages and operating ranges. The order number (valid combination) is formed
by a combination of the elements below.
Am79C981
J
C
OPTIONAL PROCESSING
Blank = Standard Processing
OPERATING CONDITIONS
C = Commercial (0°C to +70°C)
PACKAGE TYPE
J = 84-Pin Plastic Leaded Chip Carrier (PL 084)
SPEED
Not Applicable
DEVICE NUMBER/DESCRIPTION
Am79C981
Integrated Multiport Repeater Plus (IMR+)
Valid Combinations
Valid Combinations
Am79C981 JC
Valid combinations list configurations planned to be sup-
ported in volume for this device. Consult the local AMD sales
office to confirm availability of specific valid combinations and
to check on newly released combinations.
Am79C981
1–75
P R E L I M I N A R Y
When ACK is not asserted, DAT is in high impedance.
PIN DESCRIPTION
ACK
If REQ and ACK are both asserted, then DAT is an out-
put. If ACK is asserted and REQ not asserted, then
DAT is an input.
Acknowledge
Input, Active LOW
This pin needs to be either pulled up or pulled down
through a high-value resistor.
When this input is asserted, it signals to the requesting
IMR+ device that it may control the DAT and JAM pins.
If the IMR+ chip is not requesting control of the DAT line
(REQ pin HIGH), then the assertion of the ACK signal
indicates the presence of valid collision status on the
JAM or valid data on the DAT line.
DI+, DI–
Data In
Input
AUI port differential receiver. Signals comply with IEEE
802.3, Section 7.
AVDD
Analog Power
Power Pin
DO+, DO–
Data Out
Output
These pins supply the +5 V to the RXD+/– receivers,
the DI+/– and CI+/– receivers, the DO+/– drivers, the
internal PLL, and the internal voltage reference of the
IMR+ device. These power pins should be decoupled
and kept separate from other power and ground
planes.
AUI port differential driver. Signals comply with IEEE
802.3, Section 7.
DVDD
Digital Power
Power Pin
AVSS
These pins supply +5 V to the logic portions of the
IMR+ chip and the TXP+/–, TXD+/–, and DO+/– line
drivers.
Analog Ground
Ground Pin
These pins are the 0 V reference for AVDD
.
DVSS
COL
Digital Ground
Ground Pin
Expansion Collision
Input, Active LOW
These pins are the 0 V reference for DVDD
.
When this input is asserted by an external arbiter, it sig-
nifies that more than one IMR+ device is active and that
each IMR+ device should generate the Collision Jam
sequence independently.
DVDD Pin #
DVSS Pin #
Function
19
28
16
31
TP ports 0 & 1 drivers
TP ports 2 & 3 drivers
CI+, CI–
Core logic and expansion
and control pins
Control In
Input
43, 49
35, 37, 46, 51
AUI port differential receiver. Signals comply with IEEE
802.3, Section 7.
59
68
56
71
TP ports 4 & 5 drivers
TP ports 6 & 7 drivers
CRS
JAM
Carrier Sense
Output
Jam
Input/Output/3-State
The states of the internal carrier sense signals for the
AUI port and the eight twisted-pair ports are serially
output on this pin continuously. The output serial bit
stream is synchronized to the X1 clock.
When JAM is asserted, the state of DAT will indicate
either a multiport (DAT = 0) or single-port (DAT = 1) col-
lision condition.
When ACK is not asserted, JAM is in high impedance.
If REQ and ACK are both asserted, then JAM is an out-
put. If ACK is asserted and REQ not asserted, then
JAM is an input.
DAT
Data
Input/Output/3-State
In non-collision conditions, the active IMR+ device will
drive DAT with NRZ data, including regenerated pre-
amble. During collision, when JAM = HIGH, DAT is
used to signal a multiport (DAT = 0) or single-port
(DAT = 1) condition.
This pin needs to be either pulled up or pulled down
through a high-value resistor.
1–76
Am79C981
P R E L I M I N A R Y
input. In Minimum mode, the SO pin is used to serially
REQ
output the various status information based on the
state of the SI and SCLK pins.
Request
Output, Active LOW
This pin is driven LOW when the IMR+ chip is active.
An IMR+ chip is active when it has one or more ports
receiving or colliding or is in the state where it is still
transmitting data from the internal FIFO. The assertion
of this signal signifies that the IMR+ device is request-
ing the use of the DAT and JAM lines for the transfer of
repeated data or collision status to other IMR+ devices.
SCLK
SI
0
SO Output
TP Ports Receive Polarity Status + AUI
SQE Test Error Status
0
0
1
1
1
Bit Rate Error (all ports)
TP Ports Link Status + AUI Loopback
Status
0
RST
1
Port Partitioning Status (all ports)
Reset
Input, Active LOW
STR
Driving this pin LOW resets the internal logic of the
IMR+ device. Reset should be synchronized to the X1
clock if either expansion or port activity monitor is used.
Store
Input/Output
As an output, this pin goes HIGH for two X1 clock cycle
times after the nine carrier sense bits are output on the
CRS pin. Note that the carrier sense signals arriving
from each port are latched internally, so that an active
transition is remembered between samples. The accu-
racy of the carrier sense signals produced in this man-
ner is 10 bit times (1 µs).
RXD+0–7, RXD–0–7
Receive Data
Input
10BASE-T port differential receive inputs (8 ports).
SCLK
When used in conjunction with the HIMIB device, the
STR pin will be configured as an input automatically
after a hardware reset. The HIMIB device uses this
input to communicate with the IMR+ device. When
used with the HIMIB chip, this pin must be pulled up via
a high-value resistor.
Serial Clock
Input
In normal operating mode, serial data (input or output)
is clocked (in or out) on the rising edge of the signal on
this pin. SCLK is asynchronous to X1 and can operate
up to 10 MHz. In Minimum mode, this pin, together with
the SI pin, controls which information is output on the
SO pin.
TEST
Test Pin
Input, Active HIGH
SI
This pin should be tied LOW for normal operation. If
this pin is driven HIGH, then the IMR+ device can be
programmed for Loopback Test mode. Also, if this pin is
HIGH when the RST pin is deasserted, the IMR+ de-
vice will enter the Minimum mode. An inverted version
of the RST signal can be used to program the device
into the Minimum mode.
Serial In
Input
In normal operating mode, the SI pin is used for test/
management serial input port. Management com-
mands are clocked in on this pin synchronous to the
SCLK input. In Minimum mode, this pin, together with
the SCLK pin, controls which information is output on
the SO pin.
Test
SI
0
Functions
Normal Management Mode
Normal Management Mode
In Minimum mode, the state of SI at the deassertion of
RST signal determines the programming of automatic
polarity detection/correction for 10BASE-T ports.
0
0
1
Minimum Mode, Receive Polarity
Correction Disabled
SO
1
1
0
1
Serial Out
Output
Minimum Mode, Receive Polarity
Correction Enabled
In normal operating mode, the SO pin is used for test/
management serial output port. Management results
are clocked out on this pin synchronous to the SCLK
Am79C981
1–77
P R E L I M I N A R Y
TXD+0–7, TXD–0–7
X1
Transmit Data
Output
Crystal 1
Crystal Connection
10BASE-T port differential drivers (8 ports).
The internal clock generator uses a 20 MHz crystal at-
tached to pins X1 and X2. Alternatively, an external
20MHz CMOS clock signal can be used to drive this
pin.
TXP+0–7, TXP–0–7
Transmit Predistortion
Output
X2
10BASE-T transmit waveform predistortion control
differential outputs (8 ports).
Crystal 2
Crystal Connection
The internal clock generator uses a 20 MHz crystal at-
tached to pins X1 and X2. If an external clock source is
used, this pin should be left unconnected.
1–78
Am79C981
PRELIMINARY
AMD
IMR+ chip can be read through the Management Port
using the Get MJLP Status command (M bit returned).
FUNCTIONAL DESCRIPTION
The Am79C981 Integrated Multiport Repeater Plus de-
vice is a single chip implementation of an IEEE
802.3/Ethernet repeater (or hub). In addition to the eight
integral 10BASE-T ports plus one AUI port comprising
the basic repeater, the IMR+ chip also provides the
hooks necessary for complex network management
and diagnostics. The IMR+ device is also expandable,
enabling the implementation of high port count repeat-
ers based on several IMR+ devices.
Collision Handling
The IMR+ chip will detect and respond to collision condi-
tions as specified in 802.3. A multiple-IMR+ device re-
peater implementation also complies with the 802.3
specification due to the inter-IMR+ chip status commu-
nication provided by the expansion port. Specifically, a
repeater based on one or more IMR+ devices will han-
dle the transmit collision and one-port-left collision con-
ditions correctly as specified in Section 9 of the 802.3
specification.
The IMR+ device interfaces directly with AMD’s
Am79C987 Hardware Implemented Management Infor-
mation Base (HIMIB) device to allow a fully managed
multiportrepeatertobeimplementedasspecifiedbythe
Layer Management for 10 Mb/s Baseband Repeaters
Standard. When the IMR+ and HIMIB devices are used
as a chip set, the HIMIB device maintains complete re-
peater and per port statistics which can be accessed on
demand by a microprocessor through a simple 8-bit par-
allel port.
Fragment Extension
If the total packet length received by the IMR+ device is
less than 96 bits, including preamble, the IMR+ chip will
extend the repeated packet length to 96 bits by append-
ing a Jam sequence to the original fragment.
Auto Partitioning/Reconnection
Any of the integral TP ports and AUI port can be parti-
tioned under excessive duration or frequency of colli-
sion conditions. Once partitioned, the IMR+ device will
continue to transmit data packets to a partitioned port,
but will not respond (as a repeater) to activity on the par-
titioned port’s receiver. The IMR+ chip will monitor the
port and reconnect it once certain criteria indicating port
‘wellness’ are met. The criteria for reconnection are
specified by the 802.3 standard. In addition to the stan-
dard reconnection algorithm, the IMR+ device imple-
ments an alternative reconnection algorithm which
provides a more robust partitioning function for the TP
ports and/or the AUI port. Each TP port and the AUI port
are partitioned and/or reconnected separately and inde-
pendently of other network ports.
The IMR+ chip complies with the full set of repeater ba-
sic functions as defined in section 9 of ISO 8802.3
(ANSI/IEEE 802.3c). These functions are summarized
below.
Repeater Function
If any single network port senses the start of a valid
packet on its receive lines, then the IMR+ device will re-
transmit the received data to all other enabled network
ports. The repeated data will also be presented on the
DAT line to facilitate multiple-IMR+ device repeater
applications.
Signal Regeneration
When re-transmitting a packet, the IMR+ device en-
sures that the outgoing packet complies with the 802.3
specificationintermsofpreamblestructure, voltageam-
plitude, and timing characteristics. Specifically, data
packets repeated by the IMR+ chip will contain a mini-
mum of 56 preamble bits before the Start of Frame De-
limiter. Inaddition, thevoltageamplitudeoftherepeated
packet waveform will be restored to levels specified in
the 802.3 specification. Finally, signal symmetry is re-
stored to data packets repeated by the IMR+ device,
removing jitter and distortion caused by the network
cabling.
Either one of the following conditions occuring on any
enabled IMR+ device network port will cause the port to
partition:
a. A collision condition exists continuously for a time
between 1024- to 2048-bit times (AUI port—SQE
signal active; TP port—simultaneous transmit and
receive)
b. A collision condition occurs during each of 32 con-
secutive attempts to transmit to that port.
Once a network port is partitioned, the IMR+ device will
reconnect that port if the following is met:
Jabber Lockup Protection
The IMR+ chip implements a built-in jabber protection
scheme to ensure that the network is not disabled due to
transmission of excessively long data packets. This pro-
tection scheme will automatically interrupt the transmit-
ter circuits of the IMR+ device for 96-bit times if the IMR+
devicehasbeentransmittingcontinuouslyformorethan
65,536-bit times. This is referred to as MAU Jabber
Lockup Protection (MJLP). The MJLP status for the
a. Standard reconnection algorithm—A data packet
longer than 512-bit times (nominal) is transmitted or
received by the partitioned port without a collision.
b. Alternate reconnection algorithm—A data packet
longer than 512-bit times (nominal) is transmitted by
the partitioned port without a collision.
Am79C981
1–79
PRELIMINARY
AMD
The reconnection algorithm option (standard or alter-
nate) is a global function for the TP ports, i.e. all TP ports
use the same reconnection algorithm. The AUI
reconnection algorithm option is programmed inde-
pendently of the TP port reconnection option.
to be repeated with correct polarity. This function is exe-
cuted once following reset or link fail, and has a
programmable enable/disable option on a port-by-port
basis. This function is disabled upon reset and can be
enabled via the IMR+ chip Management Port.
Link Test
Reset
The integral TP ports implement the Link Test function
asspecifiedinthe802.310BASE-Tstandard. TheIMR+
device will transmit Link Test pulses to any TP port after
that port’s transmitter has been inactive for more than 8
to 17 ms. Conversely, if a TP port does not receive any
data packets or Link Test pulses for more than 65 to
132 ms and the Link Test function is enabled for that
port then that port will enter link fail state. A port in link
fail state will be disabled by the IMR+ chip (repeater
transmit and receive functions disabled) until it receives
either four consecutive Link Test pulses or a data pack-
et. The Link Test receive function itself can be disabled
via the IMR+ chip management port on a port-by-port
basis to allow the IMR+ device to interoperate with pre-
10BASE-T twisted pair networks that do not implement
the Link Test function. This interoperability is possible
becausetheIMR+devicewillnotallowtheTPporttoen-
ter link fail state, even if no Link Test pulses or data
packets are being received. Note however that the
IMR+ chip will always transmit Link Test pulses to all TP
ports regardless of whether or not the port is enabled,
partitioned, in link fail state, or has its Link Test receive
function disabled.
The IMR+ device enters reset state when the RST pin is
driven LOW. After the initial application of power, the
RST pin must be held LOW for a minimum of 150 µs
(3000 X1 clock cycles). If the RST pin is subsequently
asserted while power is maintained to the IMR+ device,
a reset duration of only 4 µs is required. The IMR+ chip
continues to be in the reset state for 10 X1 clocks
(0.5 µs) following the rising edge of RST. During reset,
the output signals are placed in their inactive states.
This means that all analog signals are placed in their idle
states, bidirectional signals (except STR signal) are not
driven, active LOW signals are driven HIGH, and all ac-
tive HIGH signals and the STR pin are driven LOW.
An internal circuit ensures that a minimum reset pulse is
generated for all internal circuits. For a RST input with a
slow rising edge, the input buffer threshold may be
crossed several times due to ripple on the input
waveform.
In a multiple IMR+ chip repeater the RST signal should
be applied simultaneously to all IMR+ devices and
should be synchronized to the external X1 clock. Reset
synchronization is also required when accessing the
PAM (Port Activity Monitor).
Polarity Reversal
The SI signal should be held HIGH for at least 500 ns fol-
lowing the rising edge of RST.
The TP ports have the optional (programmable) ability
to invert (correct) the polarity of the received data if the
TP port senses that the received data packet waveform
polarity is reversed due to a wiring error. This receive
circuitry polarity correction allows subsequent packets
Table 1 summarizes the state of the IMR+ chip following
reset.
Table 1. IMR+ Chip After Reset
State After Reset
Function
Active LOW outputs
Pull Up/Pull Down
HIGH
LOW
HIGH
No
No
Active HIGH outputs
SO Output
No
DAT, JAM
HI-IMPEDANCE
LOW
Either
Pull Up*
No
STR
Transmitters (TP and AUI)
Receivers (TP and AUI)
AUI Partitioning/Reconnection Algorithm
TP Port Partitioning/Reconnection Algorithm
Link Test Function for TP Ports
IDLE
ENABLED
Terminated
N/A
STANDARD ALGORITHM
STANDARD ALGORITHM
ENABLED, TP PORTS IN LINK FAIL
DISABLED
N/A
N/A
Automatic Receiver Polarity Reversal Function
*Only when used with the HIMIB device.
N/A
1–80
Am79C981
PRELIMINARY
AMD
than one active IMR+ device at a time constitutes a colli-
sion condition, and all IMR+ devices are notified of this
occurence via the COL line of the Expansion Port.
Expansion Port
The IMR+ chip Expansion Port is comprised of five pins;
two are bi-directional signals (DAT and JAM), two arein-
put signals (ACK and COL), and one is an output signal
(REQ). These signals are used when a multiple-IMR+
device repeater application is employed. In this configu-
ration, all IMR+ chips must be clocked synchronously
with a common clock connected to the X1 inputs of all
IMR+ devices. Reset needs to be synchronized to
X1 clock.
Note that a transition from multiple IMR+ devices arbi-
trating for the DAT and JAM pins (with COL asserted,
ACK deasserted) to a condition when only one IMR+
chip is arbitrating for the DAT and JAM pins (with ACK
asserted, COLdeasserted)involvesoneexpansionport
bus cycle (100 ns). During this transitional bus cycle,
COL is deasserted, ACK is asserted, and the DAT and
JAM pins are not driven. However, each IMR+ device
will remain in the collision state (transmitting jam se-
quence) during this transitional bus cycle. In subse-
quent expansion port bus cycles (REQ and ACK still
asserted), the IMR+ devices will return to the ‘master
and slaves’ condition where only one IMR+ device is ac-
tive (with collision) and is driving the DAT and JAM pins.
An understanding of this sequence is crucial if non-
IMR+ devices (such as an Ethernet controller) are con-
nected to the expansion bus. Specifically, the last
device to back off of the Expansion Port after a multi-
IMR+ chip collision must assert the JAM line until it too
drops its request for the Expansion Port.
The IMR+ device expansion scheme allows the use of
multiple IMR+ chips in a single board repeater or a
modular multiport repeater with a backplane architec-
ture. The DAT pin is a bidirectional I/O pin which can be
used to transfer data between the IMR+ devices in a
multiple-IMR+ chip design. The data sent over the DAT
line is in NRZ format and is synchronized to the common
clock. The JAM pin is another bidirectional I/O pin that is
usedbytheactiveIMR+chiptocommunicateitsinternal
status to the remaining (inactive) IMR+ devices. When
JAM is asserted HIGH, it indicates that the active IMR+
device has detected a collision condition and is generat-
ing Jam Sequence. During this time when JAM is as-
serted HIGH, the DAT line is used to indicate whether
the active IMR+ chip is detecting collision on one port
only or on more than one port. When DAT is driven
HIGH by the IMR+ chip (while JAM is asserted by the
IMR+ chip), then the active IMR+ device is detecting a
collision condition on one port only. This ‘one-port-left’
signaling is necessary for a multiple-IMR+ device re-
peatertofunctioncorrectlyasasinglemultiportrepeater
unit. The IMR+ chip also signals the ‘one port left’ colli-
sion condition in the event of a runt packet or collision
fragment;thissignalwillcontinueforoneexpansionport
bus cycle (100 ns) before deasserting REQ.
External Arbiter
A simple arbitration scheme is required when multiple
IMR+devicesareconnectedtogethertoincreasetheto-
tal number of repeater ports. The arbiter should have
one input (REQ1...REQn) for each of the n IMR+ de-
vices to be used, and two global outputs (COL and
ACK). This function is easily implemented in a PAL de-
vice, with the following logic equations:
ACK = REQ1 & REQ2 & REQ3 & ....REQn
+
REQ1 & REQ2 & REQ3 & ....REQn
•
•
•
The arbitration for access to the bussed bi-directional
signals (DAT and JAM) is provided by one output (REQ)
and two inputs (ACK and COL). The IMR+ chip asserts
the REQ pin to indicate that it is active and wishes to
drive the DAT and JAM pins. An external arbiter senses
the REQ lines from all the IMR+ devices and asserts the
ACK line when one and only one IMR+ chip is asserting
its REQ line. If more than one IMR+ chip is asserting its
REQ line, the arbiter must assert the COL signal, indi-
cating that more than one IMR+ device is active. More
+
REQ1 & REQ2 & REQ3 & .... REQn
COL = ACK & (REQ1 + REQ2 + REQ3 + ... REQn)
Above equations are in positive logic, i.e., a variable is
true when asserted.
A single PALCE16V8 will perform the arbitration func-
tion for a repeater based on several IMR+ devices.
Am79C981
1–81
PRELIMINARY
AMD
Bus transceivers needed
if DAT and JAM buses
exceed 100 pF loading.
REQ2 REQ3 REQ1
COL
ARBITER
ACK
ACK
REQ
DIR
DAT
JAM
Note 1
A
B
REQ
ACK
1/2 ’74
ASYNC
RESET
Am79C981
IMR+ Chip
1
D
D FF
CK
COL
RST
Q
X1
XTAL
OSC.
REQ
ACK
COL
RST
X1
DAT
JAM
Am79C981
IMR+ Chip
2
REQ
ACK
DAT
JAM
COL Am79C981
IMR+ Chip
3
RST
Note 1:
X1
Direction
DIR
17306B-5
B → A
A → B
LOW
HIGH
Figure 1. Multiple IMR+ Devices
repeater module performs the local arbitration function
for the IMR+ devices on that module, and provides sig-
nals to the backplane for use by a global arbiter.
Modular Repeater Design
The expansion port of the IMR+ chip also allows for
modularexpansion. Bysharingthearbitrationdutiesbe-
tween a backplane bus architecture and several sepa-
rate repeater modules one can build an expandable
repeater based on modular ‘plug-in’ cards. Each
For more detailed information, see AMD’s IEEE 802.3
Repeater Technical Manual, PID# 17314A.
1–82
Am79C981
PRELIMINARY
AMD
network, andthenetworkaddressabilityallowsaremote
management station to monitor this statistical data and
to request actions to be performed by the repeater (i.e.
port enable/disable).
Repeater MAC Interconnection
Because all repeated data in the IMR+ chip or multi-
IMR+ chip design is available on the Expansion Port, all
network traffic can be monitored by an external Media
Access Controller (MAC) device such as the Am7990,
Am79C900, Am79C940, orAm79C960. A repeaterwith
such a controller is capable of providing extensive hub
managementfunctions, aswellasbeingaddressableas
a network node. The MAC device can gather statistics
and data concerning the state of the hub and the
Figure 2 shows how to interface a repeater based on
multiple IMR+ devices to an Ethernet controller such as
theAm79C900ILACCortheAm7990LANCE. Formore
information on this design, refer to AMD’s IEEE 802.3
Repeater Technical Manual, PID# 17314A.
Am7990 LANCE
Am79C900 ILACC
Am79C940 MACE
or
Am79C960 PCnet-ISA
DONE_COUNT
NEW96
DONE_COUNT
NEW96
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Interface
PALCE16V8
TCK
Arbiter
PALCE16V8
Counter
PALCE22V10
RTSCLK
CDT
CDT
RCKEN
ACKCLK
ARST
IMR+1
IMR+2
IMR+n
X1
X1
X1
RST
RST
RST
17306B-6
20 MHz Osc.
Figure 2. Expandable Modular Repeater
Am79C981
1–83
PRELIMINARY
setup and hold times with respect to the input bit pattern.
AMD
Management Port
If the latter method is used, it is to be noted that 20 SCLK
clock transitions are required for proper execution of
management commands that produce SO data, and
that 14 SCLK clock transitions are needed to execute
management commands that do not produce SO data.
The IMR+ device management functions are enabled
when the TEST pin is tied LOW. The management com-
mands are byte oriented data and are input serially on
theSIpin. Anyresponsesgeneratedduringexecutionof
a management command are output serially in a byte-
oriented format by the IMR+ device on the SO pin. Both
the input and output data streams are clocked with the
rising edge of the SCLK pin. The serial command data
stream and any associated results data stream are
structured in a manner similar to the RS232 serial data
format, i.e., one Start Bit followed by eight Data Bits.
Management Commands
The following section details the operation of each man-
agement command available in the IMR+ chip. In all
cases, the individual bits in each command byte are
shown with the MSB on the left and the LSB on the right.
Data bytes are received and transmitted LSB first and
MSB last. See Table 2 for a summary of the manage-
ment commands.
The externally generated clock at the SCLK pin can be
either a free running clock synchronized to the input bit
patterns or a series of individual transitions meeting the
Command Execution Phase
Results Phase
Next Command
SCLK
SI
STRT D0 D1 D2 D3 D4 D5 D6 D7
SO
STRT D0 D1 D2 D3 D4 D5 D6 D7
17306B-17
Management Command/Response Timing
Command Execution Phase
Next Command Execution Phase
SCLK
SI
STRT D0 D1 D2 D3 D4 D5 D6 D7
STRT D0 D1 D2 D3 D4 D5 D6 D7
17306B-18
SO
Management Command Timing with No Response
1–84
Am79C981
PRELIMINARY
AMD
Table 2. Management Port Command Summary
Commands
SI Data
SO Data
Set (Write) Opcodes
IMR+ Chip Programmable Options
Alternate AUI Partitioning Algorithm
Alternate TP Partitioning Algorithm
AUI Port Disable
0000 1CSA
0001 1111
0001 0000
0010 1111
0011 1111
0010 0###
0011 0###
AUI Port Enable
TP Port Disable
TP Port Enable
Disable Link Test Function (per TP port)
Enable Link Test Function (per TP port)
Disable Automatic Receiver Polarity Reversal (per TP port)
Enable Automatic Receiver Polarity Reversal (per TP port)
Get (Read) Opcodes
0100 0###
0101 0###
0110 0###
0111 0###
AUI Port Status (B, S, L Cleared)
TP Port Partitioning Status
1000 1111
1000 0000
1010 0000
1101 0000
1110 0000
1111 0000
1111 1111
1000 1011
1000 1101
1000 1001
PBSL 0000
C7...C0
Bit Rate Status of TP ports
E7...E0
Link Test Status of TP ports
L7...L0
Receive Polarity Status of all TP ports
MJLP Status
P7...P0
M000 0000
XXXX 0001
PBSL 0000
PBSL 0000
PBSL 0000
Version
AUI Port Status (S, L Cleared)
AUI Port Status (B Cleared)
AUI Port Status (None Cleared)
Notes:
1. Unused opcodes are reserved for future use.
2. ### is the port number (000 to 111 for TP0 to TP7)
Am79C981
1–85
PRELIMINARY
A—Alternative Port Activity Monitor (PAM)
AMD
SET (Write) Opcodes
IMR+ Chip Programmable Options
Function
Setting the Alternative Port Activity Monitor Function al-
lows the PAM function to be altered such that the Carrier
Sense data is presented unmodified. In default opera-
tion the PAM output (Carrier Sense bits in the CRS bit
stream) are masked if the port is either disabled or parti-
tioned. This does not allow the Repeater Management
software to sense activity on all segments at all times.
Theabilitytomonitorpartitionedordisabledportsallows
faulttolerancetobebuiltintotheRepeaterManagement
software.
SI data:
0000 1CSA
SO data: None
IMR+ Chip Programmable Options can be enabled (dis-
abled) by setting (resetting) the appropriate bit in the
command string. The three programmable bits are:
C—CI Reporting; S—AUI SQE Test Mask, and
A—Alternative Port Activity Monitor (PAM) Function.
These options can be enabled (disabled) by setting (re-
setting) the appropriate bit in the command string.
Alternate AUI Port Partitioning Algorithm
When writing to this register through the Am79C987
HIMIB device, the A and C bits should not be changed
(A=0, C=1).
SI data:
00011111
SO data: None
The AUI port Partitioning/Reconnection scheme can be
programmed for the alternate (transmit only) reconnec-
tion algorithm by invoking this command. To return the
AUI back to the standard (transmit or receive)
reconnection algorithm, it is necessary to reset the
IMR+ device. Standard partitioning algorithm is se-
lected upon reset.
C—CI Reporting
Setting this bit alters the function of the STR pin. In this
mode, the STR pin becomes an input in response to the
AMD’s Am79C987 HIMIB device. Upon deassertion of
RST, theHIMIBautomaticallysetsthisbitfollowingIMR/
IMR+ device type detection.
Alternate TP Ports Partitioning Algorithm
When this mode is selected, the CRS output bit string
format is modified to include CI carrier bit (in addition to
AUI carrier). This bit occupies the bit position immedi-
ately preceding the AUI bit in the CRS bit string (10 bits)
output. Note that the AUI bit gets asserted if either the CI
or DI signal pairs are active.
SI data:
00010000
SO data: None
The TP ports Partitioning/Reconnection scheme can be
programmed for the alternate (transmit only)
reconnection algorithm by invoking this command. All
TP ports are affected as a group by this command. To
return the TP ports back to the standard (transmit or re-
ceive) reconnection algorithm, it is necessary to reset
the IMR+ device. The standard partitioning algorithm is
selected upon reset.
S—AUI SQE Test Mask
Setting this bit allows the IMR+ chip to ignore activity on
the CI signal pair, in the SQE Test Window, following a
transmission on the AUI port. This event occurs when
the attached MAU has the SQE Test option enabled,
thereforegeneratingaburstofCIactivityfollowingevery
transmission. This is interpreted by the IMR+ device as
a collision, causing the IMR+ device to generate a full
Jampattern. AlthoughtheMAUattachedtoarepeateris
required not to have its SQE test function active, this is a
common installation error, causing difficulty in diagnos-
ing network throughput problems.
AUI Port Disable
SI data:
00101111
SO data: None
The AUI port will be disabled upon receiving this com-
mand. Subsequently, the IMR+ chip will ignore all inputs
(Carrier Sense and SQE) appearing at the AUI port and
will not transmit any data or Jam Sequence on the AUI
port. Issuing this command will also cause the AUI port
to have its internal partitioning state machine forced to
its idle state. Therefore, a Partitioned Port may be re-
connected by first disabling and then re-enabling
the port.
The SQE Test Window, as defined by the IEEE 802.3
(Section 7.2.2.2.4), is from 6-bit times to 34-bit times
(0.6 µs to 3.4 µs). This includes delay introduced by a
50 m AUI. CI activity that occurs outside this window is
not ignored and is treated as true collision.
Note that enabling this function does not prevent the re-
porting of this condition by the IMR+ device and the two
functions operate independently.
1–86
Am79C981
PRELIMINARY
Enable Link Test Function of a TP Port
SI data: 01010###
AMD
AUI Port Enable
SI data:
SO data: None
00111111
SO data: None
This command enables a previously disabled AUI port.
Note that a partitioned AUI port may be reconnected by
first disabling (AUI Port Disable Command) and then re-
enabling the port with this command.
(### is TP port number)
This command re-enables the Link Test Function in the
TP port designated in the command byte. This com-
mand executes only if the designated TP port has had
the Link Test Function disabled by the Disable Link Test
Function command. Otherwise, the command is ig-
nored. Link Test is enabled upon reset.
All ports are enabled upon reset.
TP Port Disable
SI data:
SO data: None
00100###
Disable Automatic Receiver Polarity Reversal
SI data:
SO data: None
01100###
(### is TP port number)
The TP port designated in the command byte will be dis-
abled upon receiving this command. Subsequently, the
IMR+ device will ignore all inputs appearing at the dis-
abledport’sreceivepinsandwillnottransmitanydataor
JAM Sequence on that port’s transmit pins. Issuing this
command will also cause a TP port to have its partition-
ing state machine returned to its Idle State (Port Recon-
(### is TP port number)
ThiscommanddisablestheAutomaticReceiverPolarity
Reversal Function for the TP port designated in the
command byte. If this function is disabled on a TP port
with reverse polarity (due to a wiring error), then the TP
port will fail Link Test due to the reversed polarity of the
Link Pulses. If the Link Test Function is also disabled on
the TP port, then the received reversed polarity packets
would be repeated to all other network ports in the IMR+
chip as inverted data. Automatic Polarity reversal is dis-
abled upon reset.
nected). Therefore,
a partitioned port may be
reconnected by first disabling and then re-enabling the
port. The disabled port will continue to report correct
Link Test Status.
TP Port Enable
Enable Automatic Receiver Polarity Reversal
SI data:
00110###
SO data: None
SI data:
01110###
SO data: None
(### is TP port number)
(### is TP port number)
This command enables a previously disabled TP port.
Re-enablingadisabledportcausestheporttobeplaced
into Link Test Fail state. This ensures that packet frag-
mentsreceivedontheportarenotrepeatedtotherestof
the network. Note that to force a TP port into the Link Fail
state and/or to reconnect a partitioned TP port, the port
should first be disabled (TP Port Disable Command)
and then re-enabled with this command. All ports are
enabled upon reset.
This command enables the Automatic Receiver Polarity
Reversal Function for the TP port designated in the
command byte. If enabled in a TP port, the IMR+ chip
will automatically invert the polarity of that TP port’s re-
ceiver circuitry if the TP port is detected as having
reversed polarity (due to a wiring error). After reversing
the receiver polarity, the TP port could then receive sub-
sequent (reverse polarity) packets correctly.
Disable Link Test Function of a TP Port
GET (Read) Opcodes
SI data:
SO data: None
01000###
AUI Port Status
SI data:
SO data: PBSL0000
10001111
(### is TP port number)
The combined AUI status allows a single instruction to
be used for monitoring AUI port. The four status bits re-
ported are:
This command disables the Link Test Function at the TP
port designated in the command byte, i.e., the TP port
willnolongerbedisconnectedduetoLinkFail. ATPport
which has its Link Test Function disabled will continue to
transmit Link Test Pulses. If a twisted pair port has Link
Test disabled, then reading the Link Test Status indi-
cates it being in Link Test Pass.
Am79C981
1–87
PRELIMINARY
Bit Rate Error Status of TP Ports
SI data: 10100000
AMD
P Partitioning Status. This bit is 0 if the AUI port is
partitioned and 1 if connected.
B Bit Rate Error. This bit is set to 1 if there has been
an instance of FIFO Overflow or Underflow,
caused by data received at the AUI port. This bit is
cleared when the status is read.
SO data: E7...............E0
This allows a single command to be used to report Bit
Rate Error condition (FIFO Overflow or Underflow) of all
Twisted Pair ports. The 8 bits of the output pattern corre-
spond to each of the 8 TP ports, with least significant bit
corresponding to port 0.
S SQE Test Status. This bit is set to 1 if SQE Test is
detected by the IMR+ chip. This bit is cleared
when the status is read. A MAU attached to a re-
peater must have SQE Test disabled. This bit is
set even if the AUI port is disabled or partitioned.
The status bit for a port is set to 1 if there has been an
instance when data received from that port has caused
a FIFO error.
L Loop Back Error. The MAU attached to the AUI is
required to loopback data transmitted to DO onto
the DI circuit. If loopback carrier is not detected by
the IMR+ device, then this bit is set to 1 to report
this condition. This bit is cleared when the status is
read. For a repeater this is the only indication of a
broken or missing MAU.
All status bits stay set until the status is read.
Link Test Status of TP Ports
SI data:
11010000
SO data: L7...............L0
Ln = 0
Ln = 1
TP Port n in Link Test Fail
TP Port n in Link Test Pass
Alternate AUI Port Status
SI data:
10001111
SO data: PBSL0000
The Link Test Status of all eight TP ports are accessed
by this command. A disabled port continues to report
correct Link Test Status. Re-enabling a disabled port
causes the port to be placed into Link Test Fail state.
This ensures that packet fragments received on the port
are not repeated to the rest of the network.
There are three further variations of the above com-
mand, allowing selective clearing of a combination of B,
S, and L bits. They are primarily included for use by the
HIMIB chip. These are:
Alternative 1.
Receive Polarity Status of TP Ports
SI data:
SO data: PBSL0000
10001011
SI data:
SO data: P7...............P0
11100000
B is not cleared. S and L are cleared.
Pn = 0
Pn = 1
TP Port n Polarity Correct
TP Port n Polarity Reversed
Alternative 2.
SI data:
10001101
The statuses of all eight TP port polarities are accessed
with this command. The IMR+ chip has the ability to de-
tect and correct reversed polarity on the TP ports’
RXD+/– pins. If the polarity is detected as reversed for a
TP port, then the IMR+ chip will set the appropriate bit in
this command’s result byte only if the Polarity Reversal
Function is enabled for that port.
SO data: PBSL0000
S and L are not cleared. B is cleared.
Alternative 3.
SI data:
10001001
SO data: PBSL0000
MJLP Status
None of S, B and L are cleared.
SI data:
SO data: M00000000
11110000
TP Port Partitioning Status
SI data: 10000000
SO data: P7.................P0
Each IMR+ chip contains an independent MAU Jabber
Lock Up Protection Timer. The timer is designed to in-
hibit the IMR+ device transmit function, if it has been
transmitting continuously for more than 65536 Bit
Times. The MJLP Status bit (M) is set to 1 if this
happens. This bit remains set and is only cleared when
the MJLP status is read by using this command.
Pn = 0
Pn = 1
TP port n partitioned
TP port n connected
The partitioning Status of all eight TP ports are ac-
cessed by this command. If a port is disabled, reading it
partitioning status will indicate that it is connected.
1–88
Am79C981
PRELIMINARY
AMD
Version
In Minimum Mode, the SO pin is used to serially output
the various status information based on the state of the
SI and SCLK pins. A summary of the status information
is provided in the following table.
SI data:
SO data: XXXX0001
11111111
This command (1111 1111) can be used to determine
the device version.
SCLK
SI
SO Output
0
0
TP Ports Receive Polarity Status +
AUI SQE Test Error Status.
The IMR+ chip responds by the bit pattern: XXXX 0001
The IMR chip (Am79C980) responds by the bit pattern:
XXXX 0000
0
1
1
0
Bit Rate Error (all ports).
TP Ports Link Status + AUI
LoopBack Status
Minimum Mode
1
1
Port Partitioning Status (all ports)
The Minimum Mode reconfigures the IMR+ device
Management Port and is intended to provide support for
the low end, non-managed repeaters, requiring minimal
external logic to provide LED indication of:
When SI = 0 then SO will output the related AUI status
bits (LoopBack or SQE), followed by the 8 TP status bits
(Link or Polarity), starting with the TP port 0.
■ Twisted Pair Ports Link Status indication and AUI
When SI = 1, the Port Partitioning Status or Port Bit Rate
Error Status are scanned out with the AUI first and TP
ports following. TP Port 0 is scanned out first.
Loopback Status
■ Port Partitioning Status
■ Twisted Pair Ports Receiver Polarity Status and
Note that the Bit Rate Error, AUI Loopback, and AUI
SQE Test Error status bits stay set until they are
scanned out.
AUI SQE Test Error Status
■ Port Bit Rate Error Status
The Minimum Mode is selected by controlling the state
of the TEST pin while RST is asserted. If TEST is High
(asserted), while reset is active (RST LOW), then Mini-
mum Mode is selected. The state of SI pin, at the
deassertion of the RST signal, determines whether the
IMR+ chip is to be programmed for Automatic Polarity
Detection/Correction.
The state of SI and SCLK inputs is checked at the end of
every STR cycle. The rising edge of the X1 clock, occur-
ring before falling edge of STR, is used to strobe in the
state of the SI and SCLK pins.
In this Minimum Mode, the Management Port mode is
not active. To exit the Minimum mode, the IMR+ device
must reset into the normal Management Port mode.
When entering the Minimum Mode, the TEST input has
tobedeassertedontherisingedgeofreset. Amaximum
delay of 100 ns is allowed to account for slow devices.
The following table summarizes the different modes
available.
Test
SI
0
Functions
0
0
1
Normal Management Mode
Normal Management Mode
1
0
Minimum Mode, Receive
Polarity Correction disabled
1
1
Minimum Mode, Receive
Polarity Correction enabled
Am79C981
1–89
PRELIMINARY
AMD
1/2 ’74
TCK
D
Q
TCK
CK
Q
CLR
XTAL
OSC
X1
X2
CK
SI
SIPO
SO
Am79C981
IMR+ Chip
1/2 ’74
RST
CK
D
Q
CK
Register
STR
ASYNC
RESET
TEST
T T T
P P P
7 6 5
T A
P U
SCLK SI
0
I
17306B-7
Figure 3. Minimum Mode, Non-Intelligent Repeater Example
X1
TCK
(Note 1)
CRS
AUI
CRS
TP0
CRS
TP1
CRS
TP2
CRS
TP3
CRS
TP4
CRS
TP5
CRS
TP6
CRS
TP7
CRS
AUI
CRS
(Note 2)
SO
AUI
SO
TP0
SO
TP1
SO
TP2
SO
TP3
SO
TP4
SO
TP5
SO
TP6
SO
TP7
SO
AUI
SO
(Note 3)
STR
Notes:
17306B-8
1. Externally generated signal illustrates internal IMR+ chip clock phase relationship.
2. CRS timing with the C-bit cleared (IMR+ Chip Programmable Options)
3. For Minimum Hub Mode
Figure 4. Management Port Minimum Mode and
Port Activity Monitor Signal Relationship
The following diagram shows typical external hardware
employed to convert the serial bit stream into parallel
form. The accuracy of the CRS signals is 10 Bit Times
(BT) (1 µs). Specifically, a transition to active state by
any of the internal carrier sense bits that lasts for less
than 10BT is latched internally and is used to set the ap-
propriate bit during the next sample period.
Port Activity Monitor
Two pins, CRS and STR, are used to serially output the
state of the internal Carrier Sense signals from the AUI
and the eight TP ports. This function together with exter-
nal hardware and/or software can be used to monitor re-
peater receive and/or collision activity.
1–90
Am79C981
PRELIMINARY
AMD
1/2 ’74
TCK
TCK
D
Q
CK
Q
CLR
Shift Register
SIPO
XTAL
OSC
X1
CK
SI
CRS
Am79C981
IMR+ Chip
X2
1/2 ’74
RST
CK
D
Q
CK
Register
STR
ASYNC
RESET
T T T
P P P
7 6 5
T A
P U
0
I
Carrier Sense Outputs
17306B-9
Figure 5a. Port Activity Monitor Implementation
1
2
9
10 11
X1
RST
TCK
(Note1)
AUI
TP0
TP1
TP7
X
(Note 2)
AUI
TP0
CRS
STR
(Note 3)
Notes:
17306B-10
1. Externally generated signal illustrates internal IMR+ chip clock phase relationship.
2. IMR+ chip standalone, X will be low. When attached to a HIMIB device, X reflects the state of the CI pair.
3. STR signal is not available when the IMR+ chip is attached to HIMIB device, and must be generated externally.
Figure 5b. Port Activity Monitor Implementation (Continued)
Am79C981
1–91
PRELIMINARY
TXP outputs. Only receive data that passes the required
AMD
Loopback Test Mode
amplitude squelch criteria is looped back to the transmit
outputs. Note that the data is looped back unaltered,
meaning that no signal retiming or regeneration takes
place. Therefore, any signal distortion present on the re-
ceive data paths will be retransmitted.
The IMR+ chip can be programmed to enter Loopback
Mode on all network ports. This is accomplished by first
driving the TEST pin HIGH, then clocking (using the
SCLK pin) a minimum of three 0s into the SI pin. This
causes the IMR+ chip to loop all received data on each
port back to each port’s corresponding transmit outputs.
Specifically, the AUI DI input is passed unaltered to the
AUI DO output, and each RXD input on the twisted pair
ports is passed (unaltered) to the respective TXD and
In Minimum Mode, the Loopback Test Mode cannot be
accessed. The IMR+ device will return to normal opera-
tion when the TEST pin is again driven LOW.
TEST
SI
SCLK
17306B-11
Figure 6. Programming the IMR+ Device for Loopback Mode
1–92
Am79C981
PRELIMINARY
AMD
the twisted pair receivers employ several criteria to con-
tinuously monitor the incoming signal’s amplitude and
timing characteristics to determine when and if to assert
the internal carrier sense. For these reasons, it is crucial
that the values and tolerances of the external compo-
nents be as specified. Several manufacturers produce a
module that combines the functions of the transmit and
receive filters and the pulse transformers into one
package.
IMR+ Chip External Components
Figure 6 shows a typical twisted pair port external com-
ponents schematic. The resistors used should have a
1% tolerance to ensure interoperability with 10BASE-T
compliant networks. The filters and pulse transformers
are necessary devices that have a major influence on
theperformanceandcomplianceofthe10BASE-Tports
of the repeater. Specifically, the transmitted waveforms
are heavily influenced by the filter characteristics and
Filter &
Transformer
Module
RJ45
Connector
61.9Ω
TXD+
422Ω
1:1
TXP+
TD+
TD–
3
6
XMT
Filter
61.9Ω
1.21KΩ
TXD–
Am79C981
422Ω
TXP–
RXD+
RXD–
Note 2
Note 1
1:1
RD+
RD–
1
2
RCV
Filter
100Ω
17306B-12
Notes:
1. Compatible filter modules, with a brief description of package type and features are included in the Appendix.
2. The resistor values are recommended for general purpose use and should allow compliance to the 10BASE-T specification
for template fit and jitter performance. However, the overall performance of the transmitter is also affected by the transmit
filter configuration.
Figure 7a. Typical TP Port External Components
Pulse
Transformer
AUI
Connector
DO+
DO–
DI+
DI–
3
10
5
Note 1
Am79C981
12
2
CI+
CI–
9
40.2Ω
40.2Ω
40.2Ω
40.2Ω
0.1µF
Optional
0.1µF
ANLG GND
17306B-13
Notes:
1. Compatible AUI transformer modules, with a brief description of package type and features are included in the Appendix.
2. The differential input DI± and the CI± pairs are externally terminated by two 40.2 Ω ±1% resistors and one optional common-
mode bypass capacitor. The differential input impedance, ZIDF, and the common-mode input impedance, ZICM, are speci-
fied so that the Ethernet specification for cable termination impedance is met using standard 1% resistor terminators. If SIP
devices are used, 39 Ω is the nearest usable equivalent value.
Figure 7b. Typical AUI Port Components
Am79C981
1–93
PRELIMINARY
AMD
APPLICATIONS
A fully managed multiport repeater can be easily built by
interfacing the IMR+ chip with the Hardware Imple-
mented Management Information Base (HIMIB),
Am79C987 device. The HIMIB device interfaces with all
common Microprocessor System Busses with a
minimum of external logic. Note that additional buffering
of DAT and JAM are required for most applications. For
more information, refer to AMD’s IEEE 802.3 Repeater
Technical Manual (PID# 17314A).
Host
System
Bus
Expansion
Bus
DAT
JAM
Address
CS
Decode
HIMIB
C/D
CRS
STR
SI
CRS
STR
SI
IMR+
SO
SO
SCLK
SCLK
X1
Data
Buffer
REQ
D [7–0]
RD
ACK
WR
COL
RST
CK
RDY
INT
17306B-14
Figure 8. Simplified ISA-HUB Block Diagram
1–94
Am79C981
PRELIMINARY
AMD
ABSOLUTE MAXIMUM RATINGS
OPERATING RANGES
Storage Temperature . . . . . . . . . . . –65°C to +150°C
Ambient Temperature Under Bias . . . . . . . 0 to 70°C
Commercial (C) Devices
Temperature (TA) . . . . . . . . . . . . . . . . 0 to +70°C
Supply Voltage (AVDD, DVDD) . . . . . . . 5 V to ±5%
Supply Voltage referenced to
AVSS or DVSS (AVDD, DVDD) . . . . . . . . . . –0.3 to +6 V
Operating ranges define those limits between which the fun-
tionality of the device is guaranteed
.
Stresses above those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent device failure. Functionality
at or above these limits is not implied. Exposure to absolute
maximum ratings for extended periods may affect device
reliability.
DC CHARACTERISTICS over operating ranges unless otherwise specified
Parameter
Symbol
Parameter Description
Test Conditions
Min
Max
Unit
Digital I/O
VIL
VIH
VOL
VOH
IIL
Input LOW Voltage
Input HIGH Voltage
Output LOW Voltage
Output HIGH Voltage
DVSS = 0.0 V
–0.5
2.0
–
0.8
V
V
DVDD+0.5
IOL = 4.0 mA
0.4
–
V
IOH = –0.4 mA
DVSS<VIN<DVDD
2.4
–
V
Input Leakage Current
10
µA
(also DAT and JAM as inputs)
VILX
VIHX
IILX
X1 Crystal Input LOW Voltage
X1 Crystal Input HIGH Voltage
Crystal Input LOW Current
Crystal Input HIGH Current
DVSS = 0.0 V
DVSS = 0.0 V
VIN = DVSS
VIN = DVDD
–0.5
3.8
–
1.0
DVDD+0.5
10
V
V
µA
µA
IIHX
AUI Port
IIAXD
–
10
Input Current at DI+/-
and CI+/- pairs
AVSS < VIN < AVDD
IIN = 0A, AVSS = 0 V
AVDD = 5.0 V
–500
AVDD – 3.0
–2.5
+500
AVDD–1.0
+2.5
µA
V
VAICM
DI+,DI-,CI+,CI- Open Circuit Input
Common Mode Voltage (bias)
VAIDV
Differential Mode Input
Voltage Range (DI, CI)
V
VASQ
VATH
VAOD
DI, CI Squelch Threshold
DI Switching Threshold
–275
–35
–160
+35
mV
mV
mV
(Note 1)
Differential Output Voltage
|(DO+) – (DO-)|
RL = 78 Ω
620
1100
VAODI
DO Differential Output
Voltage Imbalance
RL = 78 Ω
–25
+25
mV
V
AODOFF
DO Differential Idle Output Voltage
DO Differential Idle Output Current
DO+/- Common Mode Output Voltage
RL = 78 Ω
–40
–1
+40
+1
mV
mA
V
IAODOFF
VAOCM
RL = 78 Ω (Note 1)
RL = 78 Ω
2.5
AVDD
Am79C981
1–95
PRELIMINARY
AMD
DC CHARACTERISTICS (continued)
Parameter
Symbol
Parameter Description
Test Conditions
Min
Max
Unit
Twisted Pair Ports
IIRXD
RRXD
VTIVB
Input current at RXD+/-
AVSS<VIN<AVDD
(Note 1)
–500
10
+500
–
µA
KΩ
V
RXD differential input resistance
RXD+,RXD- open circuit input
voltage (bias)
IIN = 0 mA
AVDD–3.0 AVDD–1.5
VTID
VTSQ+
VTSQ-
VTHS+
VTHS-
Differential Mode input voltage
range (RXD)
AVDD = 5.0 V
–3.1
300
+3.1
520
V
RXD positive squelch threshold
(peak)
Sinusoid 5 MHz <f< 10 MHz
Sinusoid 5 MHz <f< 10 MHz
Sinusoid 5 MHz <f< 10 MHz
Sinusoid 5 MHz <f< 10 MHz
(Note 1)
mV
mV
mV
mV
RXD negative squelch threshold
(peak)
–520
150
–300
293
RXD post-squelch positive threshold
(peak)
RXD post-squelch negative threshold
(peak)
–293
–150
VRXDTH
VTXH
RXD switching threshold
–60
+60
mV
V
TXD+/- and TXP+/- output
HIGH voltage
DVSS = 0 V
(Note 2)
DVDD–0.6
DVDD
VTXL
TXD+/- and TXP+/- output
LOW voltage
DVDD = 5 V
(Note 2)
DVSS
DVSS+0.6
V
mV
mV
Ω
VTXI
TXD+/- and TXP+/- differential
output voltage imbalance
–40
–
+40
40
VTXOFF
RTXD
RTXP
TXD+/- and TXP+/- differential
idle output voltage
DVDD = 5 V
(Note 1)
TXD+/- differential driver
output impedance
–
40
TXP+/- differential driver
output impedance
(Note 1)
–
80
Ω
Power Supply Current
IDD Power supply current (idle)
fX1 = 20 MHz
fX1 = 20 MHz
–
–
180
300
mA
mA
Power supply current (transmitting
– no TP load)
Power supply current (transmitting
– with TP load)
fX1 = 20 MHz
–
(Note 8)
mA
1–96
Am79C981
PRELIMINARY
AMD
SWITCHING CHARACTERISTICS over operating ranges unless otherwise specified
Parameter
Symbol
Parameter Description
Test Conditions
Min
Max
Unit
Clock and Reset
tX1
tX1H
tX1L
X1 Clock Period
X1 Clock HIGH
49.995
20
50.005
30
ns
ns
ns
ns
ns
µs
X1 Clock LOW
20
30
tX1R
tX1F
tPRST
X1 Clock Rise Time
X1 Clock Fall Time
–
10
–
10
Reset pulse width after power on
150
–
(RST pin LOW)
tRST
Reset pulse width
(RST pin LOW)
4
20
0
–
–
–
µs
ns
ns
tRSTSET
RST HIGH setup time with
respect to X1 Clock
tRSTHLD
RST LOW hold time with
respect to X1 Clock
Management Port
tSCLK
tSCLKH
tSCLKL
tSCLKR
tSCLKF
tSISET
SCLK Clock Period
100
30
30
–
–
–
ns
ns
ns
ns
ns
ns
SCLK Clock HIGH
SCLK Clock LOW
–
SCLK Clock Rise Time
SCLK Clock Fall Time
10
10
–
–
SI input setup time with respect to SCLK
rising edge
10
tSIHLD
SI input hold time with
respect to SCLK rising edge
10
–
–
ns
ns
tSODLY
SO output delay with
CL = 100 pF
40
respect to SCLK rising edge
tX1HCRS
tX1HSTH
tX1HSTL
tTESTSET
X1 rising edge to CRS valid
X1 rising edge to STR HIGH
X1 rising edge to STR LOW
CL = 100 pF
CL = 100 pF
CL = 100 pF
5
–
40
40
40
–
ns
ns
ns
ns
–
TEST input setup time with respect to
SCLK rising edge
10
tTESTHLD
TEST input hold time with respect to
SCLK rising edge
10
–
ns
tSTRSET
STR setup time
STR hold time
5
–
–
ns
ns
tSTRHLD
12
Expansion Port
tX1HRL
tX1HRH
tX1HDR
tX1HDZ
X1 rising edge to REQ driven LOW
X1 rising edge to REQ driven HIGH
X1 rising edge to DAT/JAM driven
X1 rising edge to DAT/JAM not driven
CL = 100 pF
CL = 100 pF
CL = 100 pF
CL = 100 pF
14
14
14
14
40
40
40
40
ns
ns
ns
ns
Am79C981
1–97
PRELIMINARY
AMD
SWITCHING CHARACTERISTICS (continued)
Parameter
Symbol
Parameter Description
Test Conditions
Min
Max
Unit
Expansion Port (Continued)
tDJSET
tDJHOLD
tCASET
DAT/JAM setup time
10
14
5
–
–
–
–
–
ns
ns
ns
ns
ns
DAT/JAM hold time
COL/ACK setup time
COL/ACK hold time
tCAHOLD
tMHSET
14
200
TEST setup time with respect to RST
to enter Minimum Hub Mode
tMHHLD
TEST hold time with respect to RST
0
100
ns
to enter Minimum Hub Mode
tSCLKSET
SI, SCLK set up time with respect to X1
SI, SCLK hold time with respect to X1
50
50
–
–
ns
ns
tSCLKHLD
AUI Port
tDOTD
tDOTR
tDOTF
X1 rising edge to DO toggle
–
2.5
2.5
–
30
5.0
5.0
1.0
375
45
ns
ns
ns
ns
ns
ns
DO+,DO- rise time (10% to 90%)
DO+,DO- fall time (90% to 10%)
DO+,DO- rise and fall time mismatch
DO+/- End of Transmission
tDORM
tDOETD
tPWODI
275
15
DI pulse width accept/reject
threshold
|VIN| > |VASQ
(Note 3)
|
|
|
|
tPWKDI
tPWOCI
tPWKCI
DI pulse width maintain/turn-off
threshold
|VIN| > |VASQ
(Note 4)
136
10
200
26
ns
ns
ns
CI pulse width accept/reject
threshold
|VIN| > |VASQ
(Note 5)
CI pulse width maintain/turn-off
threshold
|VIN| > |VASQ
(Note 6)
90
160
Twisted Pair Ports
tTXTD
X1 rising edge to TXD+,TXP+
–
50
ns
TXD-,TXP- transition delay
tTR
tTF
tTM
TXD+,TXD-,TXP+,TXP- rise time
TXD+,TXD-,TXP+,TXP- fall time
–
–
–
20
20
6
ns
ns
ns
TXD+,TXD-,TXP+,TXP- rise
and fall time mismatch
tTETD
Transmit End of Transmission
275
130
375
200
ns
ns
tPWKRD
RXD pulse width maintain/turn-off
threshold
|VIN| > |VTHS
(Note 7)
|
tPERLP
tPWLP
Idle signal period
8
24
120
60
ms
ns
ns
Idle Link Test pulse width (TXD+)
Idle Link Test pulse width (TXP+,TXP-)
75
40
tPWPLP
1–98
Am79C981
PRELIMINARY
AMD
SWITCHING CHARACTERISTICS (continued)
Notes:
1. Parameter not tested.
2. Uses switching test load.
3. DI pulses narrower than tPWODI (min) will be rejected; pulses wider than tPWODI (max) will turn internal DI carrier sense on.
4. DI pulses narrower than tPWKDI (min) will maintain internal DI carrier sense on; pulses wider than tPWKDI (max) will turn internal
DI carrier sense off.
5. CI pulses narrower than tPWOCI (min) will be rejected; pulses wider than tPWOCI (max) will turn internal CI carrier sense on.
6. CI pulses narrower than tPWKCI (min) will maintain internal CI carrier sense on; pulses wider than tPWKCI (max) will turn
internal CI carrier sense off.
7. RXD pulses narrower than tPWKRD (min) will maintain internal RXD carrier sense on; pulse wider than tPWKRD (max) will
turn internal RXD carrier sense off.
8. For the typical twisted pair load as shown in Figure 7, using a 100 Ω cable, an additional 28 mA (max) of IDD current is
required for each twisted pair port used. Less than 18% of the power associated with this additional current is dissipated
by the IMR+ chip; the remainder is dissipated externally in the twisted pair load and cable.
Am79C981
1–99
PRELIMINARY
INPUTS
AMD
KEY TO SWITCHING WAVEFORMS
WAVEFORM
OUTPUTS
Must Be
Steady
Will Be
Steady
May
Change
from H to L
Will Be
Changing
from H to L
May
Change
from L to H
Will Be
Changing
from L to H
Don’t Care
Any Change
Permitted
Changing
State
Unknown
Does Not
Apply
Center
Line is High
Impedance
“Off” State
KS000010
SWITCHING WAVEFORMS
tX1
tX1H
tX1L
X1
17306B-15
tX1R
tX1F
Clock Timing
1–100
Am79C981
PRELIMINARY
AMD
SWITCHING WAVEFORMS
X1
tRSTHLD
RST
tRSTSET
tRST
or tPRST
TCK*
Notes:
17306B-16
tRSTSET refers to synchronous Reset Timing.
*Externally generated (Figure 4) signal illustrates internal IMR+ device clock phase relationships.
Reset Timing
tSCLK
tSCLKF
tSCLKR
SCLK
tSCLKH
tSCLKL
SI/TEST
tSISET
tTESTSET
tSIHLD
tTESTHLD
SO
17306B-19
tSODLY
tSODLY
Management Port Clock Timing
Am79C981
1–101
PRELIMINARY
AMD
SWITCHING WAVEFORMS
X1
TCK*
REQ
ACK
COL
tDJSET
tDJHOLD
DAT
JAM
IN
Note:
17306B-20
*Externally generated (Figure 4) signal illustrates internal IMR+ chip clock phase relationships.
Expansion Port Input Timing
X1
TCK*
tX1HRL
tX1HRH
REQ
tCASET
tCASET
ACK
COL
tCAHOLD
tX1HDR
tX1HDZ
DAT
JAM
OUT
Note:
17306B-21
*Externally generated (Figure 4) signal illustrates internal IMR+ chip clock phase relationships.
Expansion Port Output Timing
1–102
Am79C981
PRELIMINARY
AMD
SWITCHING WAVEFORMS
X1
TCK*
tX1HRL
REQ
tX1HRH
ACK
tCASET
tCASET
COL
tCAHOLD
DAT
IN
IN
JAM
Note:
17306B-22
*Externally generated (Figure 4) signal illustrates internal IMR+ chip clock phase relationships.
Expansion Port Collision Timing
Test
tMHSET
RST
tMHHLD
17306B-23
To Enter Minimum Mode
X1
STR
tX1HSTH
tX1HSTL
SI,
SCLK
Don’t Care
Don’t Care
tSCLKSET
tSCLKHLD
17306B-24
Minimum Mode
Am79C981
1–103
PRELIMINARY
AMD
SWITCHING WAVEFORMS
1
0
1
1
1
0
1
0
ETD
X1
tDOTD
tDOTR
tDOTF
tDOETD
D0+
D0–
17306B-25
AUI DO Timing Diagram
tDOETD
40 mV
DO+/–
0 V
100 mV max.
80-Bit Times
17306B-26
AUI Port DO ETD Waveform
tPWKDI
DI+/–
VASQ
tPWKDI
tPWODI
17306B-27
AUI Receive Timing Diagram
1–104
Am79C981
PRELIMINARY
AMD
SWITCHING WAVEFORMS
tPWKCI
CI+/–
VASQ
tPWOCI
tPWKCI
17306B-28
AUI Collision Timing Diagram
1
0
1
0
1
1
1
0
1
0
ETD
X1
tTXTD
tTXTR
tXTXTF
tTXETD
TXD+
TXP+
tTXTD
TXD–
TXP–
17306B-29
TP Ports Output Timing Diagram
Am79C981
1–105
PRELIMINARY
AMD
SWITCHING WAVEFORMS
tPWPLP
TXD+
TXP+
TXD–
tPWPLP
TXP–
tPWLP
tPERLP
17306B-30
TP Idle Link Test Pulse
tPWKRD
VTSQ+
RXD+/–
VTHS+
VTHS–
VTSQ–
17306B-31
tPWKRD
tPWKRD
TP Receive Timing Diagram
1–106
Am79C981
PRELIMINARY
AMD
SWITCHING TEST CIRCUITS
AVDD
52.3 Ω
DO+
DO–
Test Point
154 Ω
100 pF
Includes Test
Jig Capacitance
AVSS
17306B-32
AUI DO Switching Test Circuit
DVDD
294 Ω
TXD+
TXD–
Test Point
294 Ω
100 pF
Includes Test
Jig Capacitance
DVSS
17306B-33
TXD Switching Test Circuit
DVDD
715 Ω
TXP+
TXP–
Test Point
715 Ω
100 pF
Includes Test
Jig Capacitance
DVSS
17306B-34
TXP Outputs Test Circuit
Am79C981
1–107
APPENDIX
1 0 BAS E-T INTERFACE
A
The table below lists the recommended resistor values and filter and transformer modules for the IMR+ device.
IMR+ De vic e Co m p a t ib le 1 0 BAS E-T Me d ia In t e rfa c e Mo d u le s
¶ Manufacturer
Part #
Package
Description
Bel Fuse
Bel Fuse
Bel Fuse
Bel Fuse
S556-5999-32
0556-2006-14
A556-2006-DE
A556-2006-00
16-pin SMD
Transmit and receive filters, transformers and common mode chokes.
Transmit and receive filters, transformers and common mode chokes.
Transmit and receive filters and transformers.
10-pin SIL
16-pin 0.3" DIL
16-pin DIL
Transmit filter, transformers and common mode choke. Receive filter and
transformer.
Halo Electronics
Halo Electronics
FS02-101Y4
FS12-101Y4
"Slim SIP"
"Slim SIP"
Transmit and receive filters and transformers.
Transmit and receive filters and transformers, transmit common mode reduction
choke.
Halo Electronics
Halo Electronics
Halo Electronics
Halo Electronics
Halo Electronics
FS22-101Y4
FD02-101G
FD12-101G
FD22-101G
FD22-101R2
"Slim SIP"
Transmit and receive filters, transformers and common mode chokes.
Transmit and receive filters and transformers.
16-pin 0.3" DIL
16-pin 0.3" DIL
16-pin 0.3" DIL
16-pin 0.3" DIL
Transmit and receive filters and transformers, transmit common mode choke.
Transmit and receive filters, transformers and common mode chokes.
Termination and equalization resistors, transmit and receive filters, transformers
and common mode chokes.
Nano Pulse
Nano Pulse
Nano Pulse
5408-37
5408-40
6612-21
16-pin SMD
9-pin SIP
7 pole transmit and receive filters with 1CT:1CT Xfmrs (transmit & receive) and a
separate common mode choke for each channel.
7 pole transmit and receive filters with 1CT:1CT Xfmrs (transmit & receive) and a
separate common mode choke for each channel.
12-pin DIL
7 pole transmit and receive filters with 1CT:1CT Xfmrs (transmit & receive) and a
separate common mode choke for each channel.
PCA Electronics
PCA Electronics
PCA Electronics
PCA Electronics
Pulse Engineering
Pulse Engineering
Pulse Engineering
Pulse Engineering
Pulse Engineering
Pulse Engineering
Pulse Engineering
TDK
EPA1990A
16-pin 0.3" DIL
SMT device
16-pin 0.3" DIL
SMT device
16-pin DIL
Transmit and receive filters and transformers.
EPA1990AG
EPA2013D
Transmit and receive filters and transformers.
Transmit and receive filters and transformers, transmit common mode choke.
Transmit and receive filters and transformers, transmit common mode choke.
Transmit and receive filters and transformers, transmit common mode chokes.
Transmit and receive filters and transformers.
EPA2013DG
78Z034C
78Z1120B-01
78Z1122B-01
PE-68017S
PE-68026
16-pin DIL
16-pin DIL
Transmit and receive filters, transformers and common mode chokes.
Transmit and receive filters, transformers and common mode chokes.
Transmit and receive filters, transformers and common mode chokes.
Transmit and receive filters, transformers and common mode chokes.
Transmit and receive filters and transformers, transmit common mode chokes.
Transmit and receive filters and transformers, transmit common mode chokes.
10-pin SIL
16-pin SMT
16-pin SMT
13-pin PCMCIA-SMT
10-pin SIP
PE-68056
PE-68032
TLA-3M601-RS
TLA-3M102(-T)
TDK
16-pin SMD
Integrated resistors, transmit and receive filters and transformers, transmit common
mode chokes.
TDK
TLA-3M103(-T)
PT3877
16-pin SMD
Transmit and receive filters and transformers, transmit common mode chokes.
Transmit and receive filters and transformers.
Valor Electronics
Valor Electronics
Valor Electronics
16-pin 0.3" DIL
8-pin 0.3" DIL
16-pin 0.3" DIL
PT3983
Transmit and receive common mode chokes.
FL1012
Transmit and receive filters and transformers, transmit common mode chokes.
1-108
Am79C981
APPENDIX B
Glossary
Active Status
Partitioning
In a non-collision state, an IMR+ chip is considered ac-
tive if it is receiving data on any one of its network ports,
or is in the process of broadcasting (repeating) FIFO
data from a recently completed data reception. In a colli-
sion state (the IMR+ device is generating Jam Se-
quence), an IMR+ device is considered active if any one
or more network ports is receiving data. The IMR+ de-
vice asserts the REQ line to indicate that it is active.
A network port on a repeater has been partitioned if the
repeater has internally ‘disconnected’ it from the repeat-
er due to localized faults that would otherwise bring the
entire network down. These faults are generally cable
shortsandopensthattendtocauseexcessivecollisions
at the network ports. The partitioned network port will be
internally re-connected if the network port starts behav-
ing correctly again, usually when successful ‘collision-
less’ transmissions and/or receptions resume.
Collision
Receive Collision
In a carrier sense multiple access/collision detection
(CSMA/CD) network such as Ethernet, only one node
can successfully transfer data at any one time. When
two or more separate nodes (DTEs or repeaters) are si-
multaneously transmitting data onto the network, a Col-
lision state exists. In a repeater using one or more IMR+
devices, a Collision state exists when more than one
network port is receiving data at any instant, or when
any one or more network ports receives data while the
IMR+ device is transmitting (repeating) data, or when
the CI+/- pins become active (nominal 10 MHz signal)
on the AUI port.
A network port is in a Receive Collision state when it de-
tects collision and is not one of the colliding network
‘nodes’. This applies mainly to a non-transmitting AUI
port because a remote collision is clearly identified by
the presence of a nominal 10 MHz signal on the CI+/-
pins. However, any repeater port would be considered
to be in a receive collision state if the repeater unit is re-
ceiving data from that port as the ‘one-port-left’ in the
collision sequence.
Transmit Collision
A network port is in a Transmit Collision state when colli-
sion occurs while that port is transmitting. On the AUI
port, Transmit Collision is indicated by the presence of a
nominal 10 MHz signal on the CI+/- pins while the AUI
port is transmitting on the DO+/- pins. On a 10BASE-T
port, Transmit Collision occurs when incoming data ap-
pears on the RXD+/- pins while the 10BASE-T port is
transmitting on the TXD+/- and TXP+/- pins.
Jam Sequence
A signal consisting of alternating 1s and 0s that is gener-
ated by the IMR+ device when a Collision state is de-
tected. This signal is transmitted by the IMR+ device to
indicate to the network that one or more network ports in
the repeater is involved in a collision.
Network Port
Any of the eight 10BASE-T ports or the AUI port present
in the IMR+ device (i.e. not the Expansion Port or the
Management Port).
Am79C981
1–109
1-110
Am79C981
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